Microelectronic devices, including stadium structures, as well as related memory devices and electronic systems.
By employing block, conductive contact structures, and conductive filled vias in 3D memory arrays, the complexity of electrical connections is addressed, resulting in increased memory density, reduced manufacturing costs, and optimized reliability and efficiency of electrical connections.
CN115700031BActive Publication Date: 2026-05-26MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2021-05-19
- Publication Date
- 2026-05-26
AI Technical Summary
Technical Problem
In existing 3D memory arrays, as the number of memory cells increases, the complexity of electrical connections and the number and size of wiring interconnect structures also increase, hindering the improvement of memory density and the reduction of manufacturing costs.
Method used
The design employs a block, conductive contact structure, and conductive filled vias. By combining forward and reverse stepped structures, conductive connections are achieved, simplifying electrical connections within the substrate structure and reducing the complexity of wiring and interconnect structures.
Benefits of technology
It increases memory density, reduces manufacturing costs, and optimizes the reliability and efficiency of electrical connections.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN115700031B_ABST
Abstract
A microelectronic device includes blocks, contact structures, filled vias, and a substrate structure. Each block has a vertically alternating sequence of conductive and insulating structures arranged in layers. Each block includes a forward stepped structure and a reverse stepped structure. The contact structures are located on steps of the forward stepped structure of a first block and on additional steps of the reverse stepped structure of a second block horizontally adjacent to the first block. The filled vias extend within a portion of the first block within the horizontal boundary of the reverse stepped structure of the first block and within a portion of the second block within the horizontal boundary of the forward stepped structure of the second block. The substrate structure is located beneath the blocks and includes transistors coupled to the filled vias.
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