Dc-dc power supply control method
By using the DC-DC power control method and utilizing the GPIO resources of the MCU for closed-loop management, the problem of power timing management in complex multi-power rail electronic systems is solved, achieving high reliability and low cost power management, eliminating system failures caused by residual voltage, and providing flexibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU SINO MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-04-20
- Publication Date
- 2026-07-14
AI Technical Summary
Existing technologies cannot effectively manage power timing in complex multi-rail electronic systems, leading to latch-up effects, bus contention, chaotic initialization logic, and system failures caused by residual voltage after power-down. Furthermore, existing solutions are costly, lack flexibility, or have poor robustness.
The DC-DC power control method is adopted, which utilizes the GPIO resources of the MCU to monitor the output voltage of the DC-DC power supply and realize closed-loop management of the power rail power-on and power-off process, including initialization, power-on detection, power-off detection and active discharge, to ensure that the power rail returns to zero. The system safety is guaranteed by using state machine logic and interlocking mechanism.
It achieves highly reliable and low-cost power management, eliminates system anomalies caused by residual voltage, and has flexibility and scalability to adapt to different power chips and load scenarios, thereby improving system reliability.
Smart Images
Figure CN122394366A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power management technology for electronic systems. Background Technology
[0002] In complex multi-rail electronic systems (such as communication equipment, industrial controllers, and smart hardware), the power supply timing of each functional module is crucial. Incorrect power-on timing can lead to latch-up, bus contention, or initialization logic chaos. Incomplete power-down processes, especially those with residual power rail voltage due to high-capacity energy storage components in the downstream load, are a major cause of latent faults such as system crashes, startup failures, and program crashes if power is attempted again before the residual voltage has been fully discharged.
[0003] In existing technologies, solving power timing management problems typically relies on the following solutions:
[0004] 1. Dedicated power timing management chip: This solution is reliable, but it increases the cost of dedicated materials and board area, and the timing is fixed or needs to be adjusted by external circuits, which is not flexible enough.
[0005] 2. Chain triggering using reset or voltage monitoring chips: Simple timing is achieved by cascading the "reset" and "enable" pins of multiple monitoring chips. However, this approach is cumbersome to design for complex timing scenarios and also fails to actively manage the power-down waveform, thus failing to address the issue of residual power-down waveforms.
[0006] 3. Pure software delay control: After the MCU enables the power supply via GPIO, it simply delays before executing subsequent operations. This solution has the lowest cost, but its robustness is extremely poor. It cannot sense the actual voltage build-up or shutdown status, has no adaptability to load changes, temperature drift, and device aging, and cannot detect whether the power-down is complete, posing a potential threat to system reliability.
[0007] Therefore, the industry urgently needs a power management solution that combines low cost, high reliability, and high flexibility, and can proactively shape and verify the power-on and power-off behavior of the power rails, fundamentally eliminating system failures caused by uncontrolled power-on and power-off processes. Summary of the Invention
[0008] The technical problem to be solved by this invention is to provide a DC-DC power supply active control method that utilizes existing MCU resources, which features active protection of power-down integrity, real-time monitoring of the power-up process, high economy and integration, and flexible software configuration.
[0009] The technical solution adopted by the present invention to solve the aforementioned technical problem is a DC-DC power supply control method, comprising the following steps:
[0010] (1) Initialization: Turn off the DCDC power supply, and then monitor the output voltage of the DCDC power supply. If the output voltage of the DCDC power supply is lower than the preset threshold, proceed to step (2); otherwise, issue an alarm, or turn off the DCDC power supply, or issue an alarm and turn off the DCDC power supply.
[0011] (2) Power-on detection: Turn on the DC-DC power supply and then monitor the output voltage of the DC-DC power supply; if the output voltage of the DC-DC power supply does not reach the preset value within the preset time limit, it is determined to be a power-on fault and the power supply is turned off.
[0012] (3) Power-off detection: When it is necessary to turn off the DCDC power supply, monitor the output voltage of the DCDC power supply. When the voltage is lower than the discharge threshold, discharge the power supply output terminal to ground.
[0013] During the ground discharge process in step (3), the voltage at the output terminal of the DC-DC converter is monitored. When the voltage is lower than the zero voltage threshold, the discharge is considered complete.
[0014] Furthermore, the MCU controls the DC-DC power supply through the first GPIO connected to the power control terminal, turning the DC-DC power supply off or on. The MCU configures the second GPIO connected to the power output terminal to ADC mode and samples and monitors the output of the DC-DC power supply.
[0015] In step (3), the MCU configures the second GPIO to strong pull-down output mode to enable the power output terminal to be grounded.
[0016] The MCU is configured to have two mutually exclusive states: the DC-DC power enable state of the first GPIO and the output low state of the second GPIO.
[0017] In step (3), when the output voltage of the DC-DC power supply is lower than the discharge threshold and the output of the first GPIO is a turn-off control signal for the DC-DC, the power supply output terminal is discharged to ground.
[0018] Compared with the prior art, the present invention achieves the following significant beneficial effects:
[0019] 1. Eliminate residual power-off hazards: Through a closed loop of "monitoring-active discharge-confirmation", the power rail is forced to return to zero, fundamentally avoiding system startup anomalies caused by residual voltage and greatly improving system reliability.
[0020] 2. Achieve true intelligent management: Upgrade power control from "open-loop delay" to "closed-loop feedback", with voltage establishment verification and fault detection capabilities.
[0021] 3. Extremely cost-effective: It makes full use of the redundant resources of the MCU without increasing the cost of any dedicated hardware, thus realizing the "democratization" of "high-end functions".
[0022] 4. High flexibility and scalability: All behaviors are software-defined, which can be easily adapted to different power chips and different load scenarios, and can be expanded into a complex multi-power timing management system. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the hardware structure of the present invention.
[0024] Figure 2 This is a logic flowchart of the present invention.
[0025] Figure 3 This is the state transition diagram and interlock truth table of the present invention. Detailed Implementation
[0026] This invention proposes an active power-on / off management method for DC-DC power supplies based on an MCU. Its core lies in using one GPIO as the control terminal and another GPIO with both analog sampling and digital output functions as the intelligent monitoring / execution terminal. By embedding specific state machine logic inside the MCU, closed-loop management of the entire lifecycle of the power rail is achieved, from "return to zero-power-monitoring-shutdown-discharge-confirmation of return to zero".
[0027] See Figure 1 The minimum hardware configuration for implementing the present invention includes a DC-DC power supply chip with an enable pin and a microcontroller with at least two GPIOs and an internal ADC.
[0028] The MCU's control GPIO is connected to the enable pin of the DC-DC power supply chip; the output voltage rail of the DC-DC power supply is connected to the MCU's monitoring GPIO via a voltage divider network (if required).
[0029] The method of the present invention includes the following steps:
[0030] 1. Initialization and Safety Status Confirmation: Upon system startup, the MCU initializes and forces the first GPIO (also known as the "control GPIO") to output an invalid level to disable the DC-DC converter. Subsequently, the second GPIO (also known as the "monitor GPIO") is configured as an ADC input to sample the output voltage of the DC-DC power supply. Only when the sampled voltage is below the zero voltage threshold V_zero (close to 0V) is the power rail considered to be in a safe "absolute zero" state, allowing the power-on process to proceed.
[0031] 2. Controlled Power-On and Verification: The MCU sets the first GPIO to enable the DC-DC converter. It continuously samples the output voltage of the DC-DC power supply through the second GPIO (in ADC mode) until the output voltage reaches the target voltage threshold V_target. If the target is not reached within a preset time, a power-on fault is identified, triggering an alarm and disabling the DC-DC converter.
[0032] 3. Intelligent Power-Down and Active Discharge: When power needs to be turned off, the MCU clears the first GPIO to shut down the DC-DC converter. The voltage drop process is monitored via the second GPIO (ADC mode). The discharge process consists of two stages: a natural discharge stage and an active accelerated discharge stage. When the voltage drops below the discharge threshold V_slow (indicating the main discharge path is closed), the MCU dynamically reconfigures the second GPIO to a strong pull-down output mode (outputting a low level), forming an active discharge path to ground to quickly discharge residual charge stored in PCB parasitic capacitance and other components.
[0033] 4. Power-down Completion Confirmation: During the active discharge process, the MCU periodically switches the second GPIO temporarily back to ADC mode to sample the DC-DC power supply output voltage (or achieves this through another independent ADC channel). When the output voltage is lower than the zero voltage threshold V_zero (close to 0V), the power-down is considered completely complete. Subsequently, the second GPIO returns to high-impedance input mode, and the system returns to the "safe state" in step 1, completing a full management cycle.
[0034] Key logic and interlocking relationships:
[0035] To ensure system security, the operating modes of the first GPIO and the second GPIO must adhere to a strict state interlocking mechanism:
[0036] (1) Absolutely Disabled State: When the first GPIO output is valid (DC-CDC enabled), the second GPIO must not be configured to output a low level. This state will short-circuit the DC-CDC power supply output, which may cause DC-CDC overcurrent damage, MCU pin burnout, or subsequent system malfunctions.
[0037] (2) Controlled activation state: The active pull-down output function of the second GPIO is only allowed to be activated when the following two conditions are met simultaneously: a) The first GPIO has output an invalid level (DC-CDC confirmation shutdown). b) The voltage sampled by the second GPIO as an ADC is lower than the preset discharge threshold V_slow (indicating that it has entered the slow discharge stage). This interlock logic is strictly guaranteed by the state machine in the MCU firmware.
[0038] Example
[0039] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0040] Hardware implementation: such as Figure 1 As shown, any microcontroller with GPIO and ADC functions can be selected as the MCU. The DC-DC power supply chip (hereinafter referred to as DC-DC) has an enable terminal. The monitoring point can be directly taken from both ends of the DC-DC output capacitor, and then connected to the MCU's monitoring GPIO after voltage division. The MCU's first GPIO ( Figure 1 GPIO1 is used as the enable pin EN for controlling the GPIO connection to the DC-DC converter. The first GPIO of the MCU ( Figure 1 GPIO2 is used as the voltage output terminal LX of the DC-DC converter to monitor the GPIO connection. The voltage output terminal LX of the DC-DC converter can drive multiple load devices, such as DSP, CPU, FPGA, etc.
[0041] Figure 2 The core operational logic and state transitions of the method described in this invention are demonstrated, with particular emphasis on the coordinated control and strict interlocking relationship between the two GPIOs (GPIO1 and GPIO2):
[0042] S1 (Safe Initialization and Forced Zeroing): After system startup, the DC-DC converter is first forcibly shut down (GPIO1=0), and the DC-DC output voltage V is checked. If V is not zero (indicating the presence of abnormal residual voltage), the system will actively enter a forced discharge cycle (by configuring GPIO2 to output low level) until the power rail is confirmed to be completely zero, ensuring an absolutely safe starting state.
[0043] S2 (Controlled Power-On and Monitoring): The DC-DC converter is only allowed to be turned on (GPIO1=1) after the DC-DC output voltage V is confirmed to be zero. During power-on, GPIO2 continuously monitors the DC-DC output voltage V establishment process as an ADC input mode, and a timeout fault detection mechanism can be set.
[0044] Intelligent power-down and two-stage discharge: After the power-down command is triggered, the DC-DC converter is first turned off (GPIO1=0). The discharge process is clearly divided into two stages:
[0045] S3 (Natural Discharge Stage): When GPIO2 samples the DC-DC output voltage V > V_slow, GPIO2, as the ADC monitoring voltage, drops rapidly.
[0046] S4 (Active Accelerated Discharge Stage): When the DC-DC output voltage V sampled by GPIO2 satisfies V_zero≤V≤V_slow, the main discharge circuit is closed, and the discharge speed slows down. At this time, the system dynamically reconfigures GPIO2 from ADC input mode to strong pull-down output mode (output low level), forming an active discharge circuit to accelerate the discharge of residual charge.
[0047] Key interlocking logic: The process strictly adheres to the core principle that "when GPIO1 is enabled, GPIO2 must be absolutely prohibited from being output low." The active discharge function is only activated when GPIO1=0 (DC-CDC is confirmed to be off) and the DC-CDC output voltage V has dropped below the safe threshold (V_slow). This fundamentally prevents the risk of short-circuiting the power output, protecting the DC-CDC chip and the MCU's GPIO pins.
[0048] Closed-loop completion and state reset: Active discharge continues until the DC-DC output voltage V approaches 0V, then GPIO2 returns to the high-impedance ADC input mode, and the system state machine returns to the "safe initial state", forming a complete closed-loop power management cycle, preparing for the next reliable power-on.
[0049] This flowchart visually illustrates the core idea of this invention, which moves from "passive control" to "active management and closed-loop verification".
[0050] Software implementation:
[0051] 1. Parameter configuration: Preset key parameters in the software, including: target voltage threshold V_target, discharge threshold V_slow, zero voltage threshold V_zero, power-on timeout (optional), and total power-off timeout (optional).
[0052] 2. State Machine Implementation: The core is a five-state machine: safe state, power-on state, operating state, power-off natural discharge state, and power-off active discharge state. State transition conditions strictly follow the attached... Figure 3 The state transition diagram and interlock truth table.
[0053] 3. Enhanced functionality: It can integrate functions such as fault diagnosis, bleed resistor simulation, and multi-power rail extension management.
[0054] Implementation details: In a system that generates +3.3V from a +12V input, an MCU's PA1 pin is used as a control GPIO connected to the EN pin of the DC-DC converter, and the PA2 pin is used as a monitoring GPIO. The corresponding voltage threshold is set in software. When the system receives a shutdown command, PA1 is set low. Once the MCU detects that the voltage has dropped below the threshold, PA2 is reconfigured to open-drain output low to accelerate discharge. This solution successfully resolved the previous anomaly in the system where the interval between multiple restarts had to be greater than 2 seconds due to residual voltage.
Claims
1. A DC-DC power supply control method, characterized in that, Includes the following steps (1) Initialization: Turn off the DCDC power supply, and then monitor the output voltage of the DCDC power supply. If the output voltage of the DCDC power supply is lower than the preset threshold, proceed to step (2); otherwise, issue an alarm, or turn off the DCDC power supply, or issue an alarm and turn off the DCDC power supply. (2) Power-on detection: Turn on the DC-DC power supply and then monitor the output voltage of the DC-DC power supply; if the output voltage of the DC-DC power supply does not reach the preset value within the preset time limit, it is determined to be a power-on fault and the power supply is turned off. (3) Power-off detection: When it is necessary to turn off the DCDC power supply, monitor the output voltage of the DCDC power supply. When the voltage is lower than the discharge threshold, discharge the power supply output terminal to ground.
2. The DC-DC power supply control method as described in claim 1, characterized in that, During the ground discharge process in step (3), the output voltage of the DC-DC power supply is monitored. When the voltage is lower than the zero voltage threshold, the discharge is considered complete.
3. The DC-DC power supply control method as described in claim 1, characterized in that, The MCU controls the DC-DC power supply by turning it off or on through the first GPIO connected to the power control terminal. The MCU configures the second GPIO connected to the power output terminal to ADC mode and samples and monitors the output of the DC-DC power supply.
4. The DC-DC power supply control method as described in claim 3, characterized in that, In step (3), the MCU configures the second GPIO to strong pull-down output mode to enable power output to be discharged to ground.
5. The DC-DC power supply control method as described in claim 3, characterized in that, The MCU is configured to have two mutually exclusive states: the DC-DC power enable state of the first GPIO and the output low state of the second GPIO.
6. The DC-DC power supply control method as described in claim 4, characterized in that, In step (3), when the output voltage of the DC-DC power supply is lower than the discharge threshold and the output of the first GPIO is a control signal to turn off the DC-DC power supply, the power supply output terminal is discharged to ground.