Phase change device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2021-06-10
- Publication Date
- 2026-06-30
Smart Images
Figure CN115700036B_ABST
Abstract
Description
Background Technology
[0001] This invention relates to phase change devices. More specifically, this invention relates to phase change devices having multiple states.
[0002] Some phase change devices (PCDs) can operate in two states, such as a high or higher resistance state (HRS) and a low or lower resistance state (LRS). Other PCDs can operate in multiple states, such as at a resistance value between HRS and LRS. Different voltages applied to these devices can set and reset the device state.
[0003] In some devices, a normally insulating dielectric (in a low resistance state (LRS)) can be made conductive through one or more filaments or conductive paths formed by applying a sufficiently high voltage. Once the filaments / paths are formed, a change in voltage can either "reset" the dielectric (e.g., disconnect the filaments / paths, thus generating HRS) or "set" (re-form the filaments / paths, thus generating LRS) the dielectric. It is also possible to form / store intermediate states between LRS and HRS by changing the configuration of the filaments via an electrical bias.
[0004] PCD (like resistive random access memory (RRAM)) is considered a promising technology for use as an electronic synaptic device or memristor in neuromorphic computing, as well as for high-density and high-speed non-volatile memory applications. In neuromorphic computing applications, resistive memory devices can be used as connections (synapses) between preneurons and postneurons, with the connection weights represented by the device resistance. Multiple preneurons and postneurons can be connected via a cross-shaped array of RRAMs, which naturally represents a fully connected neural network.
[0005] Fabricating PCDs in the back-end of the line (BEOL) can present challenges. While device circuitry is typically placed in lower-level circuitry within the front-end of the line (FEOL) process, BEOLs often have multiple dielectric substrate layers that can be difficult to use when fabricating phase-change devices, especially when forming dense arrays of PCDs that resemble large memory structures.
[0006] There is a need for structures and methods, particularly in the BEOL region, capable of constructing PCDs and higher-density PCD arrays. Furthermore, there is a need for multi-state PCD structures and methods for fabricating these multi-state PCD structures. Summary of the Invention
[0007] According to some embodiments of the present invention, a phase change device (PCD) has a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and the first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state under one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and the second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with each other at the interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state under one or more second conditions. The first electrode is in physical and electrical contact with the first electrode surface of the first semiconductor layer, and the second electrode is in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and the second conditions are different. Therefore, in some embodiments, the first semiconductor material and the second semiconductor material can be in different amorphous states and / or crystalline states.
[0008] In some embodiments, the first semiconductor layer is divided or split into a first epitaxial crystalline layer and a first amorphous residual layer. The first epitaxial crystalline layer has an epitaxial thickness and an epitaxial resistance, and the first amorphous residual layer has a residual thickness and a residual resistance. By controlling the epitaxial thickness, the resistance across the first semiconductor and thus the total resistance across the device (electrodes) is controlled to produce multiple resistance states from LRS to multiple HRS.
[0009] Methods for preparing and using PCD are disclosed. Attached Figure Description
[0010] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, which will now be described briefly. The drawings illustrate various apparatuses, structures, and related method steps of the present invention.
[0011] Figure 1 This is a block diagram of the preliminary layered structure at the initial step in the process of manufacturing a phase change device (PCD).
[0012] Figure 2 This is a block diagram of the initial layered structure after the addition of two semiconductor layers and an optional diffusion barrier layer.
[0013] Figure 3 This is a block diagram of the preliminary layered structure after the mask etching step that defines the PCD coverage area.
[0014] Figure 4 It is a block diagram of the front view of the preliminary layered structure covered with dielectric.
[0015] Figure 5 It is a front view of the layered structure including the top electrode, which serves as a precursor to the PCD.
[0016] Figure 6 This is a front view of a precursor PCD embodiment after the first and second semiconductor layers have been heated and cooled to form a crystalline structure.
[0017] Figure 7 This is a front view of a PCD embodiment after the first semiconductor layer has been reset to an amorphous structure.
[0018] Figure 8 This is a front view of a PCD embodiment after the first semiconductor layer is positioned as one of a plurality of bilayer structures (a first semiconductor crystalline layer and a first semiconductor amorphous layer).
[0019] Figure 9 This is a front view of an alternative PCD embodiment with a diffusion barrier layer.
[0020] Figure 10A It is a graph showing the voltage versus time of one or more reset pulses.
[0021] Figure 10B It is a graph showing the voltage versus time of one or more set pulses.
[0022] Figure 11 This is a flowchart of an embodiment of the process for manufacturing a PCD.
[0023] Figure 12 This is a flowchart of an embodiment of the process for operating the PCD. Detailed Implementation
[0024] It should be understood that embodiments of the present invention are not limited to the illustrative methods, apparatuses, structures, systems and devices disclosed herein, but are more broadly applicable to other alternative and broader methods, apparatuses, structures, systems and devices, which will become apparent to those skilled in the art in the context of the present invention.
[0025] Furthermore, it should be understood that the various layers, structures, and / or regions shown in the accompanying drawings are not drawn to scale, and one or more layers, structures, and / or regions of commonly used types may not be explicitly shown in a given drawing. This does not mean that layers, structures, and / or regions not explicitly shown are omitted from the actual device.
[0026] Furthermore, when the explanation does not necessarily focus on such omitted elements, certain elements may be omitted from the view for clarity and / or simplicity. Additionally, the same or similar reference numerals used throughout the figures denote the same or similar features, elements, or structures; therefore, detailed descriptions of the same or similar features, elements, or structures will not be repeated in each figure.
[0027] The semiconductor devices, structures, and methods disclosed according to embodiments of the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, etc. Systems and hardware comprising semiconductor devices and structures are contemplated embodiments of the present invention.
[0028] As used herein, “height” refers to the vertical dimension of an element (e.g., layer, groove, hole, opening, etc.) in a cross-sectional or elevation view measured from the bottom surface of the element to the top surface and / or relative to the surface on which the element is located.
[0029] Conversely, "depth" refers to the vertical dimension of a component (e.g., layer, trench, hole, opening, etc.) in a cross-sectional or frontal view measured from the top surface to the bottom surface of the component. Where indicated, terms such as "thickness," "thickness," "thin," or derivatives thereof may be used instead of "height."
[0030] As used herein, “lateral,” “lateral side,” “side,” and “lateral surface” refer to the side surface of an element (e.g., a layer, an opening, etc.), such as the left or right side surface in the accompanying drawings.
[0031] As used herein, “width” or “length” refers to the dimension of an element (e.g., layer, trench, hole, opening, etc.) measured from the side surface of the element to the opposite surface in the accompanying drawings. Where indicated, terms such as “thickness,” “thickness,” “thin,” or derivatives thereof may be used instead of “width” or “length.”
[0032] As used herein, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. For example, as used herein, “vertical” means a direction perpendicular to the top surface of the substrate in a front view, and “horizontal” means a direction parallel to the top surface of the substrate in a front view.
[0033] As used herein, unless otherwise specified, terms such as “on,” “covering,” “on top,” “on top of,” “positioned on,” or “positioned on top of” mean that the first element is present on the second element, wherein an intermediate element may be present between the first and second elements. As used herein, unless otherwise specified, the term “direct” as used in conjunction with the terms “on,” “covering,” “on top,” “above,” “positioned on,” “positioned on,” “placed on,” or the terms “contact” or “direct contact” means that the first and second elements are connected without any intermediate element (such as an intermediate conductive, insulating, or semiconductor layer) between the first and second elements.
[0034] It should be understood that these terms may be affected by the orientation of the device being described. For example, while the meaning of these descriptions may change if the device is rotated upside down, the descriptions remain valid because they describe the relative relationships between the features of the invention.
[0035] Embodiments of the structure of a phase change device (PCD) and the process of manufacturing and operating a PCD are disclosed.
[0036] A non-limiting example of a PCD structure includes a first semiconductor layer and a second semiconductor layer sandwiched between a top electrode and a bottom electrode. The first and second semiconductor layers have an interface, wherein each of a surface (interface surface) of the first and second semiconductor layers is in physical contact with the other interface surface. In some embodiments, a thin diffusion barrier layer exists between the first and second interface surfaces. Each of the first and second semiconductor layers has an electrode surface, which is the side of the semiconductor layer opposite to the interface surface of the corresponding semiconductor layer. The first electrode surface on the first semiconductor layer is in physical and electrical contact with the bottom or first electrode, and the second electrode surface on the second semiconductor layer is in physical and electrical contact with the top or second electrode.
[0037] The materials used to fabricate the first and second semiconductor layers have different and distinguishable thermal properties because each of the semiconductors changes from an amorphous structure to a crystalline structure under different conditions (e.g., thermal changes, such as temperature).
[0038] Perform heating and cooling steps, such as annealing, to bring both the first and second semiconductor layers into a crystalline state.
[0039] The "positioning" step enables the epitaxial growth or alteration of the first crystalline layer to form a first epitaxial crystalline layer within the first semiconductor layer, starting at the interface and penetrating the first semiconductor layer. Therefore, the first semiconductor layer is divided or split into a first epitaxial crystalline layer and a first amorphous residual layer. The first epitaxial crystalline layer has an epitaxial thickness and epitaxial resistance, and the first amorphous residual layer has a residual thickness and residual resistance.
[0040] By changing how the set step is executed, for example by changing the characteristics of the set pulse, the epitaxial thickness and residual thickness will change. Therefore, the epitaxial resistance and residual resistance can vary, and different amounts of resistance (total resistance) across the structure (e.g., different (resistance) states of the structure) can be predetermined, controlled, and enabled.
[0041] Now refer to the attached diagram.
[0042] Figure 1 This is a front view of the preliminary layered structure 100 at the initial step in the process of manufacturing an example of a phase change device (PCD).
[0043] Structure 100 has a substrate 105. A dielectric layer 110 is disposed on the substrate 105. In some embodiments, such as at the back end of the line (BEOL), the substrate 105 may be removed. A bottom electrode 115 is disposed on the dielectric layer 110.
[0044] The substrate 105 may be made of a single element (e.g., silicon or germanium); primarily a single element (e.g., doped), such as silicon; or a compound semiconductor, such as gallium arsenide (GaAs); or a semiconductor alloy, such as silicon-germanium (SiGe). In some embodiments, the substrate 105 comprises one or more semiconductor materials, including but not limited to: silicon (Si), SiGe, Si:C (carbon-doped silicon), germanium (Ge), carbon-doped silicon-germanium (SiGe:C), Si alloys, Ge alloys, III-V materials (e.g., GaAs, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.), II-V materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), or any combination thereof) or other similar semiconductors. Furthermore, multilayer semiconductor materials may be used as the semiconductor material of the substrate 105. In some embodiments, the substrate 105 comprises both a semiconductor material and a dielectric material. In silicon-on-insulator (SOI) implementations, a buried oxide layer BOX (e.g., SiO2) is buried within the substrate 105.
[0045] In some embodiments, the dielectric layer 110 is made of a low-k dielectric. The term "low-k dielectric" generally refers to an insulating material with a dielectric constant less than that of silicon dioxide (e.g., less than 3.9). As a non-limiting example, the dielectric layer 110 is made of materials including: dielectric oxides (e.g., silicon oxide, SiOx); dielectric nitrides (e.g., silicon nitride, SiN; silicon boron carbonitride, SiBCN; silicon carbonitride, SiCN; and silicon boron nitride, SiBN); dielectric oxynitrides (e.g., silicon carbonitride, SiOCN and silicon oxynitride, SiON); silicon carbide (SiC); silicon carbonitride (SiCO); or any combination thereof.
[0046] The dielectric layer 110 can be deposited using known deposition techniques, including: atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), radio frequency chemical vapor deposition (RFCVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), and / or liquid source atomized chemical vapor deposition (LSMCD).
[0047] In some embodiments, the dielectric layer 110 has a dielectric layer thickness 111 between 50 nanometers (nm) and 100 nm. Other thicknesses 111 are contemplated.
[0048] The first electrode or bottom electrode 115 is made of a conductive material (e.g., a metal). Non-limiting examples of metals include copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), thallium nitride (Tl3N), and titanium nitride (TiN). In some embodiments, the first / bottom electrode 115 is made of Al.
[0049] The first / bottom electrode 115 can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, LSMCD and / or sputtering.
[0050] In some embodiments, the thickness 116 of the first electrode 115 is between 50 nanometers (nm) and 100 nm. Other thicknesses 116 are contemplated.
[0051] Figure 2 This is a front view of the initial layered structure 200 after the addition of two semiconductor layers (250, 225) and an optional diffusion barrier layer 285.
[0052] The first semiconductor layer 250 is made of a first semiconductor material capable of existing in both an amorphous (first amorphous) and crystalline (first crystalline) form. The second semiconductor layer 225 is made of a second semiconductor material capable of existing in both an amorphous (second amorphous) and crystalline (second crystalline) form. The amorphous form can transform into the crystalline form under various physical conditions (and vice versa). The first semiconductor material has the property of transforming from an amorphous to a crystalline form under conditions different from those of the second semiconductor (e.g., the application of temperature and / or voltage).
[0053] In some embodiments, the first semiconductor layer 250 is made of germanium (Ge), and the second semiconductor layer 225 is made of silicon (Si). Other materials are contemplated.
[0054] The first semiconductor layer 250 has a thickness 251 between 20 nm and 50 nm. The second semiconductor layer 225 also has a thickness 226 between 20 nm and 50 nm.
[0055] The first semiconductor layer 250 has a first interface surface 257 and a first electrode surface 258. The first interface surface 257 and the first electrode surface 258 are opposite to each other, that is, on opposite sides of the first semiconductor layer 250.
[0056] The second semiconductor layer 225 has a second interface surface 227 and a second electrode surface 228. The second interface surface 227 and the second electrode surface 228 are opposite to each other, that is, on opposite sides of the first semiconductor layer 225.
[0057] The first electrode surface is in physical and electrical contact with the first electrode / bottom electrode 115. In some embodiments, the first interface surface 257 is in physical, chemical, and electrical contact with the second interface surface 227. In an alternative embodiment, an optional diffusion barrier layer (DBL) 285 is present, "caged" between the first interface surface 257 and the second interface surface 227. The second electrode surface 228 is in physical and electrical contact with the second electrode / top electrode 515, for example, as shown below. Figure 5 middle.
[0058] DBL285 prevents the diffusion of the first semiconductor layer 250 material (e.g., Ge) into the second semiconductor layer 225 material (e.g., Si). DBL can be made of titanium nitride (TiN) or carbon (C). Other known barrier or diffusion-resistant materials can be used.
[0059] DBL285 is a thin layer with a thickness of 286 nm, ranging from 1 nm to 10 nm.
[0060] The first semiconductor layer 250 and the second semiconductor layer 225, as well as the DBL 285, can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, and / or LSMCD. The order of deposition is irrelevant. However, if an optional DBL layer 285 is placed, it will be located between the first interface surface 257 and the second interface surface 227. If the order of deposition of the semiconductor layers (250, 225) is reversed, the second electrode surface 228 will be in physical and electrical contact with the first electrode / bottom electrode 115, while the first electrode surface 258 will be in physical and electrical contact with the second electrode / top electrode 515. However, in either case, the first semiconductor layer 250 will be a semiconductor layer with epitaxial growth, as described below, without loss of generality.
[0061] Figure 3 A block diagram of, for example, a front view of the preliminary layered structure 300 after a known mask etching step. Directional reactive ion etching (RIE) defines the PCD footprint. A mask protects portions of the semiconductor layers (225, 250) while removing volumes of semiconductor layers (225, 250) around the remaining semiconductor layers (350, 325) (left and right – and front and back, not shown). One or more known chemicals suitable for removing the unmasked first semiconductor layer 250 and second semiconductor layer 225 can be used. In some embodiments, the etching stops at a barrier layer (e.g., the first electrode / bottom electrode 115).
[0062] In structure 300 and subsequent structures, DBL 285 may or may not be included in the structure, but DBL 285 is not shown for clarity. This masked etching defines the size and / or area of the PCD used on the surface of the first electrode / bottom electrode 115, i.e., the PCD footprint.
[0063] Figure 4 This is a front view of the preliminary layered structure 400 covered with dielectric 410.
[0064] In some embodiments, dielectric 410 may be of the same type and / or placed using the same method as in dielectric layer 110. In some embodiments, dielectric 410 may be an interlayer dielectric (ILD). ILD 410 may be formed of, for example, a low-k dielectric material (where k < 4.0), including but not limited to silicon oxide, spin-coated glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. ILD 410 is deposited by deposition processes, including but not limited to CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or similar processes.
[0065] Figure 5This is a front view of the layered structure 500 including the second electrode / top electrode 515. Structure 500 is a precursor to PCD because structure 500 is complete, but the semiconductor layers (325, 350) need to have their chemical structure transformed to function effectively as PCD, as described below.
[0066] The second electrode / top electrode 515 is formed by performing a masked etching (e.g., oriented RIE) through the ILD / dielectric layer 410 above the second semiconductor layer 325. In some embodiments, the etching stops at the second electrode surface 228. The second electrode / top electrode 515 is deposited to make physical and electrical contact with the second electrode surface 228 using the same materials and methods used for depositing the first electrode layer 115.
[0067] Figure 6 This is a front view of the precursor PCD embodiment 600 after heating and cooling the first semiconductor layer 350 and the second semiconductor layer 325 to form a crystalline structure (650, 625).
[0068] Perform physical processes such that the first semiconductor layer 350 and the second semiconductor layer 325 are subjected to one or more altered physical conditions that convert the first semiconductor structure 350 into a first crystalline state 650 and the second semiconductor structure 325 into a second crystalline state 625.
[0069] In some embodiments, the altered physical condition is thermal annealing. In other words, both semiconductor layers (350, 325) are heated above their melting temperatures and then cooled over time, thus forming a first crystalline semiconductor layer 650 and a second crystalline semiconductor layer 625. The time and temperature level at which the first layer 650 and the second layer 625 crystallize depend on the type of material in the layers and the volume of the material within the layers. While actual time and temperature values need to be determined for specific cases, as a non-limiting example, it is possible to locally raise the temperature within the device to between 900 degrees Celsius (C) and 1000 degrees Celsius, and allow cooling to room temperature over time periods between 1 microsecond and 10 microseconds.
[0070] In a non-limiting example, the amorphous Ge (α-Ge) in the first semiconductor layer 350 is changed to crystalline Ge (c-Ge) 650 by an annealing step, and the amorphous Si (α-Si) in the second semiconductor layer 325 is changed to crystalline Si (c-Si) 625.
[0071] Figure 7 This is a front view of PCD embodiment 700 after the first crystalline semiconductor layer 650 has been reset to an amorphous structure 750.
[0072] Without altering the structure of the second crystalline semiconductor layer 625, the first crystalline semiconductor layer 650 is "reset" to an amorphous structure 750. This is due to the fact that both the first semiconductor layer (350, 650) and the second semiconductor layer (325, 625) possess the property of transitioning from an amorphous state to a crystalline state (and back again) under one or more different and distinguishable physical conditions. Therefore, the transition from amorphous to crystalline (and back again) can occur within the first (350, 650) semiconductor layer structure without affecting the second (325, 625) semiconductor layer structure.
[0073] In a non-limiting example, Ge transitions from an amorphous state to a crystalline state (and back again) at a lower temperature than Si. Current flows through the first semiconductor layer (350, 650) and the second semiconductor layer (325, 625) by applying one or more electrical / voltage pulses to the first electrode / bottom electrode 115 and the second electrode / top electrode 515, causing them to heat. The pulses are designed to heat Ge to a temperature above the Ge transition point (temperature) but below the Si transition point. Therefore, the first crystalline semiconductor layer 650 (e.g., c-Ge) melts, while the second crystalline semiconductor layer 625 does not melt. There is a rapid cooling cycle that is too fast to reform the first amorphous semiconductor layer 650 into a crystalline state. The second crystalline semiconductor layer 625 (e.g., c-Si) does not change from its crystalline state 625 due to temperature / voltage variations.
[0074] Now, structure 700 is "reset," causing the first semiconductor layer 350 to be in an amorphous state 750 with higher resistance. Therefore, due to the increased resistance of the first amorphous semiconductor layer 750, the overall resistance of structure 700 is higher. Because of the amorphous structure of the first semiconductor layer 350, structure 700 is reset in the HRS. The "setting," described below, returns the first semiconductor layer 350 to a crystalline structure, reducing the resistance across the first semiconductor layers (350, 650), and places structure 700 in multiple HRSs until LRS-PCD (having two or more states), LRS, and multiple HRSs are reached.
[0075] The material type, layer volume, and other factors in the first semiconductor layer 350 and the second semiconductor layer 325 are used to design the timing, shape, and amplitude of the voltage pulse. The following... Figure 10A Examples of the pulse timing, shape, and amplitude of the voltage pulse used for "reset" are given. In some embodiments, in the reset state, the entire volume of the first semiconductor layer 350 is in an amorphous state.
[0076] Figure 8This is a front view of PCD embodiment 800 after the first amorphous semiconductor layer 850 is "positioned" into one of a plurality of double-layer structures (850A, 850B), the first semiconductor crystalline layer 850A, and the first semiconductor amorphous layer 850B.
[0077] In one embodiment, the set pulse (see...) Figure 10B This causes the first amorphous semiconductor layer (e.g., after a reset pulse completely resets the first semiconductor layer to an amorphous state 750) to become a split first semiconductor layer 850, splitting into two layers: 1. a first epitaxial crystalline layer 850A having an epitaxial thickness 865 and an epitaxial resistance, and 2. a first amorphous residual layer 850B having a residual thickness 860 and a residual resistance. The residual layer 850B is what remains of the amorphous layer 750 of the first semiconductor amorphous layer 750 after the set pulse.
[0078] The shape, duration, timing, and amplitude of the set pulse determine, for example, the thickness 865 of the first epitaxial crystalline layer 850A and the thickness 860 of the first amorphous residual layer 850B. Therefore, the epitaxial resistance and residual resistance can be controlled by designing the set pulses that control the thicknesses (825, 860) of the corresponding epitaxial crystalline layer 850A and residual layer 850B. Thus, the resistance of the split first semiconductor layer 850 and the total resistance of the entire device 800 in the set state (measured across the first electrode 115 and the second electrode 115 / 515), i.e., the amount of resistance in the HRS, is controlled by the design of the set pulses.
[0079] Other factors that affect the resistance of device 800 in one of the multiple HRS and how the set pulse is designed include the material of the first semiconductor layer 250 and the second semiconductor layer 225, as well as the thickness (251, 226) and the material type and thickness 286 (if any) of the DBL layer 285.
[0080] Therefore, while other external physical conditions of the first semiconductor layer 250 and the second semiconductor layer 225 remain constant, such as multiple high-resistance states, the total resistance value of the device 800 in a set state can be created by changing the shape, duration, timing, and amplitude of the set pulse. Thus, the structure 800 can be a PCD that has multiple (resistance) set states by changing the set pulse.
[0081] By changing how the set step is performed, for example by changing the characteristics of the set pulse, the epitaxial thickness and residual thickness will change. Therefore, the epitaxial resistance and residual resistance can be varied, and different resistance values across the structure (e.g., different states of the structure) can be predetermined, controlled, and enabled.
[0082] The design of the positioning pulse determines how the first epitaxial crystalline layer 850A is formed.
[0083] The term "epitaxy growth" refers to the growth of a semiconductor material on a contact surface of a semiconductor material, wherein the grown semiconductor material has the same crystallinity as the semiconductor material deposited on the surface. Material parameters can be created such that the atoms at the surface 875 of the growth layer 850A have sufficient energy to move around on the surface 875 and orient themselves toward the crystal arrangement of atoms where epitaxial growth continues.
[0084] For example, if the set pulse is designed to heat and melt the first amorphous semiconductor layer 750, the atoms in the first amorphous semiconductor layer 750 will have enough energy to move back and forth. Alternatively, if the set pulse allows the first amorphous semiconductor layer 750 to cool slowly, the moving atoms (e.g., Ge) will move into the crystal orientation of the crystal surface in which they come into contact.
[0085] When DBL 985 is present, it can serve as a template for Ge crystallization.
[0086] To continue this non-limiting example, when the set pulse melts the material (Ge) of the first amorphous semiconductor layer 750, the material (Si) in the second semiconductor layer 625 remains in a crystalline structure. As the atoms in the first amorphous semiconductor layer 750 slowly cool, they align themselves in the crystalline order of the second semiconductor layer 625, starting at interface 825. As layer 850 continues to cool slowly, more atoms in the first amorphous semiconductor layer 750 align in the crystalline order, thus growing the thickness 865 of the first epitaxial crystalline layer 850A and moving the boundary surface 875 deeper into the first amorphous semiconductor layer 750. As the thickness 865 of the first epitaxial crystalline layer 850A increases, the thickness 860 of the remaining layer 850B decreases.
[0087] By changing the thickness 865 of the first epitaxial crystal layer 850A and the thickness 860 of the remaining layer 850B, the resistance of these layers changes, and therefore, the overall resistance of the device 800 is changed by controlling the set pulse.
[0088] In some embodiments, for example, by causing the values of (a plurality of) set pulses to decrease slowly over time. By reducing the rate of change of cooling and / or increasing the cooling time of the split first semiconductor layer 850, the thickness 865 of the first epitaxial crystal layer 850A will increase and the thickness 860 of the remaining layer 850B will decrease.
[0089] Figure 9 This is a front view of an alternative PCD embodiment 900 with a diffusion barrier layer (DBL) 985. The barrier layer 985 is formed by deposition. Figure 2The optional layer 285 shown is formed by continuing the process steps performed when DBL 285 is not deposited.
[0090] Figure 10A This is a graph 1000 showing the voltage 1030 versus time 1035 of one or more reset pulses (typically 1025). The reset pulse 1025 has a sufficiently high duration 1010 and amplitude 1020 to melt the material in the first semiconductor layer 250 (e.g., Ge) but not in the second semiconductor layer 225 (e.g., Si). However, the duration 1010 is short enough, and specifically, the fall time 1026 is fast enough, so that the first semiconductor layer material 250 does not have time to crystallize. Therefore, when the device 800 / 900 is reset, the first semiconductor layer material 250 remains / returns to the amorphous structure / state 750.
[0091] Figure 10B This is a graph 1050 showing the voltage 1030 versus time 1035 for one or more set pulses (typically 1070). The set pulse has an amplitude 1055 and a duration 1060, which has a gradual decline rate 1065 over the set pulse fall time 1075. For example, the decline rate 1065 is the amplitude 1055 of pulse 1070 divided by the set pulse fall time 1075.
[0092] As discussed, the design of amplitude (1020, 1055), timing (1010, 1060, 1075), duration (1010, 1080), and the shape of these pulses (1025, 1070), etc., depends in particular on the material type and thickness (251, 226) of the first semiconductor layer 350 and the second semiconductor layer 325.
[0093] However, in some embodiments, the reset pulse 1025 has a reset pulse amplitude 1020 between 7 volts and 10 volts (e.g., 8 volts); a reset pulse rise time 1024 between 2.0 and 3.0 nanoseconds (ns) (e.g., 2.5 ns); and a reset pulse fall time 1026 between 2.0 and 3.0 nanoseconds (ns) (e.g., 2.5 ns). The reset pulse shape can be rectangular or other shapes. However, the reset pulse fall time 1026 must be fast enough to prevent the material from crystallizing. The reset pulse amplitude 1020 must be low enough to prevent changes in the crystalline structure of the material of the second semiconductor layer 625.
[0094] In some embodiments, in a non-limiting example, the set pulse 1070 has an amplitude 1069 between 4 volts and 6 volts (e.g., 5 volts); a set pulse rise time 1069 between 2.0 nanoseconds (ns) and 3.0 nanoseconds (ns) (e.g., 2.5 ns); and a longer set pulse fall time 1075 between 0.8 milliseconds (ms) and 1.5 ms (e.g., 1.0 ms). Some set pulse shapes have a gradual fall time, for example, greater than 1.0 ms, to give time for the first semiconductor crystal layer 850A crystal structure to form. The duration 1080 of the set pulse 1070 is long enough to include a long fall time 1075, for example, 1.0 ms or more.
[0095] Figure 11 This is a flowchart of an example of the process of manufacturing 1100 PCDs.
[0096] Step 1105 of the method begins by depositing a first electrode 115 on a dielectric layer 110 and / or a substrate 105. Then, a first semiconductor layer 250 and a second semiconductor layer 225 are deposited. In some embodiments, a diffusion barrier layer 285 is deposited between the first semiconductor layer 250 and the second semiconductor layer 225.
[0097] Step 1110 involves etching the defined PCD footprint and, as... Figures 3 to 5 The second electrode 515 is deposited after other photolithography steps specified in the diagram.
[0098] Step 1115 involves heating and cooling processes (e.g., annealing, as...) Figure 6 (As shown) the first semiconductor layer 250 and the second semiconductor layer 225 are crystallized. Other crystallization methods are possible.
[0099] Step 1120 amorphizes the first semiconductor layer by changing physical conditions, for example, by using a reset voltage pulse 1025 to place the device in a reset state or LRS.
[0100] Step 1125 splits the first semiconductor layer 850 into a first semiconductor crystalline layer 850A and a first semiconductor amorphous layer 850B by changing physical conditions, for example, with a set voltage pulse 1075. This places the device 800 in one of a plurality of resistance states, such as those selected by the design of the set voltage pulse 1075 (e.g., by measuring the total resistance across the first electrode 115 and the second electrode 515). The resistance state will have a total resistance across the device 800, where one of a plurality of values is between LRS and HRS. In LRS, the first semiconductor crystalline layer 850A has a width or epitaxial thickness 865 equal to the total width 251 of the first semiconductor layer 250.
[0101] Figure 12This is a flowchart of an embodiment of the process for operating 1200 PCD.
[0102] Process 1200 begins at step 1205, which resets the first semiconductor layer 850 to an amorphous state, wherein all the first semiconductor 850 material is in an amorphous state 750. In some embodiments, this step is performed using a reset pulse 1025.
[0103] In step 1210, the setting device (e.g., 800) divides the first semiconductor layer 850 into a first semiconductor crystal layer 850A and a remaining layer 850B.
[0104] In step 1215, the total resistance across the device (e.g., 800 Ω) is determined by, for example, Figure 10B The set pulse selection is described herein. The total resistance is the resistance measured across the first electrode 115 and the second electrode 515. The total resistance is greatly influenced by the resistance of the first semiconductor layer 850, which in turn is influenced by the width or epitaxial thickness 865 of the first semiconductor crystalline layer 850A. The larger the epitaxial thickness 865, the larger the volume of the first semiconductor layer 850 material in the crystalline state (a state with lower resistance). Therefore, by controlling the epitaxial thickness 865, the total resistance can be changed to one of several values between LRS and HRS, or between a completely amorphous or completely crystalline structure of the first semiconductor layer 850 material. The design of the set pulse determines how much the epitaxial growth of the first semiconductor layer 850 material, the increase in the epitaxial thickness 865, and the reduction in the total resistance are.
[0105] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. For example, semiconductor devices, structures, and methods disclosed according to embodiments of the invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, etc. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the invention.
[0106] The terminology used herein is chosen to explain the principles of the embodiments and their practical application or technical improvements over those found in the market, or otherwise enable others skilled in the art to understand the embodiments disclosed herein. Apparatus, components, elements, features, devices, systems, structures, techniques, and methods described using different terms perform substantially the same functions, operate in substantially the same manner, have substantially the same purpose, and / or perform similar steps as embodiments of the invention.
Claims
1. A phase change device (PCD), comprising: A first semiconductor layer, the first semiconductor layer being made of a first semiconductor material and having a first semiconductor thickness, the first semiconductor layer further having a first interface surface and a first electrode surface, the first interface surface and the first electrode surface being on opposite sides of the first semiconductor layer, the first semiconductor material being transformed between a first amorphous state and a first crystalline state under one or more first conditions; The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness. The second semiconductor layer also has a second interface surface and a second electrode surface. The second interface surface and the second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical contact, physical contact and chemical contact with each other at the interface. The second semiconductor material is transformed between a second amorphous state and a second crystalline state under one or more second conditions. The first electrode is in physical and electrical contact with the surface of the first electrode of the first semiconductor layer. The second electrode is in physical and electrical contact with the surface of the second electrode in the second semiconductor layer. The first condition and the second condition are different; Wherein, when the first semiconductor layer is split into a first semiconductor crystalline layer having an epitaxial thickness less than the thickness of the first semiconductor and a first amorphous residual layer having a remaining thickness, the first resistance across the first semiconductor material is less than the first resistance of the first semiconductor material when the first semiconductor material is in the first amorphous state and greater than the first resistance of the first semiconductor material when the first semiconductor material is in the first crystalline state.
2. The PCD according to claim 1, wherein, The first condition is a lower temperature, and the second condition is a higher temperature.
3. The PCD according to claim 2, wherein, The lower and higher temperatures are caused by voltage pulses across the first and second electrodes.
4. The PCD according to claim 3, wherein, The voltage pulse is a reset pulse, which has a sufficiently high voltage amplitude to transform the first semiconductor material into the first amorphous state without transforming the second semiconductor material from the second crystalline state.
5. The PCD according to claim 4, wherein, The reset pulse has a sufficiently fast reset pulse fall time so that the first amorphous state does not transition to the first crystalline state.
6. The PCD according to claim 5, wherein, The first resistance of the first semiconductor material when all of the first semiconductor material is in the first amorphous state is greater than the first resistance across the first semiconductor material when a portion of the first semiconductor material is in the first crystalline state.
7. The PCD according to claim 6, wherein, The voltage pulse is a set pulse, which has a sufficiently high voltage amplitude to transform the first semiconductor material that has transitioned out of the first amorphous state.
8. The PCD according to claim 7, wherein, The set pulse has a sufficiently slow, gradual set pulse fall time, such that the first semiconductor crystalline layer is epitaxially grown from the interface to split the first semiconductor layer into a first semiconductor crystalline layer having an epitaxial thickness less than the thickness of the first semiconductor layer and a first amorphous residual layer having a remaining thickness.
9. The PCD according to claim 8, wherein, The epitaxial thickness is determined by the fall time of the set pulse.
10. The PCD of claim 1, further comprising a diffusion barrier layer at the interface between the first semiconductor layer and the second semiconductor layer.
11. A phase change device (PCD), comprising: A first semiconductor layer, the first semiconductor layer being made of a first semiconductor material and having a first semiconductor thickness, the first semiconductor layer further having a first interface surface and a first electrode surface, the first interface surface and the first electrode surface being on opposite sides of the first semiconductor layer, the first semiconductor material being split into a first semiconductor crystalline layer having an epitaxial thickness less than the first semiconductor thickness and a first amorphous residual layer having a remaining thickness. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness. The second semiconductor layer also has a second interface surface and a second electrode surface. The second interface surface and the second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical contact, physical contact and chemical contact with each other at the interface. The second semiconductor material is transformed between a second amorphous state and a second crystalline state under one or more second conditions. The first electrode is in physical and electrical contact with the surface of the first electrode of the first semiconductor layer. The second electrode is in physical and electrical contact with the surface of the second electrode in the second semiconductor layer. as well as The total resistance measured between the first electrode and the second electrode.
12. The PCD according to claim 11, wherein, The total resistance decreases as the epitaxial thickness increases.
13. The PCD according to claim 11, wherein the PCD can have multiple total resistance states by changing the epitaxial thickness.
14. The PCD according to claim 13, wherein, One of the multiple total resistance states is selected by a set voltage pulse.
15. The PCD according to claim 11, wherein, The first semiconductor material is germanium and the second semiconductor material is silicon.
16. A method for manufacturing a phase change device (PCD), comprising the following steps: Deposit the first electrode on the dielectric layer; A first semiconductor layer is deposited on the first electrode; Deposit a second semiconductor layer on the first semiconductor layer; Crystallize the first semiconductor layer and the second semiconductor layer; Amorphize the first semiconductor layer; as well as The first semiconductor layer is split into a first semiconductor crystalline layer and a first semiconductor amorphous layer using a set voltage pulse.
17. The method according to claim 16, wherein, Heating and cooling annealing crystallize the entire first semiconductor layer and the entire second semiconductor layer.
18. The method according to claim 16, wherein, The splitting of the first semiconductor layer is accomplished by heating the first semiconductor layer and allowing the first semiconductor layer to cool during a cooling time period, during which the first semiconductor crystal layer is epitaxially grown to an epitaxial thickness determined by the length of the cooling time period.
19. The method according to claim 18, wherein, The resistance state of the PCD is determined by the cooling time period determined by the set voltage pulse.