Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method for manufacturing the semiconductor structure comprising: providing an initial structure, the initial structure comprising a substrate, a stacked structure, and a capacitor unit, the stacked structure comprising a support layer; forming a first mask layer, the first mask layer covering the top surface of the stacked structure; forming a first opening in the first mask layer, the first opening exposing the top surface of the stacked structure, wherein the projection area of the first opening on the substrate at least partially overlaps with the projection area of the capacitor unit on the substrate; forming a shielding structure, the shielding structure being located in the first opening, the shielding structure covering the sidewalls of the first opening; removing part of the support layer according to a pattern defined by the shielding structure, the retained part of the support layer forming a support structure of the capacitor unit. In the present disclosure, only the part of the support layer covered by the shielding structure is retained as the support structure, thereby reducing the space occupied by the support structure in the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As the integration of dynamic random access memory (DRAM) increases, the size of storage nodes and plate area continue to decrease, but the demand for DRAM's charge storage capacity also increases.

[0003] To meet the current charge storage capacity of DRAM, DRAM height is constantly increasing. This increasing height makes DRAM more susceptible to tipping. To reduce the risk of DRAM tipping, a support layer is required in the upper and middle regions of the capacitor structure. However, as the thickness of the support layer increases, it takes up space in the capacitor structure, affecting its charge storage capacity. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0006] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0007] Providing an initial structure, the initial structure including a substrate and a stacked structure formed on the substrate, and a capacitor unit formed in the stacked structure, wherein the stacked structure includes a support layer;

[0008] forming a first mask layer, wherein the first mask layer covers a top surface of the stacked structure;

[0009] forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the stacked structure, wherein a projection area of the first opening on the substrate at least partially overlaps with a projection area of the capacitor unit on the substrate;

[0010] forming a shielding structure, wherein the shielding structure is located in the first opening and covers a sidewall of the first opening;

[0011] According to the pattern defined by the shielding structure, a portion of the support layer is removed, and the remaining portion of the support layer forms the support structure of the capacitor unit.

[0012] According to some embodiments of the present disclosure, forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the initial structure, includes:

[0013] forming a photoresist mask layer on the first mask layer, wherein the photoresist mask layer defines a first pattern;

[0014] According to the first pattern, the first mask layer is removed to expose the top surface of the stacked structure and form the first opening.

[0015] According to some embodiments of the present disclosure, a projection area of the first opening on the substrate partially overlaps with multiple projection areas of the multiple capacitor units on the substrate.

[0016] According to some embodiments of the present disclosure, a projection area of the first opening on the substrate covers multiple projection areas of the plurality of capacitor units on the substrate.

[0017] According to some embodiments of the present disclosure, forming a shielding structure includes:

[0018] A blocking material is deposited on the sidewall of the first opening along the thickness direction of the first mask layer to obtain the blocking structure.

[0019] According to some embodiments of the present disclosure, after forming the shielding structure and before removing part of the supporting layer, the method further includes:

[0020] The first mask layer is removed.

[0021] According to some embodiments of the present disclosure, providing the initial structure includes:

[0022] providing a substrate having a capacitor contact region formed therein;

[0023] Alternatingly forming dielectric layers and support layers on the substrate to form an initial stacked structure;

[0024] forming a second mask layer on the initial stacked structure, wherein a second pattern is defined on the second mask layer;

[0025] removing a portion of the initial stacked structure according to a second pattern to form a target hole, wherein the target hole exposes the capacitor contact area and forms the stacked structure;

[0026] The capacitor unit is formed in the target hole.

[0027] According to some embodiments of the present disclosure, forming the capacitor unit in the target hole includes:

[0028] An electrode material is provided, wherein the electrode material covers at least the bottom wall and the side walls of the target hole.

[0029] According to some embodiments of the present disclosure, forming the capacitor unit in the target hole includes:

[0030] An electrode material is provided, the electrode material filling the target pore.

[0031] According to some embodiments of the present disclosure, removing a portion of the support layer according to a pattern defined by the shielding structure, and forming a support structure with the remaining portion of the support layer, includes:

[0032] The dielectric layer and the support layer not blocked by the pattern defined by the blocking structure are removed in sequence to form the support structure.

[0033] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0034] a substrate having a capacitor contact region disposed therein;

[0035] a capacitor unit, the capacitor unit being disposed on the substrate and connected to the capacitor contact area;

[0036] A supporting structure is connected to a portion of the sidewall of the capacitor unit.

[0037] According to some embodiments of the present disclosure, a plurality of the support structures are arranged between the capacitor units, and the support structures are isolated from each other.

[0038] According to some embodiments of the present disclosure, the support structure is connected to side walls of at least two of the capacitor units.

[0039] According to some embodiments of the present disclosure, the projection pattern of the support structure on the substrate includes multiple arc-shaped structures with the same curvature.

[0040] According to some embodiments of the present disclosure, the capacitor unit is a cup-shaped structure or a columnar structure.

[0041] In the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, only the portion of the support layer covered by the shielding structure is retained as the support structure, thereby reducing the space occupied by the support structure in the semiconductor structure and increasing the available space in the semiconductor.

[0042] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0044] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0045] Figure 2 The present invention is a flow chart showing a method for manufacturing a semiconductor structure according to an exemplary embodiment, wherein a first opening is formed in a first mask layer.

[0046] Figure 3 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0047] Figure 4 The present invention is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0048] Figure 5 The diagram is a schematic diagram showing forming an initial stacked structure on a substrate in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0049] Figure 6 The diagram is a schematic diagram showing forming a second mask layer on an initial stacked structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0050] Figure 7 is a schematic diagram illustrating forming a target hole in an initial stacked structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0051] Figure 8 FIG. 1 is a schematic diagram illustrating deposition of electrode materials in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0052] Figure 9 The figure is a schematic diagram showing a method for manufacturing a bit line structure according to an exemplary embodiment of the present invention.

[0053] Figure 10 FIG. 1 is a schematic diagram illustrating deposition of electrode materials in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0054] Figure 11 The figure is a schematic diagram showing a method for manufacturing a bit line structure according to an exemplary embodiment of the present invention.

[0055] Figure 12 The diagram is a schematic diagram showing forming a photoresist mask layer on a first mask layer in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0056] Figure 13 The diagram is a schematic diagram showing the process of removing a first mask layer to form a first opening in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0057] Figure 14 1 is a projection diagram of a first opening on a top surface of an initial structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0058] Figure 15 FIG. 1 is a schematic diagram showing forming a second initial dielectric unit in the BL direction in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0059] Figure 16 FIG. 1 is a schematic diagram showing forming a second initial dielectric unit in the BL direction in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0060] Figure 17 FIG. 1 is a schematic diagram illustrating forming a shielding structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0061] Figure 18 The figure is a projection diagram of a shielding structure on a top surface of an initial structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0062] Figure 19 It is a schematic diagram showing the removal of the second supporting layer according to the shielding structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0063] Figure 20 yes Figure 19 Top view of .

[0064] Figure 21 The figure is a schematic diagram showing the removal of the second dielectric layer in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0065] Figure 22 It is a schematic diagram showing the removal of a first supporting layer according to a shielding structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0066] Figure 23 The figure is a schematic diagram showing the removal of the first dielectric layer in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0067] Figure 24 yes Figure 23 Top view of .

[0068] Figure 25 FIG1 is a projection diagram of a first opening on a top surface of an initial structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0069] Figure 26 The figure is a projection diagram of a shielding structure on a top surface of an initial structure in a method for manufacturing a bit line structure according to an exemplary embodiment.

[0070] Figure 27 is based on Figure 26 A top view of a semiconductor structure formed by a blocking structure is shown.

[0071] Figure 28 FIG. 1 is a schematic diagram of an initial structure provided in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0072] Figure 29 1 is a schematic diagram of forming a mask layer on an initial structure in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0073] Figure 30 The diagram is a schematic diagram showing a method for manufacturing a bit line structure according to an exemplary comparative example, in which an upper supporting layer is removed by etching through a mask layer to form a first opening on the upper supporting layer.

[0074] Figure 31 Schematic diagram of removing an upper dielectric layer in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0075] Figure 32 1 is a schematic diagram of etching back an upper support layer in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0076] Figure 33 It is a schematic diagram of removing a lower supporting layer by etching a mask layer in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0077] Figure 34 Schematic diagram of removing a lower dielectric layer in a method for manufacturing a bit line structure according to an exemplary comparative example.

[0078] Figure 35 yes Figure 34 Top view of .

[0079] Reference numerals:

[0080] 10. First mask layer; 11. First opening; 12. Second opening;

[0081] 20. Shielding structure; 21. Shielding material layer;

[0082] 30. Photoresist mask layer; 31. First pattern;

[0083] 40. Second mask layer; 41. Second pattern;

[0084] 100, initial structure; 110, substrate; 111, capacitor contact area; 120, dielectric layer; 121, first dielectric layer; 122, second dielectric layer; 130, support layer; 131, first support layer; 132, second support layer; 150, capacitor unit; 160, target hole; 170, support structure; 171, support unit;

[0085] 200, laminated structure; 210, initial laminated structure;

[0086] 500. Electrode materials;

[0087] 10', mask layer; 11', first pattern; 12', first opening;

[0088] 100', initial structure; 110', substrate; 120', dielectric layer; 130', support layer; 150', capacitor unit; 170', support structure;

[0089] 200', laminated structure. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0091] Currently, if Figure 28 As shown, the method for fabricating a semiconductor structure includes the following steps: providing an initial structure 100', the initial structure 100' including a substrate 110', a stacked structure 200' formed on the substrate, and a capacitor unit 150' formed in the stacked structure 200'. The stacked structure 200' includes dielectric layers 120' and support layers 130' alternately stacked on the substrate 110'.

[0092] like Figure 29 As shown, a mask layer 10 ′ is formed on the top surface of the initial structure 100 ′, and a first pattern 11 ′ is defined on the mask layer 10 ′. The first pattern 11 ′ at least exposes a portion of the top surface of the capacitor unit 150 ′.

[0093] like Figure 30 As shown, refer to Figure 31 According to the first pattern 11', the support layer 130' corresponding to the first pattern 11' is removed by dry etching or wet etching to form a first opening 12' on the support layer 130'. The first opening 12' exposes the dielectric layer 120'.

[0094] like Figure 31 As shown, acid solution is injected into the first opening 12 ′, and the entire dielectric layer 120 ′ is removed using a wet etching technique.

[0095] like Figure 32 As shown, the upper support layer 130' is etched back.

[0096] Reference Figures 30 to 34 When the initial structure 100' has multiple supporting layers 130' and multiple dielectric layers 120', the upper supporting layer 130' and the upper dielectric layer 120' are removed, and the above steps are repeated to remove the lower supporting layer 130' corresponding to the first pattern 11', and all the lower dielectric layers 120' are removed until the substrate 110' is exposed to form a semiconductor structure. The retained supporting layer 130' serves as the supporting structure 170'.

[0097] In the related art, a semiconductor structure is formed, such as Figure 35 As shown, the support structure 170 ′ is connected to the sidewall portions of all capacitor units 150 ′, and the support structure 170 ′ occupies a larger space in the upper layer of the semiconductor structure.

[0098] To this end, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, such as Figure 1 As shown, Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figure 9-Figure 24 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 9-Figure 24 The fabrication method of semiconductor structures is introduced.

[0099] In this embodiment, a method for manufacturing a semiconductor structure includes:

[0100] S110: Providing an initial structure.

[0101] The initial structure includes a substrate and a stacked structure formed on the substrate, and a capacitor unit formed in the stacked structure, wherein the stacked structure includes a support layer.

[0102] like Figure 9 or Figure 11As shown, the initial structure 100 may include a plurality of independently arranged capacitor units 150, wherein the plurality of capacitor units 150 are arranged in the stacked structure 200 and separated by the stacked structure 200, the capacitor unit 150 is electrically connected to the capacitor contact area 111 in the substrate 110, and the top surface of the capacitor unit 150 is flush with the top surface of the stacked structure 200.

[0103] like Figure 9 As shown in FIG11 , the stacked structure 200 includes alternately arranged dielectric layers 120 and support layers 130 . The specific stacking number and stacking height of the dielectric layers 120 and support layers 130 in the stacked structure are set according to the height of the capacitor unit 150 .

[0104] The dielectric layer 120 is made of silicon oxide or BPSG (Boro-phospho-silicate Glass), and the dielectric layer 120 may be doped with boron or phosphorus.

[0105] The material of the support layer 130 includes any one of silicon nitride, silicon oxynitride, and silicon carbonitride, or a combination of any two or more thereof.

[0106] S120: forming a first mask layer, where the first mask layer covers the top surface of the stacked structure.

[0107] like Figure 12 As shown, the first mask layer 10 can be a single-layer or double-layer structure, and the material of the first mask layer 10 can be polysilicon, silicon nitride, silicon oxide, etc. In this embodiment, when the first mask layer 10 is a single-layer structure, the material of the first mask layer 10 is polysilicon; when the first mask layer 10 is a double-layer structure, the bottom layer material of the first mask layer 10 is polysilicon and the top layer material is silicon nitride.

[0108] S130: forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the stacked structure, wherein a projection area of the first opening on the substrate at least partially overlaps with a projection area of the capacitor unit on the substrate.

[0109] like Figure 13 、 14 As shown, the first opening 11 is defined based on the number and position distribution of the capacitor units 150 in the initial structure 100. For example, two capacitor units 150, three capacitor units 150, four capacitor units 150, or five capacitor units 150 can be arranged as a group to define the first opening 11, and the projection area of the first opening 11 on the substrate 110 at least partially overlaps with the projection area of each capacitor unit 150 in the group on the substrate 110.

[0110] S140: forming a shielding structure, where the shielding structure is located in the first opening and covers a sidewall of the first opening.

[0111] like Figure 16 As shown, a shielding structure 20 can be deposited on the sidewalls of the first opening 11 to cover the sidewalls of the first opening 11. The shielding structure 20 and the exposed bottom wall of the first opening 11 form the second opening 12. The shielding structure 20 can be made of silicon dioxide. In other embodiments, the shielding structure 20 can be made of any other suitable material.

[0112] S150: removing a portion of the support layer according to the pattern defined by the shielding structure, and the remaining portion of the support layer forms a support structure of the capacitor unit.

[0113] like Figure 23 As shown, refer to Figure 16 、 Figure 17 、 Figure 19 、 Figure 21 、 Figure 22 , dry or wet etching can be used to remove the support layer 130 exposed by the second opening 12 and all the support layer 130 blocked by the first mask layer 10, leaving only the portion of the support layer 130 blocked by the blocking structure 20 as the support structure 170 of the capacitor unit 150 (refer to Figure 24 ).

[0114] The semiconductor structure formed in this embodiment retains only a portion of the support layer covered by the shielding structure as the support structure, reducing the space occupied by the support structure in the semiconductor structure and increasing the available space in the semiconductor without increasing the size of the semiconductor.

[0115] According to an exemplary embodiment, this embodiment is an explanation of the implementation of step S130 of the above embodiment. Figure 2 As shown, Figure 2 A flow chart of step S130 in the semiconductor manufacturing method provided according to this embodiment is shown.

[0116] forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the initial structure, comprising:

[0117] S131: forming a photoresist mask layer on the first mask layer, wherein the photoresist mask layer defines a first pattern.

[0118] like Figure 12 As shown, a first pattern 31 is defined on the photoresist mask layer 30 based on the number and positional distribution of capacitor units 150 in the initial structure. When defining the first pattern 31, two capacitor units 150, three capacitor units 150, four capacitor units 150, or five capacitor units 150 can be used as a group of capacitor units 150. The projection of the first pattern 31 on the top surface of the initial structure 100 covers at least a portion of the top surface of each capacitor unit 150 in each group of capacitor units 150.

[0119] S132: removing the first mask layer according to the first pattern to expose the top surface of the stacked structure and form a first opening.

[0120] like Figure 13 As shown, refer to Figure 12 Based on the first pattern 31, the first mask layer 10 can be etched using dry or wet etching, stopping at exposing the top surface of the initial structure 100 to form a first opening 11. The first opening 11 transfers the first pattern 31 to the top surface of the initial structure 100, exposing at least a portion of the top of each capacitor unit 150 in each group of capacitor units 150 and a portion of the top surface of the stacked structure 200.

[0121] In some embodiments of the present disclosure, Figure 14 As shown, refer to Figure 24 , the projection area of the first opening 11 on the substrate 110 and the multiple projection areas of the multiple capacitor units 150 on the substrate 110 partially overlap. Two, three, four or five capacitor units 150 can be grouped together, so that the support structure 170 formed according to the first opening 11 connects each group of capacitor units into a whole, and the support structure 170 includes a plurality of support units 171 (equal to the number of capacitor units in each group of capacitor units), and each support unit 171 connects two adjacent capacitor units 150. Among them, the overlapping areas of the projection area of the first opening 11 on the substrate 110 and the projection area of each capacitor unit 150 in a group of capacitor units on the substrate 110 are equal, and the support force provided by the support structure 170 to each capacitor unit 150 is equal, so that the multiple capacitor units 150 connected by the support structure 170 have better anti-tilting properties.

[0122] like Figure 14 As shown, refer to Figure 24 The projection area of the first opening 11 on the substrate 110 is circular. The support structure 170 formed by the shielding structure 20 includes multiple arc-shaped support units 171. The arc-shaped structure has better impact resistance. The projection of the first opening 11 on the substrate 110 can also be an ellipse or other shape.

[0123] like Figure 14 As shown, refer to Figure 24, with three capacitor units 150 forming a group, the line connecting the center points of the three capacitor units 150 in each group forms an equilateral triangle, and this equilateral triangle is an inscribed triangle of the circle formed by the projection of the first opening 11 on the substrate 110. The projection area of the first opening 11 on the substrate 110 and the projection areas of the three capacitor units 150 on the substrate 110 all have a portion of the same area overlapping. The support structure 170 formed in this embodiment includes three equal arc-shaped support units 171. The three capacitor units 150 are connected into a whole by the three support units 171, which supports the capacitor units 150 and can prevent the capacitor units 150 from tipping over.

[0124] In other embodiments of the present disclosure, the projection area of the first opening 11 on the substrate 110 covers multiple projection areas of the multiple capacitor units 150 on the substrate.

[0125] like Figure 25 As shown, two, three, four or five capacitor units 150 are grouped together, and the projection area of the first opening 11 on the substrate 110 covers the entire projection area of the multiple capacitor units 150 in each group of capacitor units on the substrate 110 .

[0126] like Figure 26 As shown, a blocking structure 20 is formed on the side wall of the first opening 11, and the blocking structure 20 and the exposed bottom wall of the first opening 11 form a second opening 12, and the projection area of the second opening 12 on the substrate 110 partially overlaps with the multiple projection areas of the multiple capacitor units 150 of each group of capacitor units on the substrate 110. Among them, the projection area of the second opening 12 on the substrate 110 and the multiple projection areas of the multiple capacitor units 150 of each group of capacitor units on the substrate 110 partially overlap. The projection area of the second opening 12 on the substrate 110 may partially cover the multiple projection areas of the multiple capacitor units 150 on the substrate 110; or the edge of the projection area of the second opening 12 on the substrate 110 and the edge of the multiple projection areas of the multiple capacitor units 150 on the substrate 110 overlap; or the multiple projection areas of the multiple capacitor units 150 on the substrate 110 are inscribed figures of the projection area of the second opening 12 on the substrate 110, so as to ensure that the formed support structure 170 surrounds the multiple capacitor units 150 and is locally connected to the side wall of each capacitor unit 150, connecting the multiple capacitor units 150 into a whole.

[0127] like Figure 27 As shown, the support structure 170 formed according to the shielding structure 20 is partially connected to the side walls of multiple capacitor units 150 in a group. The support structure 170 can connect a group of capacitor units 150 into a whole. The support structure 170 supports the capacitor units 150 to prevent the capacitor units 150 from tipping over.

[0128] According to an exemplary embodiment, this embodiment is an explanation of the implementation of step S140 of the above embodiment. The method for forming a blocking junction in step S140 of the semiconductor fabrication method provided in this embodiment includes: depositing a blocking material on the sidewalls of the first opening along the thickness direction of the first mask layer to obtain a blocking structure.

[0129] like Figure 15 、 16 As shown, refer to Figure 13 , an atomic layer deposition (ALD) process can be used to deposit a blocking material layer 21, the blocking material layer 21 covers the side walls, bottom walls, and top surface of the first mask layer 10 of the first opening 11, and the blocking material layer 21 on the bottom wall of the first opening 11 and the blocking material layer 21 on the top surface of the first mask layer 10 are removed by dry or wet etching, leaving the blocking material layer 21 covering the side walls of the first opening 11 as a blocking structure.

[0130] The blocking structure 20 formed in this embodiment blocks part of the top surface of the initial structure 100. The part blocked by the blocking structure 20 is the top surface of the capacitor structure, and the other part is the top surface of the stacked structure 200, so that the support structure 170 formed according to the blocking structure 20 is connected to the side wall of the capacitor structure 150 and is sufficient to support the capacitor structure 150.

[0131] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 3 As shown, Figure 3 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown.

[0132] In this embodiment, a method for manufacturing a semiconductor structure includes:

[0133] S210: Providing an initial structure.

[0134] The initial structure includes a substrate and a stacked structure formed on the substrate, and a capacitor unit formed in the stacked structure, wherein the stacked structure includes a support layer.

[0135] S220: forming a first mask layer, where the first mask layer covers a top surface of the stacked structure.

[0136] S230: forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the stacked structure, wherein a projection area of the first opening on the substrate at least partially overlaps with a projection area of the capacitor unit on the substrate.

[0137] S240: forming a shielding structure, where the shielding structure is located in the first opening and covers a sidewall of the first opening.

[0138] S250: removing the first mask layer.

[0139] S260: removing a portion of the support layer according to a pattern defined by the shielding structure, and the remaining portion of the support layer forms a support structure of the capacitor unit.

[0140] like Figure 17 As shown, refer to Figure 18 The first mask layer 10 can be removed by dry or wet etching. The first mask layer 10 and the blocking structure 20 are made of different materials. When the first mask layer is removed by etching, the blocking structure 20 is retained.

[0141] The first mask layer 10 is removed to expose the top surface of the initial structure 100 blocked by the first mask layer 10, so that the support layer 130 originally blocked by the first mask layer 10 is completely removed, and only the part of the support layer 130 blocked by the blocking structure 20 is retained as the support structure 170, thereby reducing the space occupied by the support structure 170.

[0142] According to an exemplary embodiment, this embodiment is an explanation of the implementation of step S210 in the above embodiment. Figure 3 As shown, Figure 3 A flowchart illustrating an implementation of step S210 in the semiconductor manufacturing method provided in this embodiment is shown.

[0143] Providing an initial structure includes:

[0144] S211: providing a substrate, wherein a capacitor contact region is formed in the substrate.

[0145] Reference Figure 5 The substrate 110 is a semiconductor substrate including a silicon-containing material. The substrate 110 may include a silicon substrate, a silicon-germanium substrate, or an SOI (silicon on insulator) substrate. The capacitor contact region 111 is disposed in the substrate 110 .

[0146] S212: alternately forming dielectric layers and support layers on the substrate to form an initial stacked structure.

[0147] like Figure 5 As shown, the dielectric layer 120 can be deposited on the substrate by using an atomic layer deposition process (ALD). The support layer 130 can be deposited on the substrate by using an atomic layer deposition process (ALD).

[0148] According to the height of the capacitor unit to be formed, the steps of depositing a dielectric layer and depositing a support layer are repeated on the substrate to form an initial stacked structure 210 . The top layer of the initial stacked structure 210 may be the support layer 130 or the dielectric layer 120 .

[0149] S213: forming a second mask layer on the initial stacked structure, and defining a second pattern on the second mask layer.

[0150] like Figure 6 As shown, a second mask layer 40 is formed on the initial stacked structure 210 , and the second mask layer 40 defines a second pattern 41 . The second pattern 41 is arranged corresponding to the position of the capacitor contact area 111 of the substrate 110 , and the second pattern 41 exposes part of the top surface of the initial stacked structure 210 .

[0151] S214: removing a portion of the initial stacked structure according to the second pattern to form a target hole, wherein the target hole exposes the capacitor contact area and forms a stacked structure.

[0152] like Figure 7 As shown, refer to Figure 6 , the portion of the initial stacked structure 210 corresponding to the second pattern 41 is etched away according to the second mask layer 40 to expose the capacitor contact area 111 , and the etching is stopped to form the target hole 160 , and the retained initial stacked structure 210 is used as the stacked structure 200 .

[0153] S215: forming a capacitor unit in the target hole.

[0154] like Figure 9 or Figure 11 As shown, an atomic layer deposition (ALD) process can be used to deposit a capacitor unit 150 in the target hole 160 . The capacitor unit 150 is connected to the capacitor contact region 111 , and the top surface of the capacitor unit 150 is flush with the top surface of the stacked structure 200 .

[0155] In this embodiment, a plurality of capacitor contact areas 111 are provided in the substrate 110, and the plurality of capacitor contact areas 111 are uniformly arranged in an array in the substrate 110. The capacitor units 150 formed according to the plurality of capacitor contact areas 111 are uniformly arranged in an array, so as to simplify the formation process of the support structure 170.

[0156] According to some embodiments of the present disclosure, forming a capacitor unit in a target hole includes: providing an electrode material, where the electrode material at least covers a bottom wall and side walls of the target hole.

[0157] like Figure 8 As shown, refer to Figure 7First, an atomic layer deposition (ALD) process can be used to deposit the electrode material 500, and the electrode material 500 covers the bottom wall, sidewalls of the target hole 160, and the top surface of the stacked structure 200. Figure 9 As shown, a dry etching process is then used to remove the electrode material 500 located on the top surface of the stacked structure 200, leaving the electrode material 500 located on the sidewalls and bottom of the target hole 160 as the capacitor unit 150. The electrode material 500 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), etc.

[0158] According to other embodiments of the present disclosure, forming a capacitor unit in a target hole includes: providing an electrode material, wherein the electrode material fills the target hole.

[0159] like Figure 10 As shown, refer to Figure 7 , an atomic layer deposition process (ALD) can be used to deposit the electrode material 500, and the electrode material 500 fills the target hole 160 and covers the top surface of the stacked structure 200. Figure 11 As shown, the electrode material 500 on the top surface of the stacked structure 200 is removed by a dry etching process, and the electrode material 500 in the target hole 160 is retained as the capacitor unit 150 .

[0160] In the initial structure 100 provided in this embodiment, the capacitor unit 150 can be a cup-shaped structure covering the side wall of the target hole 160, or a columnar structure filling the target hole 160. Capacitor units 150 of different shapes can be connected and supported by the support structure 170 to increase the available space in the semiconductor structure.

[0161] According to an exemplary embodiment, this embodiment is an explanation of the implementation of step S260 of the above embodiment. In the semiconductor manufacturing method provided in this embodiment, step S260 removes a portion of the support layer according to the pattern defined by the blocking structure, and the remaining portion of the support layer forms the support structure, including: sequentially removing the dielectric layer and the portion of the support layer not blocked by the pattern defined by the blocking structure to form the support structure.

[0162] like Figure 24 As shown, refer to Figure 16In this embodiment, only the portion of the support layer 130 blocked by the blocking structure 20 is retained, and the opening formed on the stacked structure 200 is larger, so that the subsequent process operation of removing the stacked structure 200 and the operation opening for depositing dielectric materials or electrode materials in the semiconductor structure are increased.

[0163] In this embodiment, if Figure 17 As shown, the stacked structure 200 includes a first dielectric layer 121 , a first supporting layer 131 , a second dielectric layer 122 and a second supporting layer 132 , which are sequentially arranged in a direction away from the substrate 110 .

[0164] like Figure 19 、 20 As shown, refer to Figure 17 、 18 First, the second supporting layer 132 not blocked by the blocking structure 20 is removed by dry or wet etching to expose the second dielectric layer 122. Figure 21 As shown, the entire second dielectric layer 122 is removed by acid etching, as shown in FIG. Figure 22 As shown, the first supporting layer 131 is exposed, and the first supporting layer 131 not blocked by the blocking structure 20 is removed by dry or wet etching. Figure 23 As shown, the first dielectric layer 121 is exposed, and the entire first dielectric layer 121 is removed by etching with an acid solution, and the retained first supporting layer 131 and the second supporting layer 132 serve together as a supporting structure 170 .

[0165] In this embodiment, when the second supporting layer 132 is removed, only the portion of the second supporting layer 132 shielded by the shielding structure 20 is retained. Therefore, the exposed area of the second dielectric layer 122 is larger, and the operating opening for the process operation is increased when removing the second dielectric layer. Similarly, the process of removing the first supporting layer 131 and the first dielectric layer 121 is also more convenient.

[0166] An exemplary embodiment of the present disclosure provides a semiconductor structure, such as Figure 23 、 24 As shown, the present invention includes: a substrate 110, a capacitor unit 150 disposed on the substrate 110, and a support structure 170 connected to a portion of the sidewall of the capacitor unit 150. A capacitor contact area 111 is provided in the substrate 110, and the capacitor unit 150 is connected to the capacitor contact area 111. The capacitor unit 150 can be a cup-shaped structure or a columnar structure.

[0167] like Figure 24 As shown, the support structure 170 is connected to part of the side walls of part of the capacitor unit 150 to connect part of the capacitor unit 150 into a whole, thereby increasing the anti-tilting ability of the capacitor unit 150, reducing the space occupied by the support structure 170 in the semiconductor structure, and increasing the available space in the semiconductor.

[0168] According to an exemplary embodiment, most of the contents of this embodiment are the same as those of the above embodiment. The difference between this embodiment and the above embodiment is that, Figure 24 As shown, a plurality of support structures 170 are disposed between the capacitor units 150 , and the support structures 170 are isolated from each other.

[0169] In this embodiment, Figure 24 As shown, a plurality of capacitor contact areas 111 can be set in the substrate 110, and a plurality of capacitor units 150 are respectively set at the positions of the plurality of capacitor contact areas 111. One or several capacitor units 150 form a group, and each group of capacitor units 150 is connected into a whole through a support structure 170, so that each capacitor unit 150 can be connected to the support structure 170, and the capacitor unit 150 in the semiconductor structure is more stable and has better anti-tilting performance.

[0170] According to an exemplary embodiment, most of the contents of this embodiment are the same as those of the above embodiment. The difference between this embodiment and the above embodiment is that, Figure 24 As shown, the support structure 170 is connected to at least the side walls of two capacitor units 150 .

[0171] The more capacitor units 150 connected to a support structure 170, the smaller the space occupied by the support unit 170 in the semiconductor structure, but the overall anti-tilting performance of the multiple capacitor units 150 connected to the support structure 170 will be reduced. Figure 24 As shown, a support structure 170 connects three capacitor units, and the line connecting the center points of the three capacitor units 150 is a triangle. The overall structure at the connection point of the three capacitor units 150 has better anti-tilting performance and higher stability.

[0172] According to an exemplary embodiment, most of the contents of this embodiment are the same as those of the above embodiment. The difference between this embodiment and the above embodiment is that, Figure 24 As shown, the projection pattern of the support structure 170 on the substrate includes multiple arc-shaped structures with the same curvature.

[0173] The support structure 170 includes multiple arc-shaped support units 171, and the projections of the multiple support units 171 on the substrate are located on the same circle, wherein each support unit 171 is connected to the side walls of two capacitor units 150. In this embodiment, Figure 24As shown, a support structure 170 connects three capacitor units 150. Support structure 170 includes three support units 171 of equal curvature. The three support units 171 sequentially connect the three capacitor units 150 to form a single unit. The line connecting the center points of the three capacitor units 150 forms an inscribed triangle within the circle containing the projections of the multiple support units 170 on substrate 110. The semiconductor structure of this embodiment has the best anti-tilting properties for the capacitor units 150, the highest overall stability, and the best semiconductor structure stability.

[0174] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0175] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0176] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0177] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0178] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0179] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing an initial structure, the initial structure including a substrate and a stacked structure formed on the substrate, and a capacitor unit formed in the stacked structure, wherein the stacked structure includes a support layer; forming a first mask layer, wherein the first mask layer covers a top surface of the stacked structure; forming a first opening in the first mask layer, wherein the first opening exposes a top surface of the stacked structure, wherein a projection area of the first opening on the substrate at least partially overlaps with a projection area of the capacitor unit on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening and covers a sidewall of the first opening; According to the pattern defined by the shielding structure, a portion of the support layer is removed, and the remaining portion of the support layer forms the support structure of the capacitor unit.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the initial structure, comprises: forming a photoresist mask layer on the first mask layer, wherein the photoresist mask layer defines a first pattern; According to the first pattern, the first mask layer is removed to expose the top surface of the stacked structure and form the first opening.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: A projection area of the first opening on the substrate partially overlaps with multiple projection areas of the multiple capacitor units on the substrate.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: A projection area of the first opening on the substrate covers multiple projection areas of the capacitor units on the substrate.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the shielding structure includes: A blocking material is deposited on the sidewall of the first opening along the thickness direction of the first mask layer to obtain the blocking structure.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the shielding structure and before removing part of the support layer, the method further includes: The first mask layer is removed.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, wherein: Providing the initial structure includes: providing a substrate having a capacitor contact region formed therein; Alternatingly forming dielectric layers and support layers on the substrate to form an initial stacked structure; forming a second mask layer on the initial stacked structure, wherein a second pattern is defined on the second mask layer; removing a portion of the initial stacked structure according to a second pattern to form a target hole, wherein the target hole exposes the capacitor contact area and forms the stacked structure; The capacitor unit is formed in the target hole.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: Forming the capacitor unit in the target hole includes: An electrode material is provided, wherein the electrode material covers at least the bottom wall and the side walls of the target hole.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: Forming the capacitor unit in the target hole includes: An electrode material is provided, the electrode material filling the target pore.

10. The method for manufacturing a semiconductor structure according to claim 7, wherein: The step of removing a portion of the support layer according to a pattern defined by the shielding structure and forming a support structure with the remaining portion of the support layer comprises: The dielectric layer and the support layer not blocked by the pattern defined by the blocking structure are removed in sequence to form the support structure.

11. A semiconductor structure manufactured according to the method of any one of claims 1 to 10, characterized in that: include: a substrate having a capacitor contact region disposed therein; a capacitor unit, the capacitor unit being disposed on the substrate and connected to the capacitor contact area; A supporting structure is connected to a portion of the sidewall of the capacitor unit.

12. The semiconductor structure according to claim 11, wherein: A plurality of the support structures are arranged between the capacitor units, and the support structures are isolated from each other.

13. The semiconductor structure according to claim 12, wherein: The supporting structure is connected to at least two side walls of the capacitor units.

14. The semiconductor structure according to claim 13, wherein: The projection pattern of the support structure on the substrate includes a plurality of arc-shaped structures with the same curvature.

15. The semiconductor structure according to claim 11, wherein: The capacitor unit is a cup-shaped structure or a columnar structure.

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