Semiconductor structure and method for forming the same

Abstract

An embodiment of the present application provides a semiconductor structure and a method for forming the same. The method comprises: providing a substrate structure comprising at least a bitline structure and a plurality of landing pads formed around and partially covering the bitline structure; wherein a gap exists between two adjacent landing pads; and forming a capacitor structure on the top surface of the landing pads and in the gap. This invention enables the fabrication of a semiconductor structure with a large charge capacity.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. DRAM consists of many repetitive memory cells. Each memory cell contains a transistor and a capacitor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. A voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] With the continuous advancement of semiconductor integrated circuit device technology and the gradual reduction of line widths, increasing the charge capacity of capacitors and reducing leakage are particularly important for DRAM. However, in the DRAM manufacturing process, simply increasing the height of capacitors greatly increases the difficulty of capacitor etching, which in turn increases the difficulty of semiconductor device manufacturing. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate structure, the substrate structure comprising at least a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein a gap is provided between two adjacent landing pads;

[0007] A capacitor structure is formed on a top surface of the landing pad and in the void.

[0008] In some embodiments, forming a capacitor structure on the top surface of the landing pad and in the gap includes:

[0009] forming a first insulating layer in the gap, wherein the first insulating layer is flush with a surface of the landing pad;

[0010] forming a stacked structure on surfaces of the landing pad and the first insulating layer;

[0011] The stacked structure and the first insulating layer are processed to form the capacitor structure.

[0012] In some embodiments, the stacked structure includes a sacrificial layer and a supporting layer; and processing the stacked structure and the first insulating layer to form the capacitor structure includes:

[0013] patterning the stacked structure to form a capacitor hole in the stacked structure on the landing pad surface;

[0014] forming a first electrode layer on the inner wall of each capacitor hole and on the surface of the patterned stacked structure;

[0015] Patterning the support layer to form openings between adjacent capacitor holes;

[0016] etching the sacrificial layer and the first insulating layer through the opening;

[0017] The capacitor structure is formed in the patterned support layer.

[0018] In some embodiments, forming the capacitor structure in the patterned support layer includes:

[0019] Depositing a dielectric layer and a second electrode layer in sequence on the surface of the first electrode layer;

[0020] Depositing a conductive material, the conductive material fills the gaps between the second electrode layers and covers the upper surface of the stacked structure; wherein the first electrode layer, the dielectric layer, the second electrode layer and the conductive material constitute the capacitor structure.

[0021] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer, and the supporting layer includes a first supporting layer and a second supporting layer;

[0022] The method further includes: forming a first mask layer on a surface of the second supporting layer;

[0023] The step of patterning the stacked structure to form a capacitor hole in the stacked structure on the surface of the landing pad comprises:

[0024] patterning the first mask layer;

[0025] Using the patterned first mask layer as a mask, the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surface of each landing pad are etched to form a plurality of capacitor holes.

[0026] In some embodiments, the patterned stacked structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer, and the second supporting layer stacked in sequence, and the first mask layer and the first electrode layer are formed on the surface of the patterned stacked structure;

[0027] The step of patterning the support layer to form openings between adjacent capacitor holes and etching the sacrificial layer and the first insulating layer through the openings includes:

[0028] forming a first opening in the first mask layer and the second supporting layer;

[0029] removing the second sacrificial layer through the first opening;

[0030] forming a second opening in the first supporting layer;

[0031] The first sacrificial layer and the first insulating layer are removed through the second opening.

[0032] In some embodiments, the first opening and the second opening are formed by dry etching technology.

[0033] In some embodiments, a first spacer, a second spacer, and a sacrificial spacer located between the first spacer and the second spacer are formed on the sidewalls of each of the bit line structures, and the first insulating layer is connected to the sacrificial spacer. The method further includes:

[0034] removing the sacrificial spacer layer when removing the first sacrificial layer and the first insulating layer through the second opening;

[0035] The first sacrificial layer and the sacrificial spacer layer are formed of the same material.

[0036] In some embodiments, the second sacrificial layer, the first sacrificial layer, the first insulating layer, and the first spacer layer are removed by wet etching technology.

[0037] In some embodiments, the base structure further includes a storage node contact formed around the bit line structure and contacting each of the landing pads; the landing pads and the gaps are formed by the following steps:

[0038] forming a conductive layer covering the bit line structure on a surface contacted by each storage node; wherein a top surface of the conductive layer exceeds a top surface of the bit line structure;

[0039] forming a patterned second mask layer on the surface of the conductive layer;

[0040] The conductive layer and the first spacer layer are partially etched through the patterned second mask layer until the sacrificial spacer layer is exposed, thereby forming the landing pad located on the contact surface of each storage node and the gap located between two adjacent landing pads; wherein the cross-section of the gap along the first direction is stepped, and the first direction is perpendicular to the extension direction of the bit line structure and the arrangement direction of the bit line structure.

[0041] In some embodiments, the bit line structure includes a bit line contact layer, a bit line metal layer, and a bit line mask layer stacked sequentially from bottom to top along the first direction; the method further includes:

[0042] forming a second insulating layer between two adjacent landing pads, wherein the second insulating layer is flush with surfaces of the landing pads;

[0043] The second insulating layer and a portion of the bit line mask layer are etched to form the gap, wherein a cross section of the gap along the first direction is U-shaped.

[0044] In a second aspect, an embodiment of the present application provides a semiconductor structure, including:

[0045] A substrate structure comprising at least a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein a gap is formed between two adjacent landing pads;

[0046] A capacitor structure is located on the top surface of the landing pad and in the gap.

[0047] In some embodiments, a cross-section of the gap along a first direction is stepped, the first direction being perpendicular to an extension direction of the bit line structure and an arrangement direction of the bit line structure; the bit line structure comprises a bit line contact layer, a bit line metal layer, and a bit line mask layer stacked sequentially from bottom to top along the first direction; or,

[0048] The cross section of the gap along the first direction is U-shaped, and the bit line structure includes the bit line contact layer, the bit line metal layer, and a portion of the bit line mask layer stacked sequentially from bottom to top along the first direction.

[0049] In some embodiments, the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence, and conductive material is filled between adjacent second electrode layers.

[0050] In some embodiments, the capacitor structure is a cup-shaped structure, and the extension direction of the capacitor structure is perpendicular to the top surface of the landing pad; the capacitor structure further includes a first supporting layer and a second supporting layer arranged in parallel;

[0051] The first supporting layer is arranged on the middle periphery of the capacitor structure, and the second supporting layer is arranged on the top periphery of the capacitor structure. The first supporting layer and the second supporting layer are used together to support the capacitor structure.

[0052] In some embodiments, the thickness of the second supporting layer is greater than the thickness of the first supporting layer.

[0053] In some embodiments, a first spacer layer, a second spacer layer, and an air gap between the first spacer layer and the second spacer layer are formed on the sidewall of the bit line structure; wherein the air gap is connected to the dielectric layer.

[0054] Embodiments of the present application provide a semiconductor structure and a method for forming the same. The method includes providing a substrate structure comprising at least a bitline structure and a plurality of landing pads formed around and partially covering the bitline structure. A gap is defined between adjacent landing pads, and a capacitor structure is formed on the top surface of the landing pads and within the gap. Because the capacitor structure in the embodiments of the present application can be formed in the gap between adjacent landing pads, a semiconductor structure with a relatively large charge capacity can be fabricated. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0056] Figure 1 An optional flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application;

[0057] Figures 2a to 2k A schematic diagram of a semiconductor structure formation process according to an embodiment of the present application;

[0058] Figures 3a to 3i Another structural schematic diagram of a semiconductor structure formation process provided in an embodiment of the present application;

[0059] Figure 4a A schematic diagram of an optional structure of a semiconductor structure provided in an embodiment of the present application;

[0060] Figure 4b A schematic diagram of another optional structure of the semiconductor structure provided in an embodiment of the present application; Description of the drawings:

[0062] 101-semiconductor substrate; 1011-active region; 1012-shallow trench isolation structure; 102-bit line structure; 1021-bit line contact layer; 1022-bit line metal layer; 1023-bit line mask layer; 102a-sacrificial spacer layer; 102b-second spacer layer; 103a-conductive layer; 103-landing pad; 104-storage node contact; 105-second mask layer; 106 / 302-first insulating layer; 106a-initial insulating layer; 106b-second insulating layer; 106c-second insulating layer; 106d-second insulating layer; 106e-second insulating layer; 106f ... 07-stacked structure; 1071-first sacrificial layer; 1072-first supporting layer; 1073-second sacrificial layer; 1074-second supporting layer; 108-first mask layer; 109-capacitor hole; 110-first electrode layer; 111a-first opening; 111b-second opening; 112-dielectric layer; 113-second electrode layer; 114-conductive material; 301-second insulating layer; 401-capacitor structure; V1 / V2-gap; G-air gap. DETAILED DESCRIPTION

[0063] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0064] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0065] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0066] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0067] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0068] Increasing semiconductor process integration and reducing component size are becoming increasingly challenging in DRAM manufacturing. This is especially true in DRAM array manufacturing, where each device's process flow must overcome a series of process challenges, as well as issues that could be avoided when integrating the process flows. For example, simply increasing the height of capacitors in DRAM manufacturing significantly increases the difficulty of etching them.

[0069] The embodiments of the present application provide a semiconductor structure and a method for forming the same. The method for forming a semiconductor device provided by the embodiments of the present application can prepare a semiconductor structure with a large charge capacity.

[0070] Figure 1 An optional structural diagram of a method for forming a semiconductor structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes the following steps:

[0071] Step S101: providing a substrate structure, wherein the substrate structure at least includes a bit line structure and a plurality of landing pads formed around the bit line structure and partially covering the bit line structure; wherein a gap exists between two adjacent landing pads.

[0072] In some embodiments, the base structure further comprises a semiconductor substrate, the bitline structure is formed on a surface of the semiconductor substrate, and in embodiments of the present application, the base structure comprises a plurality of bitline structures arranged in parallel. Here, the semiconductor substrate may be a silicon substrate, or may comprise other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0073] The semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the semiconductor substrate is defined as the first direction. In the directions of the top surface and the bottom surface of the semiconductor substrate (i.e., the plane where the semiconductor substrate is located), two second directions and a third direction that intersect with each other (for example, perpendicular to each other) are defined. For example, the arrangement direction of multiple bit line structures can be defined as the second direction, and the extension direction of the bit line structure can be defined as the third direction. Based on the second direction and the third direction, the plane direction of the semiconductor substrate can be determined. Here, the first direction, the second direction and the third direction are perpendicular to each other. In the embodiment of the present application, the first direction is defined as the Z-axis direction, the second direction is defined as the X-axis direction, and the third direction is defined as the Y-axis direction.

[0074] In an embodiment of the present application, the landing pad is used to electrically connect a capacitor structure formed subsequently, and there is a gap between two adjacent landing pads. Here, two adjacent landing pads refer to two landing pads that are adjacent along the arrangement direction of the bit line structure (i.e., the second direction).

[0075] Step S102: forming a capacitor structure on the top surface of the landing pad and in the gap.

[0076] In the embodiment of the present application, the capacitor structure may be a cup-shaped capacitor.

[0077] In the embodiment of the present application, since the capacitor structure can be formed not only on the upper surface of the landing pad, but also in the gap between adjacent landing pads, a semiconductor structure with a larger charge capacity can be prepared.

[0078] Figures 2a to 2k This is a schematic diagram of the process of forming a semiconductor structure provided in the embodiment of the present application. Please refer to Figures 2a to 2k The method for forming the semiconductor structure provided in the embodiment of the present application is further described in detail.

[0079] First, you can refer to Figure 2a and 2b , executing step S101, providing a substrate structure, wherein the substrate structure at least includes a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein there is a gap between two adjacent landing pads.

[0080] like Figure 2a and 2b As shown, the base structure includes a semiconductor substrate 101 and a plurality of bitline structures 102 formed on the surface of the semiconductor substrate 101. The semiconductor substrate 101 includes a plurality of active areas 1011 arranged in an array and shallow trench isolation structures 1012 for isolating the active areas 1011. The bitline structures 102 are formed on the surfaces of the active areas 1011 and contact the active areas 1011 via bitline contact structures. The base structure also includes a plurality of landing pads (LPs) 103 formed around the bitline structures and covering portions of the bitline structures. Along the X-axis, a gap V1 is formed between two adjacent landing pads 103.

[0081] Each bitline structure 102 includes a bitline contact layer 1021, a bitline metal layer 1022, and a bitline mask layer 1023, arranged sequentially from bottom to top along the Z-axis. The bitline contact layer 1021 may be made of polysilicon; the bitline metal layer 1022 may be made of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof; and the bitline mask layer may be made of silicon nitride.

[0082] In some embodiments, the base structure further includes a word line structure (not shown) buried in the semiconductor substrate 101, and a first spacer layer, a sacrificial spacer layer 102a, and a second spacer layer 102b sequentially formed on the sidewalls of the bit line structure 102. The sizes of the first spacer layer, the sacrificial spacer layer 102a, and the second spacer layer 102b decrease sequentially along the Z-axis.

[0083] In some embodiments, the substrate structure further includes a storage node contact (NC) 104 formed around the bit line structure 102 and in contact with each of the landing pads 103. The landing pads and the gaps can be formed by the following steps:

[0084] Step S1011 , forming a conductive layer covering the bit line structure on a surface contacting each storage node; wherein a top surface of the conductive layer exceeds a top surface of the bit line structure.

[0085] like Figure 2a As shown, a conductive layer 103 a covering the bit line structure 102 is formed on the surface of each storage node contact 104 , and a top surface of the conductive layer 103 a exceeds the top surface of the bit line structure 102 .

[0086] In the embodiment of the present application, the conductive layer can be formed by any suitable deposition process, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process or a coating process.

[0087] Step S1012: forming a patterned second mask layer on the surface of the conductive layer.

[0088] Please continue to see Figure 2a A patterned second mask layer 105 is formed on the surface of the conductive layer 103a. The patterned second mask layer 105 has a plurality of openings, each of which exposes a portion of the top surface of the conductive layer 103a.

[0089] In some embodiments, the second mask layer may be an amorphous carbon layer (ACL), a spin-on hard mask layer (SOH), a polysilicon layer, or a silicon oxynitride layer.

[0090] Step S1013: Etch a portion of the conductive layer and the first spacer layer through the patterned second mask layer until the sacrificial spacer layer is exposed, thereby forming the landing pad located on the contact surface of each storage node and the gap between two adjacent landing pads.

[0091] like Figure 2bAs shown, through each opening of the patterned second mask layer 105, a portion of the conductive layer 103a and a portion of the first spacer layer are etched until the sacrificial spacer layer 102a is exposed, thereby forming a landing pad 103 located on the surface of each storage node contact 104 and a gap V1 located between two adjacent landing pads.

[0092] The gap V1 formed between adjacent landing pads in the embodiment of the present application has a stepped cross-section along the XZ direction, wherein the Z-axis direction (i.e., the first direction) is perpendicular to the extension direction (i.e., the third direction) of the bit line structure and the arrangement direction (i.e., the second direction) of the bit line structure.

[0093] Next, you can refer to Figures 2c to 2k , executing step S102, forming a capacitor structure on the top surface of the landing pad and in the gap.

[0094] In some embodiments, step S102 may include the following steps:

[0095] Step S1021: forming a first insulating layer in the gap, wherein the first insulating layer is flush with the surface of the landing pad.

[0096] like Figure 2c and 2d As shown, first, the void V1 is filled with an insulating material to form an initial insulating layer 106a. Due to process influences, the initial insulating layer 106a usually covers the surface of the landing pad 103. Then, the initial insulating layer 106a is dry-etched or chemically mechanically polished (CMP) to expose the surface of the landing pad 103. In this way, a first insulating layer 106 is formed in the void V1. In the embodiment of the present application, the first insulating layer can be a silicon oxide layer.

[0097] Step S1022: forming a laminated structure on the surfaces of the landing pad and the first insulating layer.

[0098] In an embodiment of the present application, the stacked structure includes a sacrificial layer and a supporting layer, wherein the sacrificial layer and the supporting layer are alternately stacked along the Z-axis. The sacrificial layer may be an oxide layer, such as a silicon oxide layer; and the supporting layer may be a nitride layer, such as a silicon nitride layer. The stacked structure can be formed by any suitable deposition process.

[0099] like Figure 2eAs shown, a stacked structure 107 is formed on the surface of the landing pad 103 and the first insulating layer 106. In the embodiment of the present application, the stacked structure 107 includes a first sacrificial layer 1071, a first supporting layer 1072, a second sacrificial layer 1073 and a second supporting layer 1074 stacked in sequence from bottom to top along the Z-axis direction.

[0100] Step S1023 : Process the stacked structure and the first insulating layer to form the capacitor structure.

[0101] In some embodiments, step S1023 may be implemented by the following steps:

[0102] Step S1: patterning the stacked structure to form a capacitor hole in the stacked structure on the surface of the landing pad.

[0103] In some embodiments, before performing step S1 , the method for forming a semiconductor structure further includes: forming a first mask layer on a surface of the second supporting layer.

[0104] Please continue to see Figure 2e A first mask layer 108 is formed on the surface of the second supporting layer 1074. The material of the first mask layer 108 and the material of the patterned second mask layer 105 can be the same or different.

[0105] In some embodiments, step S1 can be formed by the following steps:

[0106] Step S11 , patterning the first mask layer.

[0107] Step S12: Using the patterned first mask layer as a mask, etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer on the surface of each landing pad to form a plurality of capacitor holes.

[0108] like Figure 2f As shown, the second supporting layer 1074 , the second sacrificial layer 1073 , the first supporting layer 1072 and the first sacrificial layer 1071 on the surface of the landing pad 103 are etched through the patterned first mask layer to form a plurality of capacitor holes 109 .

[0109] Step S2: forming a first electrode layer on the inner wall of each capacitor hole and the surface of the patterned stacked structure.

[0110] Please continue to see Figure 2f A first electrode layer 110 is formed on the inner wall of each capacitor hole 109 and the surface of the patterned stacked structure. In the embodiment of the present application, the first electrode layer 110 may be a titanium nitride layer.

[0111] Step S3: patterning the support layer to form openings between adjacent capacitor holes.

[0112] Step S4: etching the sacrificial layer and the first insulating layer through the opening.

[0113] In some embodiments, the patterned stacked structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer, and the second supporting layer stacked in sequence, and the first mask layer and the first electrode layer are formed on the surface of the patterned stacked structure. Steps S3 and S4 can be formed by the following steps:

[0114] A first opening is formed in the first mask layer and the second supporting layer.

[0115] The second sacrificial layer is removed through the first opening.

[0116] like Figure 2g As shown, a conventional etching process is used to form a first opening 111a in the first mask layer 108 and the second support layer 1074, and the second sacrificial layer 1073 is removed through the first opening 111a. In the embodiment of the present application, the second sacrificial layer 1073 can be removed by wet etching using a wet etching solution. In the embodiment of the present application, when the first opening 111a is formed, the first electrode layer located on the top surface of the first mask layer 108 is also removed.

[0117] A second opening is formed in the first supporting layer.

[0118] The first sacrificial layer and the first insulating layer are removed through the second opening.

[0119] like Figure 2h and 2i As shown, a conventional etching process is used to form a second opening 111b in the second supporting layer 1072, and the first sacrificial layer 1071 and the first insulating layer 106 are removed through the second opening 111b. In the embodiment of the present application, the first sacrificial layer 1071 and the first insulating layer 106 can be removed by wet etching technology using a wet etching solution.

[0120] In some embodiments, the second sacrificial layer 1074 and the first insulating layer 106 may be made of the same material or different materials.

[0121] In the embodiment of the present application, a dry etching technology, for example, a plasma etching technology, may be used to form the first opening 111 a and the second opening 111 b .

[0122] In some embodiments, a first spacer, a second spacer 102a, and a sacrificial spacer 102b located between the first and second spacer layers are formed on the sidewalls of each bit line structure 102, and the first insulating layer 102b is connected to the sacrificial spacer 102a. The method for forming the semiconductor structure further includes removing the sacrificial spacer when removing the first sacrificial layer and the first insulating layer through the second opening; wherein the first sacrificial layer and the sacrificial spacer are formed of the same material.

[0123] Please continue to see Figure 2i While removing the first sacrificial layer 1071 and the first insulating layer 106, the sacrificial spacer 102a on the sidewall of each bit line structure 102 is removed, forming an air gap G located on the sidewall of the bit line structure. The air gap G is connected to the gap V1, and the air gap G can reduce the leakage of the semiconductor structure.

[0124] In some embodiments, a wet etching technique may be used, for example, an etching solution such as sulfuric acid, hydrofluoric acid, or nitric acid may be used to remove the second sacrificial layer, the first sacrificial layer, the first insulating layer, and the first spacer layer.

[0125] Step S5: forming the capacitor structure in the patterned support layer.

[0126] In some embodiments, step S5 may be implemented by the following steps:

[0127] A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer.

[0128] like Figure 2j As shown, a dielectric layer 112 and a second electrode layer 113 are formed on the surface of the first electrode layer. The dielectric layer 112 and the second electrode layer 113 are also used to seal the air gap G. In the embodiment of the present application, the dielectric layer 112 can be a zirconium oxide layer and / or an aluminum oxide layer, or other high dielectric constant material layer; the second electrode layer 113 can be the same as or different from the first electrode layer 110.

[0129] Depositing a conductive material, the conductive material fills the gaps between the second electrode layers and covers the upper surface of the stacked structure; wherein the first electrode layer, the dielectric layer, the second electrode layer and the conductive material constitute the capacitor structure.

[0130] like Figure 2k As shown, a conductive material 114 is deposited in the gaps between the second electrode layers to form a complete capacitor structure. The capacitor structure includes a first electrode layer 110, a dielectric layer 112, a second electrode layer 113 and a conductive material 114.

[0131] In the embodiment of the present application, the conductive material may be polysilicon, or any other suitable conductive material, such as tungsten, cobalt, or doped polysilicon.

[0132] The method for forming a semiconductor structure provided by the embodiments of the present application also forms a capacitor structure in the gap between two adjacent landing pads, thereby enabling the fabrication of a semiconductor structure with a large charge capacity. Furthermore, when forming the capacitor structure, the semiconductor structure in the embodiments of the present application also creates an air gap located on the sidewalls of the bitline structure, thereby improving the leakage performance of the semiconductor structure.

[0133] In an embodiment of the present application, a fabrication process is designed to increase capacitance and create an air gap to reduce leakage by utilizing the NON structure of the bitline (BL) and bitline contact (BLC) devices. The process involves over-etching the landing pad and then filling the area around it with an insulating material (e.g., SiO2). Based on a conventional capacitor, an air gap structure of BL / BLC / LP is formed in one step through acid etching (e.g., hydrofluoric acid). Furthermore, TIN / ZrO is deposited in the gap of the landing pad to increase the charge capacity of the capacitor.

[0134] Figures 3a to 3i Another schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application is shown below. Figures 3a to 3i The method for forming the semiconductor structure provided in the embodiment of the present application is further described in detail.

[0135] First, refer to Figure 3a and 3b , executing step S101, providing a substrate structure, wherein the substrate structure at least includes a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein there is a gap between two adjacent landing pads.

[0136] like Figure 3aAs shown, the base structure includes a semiconductor substrate 101 and multiple bitline structures 102 formed on the surface of the semiconductor substrate 101. The semiconductor substrate 101 includes multiple active regions 1011 and shallow trench isolation structures 1012 arranged alternately along the X-axis. The bitline structures 102 include a bitline contact layer 1021, a bitline metal layer 1022, and a bitline mask layer 1023 stacked sequentially from bottom to top along the Z-axis. The base structure also includes a first spacer layer, a sacrificial spacer layer 102a, and a second spacer layer 102b formed sequentially on the sidewalls of the bitline structure 102. The sizes of the first spacer layer, the sacrificial spacer layer 102a, and the second spacer layer 102b decrease sequentially along the Z-axis. The base structure also includes multiple landing pads 103 formed around the bitline structure 102 and covering a portion of the bitline structure 102.

[0137] In some embodiments, the gaps between adjacent landing pads may be formed by:

[0138] Step S301: forming a second insulating layer between two adjacent landing pads, wherein the second insulating layer is flush with the surfaces of the landing pads.

[0139] Please continue to see Figure 3a A second insulating layer 301 is formed between two adjacent landing pads 103, wherein the surface of the second insulating layer 301 is flush with the surface of the landing pad 103. Here, the second insulating layer can be a silicon oxide layer or other insulating layer.

[0140] Step S302 : Etching the second insulating layer and a portion of the bit line mask layer to form the gap, wherein the cross section of the gap along the first direction is U-shaped.

[0141] Here, dry etching technology or wet etching technology can be used to etch the second insulating layer and the bit line mask layer. Figure 3b As shown, the second insulating layer 301 and a portion of the bit line mask layer 1023 are removed by etching along the Z-axis direction, forming a gap V2 between adjacent landing pads 103 along the Z-axis direction. The cross-section of the gap V2 along the XZ direction is U-shaped.

[0142] Next, you can refer to Figures 3c to 3i , executing step S102, forming a capacitor structure on the top surface of the landing pad and in the gap.

[0143] In some embodiments, step S102 may include the following steps:

[0144] Step S1021: forming a first insulating layer in the gap, wherein the first insulating layer is flush with the surface of the landing pad.

[0145] like Figure 3c As shown, the gap V2 is filled with insulating material to form a first insulating layer 302, and the surface of the first insulating layer 302 is flush with the surface of the landing pad 103. The first insulating layer 302 and the second insulating layer 301 can be the same or different.

[0146] It should be noted that the process of forming the first insulating layer 302 in the implementation of the present application is the same as the process of forming the first insulating layer 106 in the above embodiment.

[0147] Step S1022: forming a laminated structure on the surfaces of the landing pad and the first insulating layer.

[0148] In the embodiment of the present application, the laminated structure includes a sacrificial layer and a supporting layer. Figure 3d As shown, a stacked structure 107 is formed on the surface of the landing pad 103 and the first insulating layer 302. In the embodiment of the present application, the stacked structure 107 includes a first sacrificial layer 1071, a first supporting layer 1072, a second sacrificial layer 1073 and a second supporting layer 1074 stacked in sequence from bottom to top along the Z-axis direction.

[0149] Step S1023 : Process the stacked structure and the first insulating layer to form the capacitor structure.

[0150] In some embodiments, step S1023 may be implemented by the following steps:

[0151] Step S1: patterning the stacked structure to form a capacitor hole in the stacked structure on the surface of the landing pad.

[0152] In some embodiments, before performing step S1 , the method for forming a semiconductor structure further includes: forming a first mask layer on a surface of the second supporting layer.

[0153] Please continue to see Figure 3d , a first mask layer 108 is formed on the surface of the second supporting layer 1074 .

[0154] In some embodiments, step S1 can be formed by the following steps:

[0155] Step S11 , patterning the first mask layer.

[0156] Step S12: Using the patterned first mask layer as a mask, etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer on the surface of each landing pad to form a plurality of capacitor holes.

[0157] like Figure 3eAs shown, the second supporting layer 1074 , the second sacrificial layer 1073 , the first supporting layer 1072 and the first sacrificial layer 1071 on the surface of the landing pad 103 are sequentially etched through the patterned first mask layer to form a plurality of capacitor holes 109 .

[0158] Step S2: forming a first electrode layer on the inner wall of each capacitor hole and the surface of the patterned stacked structure.

[0159] Please continue to see Figure 3e A first electrode layer 110 is formed on the inner wall of each capacitor hole 109 and on the surface of the patterned stacked structure.

[0160] Step S3: patterning the support layer to form openings between adjacent capacitor holes.

[0161] Step S4: etching the sacrificial layer and the first insulating layer through the opening.

[0162] In some embodiments, the patterned stacked structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer, and the second supporting layer stacked in sequence, and the first mask layer and the first electrode layer are formed on the surface of the patterned stacked structure. Steps S3 and S4 can be formed by the following steps:

[0163] A first opening is formed in the first mask layer and the second supporting layer.

[0164] The second sacrificial layer is removed through the first opening.

[0165] like Figure 3f As shown, a conventional etching process is used to form a first opening 111 a in the first mask layer 108 and the second supporting layer 1074 , and the second sacrificial layer 1073 is removed through the first opening 111 a .

[0166] A second opening is formed in the first supporting layer.

[0167] The first sacrificial layer and the first insulating layer are removed through the second opening.

[0168] like Figure 3g As shown, a conventional etching process is used to form a second opening 111 b in the second supporting layer 1072 , and the first sacrificial layer 1071 and the first insulating layer 302 are removed through the second opening 111 b .

[0169] In the embodiment of the present application, a dry etching technology, for example, a plasma etching technology, may be used to form the first opening 111 a and the second opening 111 b .

[0170] In some embodiments, the sacrificial spacer layer 102 a is connected to the first insulating layer 302 , and the sacrificial spacer layer is removed when the first sacrificial layer and the first insulating layer are removed through the second opening.

[0171] Please continue to see Figure 3g While removing the first sacrificial layer 1071 and the first insulating layer 302, the sacrificial spacer layer 102b on the sidewalls of each bitline structure 102 is also removed, forming an air gap G located within the bitline structure or the bitline contact layer. The air gap is connected to the gap V2, and the air gap G can reduce leakage in the semiconductor structure. In the embodiment of the present application, the first sacrificial layer and the sacrificial spacer layer can be formed of the same material or different materials.

[0172] Step S5: forming the capacitor structure in the patterned support layer.

[0173] In some embodiments, step S5 may be implemented by the following steps:

[0174] Step S51 : depositing a dielectric layer and a second electrode layer in sequence on the surface of the first electrode layer.

[0175] Step S52 : depositing a conductive material, wherein the conductive material fills the gaps between the second electrode layers and covers the upper surface of the stacked structure; wherein the first electrode layer, the dielectric layer, the second electrode layer and the conductive material constitute the capacitor structure.

[0176] like Figure 3h As shown, a dielectric layer 112 and a second electrode layer 113 are formed on the surface of the first electrode layer, and the dielectric layer 112 and the second electrode layer 113 are also used to seal the air gap G. Figure 3i As shown, a conductive material 114 is deposited in the gaps between the second electrode layers to form a complete capacitor structure. The capacitor structure includes a first electrode layer 110, a dielectric layer 112, a second electrode layer 113 and a conductive material 114.

[0177] The formation process of the semiconductor structure in the embodiment of the present application is similar to the formation process of the semiconductor structure in the above embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and no further details will be given here.

[0178] The method for forming a semiconductor structure provided by the embodiments of the present application also forms a capacitor structure in the gap between two adjacent landing pads, thereby producing a semiconductor structure with a large charge capacity. Furthermore, when forming the capacitor structure, the semiconductor structure in the embodiments of the present application also creates an air gap located on the sidewalls of the bitline structure, thereby improving the leakage performance of the semiconductor structure.

[0179] In addition, the present invention also provides a semiconductor structure, such as Figure 4a and 4b As shown, the semiconductor structure 40 includes a substrate structure and a capacitor structure 401 .

[0180] The substrate structure includes a plurality of bit line structures 102 arranged in parallel along the X-axis direction and a plurality of landing pads 103 formed around each bit line structure 102 and covering a portion of the bit line structure; wherein a gap V1 or a gap V2 is formed between two adjacent landing pads 103. Figure 4a As shown, the cross section of the gap V1 along the XZ direction is a step-shaped one, and the Z-axis direction is perpendicular to the extension direction of the bit line structure 201 and the arrangement direction of the bit line structure 201 (i.e., the X-axis direction); the bit line structure 201 includes a bit line contact layer 1021, a bit line metal layer 1022, and a bit line mask layer 1023 stacked in sequence from bottom to top along the Z-axis direction. Figure 4b As shown, the cross section of the gap V2 along the XZ direction is U-shaped; the bit line structure 201 includes the bit line contact layer 1021, the bit line metal layer 1022 and a portion of the bit line mask layer 1023 stacked sequentially from bottom to top along the Z axis.

[0181] In some embodiments, the base structure further includes a semiconductor substrate 101, the semiconductor substrate 101 including a plurality of active areas 1011 arranged in an array and shallow trench isolation structures 1012 for isolating the active areas 1011. The bit line structure 102 is formed on the surface of the active areas 1011 and contacts the active areas 1011 via a bit line contact structure. The base structure further includes a storage node contact 104 formed around the bit line structure 102 and contacting each of the landing pads 103.

[0182] In some embodiments, the base structure further includes a word line structure (not shown) buried in the semiconductor substrate 101 .

[0183] The capacitor structure 401 is located on the top surface of the landing pad 103 and in the void V1 or the void V2 .

[0184] In some embodiments, the capacitor structure 401 includes a first electrode layer 110 , a dielectric layer 112 , and a second electrode layer 113 stacked in sequence, and conductive material 114 is filled between adjacent second electrode layers 113 .

[0185] In the embodiment of the present application, the capacitor structure 401 is a cup-shaped structure, and the extension direction (Z-axis direction) of the capacitor structure is perpendicular to the top surface of the landing pad 103; the capacitor structure 401 also includes a first support layer 1072 and a second support layer 1074 arranged in parallel; wherein, the first support layer 1072 is arranged at the middle periphery of the capacitor structure 401, and the second support layer 1074 is arranged at the top periphery of the capacitor structure 401, and the first support layer 1072 and the second support layer 1074 are jointly used to support the capacitor structure 401.

[0186] In some embodiments, the thickness h1 of the second supporting layer 1074 is greater than the thickness h2 of the first supporting layer 1072 , so that a better supporting effect can be achieved.

[0187] In some embodiments, a first spacer layer, a second spacer layer 102 b and an air gap G between the first spacer layer and the second spacer layer 102 b are formed on the sidewall of the bit line structure 102 ; wherein the air gap G is connected to the dielectric layer 112 .

[0188] The semiconductor structure provided in the embodiment of the present application is similar to the formation method of the semiconductor structure in the above embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and no further details will be given here.

[0189] In the semiconductor structure provided by the embodiments of the present application, the capacitor structure is located not only on the top surface of the landing pad but also in the gap between two adjacent landing pads. This allows the fabricated semiconductor structure to have a large charge capacity. Furthermore, the semiconductor structure provided by the embodiments of the present application includes air gaps located on the sidewalls of the bitline structure, thereby improving the leakage performance of the resulting semiconductor structure.

[0190] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0191] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0192] The above are only some implementation methods of the embodiments of this application, but the scope of protection of the embodiments of this application is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed in the embodiments of this application, and they should be included in the scope of protection of the embodiments of this application. Therefore, the scope of protection of the embodiments of this application should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing a substrate structure, the substrate structure comprising at least a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein a gap is provided between two adjacent landing pads; A capacitor structure is formed on a top surface of the landing pad and in the void.

2. The method according to claim 1, characterized in that The forming of a capacitor structure on the top surface of the landing pad and in the gap comprises: forming a first insulating layer in the gap, wherein the first insulating layer is flush with a surface of the landing pad; forming a stacked structure on surfaces of the landing pad and the first insulating layer; The stacked structure and the first insulating layer are processed to form the capacitor structure.

3. The method according to claim 2, characterized in that The stacked structure includes a sacrificial layer and a supporting layer; and processing the stacked structure and the first insulating layer to form the capacitor structure includes: patterning the stacked structure to form a capacitor hole in the stacked structure on the landing pad surface; forming a first electrode layer on the inner wall of each capacitor hole and on the surface of the patterned stacked structure; Patterning the support layer to form openings between adjacent capacitor holes; etching the sacrificial layer and the first insulating layer through the opening; The capacitor structure is formed in the patterned support layer.

4. The method according to claim 3, characterized in that The forming of the capacitor structure in the patterned support layer includes: Depositing a dielectric layer and a second electrode layer in sequence on the surface of the first electrode layer; Depositing a conductive material, the conductive material fills the gaps between the second electrode layers and covers the upper surface of the stacked structure; wherein the first electrode layer, the dielectric layer, the second electrode layer and the conductive material constitute the capacitor structure.

5. The method according to claim 4, characterized in that The sacrificial layer includes a first sacrificial layer and a second sacrificial layer, and the supporting layer includes a first supporting layer and a second supporting layer; The method further includes: forming a first mask layer on a surface of the second supporting layer; The step of patterning the stacked structure to form a capacitor hole in the stacked structure on the surface of the landing pad comprises: patterning the first mask layer; Using the patterned first mask layer as a mask, the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surface of each landing pad are etched to form a plurality of capacitor holes.

6. The method according to claim 5, characterized in that The patterned stacked structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer stacked in sequence, and the first mask layer and the first electrode layer are formed on the surface of the patterned stacked structure; The step of patterning the support layer to form openings between adjacent capacitor holes and etching the sacrificial layer and the first insulating layer through the openings includes: forming a first opening in the first mask layer and the second supporting layer; removing the second sacrificial layer through the first opening; forming a second opening in the first supporting layer; The first sacrificial layer and the first insulating layer are removed through the second opening.

7. The method according to claim 6, characterized in that The first opening and the second opening are formed by using dry etching technology.

8. The method according to claim 6 or 7, characterized in that A first spacer, a second spacer, and a sacrificial spacer located between the first spacer and the second spacer are formed on the sidewalls of each of the bit line structures, and the first insulating layer is connected to the sacrificial spacer. The method further includes: removing the sacrificial spacer layer when removing the first sacrificial layer and the first insulating layer through the second opening; The first sacrificial layer and the sacrificial spacer layer are formed of the same material.

9. The method according to claim 8, characterized in that The second sacrificial layer, the first sacrificial layer, the first insulating layer and the first spacer layer are removed by using a wet etching technique.

10. The method according to claim 8, characterized in that The substrate structure further includes a storage node contact formed around the bit line structure and contacting each of the landing pads; the landing pads and the gap are formed by the following steps: forming a conductive layer covering the bit line structure on a surface contacted by each storage node; wherein a top surface of the conductive layer exceeds a top surface of the bit line structure; forming a patterned second mask layer on the surface of the conductive layer; The conductive layer and the first spacer layer are partially etched through the patterned second mask layer until the sacrificial spacer layer is exposed, thereby forming the landing pad located on the contact surface of each storage node and the gap located between two adjacent landing pads; wherein the cross-section of the gap along the first direction is stepped, and the first direction is perpendicular to the extension direction of the bit line structure and the arrangement direction of the bit line structure.

11. The method according to claim 10, characterized in that The bit line structure includes a bit line contact layer, a bit line metal layer, and a bit line mask layer stacked sequentially from bottom to top along the first direction; the method further includes: forming a second insulating layer between two adjacent landing pads, wherein the second insulating layer is flush with surfaces of the landing pads; The second insulating layer and a portion of the bit line mask layer are etched to form the gap, wherein a cross section of the gap along the first direction is U-shaped.

12. A semiconductor structure, characterized in that include: A substrate structure comprising at least a bit line structure and a plurality of landing pads formed around the bit line structure and covering a portion of the bit line structure; wherein a gap is formed between two adjacent landing pads; A capacitor structure is located on the top surface of the landing pad and in the gap.

13. The semiconductor structure according to claim 12, wherein: The cross section of the gap along a first direction is a step-shaped one, the first direction being perpendicular to the extension direction of the bit line structure and the arrangement direction of the bit line structure; the bit line structure comprises a bit line contact layer, a bit line metal layer, and a bit line mask layer stacked in sequence from bottom to top along the first direction; or, The cross section of the gap along the first direction is U-shaped, and the bit line structure includes the bit line contact layer, the bit line metal layer, and a portion of the bit line mask layer stacked sequentially from bottom to top along the first direction.

14. The semiconductor structure according to claim 12, wherein: The capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence, and conductive material is filled between adjacent second electrode layers.

15. The semiconductor structure according to claim 14, wherein: The capacitor structure is a cup-shaped structure, and the extension direction of the capacitor structure is perpendicular to the top surface of the landing pad; the capacitor structure also includes a first supporting layer and a second supporting layer arranged in parallel; The first supporting layer is arranged on the middle periphery of the capacitor structure, and the second supporting layer is arranged on the top periphery of the capacitor structure. The first supporting layer and the second supporting layer are used together to support the capacitor structure.

16. The semiconductor structure according to claim 15, wherein: The thickness of the second supporting layer is greater than that of the first supporting layer.

17. The semiconductor structure according to any one of claims 14 to 16, characterized in that: A first spacer layer, a second spacer layer, and an air gap between the first spacer layer and the second spacer layer are formed on the sidewall of the bit line structure; wherein the air gap is connected to the dielectric layer.

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