A non-volatile memory and a method for manufacturing the same

Abstract

The present invention provides a non-volatile memory and a manufacturing method thereof. The non-volatile memory includes a substrate, a floating gate structure, a silicide blocking layer, and a via etching blocking layer. Among them, the floating gate structure is located on the substrate. The floating gate structure includes a gate dielectric layer and a polysilicon layer stacked in sequence from bottom to top, and includes sidewalls located on the sides of the gate dielectric layer and the polysilicon layer. The silicide blocking layer is located on the substrate and covers the floating gate structure, and the thickness of the silicide blocking layer is greater than 35 nm. The via etching blocking layer is located on the substrate and covers the silicide blocking layer. By increasing the thickness of the silicide blocking layer between the polycrystalline floating gate and the via etching blocking layer, the present invention can effectively suppress the leakage of floating gate charges through the top dielectric, thereby improving the data retention time of the non-volatile memory. The data retention time can reach 10 years at 85 degrees. In addition, the solution of the present invention has the advantages of lower process complexity and lower process cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and relates to a non-volatile memory and a manufacturing method thereof. Background Art

[0002] Based on single-layer polycrystalline (Poly) non-volatile memories (NVMs) are classified into one-time programmable (OTP), finitely programmable (FTP), and multi-time programmable (MTP) memories according to the number of programmable times, and adopt the mechanism of storing charges in a floating gate. As Figure 1 shown is a schematic diagram of a non-volatile memory based on single-layer polycrystalline, including a bit line terminal 101, a selection terminal 102, a control terminal 103, a tunneling terminal 104, a floating gate 105, a control transistor capacitor 106, a selection transistor 107, and a floating gate transistor 108. The substrate end, source end of the floating gate transistor 108, and the substrate end of the selection transistor 107 are connected to the tunneling terminal 104, and the drain end of the floating gate transistor 108 is connected to the source end of the selection transistor 107. Programming can be performed through hot carrier injection (HCI) or Fowler-Nordheim (F-N) tunneling, and erasure can be performed through F-N tunneling.

[0003] The non-volatile memory based on single-layer polycrystalline adopts the mechanism of storing charges in a floating gate, only requires one layer of polycrystalline, and is compatible with the standard CMOS process. However, for a non-volatile memory manufactured by a general single-layer polycrystalline CMOS process, the charges stored in the floating gate may leak through the medium around the floating gate. Among them, in addition to considering the leakage of the gate oxide at the bottom of the floating gate, the leakage at the top and sidewalls of the floating gate also needs to be considered, especially the leakage at the top of the floating gate. The charges on the floating gate can affect the charge distribution of the contact etch stop layer (CESL) through capacitive coupling, which will affect the retention of the charges on the floating gate, especially during reverse coding, and the reverse coding effect will exacerbate the leakage of the floating gate charges. The leakage of the medium around the floating gate will affect the data retention time of the non-volatile memory, thus not meeting the requirements of the non-volatile memory for data retention time. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a non-volatile memory and a manufacturing method thereof, which are used to solve the problem that in a non-volatile memory based on single-layer polycrystalline, the charges stored in the floating gate are prone to leakage through the medium around the floating gate, affecting the data retention time of the non-volatile memory.

[0005] To achieve the above purpose and other related purposes, the present invention provides a non-volatile memory, including:

[0006] A substrate;

[0007] A floating gate structure is located on the substrate. The floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top.

[0008] A silicide blocking layer is located on the substrate and covers the floating gate structure. The thickness of the silicide blocking layer is greater than 35 nm.

[0009] An etch stop layer for via is located on the substrate and covers the silicide blocking layer.

[0010] Optionally, the thickness of the silicide blocking layer is greater than 100 nm.

[0011] Optionally, the non-volatile memory includes a silicided region. The silicide blocking layer surrounds the silicided region. A contact via located in the silicided region is provided in the etch stop layer for via. The distance between the boundary of the contact via and the boundary of the silicide blocking layer around the silicided region is greater than 0.15 μm.

[0012] Optionally, the material of the silicide blocking layer includes silicon oxide, and the material of the etch stop layer for via includes at least one of silicon nitride and silicon oxynitride.

[0013] The present invention also provides a method for manufacturing a non-volatile memory, including the following steps:

[0014] Provide a substrate and form a floating gate structure on the substrate. The floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top.

[0015] Perform ion implantation on the substrate to form source regions and drain regions on both sides of the floating gate structure.

[0016] Form a silicide blocking layer on the substrate. The silicide blocking layer covers the floating gate structure. The thickness of the silicide blocking layer is greater than 35 nm.

[0017] Etch the silicide blocking layer to expose the substrate in the silicided region.

[0018] Form a metal silicide layer in the silicided region.

[0019] Form an etch stop layer for via on the substrate. The etch stop layer for via covers the silicide blocking layer.

[0020] Optionally, the thickness of the silicide blocking layer is greater than 100 nm.

[0021] Optionally, it further includes forming a contact via in the etch stop layer for via. The distance between the boundary of the contact via and the boundary of the silicide blocking layer around the silicided region is greater than 0.15 μm.

[0022] Optionally, the material of the silicidation blocking layer includes silicon oxide, and the material of the hole etching blocking layer includes at least one of silicon nitride and silicon oxynitride.

[0023] As described above, the non-volatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicidation blocking layer between the polycrystalline floating gate and the hole etching blocking layer, thereby improving the data retention time of the non-volatile memory. The data retention time can reach 10 years at 85 degrees. In addition, compared with the solution of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching blocking layer, the solution of the present invention has the advantages of lower process complexity and lower process cost, and will not cause a decrease in the etching selectivity between the hole etching blocking layer and the silicidation blocking layer, which affects the etching of the holes. Description of the Drawings

[0024] Figure 1 Schematic diagram showing a non-volatile memory based on a single-layer polycrystal.

[0025] Figure 2 Schematic diagram showing a floating gate and its surrounding dielectric layer structure fabricated using a CMOS process.

[0026] Figure 3 Schematic diagram showing another floating gate and its surrounding dielectric layer structure.

[0027] Figure 4 Schematic diagram showing a floating gate and its surrounding dielectric layer structure of a non-volatile memory in an embodiment.

[0028] Figure 5 Schematic layout diagram showing the active region, floating gate, and silicidation blocking layer of a memory cell of a non-volatile memory in an embodiment.

[0029] Figure 6 Schematic layout diagram showing the active region, silicidation blocking layer, and contact hole of a memory cell of a non-volatile memory in an embodiment.

[0030] Figure 7 Process flow diagram showing the manufacturing method of a non-volatile memory in an embodiment.

[0031] Description of Component Labels

[0032] 101 Line terminal

[0033] 102 Selection terminal

[0034] 103 Control terminal

[0035] 104 Tunneling terminal

[0036] 105 Floating gate

[0037] 106 Control tube capacitor

[0038] 107 Select Tube

[0039] 108 Floating Gate Transistor

[0040] 201, 301 silicon substrate

[0041] 202, 302 gate oxide

[0042] 203, 303 polysilicon

[0043] 204, 304 side wall

[0044] 205, 305 oxide layer

[0045] 206, 306 hole etching stop layer

[0046] 401 substrate

[0047] 402 gate dielectric layer

[0048] 403 Polysilicon layer

[0049] 404 Side Wall

[0050] 405 Silicidation barrier layer

[0051] 406 hole etching stopper

[0052] 407 Active Area

[0053] 408 Floating Gate

[0054] 409 Contact hole

[0055] D1 Horizontal spacing

[0056] D2 vertical spacing

[0057] Steps S1 to S6 DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] See also Figures 1 to 7It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout pattern may also be more complex.

[0060] As Figure 2 shown, it shows a floating gate and its surrounding dielectric layer structure fabricated using CMOS technology, including. Among them, the sidewall 204 is usually a sandwich structure of an oxide layer, silicon nitride, and an oxide layer, and the material of the hole etch stop layer 206 is silicon nitride. The polycrystal is surrounded by an insulating dielectric to form a floating gate. Due to defects in the dielectric layer around the floating gate, the charge stored in the floating gate may leak through the surrounding dielectric layer. For non-volatile memories, even relatively weak leakage will affect the data retention time of the non-volatile memory. For CMOS technology, the gate oxide grown thermally at the bottom of the floating gate usually has relatively high quality, but the defect density of the dielectric layer at the top of the floating gate is relatively high, especially the hole etch stop layer. Due to its silicon nitride material, the defect density is high, and the floating gate charge may leak through the top dielectric.

[0061] As Figure 3 shown, it shows another floating gate and its surrounding dielectric layer structure, including a silicon substrate 301, a gate oxide 302, a polysilicon 303, a sidewall 304, an oxide layer 305, and a hole etch stop layer 306. Among them, the thickness of the oxide layer 305 is relatively thin, only dozens of nanometers, and the typical value is 35 nanometers. The hole etch stop layer 306 is a silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride. By adjusting the composition of the hole etch stop layer, changing the material of the hole etch stop layer from silicon nitride to silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride, the defect density of the hole etch stop layer can be reduced, and the leakage of the floating gate charge can be reduced. However, in this method, it is necessary to effectively control the defect density. The defect density must be lower than a certain level to control the leakage of the charge stored in the floating gate within the required range. And the process of controlling defects by adjusting the composition of the hole etch stop layer is relatively complex, increasing the process cost; and adjusting the composition of the hole etch stop layer affects the etching ratio of the hole etch stop layer to the oxide layer, which will affect the etching of the holes.

[0062] Therefore, the present invention also provides a new solution to reduce the leakage of the charge stored in the floating gate to improve the data retention time of the non-volatile memory. The technical solution of the present invention will be described below through specific embodiments.

[0063] Embodiment 1

[0064] In this embodiment, a non-volatile memory is provided. Please refer to Figure 4, which shows the floating gate of the non-volatile memory and the surrounding dielectric layer structure, including a substrate 401, a floating gate structure, a silicide blocking layer 405, and a hole etching blocking layer 406. Among them, the floating gate structure is located on the substrate 401, and the floating gate structure 401 includes a gate dielectric layer 402 and a polysilicon layer 403 stacked in sequence from bottom to top; the silicide blocking layer 403 is located on the substrate 401 and covers the floating gate structure, and the thickness of the silicide blocking layer 403 is greater than 35 nm; the hole etching blocking layer 406 is located on the substrate 401 and covers the silicide blocking layer 403.

[0065] As an example, the floating gate structure 401 further includes sidewalls 404 located on the sides of the gate dielectric layer 402 and the polysilicon layer 403.

[0066] As an example, please refer to Figure 5 , which shows a layout schematic diagram of the active region 407, the floating gate 408, and the silicide blocking layer 405 of the storage unit of the non-volatile memory. Among them, the floating gate of the non-volatile memory is covered by the silicide blocking layer 405.

[0067] As an example, the substrate 401 includes, but is not limited to, common semiconductor substrates such as silicon, germanium, silicon germanium, III-V compounds, and SOI (silicon on insulator). The material of the silicide blocking layer 405 is selected as silicon oxide, the material of the hole etching blocking layer 406 is selected as silicon nitride, and the sidewalls 404 are selected as an ONO composite structure, that is, a silicon oxide - silicon nitride - silicon oxide composite structure.

[0068] Specifically, the thickness of a general silicide blocking layer is in the range of dozens of nanometers, and the typical value is 35 nm. In the present invention, the thickness of the silicide blocking layer 403 between the floating gate structure and the hole etching blocking layer 406 is relatively thick. In the present invention, the thickness of the silicide blocking layer 403 is significantly increased, and the thickness can be greater than 100 nm. For example, the thickness of the silicide blocking layer 403 can be selected from one of 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, and 130 nm, and preferably 120 nm. The significantly increased silicide blocking layer can effectively suppress the leakage of floating gate charges through the top dielectric, thereby improving the data retention time of the non-volatile memory. The data retention time can reach 10 years at 85 degrees. In addition, compared with the scheme of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching blocking layer, the scheme of the present invention has the advantages of lower process complexity and lower process cost, and will not cause a decrease in the etching selectivity between the hole etching blocking layer and the silicide blocking layer and affect the etching of the holes.

[0069] Of course, in another embodiment, the material of the hole etching stop layer can also be silicon oxynitride, or a composite structure of silicon oxynitride and silicon nitride can be selected. Since the thickened silicide blocking layer has improved the leakage of floating gate charges, the requirement for controlling the defect density of the hole etching stop layer can be reduced. Compared with the solution of reducing the charge leakage stored in the floating gate only by changing the composition of the hole etching stop layer, the solution of increasing the thickness of the silicide blocking layer between the polycrystalline floating gate and the hole etching stop layer and adjusting the composition of the hole etching stop layer simultaneously used in the present invention still has a relatively low process difficulty.

[0070] However, increasing the thickness of the silicide blocking layer to improve the data retention performance of the device, although it does not involve changing the composition of the hole etching stop layer, will not affect the etching ratio between the hole etching stop layer and the oxide layer. Although this reduces the process difficulty, it brings a new technical problem: because the increase in the thickness of the silicide blocking layer makes it difficult to precisely control the hole etching, and it is easy to have insufficient hole etching, and insufficient hole etching can directly lead to device failure. As an example, please refer to Figure 6 , which shows a layout schematic diagram of the active region 407, the silicide blocking layer 405, and the contact hole 409 of the storage unit of the non-volatile memory. Among them, the non-volatile memory includes a silicided region, the silicide blocking layer 406 surrounds the silicided region, and the contact hole 409 is located in the hole etching stop layer and in the silicided region. Generally, the distance between the boundary of the contact hole and the boundary of the silicide blocking layer is set to 0.15 μm. In the present invention, in order to avoid the hole contact problem caused by the insufficient etching of the contact hole due to the increase in the thickness of the silicide blocking layer, the distance between the boundary of the contact hole 409 and the boundary of the silicide blocking layer 406 around the silicided region can be further set to be greater than 0.15 μm, where Figure 6 the lateral spacing D1 and the longitudinal spacing D2 are shown, and the lateral spacing D1 and the longitudinal spacing D2 can be set to the same value or different values, but both are greater than 0.15 μm. It should be noted that the increased spacing can be adjusted according to the specific etching process as long as it satisfies that the increased spacing can make the hole etching sufficient and not over-etch. In this embodiment, the distance between the boundary of the contact hole 409 and the boundary of the silicide blocking layer 406 around the silicided region can be selected from one of 0.18 μm, 0.19 μm, 0.2 μm, 0.21 μm, and 0.22 μm, and preferably 0.2 μm. Thus, on the premise of avoiding insufficient hole etching, the data retention performance of the device can be effectively improved.

[0071] Embodiment 2

[0072] In this embodiment, a manufacturing method of a non-volatile memory is provided. Please refer to Figure 7, which is shown as the process flow chart of the method, includes the following steps:

[0073] S1: Provide a substrate, and form a floating gate structure on the substrate. The floating gate structure includes a gate dielectric layer and a polysilicon layer stacked in sequence from bottom to top;

[0074] S2: Perform ion implantation on the substrate to form source and drain regions located on both sides of the floating gate structure;

[0075] S3: Form a silicide blocking layer on the substrate. The silicide blocking layer covers the floating gate structure, and the thickness of the silicide blocking layer is greater than 35 nm;

[0076] S4: Etch the silicide blocking layer to expose the substrate in the silicided region;

[0077] S5: Form a metal silicide layer in the silicided region;

[0078] S6: Form a via etch stop layer on the substrate. The via etch stop layer covers the silicide blocking layer.

[0079] Specifically, in the step S1, forming the floating gate structure includes the following steps: Depositing the gate dielectric layer and the polysilicon layer in sequence by chemical vapor deposition, physical vapor deposition or other suitable methods, and patterning the polysilicon layer and the gate dielectric layer by dry etching and / or wet etching to obtain a gate structure with a desired shape. In this embodiment, sidewall dielectric deposition and etching are further performed to obtain sidewalls located on both sides of the side of the gate dielectric layer and the polysilicon layer.

[0080] In the step S4, due to the thickness change of the silicide blocking layer, the etch menu for the silicide blocking layer needs to be adjusted accordingly, and the etch amount of the corresponding thickness is increased to expose the substrate.

[0081] As an example, the thickness of the silicide blocking layer is greater than 100 nm. For example, the thickness of the silicide blocking layer can be selected from one of 105 nm, 110 nm, 115 nm, 120 nm, 125 nm and 130 nm.

[0082] As an example, it further includes the step of forming contact holes in the hole etching barrier layer. In the present invention, in order to avoid the hole contact problem caused by the unsatisfactory contact hole etching due to the increase in the thickness of the silicide barrier layer, the distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region can be further set to be greater than the conventional distance, for example, greater than 0.15 μm. It should be noted that the increased distance can be adjusted according to the specific etching process, as long as it satisfies that the increased distance can make the hole etching sufficient and not over-etch. In this embodiment, the distance between the contact hole and the silicide barrier layer around the silicide region can be selected from one of 0.18 μm, 0.19 μm, 0.2 μm, 0.21 μm, and 0.22 μm. Thus, on the premise of avoiding insufficient hole etching, the data retention performance of the device can be effectively improved.

[0083] As an example, the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.

[0084] The manufacturing method of the non-volatile memory in this embodiment suppresses the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. It only needs to increase the deposition time to increase the thickness of the silicide barrier layer and increase the etching amount of the silicide barrier layer when defining the silicide region, and has the advantages of lower process complexity and lower process cost. In addition, the scheme of increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer can also be used simultaneously with the scheme of adjusting the composition of the hole etching barrier layer to achieve a better effect of suppressing the leakage of floating gate charges through the top dielectric.

[0085] In summary, the non-volatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer, thereby increasing the data retention time of the non-volatile memory, and the data retention time can reach 10 years at 85 degrees. In addition, compared with the scheme of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching barrier layer, the scheme of the present invention has the advantages of lower process complexity and lower process cost, and will not cause a decrease in the etching selectivity between the hole etching barrier layer and the silicide barrier layer and affect the etching of the hole. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0086] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A non-volatile memory, characterized in that, Comprising: A substrate; A floating gate structure located on the substrate, the floating gate structure including a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top, and the floating gate structure further including sidewalls located on the sides of the gate dielectric layer and the polysilicon layer; A silicide blocking layer located on the substrate and covering the floating gate structure, the thickness of the silicide blocking layer being greater than 100 nm and less than or equal to 130 nm; A hole etching blocking layer located on the substrate and covering the silicide blocking layer; The non-volatile memory includes a silicided region, the silicide blocking layer surrounds the silicided region, a contact hole located in the silicided region is provided in the hole etching blocking layer, and the distance between the boundary of the contact hole and the boundary of the silicide blocking layer around the silicided region is greater than 0.15 μm; Wherein, the non-volatile memory adopts a mechanism of storing charges in the floating gate; The material of the silicide blocking layer is selected as silicon oxide, the material of the hole etching blocking layer is selected as silicon nitride, silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride, and the sidewall is selected as a silicon oxide - silicon nitride - silicon oxide composite structure.

2. The non-volatile memory according to claim 1, wherein: The thickness of the silicide blocking layer is selected from one of 105 nm, 110 nm, 115 nm, 120 nm, 125 nm and 130 nm.

3. The non-volatile memory according to claim 1, wherein: The distance between the contact hole and the silicide blocking layer around the silicided region is selected from one of 0.18 μm, 0.19 μm, 0.2 μm, 0.21 μm and 0.22 μm.

4. A method for manufacturing a non-volatile memory, characterized in that, Including the following steps: Providing a substrate and forming a floating gate structure on the substrate, the floating gate structure including a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top, and the floating gate structure further including sidewalls located on the sides of the gate dielectric layer and the polysilicon layer; Performing ion implantation on the substrate to form source regions and drain regions located on both sides of the floating gate structure; Forming a silicide blocking layer on the substrate, the silicide blocking layer covering the floating gate structure, the thickness of the silicide blocking layer being greater than 100 nm and less than or equal to 130 nm; Etching the silicide blocking layer to expose the substrate of the silicided region; Forming a metal silicide layer in the silicided region; Forming a hole etching blocking layer on the substrate, the hole etching blocking layer covering the silicide blocking layer; Forming a contact hole in the hole etching blocking layer, the distance between the boundary of the contact hole and the boundary of the silicide blocking layer around the silicided region being greater than 0.15 μm; Wherein, the non-volatile memory adopts a mechanism of storing charges in the floating gate; The material of the silicide blocking layer is selected as silicon oxide, the material of the hole etching blocking layer is selected as silicon nitride, silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride, and the sidewall is selected as a silicon oxide - silicon nitride - silicon oxide composite structure.

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