Pixel driving circuit, display and electronic device

Abstract

The present application provides a pixel driving circuit, a display device, and an electronic device. The pixel driving circuit includes a switching circuit, a scanning circuit, and a pixel circuit. The switching circuit is electrically connected between the pixel circuit and the scanning circuit and is configured to conduct or disconnect the electrical connection between the pixel circuit and the scanning circuit. The scanning circuit outputs a gate driving signal to the pixel circuit. The pixel circuit includes a reset unit and a light-emitting unit. The reset unit is electrically connected to the switching circuit and the reset unit is electrically connected to the light-emitting unit. When the display device is in the first state, the switching circuit disconnects the electrical connection between the pixel circuit and the scanning circuit, and the switching circuit outputs a control signal to the reset unit. The reset unit outputs a reverse bias voltage to the light-emitting unit according to the control signal to control the light-emitting unit to be in a reverse bias state. By adopting the embodiment of the present application, the OLED can be in a bias state opposite to that during the display period, which can avoid the deviation of the device characteristics of the OLED and improve the lifespan of the light-emitting element.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and in particular, to a pixel driving circuit, a display, and an electronic device. Background Art

[0002] Organic light-emitting diode (OLED) display panels are currently the mainstream display technology and are widely used in products such as high-end mobile phones and wearables.

[0003] Under the drive of an external voltage, holes generated at the anode and electrons generated at the cathode of the OLED will move, be injected into the hole transport layer and the electron transport layer respectively, and migrate to the light-emitting layer. When the two meet in the light-emitting layer, energy excitons are generated, which excite the light-emitting molecules to finally generate visible light. However, when the OLED emits light, its anode and cathode are in a long-term forward bias, which will cause an increase in the startup voltage of the OLED and a decrease in the photoelectric conversion efficiency, affecting the lifespan of the OLED. Summary of the Invention

[0004] Embodiments of this application provide a pixel driving circuit, a display, and an electronic device, which can make the OLED in a bias state opposite to that during the display period during the non-display period, avoid the deviation of the OLED device characteristics, and improve the lifespan of the OLED panel.

[0005] In a first aspect, embodiments of this application provide a pixel driving circuit, which is applied to a display. The pixel driving circuit includes a switching circuit, a scanning circuit, and a pixel circuit; the switching circuit is electrically connected between the pixel circuit and the scanning circuit, and is used to conduct or disconnect the electrical connection between the pixel circuit and the scanning circuit; the scanning circuit is used to output a gate driving signal to the pixel circuit; the pixel circuit includes a reset unit and a light-emitting unit, the reset unit is electrically connected to the switching circuit, and the reset unit is electrically connected to the light-emitting unit; when the display is in a first state, the switching circuit disconnects the electrical connection between the pixel circuit and the scanning circuit, and the switching circuit outputs a control signal to the reset unit; the reset unit outputs a reverse bias voltage to the light-emitting unit according to the control signal output by the switching circuit, so as to control the light-emitting unit to be in a reverse bias state.

[0006] By adopting the embodiments of this application, in the first state of the display, the switching circuit can control the reset unit to output a reverse bias voltage to the light-emitting unit, so as to control the light-emitting unit to be in a reverse bias state. Based on such a design, the OLED can be in a bias state opposite to that during the display period during the non-display period, avoiding the deviation of the OLED device characteristics and improving the lifespan of the OLED panel.

[0007] In a possible design, when the display is in the second state, the switch circuit conducts the electrical connection between the pixel circuit and the scan circuit, and the scan circuit outputs the gate drive signal to the pixel circuit.

[0008] Based on such a design, in the second state of the display, the scan circuit works normally and can output a gate control signal to the pixel circuit to control the light-emitting unit of the pixel circuit to emit light normally.

[0009] In a possible design, the switch circuit includes a first transistor. The first end of the first transistor is used to receive a first drive signal from a drive chip. The second end of the first transistor is electrically connected to a first signal source, and the third end of the first transistor is electrically connected to the reset unit.

[0010] In a possible design, the switch circuit includes a second transistor. The first end of the second transistor is used to receive a second drive signal from the drive chip. The second end of the second transistor is electrically connected to the output end of the scan circuit and the third end of the first transistor, and the third end of the second transistor is electrically connected to the pixel circuit.

[0011] In a possible design, when the display is in the first state, the scan circuit does not work. The drive chip outputs the first drive signal to control the first transistor to be in the conducting state, and the drive chip outputs the second drive signal to control the second transistor to be in the cut-off state. The first signal source inputs the reset unit of the pixel circuit to control the reset unit to output a reverse bias voltage to the light-emitting unit.

[0012] Based on such a design, the OLED can be in a bias state opposite to that during the display period during non-display, avoiding the deviation of the OLED device characteristics and improving the life of the OLED panel.

[0013] In a possible design, when the display is in the second state, the scan circuit works normally. The drive chip outputs the first drive signal to control the first transistor to be in the cut-off state, and the drive chip outputs the second drive signal to control the second transistor to be in the conducting state. The gate control signal output by the scan circuit is transmitted to the drive unit of the pixel circuit through the second transistor.

[0014] Based on such a design, in the second state of the display, the scan circuit can output a gate control signal to the pixel circuit to control the light-emitting unit of the pixel circuit to emit light normally.

[0015] In a possible design, the first transistor and the second transistor are of the same type, and the level states of the first driving signal and the second driving signal are opposite to each other.

[0016] In a possible design, the type of the first transistor is different from that of the second transistor, and the level states of the first driving signal and the second driving signal are the same.

[0017] In a possible design, the reset unit includes a third transistor. The first end of the third transistor is electrically connected to the node between the second end of the second transistor and the third end of the first transistor. The second end of the third transistor is electrically connected to the second signal source, and the third end of the third transistor is electrically connected to the light-emitting unit. When the display is in the first state, the first signal source is input to the first end of the third transistor, so as to control the third transistor to be in the conducting state, and the second signal source is used as the reverse bias voltage and transmitted to the light-emitting unit.

[0018] In a possible design, the reset unit further includes a fourth transistor. The first end of the fourth transistor is electrically connected to the third end of the second transistor or the node between the second end of the second transistor and the third end of the first transistor. The third end of the fourth transistor is electrically connected to the second signal source, and the second end of the fourth transistor is electrically connected to the third signal source.

[0019] Based on such a design, the OLED can be in a bias state opposite to that during the display period, thereby avoiding the deviation of the device characteristics of the OLED and improving the lifespan of the light-emitting element.

[0020] In a second aspect, an embodiment of the present application further provides a display, including: a driving chip for outputting a first driving signal and a second driving signal; and a plurality of the above-mentioned pixel driving circuits, each pixel driving circuit being electrically connected to the driving chip.

[0021] In a third aspect, an embodiment of the present application further provides an electronic device, including the display as described above.

[0022] By using the pixel driving circuit, the display, and the electronic device provided by the embodiments of the present application, during the non-display period, the light-emitting element is controlled to be in a bias state opposite to that during the display period, avoiding the deviation of the device characteristics of the light-emitting element and improving the panel lifespan of the light-emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic plan view of the display provided by the embodiment of the present application.

[0024] Figure 2 isFigure 1 Schematic diagram of the circuit structure of the pixel circuit shown in

[0025] Figure 3 Schematic diagram of the circuit structure of the pixel driving circuit according to an embodiment of the present application.

[0026] Figure 4 Another schematic diagram of the circuit structure of the pixel driving circuit according to an embodiment of the present application.

[0027] Figure 5 Signal timing diagram of the pixel driving circuit according to an embodiment of the present application during display.

[0028] Figure 6 Signal timing diagram of the pixel driving circuit according to an embodiment of the present application during non-display.

[0029] Figure 7 Another schematic diagram of the circuit structure of the pixel driving circuit according to an embodiment of the present application.

[0030] Figure 8 Schematic diagram of the structure of the electronic device according to an embodiment of the present application.

[0031] Description of main component symbols

[0032] Display 100

[0033] Gate lines GL, GL1, GL2... GLn-1, GLn

[0034] Data lines DL, DL1, DL2... DLm-1, DLm

[0035] Conductor lines CL, CL1, CL2... CLn-1, CLn

[0036] Pixel driving circuit 10

[0037] Substrate 11

[0038] Gate driver 12

[0039] Source driver 13

[0040] Light-emitting controller 14

[0041] Reset unit 151

[0042] Drive unit 152

[0043] Light-emitting control unit 153

[0044] Light-emitting unit 154

[0045] Switching circuit 20

[0046] Pixel circuit 30

[0047] Scanning circuit 40

[0048] First transistor T1

[0049] Second transistor T2

[0050] Third transistor T3

[0051] Fourth transistor T4

[0052] Fifth transistor T5

[0053] Sixth transistor T6

[0054] Seventh transistor T7

[0055] Eighth transistor T8

[0056] Ninth transistor T9

[0057] Capacitor Cst

[0058] Voltage signals ELVDD, ELVSS

[0059] Luminescence control signal Em

[0060] Gate drive signals SCAN(n), SCAN(n - 1)

[0061] Reset signal SCAN(n - 1)

[0062] Initial signal Vint

[0063] The following specific embodiments will further illustrate the present application in conjunction with the above - mentioned drawings. Specific embodiments

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application.

[0065] In the embodiments of the present application, terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. For example, the first application, the second application, etc. are used to distinguish different applications, rather than to describe a specific order of applications. Features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0066] In the description of the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0067] The display in the embodiments of the present application can be, for example, a smart terminal (such as a mobile phone), a portable office computer, a wearable device (such as a smart watch), or other devices with the function of displaying images. The display can be an active matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED) display, a micro-light emitting diode (Micro-LED) display, a quantum dot light emitting diode (QLED) display, etc. The above displays all emit light through the driving of a pixel driving circuit, and the process of the pixel driving circuit can be low-temperature poly-silicon (LTPS), low-temperature polycrystalline oxide (LTPO), etc. The embodiments of the present application take LTPS as an example for illustration.

[0068] Please refer to Figure 1 , which is a schematic structural diagram of a display 100 provided by an embodiment of the present application. In this embodiment, the display 100 may include a substrate 11, a gate driver 12, a source driver 13, and a light-emitting controller 14 disposed on the same surface of the substrate 11. The display 100 further includes a plurality of gate lines GL (including gate lines GL1-GLn), a plurality of data lines DL (including data lines DL1-DLm), and a plurality of conductive lines CL (including conductive lines CL1-CLn) disposed on the same surface of the substrate 11.

[0069] It can be understood that the multiple gate lines GL are arranged in parallel with each other on the substrate 11, the multiple data lines DL are arranged in parallel with each other on the substrate 11, the multiple conductive lines CL are arranged in parallel with each other on the substrate 11, the gate lines GL1 - GLn and the data lines DL1 - DLm are insulated and cross each other, and the gate lines GL1 to GLn and the conductive lines CL1 - CLn are parallel to each other. The gate driver 12 is electrically connected to the gate lines GL1 - GLn. The gate driver 12 is configured to output scan signals to the gate lines GL1 - GLn respectively. The source driver 13 is electrically connected to the data lines DL1 - DLm and is configured to output image data to the data lines DL1 - DLm respectively. The conductive lines CL1 - CLn are electrically connected to the light-emitting controller 14 and are configured to receive the light-emitting control signals output by the light-emitting controller 14 respectively.

[0070] The display 100 may further include a plurality of pixel circuits 30 disposed on the substrate 11. Taking Figure 1 this as a reference, the horizontal direction is defined as the row direction, and the vertical direction is defined as the column direction. Each gate line GL is electrically connected to the pixel circuits 30 arranged in the same row. Each data line DL is electrically connected to the pixel circuits 30 arranged in the same column, and each conductive line CL is electrically connected to the pixel circuits 30 arranged in the same row. Each pixel circuit 30 is electrically connected to two gate lines GL, one data line DL, and one conductive line CL. Each pixel circuit 30 is configured to drive the sub-pixels where it is located to display an image according to the gate line GL, data line DL, and conductive line CL to which it is electrically connected. In this embodiment, the two gate lines electrically connected to each pixel circuit 30 are two adjacent gate lines, and the signal output from one of the gate lines to the pixel circuit 30 can be used as the reset signal of the pixel circuit 10.

[0071] The display 100 operates in multiple display cycles, and the display 100 displays one frame of image in each display cycle.

[0072] Within one display cycle, the gate driver 12 sequentially outputs gate driving signals to the gate lines GL1 - GLn, and the source driver 13 simultaneously outputs image data to the data lines DL1 - DLm. When the gate driver 12 outputs a gate driving signal to the gate line GL1, the image data output from the source driver 13 to the data lines DL1 - DLm can be written into each pixel circuit 30 electrically connected to the gate line GL1, and the sub-pixels where each pixel circuit 30 electrically connected to the gate line GL1 is located are controlled to emit light.

[0073] In a display period, by sequentially outputting gate driving signals to gate lines GL1 - GLn, the pixel circuits 30 electrically connected to the gate lines GL1 - GLn are sequentially in a state capable of receiving image data, so that data lines DL1 - DLm can sequentially write the image data into the pixel circuits 30 electrically connected to each gate line GL, that is, the data lines DL1 - DLm can sequentially write the image data into the pixel circuits 30 of each row, and sequentially drive the sub - pixels of each row to emit light.

[0074] In this embodiment, each of the pixel circuits 30 is a pixel driving circuit with a 7T1C architecture (including 7 transistors and 1 capacitor). The structures of the pixel circuits 30 in the display 100 are basically the same. Figure 2 Only the structure of one of the pixel circuits 30 is shown for exemplary illustration. It can be understood that the "transistor" in the embodiments of the present application can be a three - terminal element including a gate, a source, and a drain.

[0075] Please refer to Figure 2 and Figure 3 , the pixel circuit 30 may include a reset unit 151, a driving unit 152, a light - emitting control unit 153, and a light - emitting unit 154.

[0076] The light - emitting unit 154 may include one or more light - emitting elements D1. The light - emitting element D1 may be a self - light - emitting element such as an Organic Light - Emitting Diode (OLED), a Micro - LED, etc. In this embodiment, the light - emitting unit 154 may include one OLED. The light - emitting unit 154 is used to emit light when receiving a driving current and may have different light - emitting intensities according to different magnitudes of the driving current. Specifically, the cathode of the light - emitting element D1 is used to receive a voltage signal ELVSS, and the anode of the light - emitting element D1 is electrically connected to the reset unit 151 and the light - emitting control unit 153.

[0077] One end of the reset unit 151 is electrically connected to the anode of the light - emitting element D1 and the light - emitting control unit 153, one end of the reset unit 151 is electrically connected to the driving unit 152, one end of the reset unit 151 can be used as an input port for a reset signal (i.e., a gate driving signal) SCAN(n - 1), and the other end of the reset unit 151 can be used as an input port for an initial signal Vint. The reset unit 151 is used to reset the driving unit 152 and the light - emitting unit 154 according to the received reset signal SCAN(n - 1) and the initial signal Vint.

[0078] The driving unit 152 is electrically connected to the data line DL and the gate line GL. The driving unit 152 can be configured to write the image data data output by the data line DL according to the gate driving signal output by the gate line GL, and to generate a driving current according to the image data data. It can be understood that in this embodiment, the driving current can be used to drive the light-emitting element D1 of the light-emitting unit 154 to emit light.

[0079] One end of the light-emitting control unit 153 is electrically connected to the light-emitting controller 14 through a wire 16. The light-emitting control unit 153 can be configured to receive the light-emitting control signal Em. The other end of the light-emitting control unit 153 is electrically connected to the driving unit 152 and the light-emitting unit 154. The light-emitting control unit 153 can be configured to drive the light-emitting element D1 in the light-emitting unit 154 to emit light according to the light-emitting control signal Em and the driving current.

[0080] In this embodiment, the driving unit 152 includes a first transistor T1, a second transistor T2, and a third transistor T3. The pixel circuit 30 may further include a capacitor Cst. The gate of the first transistor T1 is electrically connected to the reset unit 151. The source of the first transistor T1 is electrically connected to the drain of the second transistor T2. The drain of the first transistor T1 is electrically connected to the source of the third transistor T3. The gate of the second transistor T2 is connected to the gate line GLn to receive the gate driving signal SCAN(n). The source of the second transistor T2 is electrically connected to the data line DL to receive the image data output by the data line DL. The gate of the third transistor T3 is electrically connected to the gate line GLn to receive the gate driving signal SCAN(n). The drain of the third transistor T3 is connected between the gate of the first transistor T1 and the capacitor Cst.

[0081] In this embodiment, the light-emitting control unit 153 may include a fourth transistor T4 and a fifth transistor T5. The gates of the fourth transistor T4 and the fifth transistor T5 are both electrically connected to the light-emitting controller 14 and are configured to receive the light-emitting control signal Em output by the light-emitting controller 14. The source of the fourth transistor T4 can be configured to receive the voltage signal ELVDD and is electrically connected to the capacitor Cst. The drain of the fourth transistor T4 is electrically connected to the drain of the second transistor T2 and the source of the first transistor T1. The gate of the fifth transistor T5 is electrically connected to the light-emitting controller 14 to receive the light-emitting control signal Em output by the light-emitting controller 14. The source of the fifth transistor T5 is electrically connected to the drain of the first transistor T1. The drain of the fifth transistor T5 is electrically connected to the anode of the light-emitting element D1 in the light-emitting unit 154.

[0082] In the embodiment of the present application, the reset unit 151 may include a sixth transistor T6 and a seventh transistor T7. The gates of the sixth transistor T6 and the seventh transistor T7 are both electrically connected to the gate line GLn-1 to receive the gate driving signal SCAN(n-1) output by the gate line GLn-1 as a reset signal. The sources of the sixth transistor T6 and the seventh transistor T7 may both serve as input ports for the initial signal Vint. The drain of the sixth transistor T6 is electrically connected to the node between the gate of the first transistor T1 and the capacitor Cst. The drain of the seventh transistor T7 is electrically connected to the anode of the light-emitting element D1 in the light-emitting unit 154.

[0083] It can be understood that when the pixels in the nth row emit light, that is, the light-emitting element D1 in the pixel circuit 30 of the nth row can be in the light-emitting period. Since the anode voltage of the light-emitting element D1 is always greater than its cathode voltage, that is, the light-emitting element D1 is in a forward-biased state, it will affect the lifespan of the light-emitting element D1.

[0084] It can be understood that when the pixel circuit of the (n-1)th row is charging, the pixel circuit 30 of the nth row does not emit light. That is, the gate driving signal controls the sixth transistor T6 and the seventh transistor T7 to conduct, and charges the gate of the first transistor T1 to the Vint signal. Since the initial signal Vint charged to the gate of the first transistor T1 is small, the current generated by it is inconsistent with the current during normal light emission. Therefore, the fourth transistor T4 and the fifth transistor T5 need to be turned off. At this time, the seventh transistor T7 conducts, and the anode of the light-emitting element D1 can be charged to the initial signal Vint. Since the initial signal Vint is less than the voltage signal ELVSS, the light-emitting element D1 is in a reverse-biased state at this time, thereby avoiding the light-emitting element D1 from being in a forward-biased state for a long time and slowing down the lifespan attenuation of the light-emitting element.

[0085] In the above embodiment, for a display with n rows of pixel circuits, the light-emitting element D1 can be in a reverse-biased state only for 1 / n of the time, and in the forward-biased state at other times. As an example, for a display with a resolution of 1080*720 and a refresh rate of 60 Hz, the light-emitting element D1 is in a reverse-biased state only for 0.0232 ms within a frame time of 16.7 ms. In this application scenario, it has a great impact on the lifespan of the light-emitting element.

[0086] Please refer to Figure 4 , which is a schematic structural diagram of a pixel driving circuit 10 provided by an embodiment of the present application. The pixel driving circuit 10 provided by the embodiment of the present application can make the OLED in a bias state opposite to that during the display period during the non-display period, avoid the deviation of the OLED device characteristics, and improve the lifespan of the OLED panel.

[0087] Specifically, the pixel driving circuit 10 may include a scanning circuit 40, a switching circuit 20, and a plurality of pixel circuits 30. Among them, the plurality of pixel circuits 30 are electrically connected to the switching circuit 20, and each pixel circuit 30 can receive the gate driving signal output by the scanning circuit 40 through the switching circuit 20. Among them, the switching circuit 20 is used to receive the driving signal of the driving chip. In this embodiment, the gates of the sixth transistor T6 and the seventh transistor T7 are both electrically connected to the scanning circuit 40 of the previous row.

[0088] As Figure 4 shown, in the pixel circuit of the (n - 1)-th row, the scanning circuit 40 outputs a gate driving signal SCAN(n - 1). In the pixel circuit of the n-th row, the scanning circuit 40 outputs a gate driving signal SCAN(n). In the pixel circuit of the (n + 1)-th row, the scanning circuit 40 outputs a gate driving signal SCAN(n + 1).

[0089] In this embodiment, the switching circuit 20 in each row of pixel circuits may include an eighth transistor T8 and a ninth transistor T9.

[0090] The gates of the eighth transistor T8 and the ninth transistor T9 are both electrically connected to the driving chip. Specifically, the gate of the eighth transistor T8 can receive the driving signal SW1 of the driving chip, and the gate of the ninth transistor T9 can receive the driving signal SW2 of the driving chip. That is, the driving signals SW1 and SW2 can be used to control the states of the eighth transistor T8 and the ninth transistor T9 respectively.

[0091] The source of the eighth transistor T8 can be used to receive a reference voltage signal Vref, the drain of the eighth transistor T8 is electrically connected to the output terminal of the scanning circuit 40, and this output terminal can be used to output the gate driving signal. The source of the ninth transistor T9 is electrically connected to the drain of the transistor T8 and the output terminal of the scanning circuit 40. The drain of the ninth transistor T9 is electrically connected to the gates of the second transistor T2 and the third transistor T3 in the pixel circuit 30.

[0092] In this embodiment, in the pixel driving circuit 10 of the n-th row, the gates of the sixth transistor T6 and the seventh transistor T7 can be electrically connected to the node between the drain of the eighth transistor T8 and the source of the ninth transistor T9 in the pixel driving circuit of the (n - 1)-th row.

[0093] Please refer to Figure 5 , Figure 5 shows Figure 4 the signal timing diagram of the pixel driving circuit 10 during display.

[0094] It can be understood that in one embodiment, during the display of the pixel driving circuit 10 (i.e., the bright screen state), the voltage signal ELVDD and the driving signal SW1 are always in the high level state, and the voltage signal ELVSS, the initial signal Vint, and the driving signal SW2 are always in the low level state. For example, the voltage signal ELVDD can be a voltage signal of 3.5V all the time, so the driving signal SW1 can be a voltage signal of 6V all the time. The voltage signal ELVSS can be a voltage signal of -3.5V, the initial signal Vint can be a voltage signal of -4.5V, and the driving signal SW2 can be a voltage signal of -6V.

[0095] Under the control of the driving signal SW1, the eighth transistor T8 is in the cut-off state, and under the control of the driving signal SW2, the ninth transistor T9 is in the conducting state. Based on such a design, the scanning circuit 40 can work normally, that is, the scanning circuit 40 can output a gate driving signal. For example, the gate driving signal SCAN(n) can be output to the second transistor T2 and the third transistor T3 through the ninth transistor T9, so as to control the light-emitting element D1 in the pixel circuit 30 to emit light.

[0096] During the first stage t1, a light-emitting control signal having a first level (such as a high level) is provided (see EM), and a gate driving signal having a second level (such as a low level) is provided (see SCAN(n - 1)).

[0097] It can be understood that during the first stage t1, under the control of the light-emitting control signal, the fourth transistor T4 and the fifth transistor T5 are cut off, and under the control of the gate driving signal (i.e., the reset signal), the sixth transistor T6 and the seventh transistor T7 are conducting. At this time, the initial signal Vint acts on the anode of the light-emitting element D1 and the gate of the first transistor T1 to reset the anode of the light-emitting element D1 and the gate of the first transistor T1. Since the initial signal Vint is at a low level, the gate of the first transistor T1 is at a low level, and the first transistor T1 is conducting. During the first stage t1, the pixel driving circuit 10 can work in the reset stage. During the second stage t2, a light-emitting control signal and a gate driving signal having a first level (such as a high level) are provided (see SCAN(n - 1)), an image data signal having a first level (such as a high level) is provided (see Data), and a gate driving signal having a second level (such as a low level) is provided (see SCAN(n)).

[0098] During the second stage t2, under the control of the light emission control signal, both the fourth transistor T4 and the fifth transistor T5 are in the cut-off state. Under the control of the gate drive signal SCAN(n), the second transistor T2 and the third transistor T3 are turned on. Under the control of the gate drive signal SCAN(n - 1), the sixth transistor T6 and the seventh transistor T7 are in the cut-off state. Since the second transistor T2 and the third transistor T3 are turned on, the image data data output from the data line DL is written into the gate of the first transistor T1 through the second transistor T2 and the third transistor T3, that is, the gate of the first transistor T1 can be charged. During the charging of the gate of the first transistor T1, the capacitor Cst can maintain the potential of the gate of the first transistor T1. During the second stage t2, the pixel driving circuit 10 can operate in the data writing stage.

[0099] During the third stage t3, a light emission control signal having a second level (such as a low level) is provided. A gate drive signal (see SCAN(n - 1)) and a gate drive signal (see SCAN(n)) having a first level (such as a high level) are provided.

[0100] It can be understood that during the third stage t3, under the control of the light emission control signal, the fourth transistor T4 and the fifth transistor T5 are turned on. Under the control of the gate drive signal SCAN(n), the second transistor T2 and the third transistor T3 are in the cut-off state. Under the control of the gate drive signal SCAN(n - 1), the sixth transistor T6 and the seventh transistor T7 are in the cut-off state. Since the fourth transistor T4 is turned on, the voltage signal ELVDD can act on the source of the first transistor T1. Since both the third transistor T3 and the sixth transistor T6 are in the cut-off state, the gate of the first transistor T1 is in a floating state. Thus, the voltage holding Vgs (the voltage difference between the gate and the source of the first transistor T1) < the threshold voltage of the first transistor T1, and the first transistor T1 remains turned on to generate the drive current. Since the fifth transistor T5 is turned on, the drive current generated by the first transistor T1 acts on the light emitting element D1, and the light emitting element D1 emits light, that is, the pixel where the pixel circuit 30 is located emits light. Therefore, during the third stage t3, the pixel driving circuit 10 can operate in the light emission stage. It can be understood that the magnitude of the drive current can be proportional to the light emission intensity of the light emitting element D1.

[0101] As can be seen from the above, during the display, the pixel circuit 30 in this embodiment can sequentially operate in the reset period, the data writing period, and the light emission period.

[0102] Please refer to Figure 6 , Figure 6shows Figure 4 The signal timing diagram of the pixel driving circuit 10 during the non-display period.

[0103] It can be understood that during the non-display period of the pixel driving circuit 10 (i.e., the black screen state), only the voltage signal ELVSS, the initial signal Vint, the driving signal SW1, and the driving signal SW2 need to be provided to the pixel driving circuit 10.

[0104] The voltage signal ELVSS, the initial signal Vint, and the driving signal SW1 are always in the low level state, and the driving signal SW2 is always in the high level state. For example, the voltage signal ELVSS can always be a voltage signal of -3.5V, so the driving signal SW1 can always be a voltage signal of -6V. The initial signal Vint can be a voltage signal of -4.5V, and the driving signal SW2 can always be a voltage signal of 6V. The reference voltage signal Vref can always be a voltage signal of -6V.

[0105] It can be understood that during the non-display period, under the control of the driving signal SW1, the eighth transistor T8 is in the on state, and under the control of the driving signal SW2, the ninth transistor T9 is in the off state. Based on such a design, the scanning circuit 40 does not work, that is, the scanning circuit 40 does not output the gate driving signal, that is, the gate driving signal SCAN(n - 1) is not output to the gates of the sixth transistor T6 and the seventh transistor T7 in the nth row pixel circuit. The reference voltage signal Vref can be input to the gates of the sixth transistor T6 and the seventh transistor T7 in each pixel circuit 30 to control the sixth transistor T6 and the seventh transistor T7 to conduct. At this time, the initial signal Vint can be input to the anode of the light-emitting element D1. Since the initial signal Vint is -4.5V and the voltage signal ELVSS is -3.5V, that is, the initial signal Vint is less than the voltage signal ELVSS, a reverse bias is formed. Based on such a design, the light-emitting element D1 can be in a bias state opposite to that during the display period, thereby avoiding the deviation of the device characteristics of the light-emitting element and improving the lifespan of the light-emitting element.

[0106] It can be understood that in a possible embodiment, the driving chip can set the OLED reverse bias time during the non-display period according to the continuous light-emitting time of the OLED, that is, establish a functional relationship between the continuous light-emitting time of the OLED and the reverse bias time required when not emitting light. Thus, by adopting the embodiment of the present application, the OLED parameter characteristics can be accurately adjusted, and the deviation speed of the OLED device characteristics can be slowed down.

[0107] Please refer to Figure 7 , Figure 7The circuit structure diagram of the pixel driving circuit 10 provided by another embodiment of the present application is shown as follows.

[0108] Different from Figure 4 the embodiment of the pixel driving circuit 10 shown, as Figure 7 shown, in the pixel driving circuit 10 of the nth row in this embodiment, the gate of the seventh transistor T7 can be electrically connected to the node between the drain of the eighth transistor T8 and the source of the ninth transistor T9 in the pixel driving circuit of the (n - 1)th row. The gate of the sixth transistor T6 can be electrically connected to the node between the drain of the ninth transistor T9 and the pixel circuit 30 of the (n - 1)th row in the pixel driving circuit of the (n - 1)th row.

[0109] It can be understood that during the display period, Figure 7 the embodiment shown and Figure 4 the embodiment shown have the same working principle. During the non - display period, the driving signal SW1 controls all the eighth transistors T8 to be turned on, and the driving signal SW2 controls all the ninth transistors T9 to be turned off. In this embodiment, only the reference voltage signal Vref will be output to the gates of all the seventh transistors T7 in the pixel circuits 30, that is, only the seventh transistor T7 will be controlled to be turned on, and the sixth transistor T6 will not be controlled to be turned on. Based on such a design, the initial signal Vint can be input to the anode of the light - emitting element D1. Since the initial signal Vint is less than the voltage signal ELVSS, the OLED can be in a bias state opposite to that during the display period. Thereby, the device characteristics of the OLED can be prevented from shifting, and the lifespan of the light - emitting element can be improved.

[0110] In this embodiment, the eighth transistor T8 and the ninth transistor T9 can be transistors of the same type, and the driving signal SW1 and the driving signal SW2 are opposite signals. For example, the eighth transistor T8 and the ninth transistor T9 can both be P - type transistors or N - type transistors, and the driving signal SW1 and the driving signal SW2 are signals with opposite levels.

[0111] In another possible embodiment, the eighth transistor T8 and the ninth transistor T9 can be transistors of different types. For example, the eighth transistor T8 is an N - type transistor and the ninth transistor T9 is a P - type transistor, then the driving signal SW1 and the driving signal SW2 can be the same driving signal. Based on such a design, one of the eighth transistor T8 and the ninth transistor T9 can be controlled to be turned on, and the other can be controlled to be turned off.

[0112] Please refer to Figure 8, some embodiments of the present application further provide an electronic device 200, which may be a television, a laptop, a wearable device, etc., and the present application does not limit this. As Figure 8 shown, the electronic device 200 may include the display 100 described in the above embodiments.

[0113] Those of ordinary skill in the art of this technology should recognize that the above embodiments are only used to illustrate the present application, rather than to limit the present application. As long as within the substantial scope of the present application, appropriate changes and variations made to the above embodiments fall within the scope of protection required by the present application.

Claims

1. A pixel driving circuit is applied to a display. Characterized in that, the pixel driving circuit includes a switching circuit, a scanning circuit and a pixel circuit; the switching circuit is electrically connected between the pixel circuit and the scanning circuit, and is used to conduct or disconnect the electrical connection between the pixel circuit and the scanning circuit; the scanning circuit is used to output a gate driving signal to the pixel circuit; the pixel circuit includes a reset unit and a light-emitting unit, the reset unit is electrically connected to the switching circuit, and the reset unit is electrically connected to the light-emitting unit; when the display is in the first state, the switching circuit disconnects the electrical connection between the pixel circuit and the scanning circuit, and the switching circuit outputs a control signal to the reset unit; the reset unit outputs a reverse bias voltage to the light-emitting unit according to the control signal output by the switching circuit to control the light-emitting unit to be in a reverse bias state.

2. The pixel driving circuit according to claim 1, Characterized in that, when the display is in the second state, the switching circuit conducts the electrical connection between the pixel circuit and the scanning circuit, and the scanning circuit outputs the gate driving signal to the pixel circuit.

3. The pixel driving circuit according to claim 1 or 2, Characterized in that, the switching circuit includes a first transistor, a first end of the first transistor is used to receive a first driving signal of a driving chip, a second end of the first transistor is electrically connected to a first signal source; a third end of the first transistor is electrically connected to the reset unit.

4. The pixel driving circuit according to claim 3, Characterized in that, the switching circuit includes a second transistor, a first end of the second transistor is used to receive a second driving signal of the driving chip, a second end of the second transistor is electrically connected to an output end of the scanning circuit and a third end of the first transistor; a third end of the second transistor is electrically connected to the pixel circuit.

5. The pixel driving circuit according to claim 4, Characterized in that, when the display is in the first state, the scanning circuit does not work, the driving chip outputs the first driving signal to control the first transistor to be in a conducting state, the driving chip outputs the second driving signal to control the second transistor to be in a cut-off state, and the first signal source inputs the reset unit of the pixel circuit to control the reset unit to output a reverse bias voltage to the light-emitting unit.

6. The pixel driving circuit according to claim 4, Characterized in that, when the display is in the second state, the scanning circuit works normally, the driving chip outputs the first driving signal to control the first transistor to be in a cut-off state, the driving chip outputs the second driving signal to control the second transistor to be in a conducting state, and the gate control signal output by the scanning circuit is transmitted to the driving unit of the pixel circuit through the second transistor.

7. The pixel driving circuit according to any one of claims 4-6, Characterized in that, The first transistor and the second transistor are transistors of the same type, and the level states of the first driving signal and the second driving signal are opposite to each other.

8. The pixel driving circuit according to any one of claims 4-6, characterized in that the type of the first transistor is different from that of the second transistor, and the level states of the first driving signal and the second driving signal are the same.

9. The pixel driving circuit according to any one of claims 4-6, characterized in that the reset unit includes a third transistor. A first end of the third transistor is electrically connected to a node between a second end of the second transistor and a third end of the first transistor. A second end of the third transistor is electrically connected to a second signal source. A third end of the third transistor is electrically connected to the light-emitting unit; When the display is in a first state, the first signal source is input to the first end of the third transistor, so as to control the third transistor to be in a conducting state, and the second signal source is used as the reverse bias voltage and transmitted to the light-emitting unit.

10. The pixel driving circuit according to claim 9, characterized in that the reset unit further includes a fourth transistor. A first end of the fourth transistor is electrically connected to a third end of the second transistor or a node between a second end of the second transistor and a third end of the first transistor. A third end of the fourth transistor is electrically connected to the second signal source. A second end of the fourth transistor is electrically connected to a third signal source.

11. A display, characterized in that it includes: a driving chip for outputting a first driving signal and a second driving signal; a plurality of pixel driving circuits according to any one of claims 1-10, and each pixel driving circuit is electrically connected to the driving chip.

12. An electronic device, characterized in that it includes the display according to claim 11.

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