Logical remapping technology

Abstract

The present application relates to logical remapping technology. A memory system may receive a write command to store information at a first logical address in the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address to a first physical address storing the information. The memory system may perform a defragmentation operation or other remapping operation. During such a defragmentation operation, the memory system may remap the first logical address to a second logical address such that the second logical address is mapped to a first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address to the second logical address.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 399,406, filed by PARRY et al. on August 11, 2021, entitled “LOGIC REMAPPING TECHNIQUES,” which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to logic remapping technology. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, consumer devices, cameras, digital displays, or other devices. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receive a write command to store information at a first logical address associated with the device; based at least in part on receiving the write command, generate a first entry of a logical-to-physical mapping that maps the first logical address to a first physical address of the device storing the information; as part of a defragmentation operation, generate a second entry of the logical-to-logical mapping that maps the first logical address to a second logical address associated with the information stored at the first physical address after the defragmentation operation; and based at least in part on generating the second entry, generate a third entry of the logical-to-physical mapping that maps the second logical address to an indication of the first physical address as part of the defragmentation operation.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a write command to store information at a first logical address associated with a memory system; based at least in part on receiving the write command, generate a first entry of a logical-to-physical map that maps the first logical address to a first physical address of the memory system storing the information; as part of a defragmentation operation, generate a second entry of the logical-to-logical map that maps the first logical address to a second logical address associated with information stored at the first physical address after the defragmentation operation; and based at least in part on generating the second entry, generate a third entry of the logical-to-physical map that maps the second logical address to an indication of the first physical address as part of the defragmentation operation.

[0008] A method is described. The method may include receiving a write command to store information at a first logical address associated with a memory system; based at least in part on receiving the write command, generating a first entry of a logical-to-physical map that maps the first logical address to a first physical address of the memory system where the information is stored; generating, as part of a defragmentation operation, a second entry of the logical-to-logical map that maps the first logical address to a second logical address associated with information stored at the first physical address after the defragmentation operation; and generating, based at least in part on generating the second entry, a third entry of the logical-to-physical map that maps the second logical address to an indication of the first physical address as part of the defragmentation operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting logic remapping techniques according to examples as disclosed herein is shown.

[0010] Figure 2 An example of a system supporting logic remapping techniques according to examples as disclosed herein is shown.

[0011] Figure 3 An example of a mapping scheme supporting logic remapping techniques according to examples as disclosed herein is shown.

[0012] Figure 4 An example of a mapping scheme supporting logic remapping techniques according to examples as disclosed herein is shown.

[0013] Figure 5 An example of a process flow supporting logic remapping techniques according to examples as disclosed herein is shown.

[0014] Figure 6 A block diagram of a memory device supporting logic remapping techniques according to examples as disclosed herein is shown.

[0015] Figure 7 A flowchart illustrating one or more methods of supporting logic remapping techniques according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0016] The memory devices of the memory system may store data at physical addresses. For example, the memory system may receive a write command that instructs the memory system to write data in one or more memory devices. The write command may include a logical address for storing the data, which may be different from the physical address for storing the data. The memory system may store the data at a physical location of the memory device corresponding to the physical address. In some cases, the physical or logical location of the data within the memory device may change over time due to the writing of additional data to the memory device, maintenance operations performed by the memory device (e.g., garbage collection operations), or other reasons. In some instances, the host system or the memory system may perform a defragmentation operation to improve system performance. For example, the defragmentation process may include reorganizing the logical addresses of one or more files in a continuous logical address space (rather than scattering these logical addresses throughout the entire logical address space), which may improve performance and storage density in the system.

[0017] In some cases, a host system coupled to a memory system may reference data using a logical address (e.g., a logical block address (LBA), a virtual address, a system address, or other logical address) (e.g., if a read, write, or other command associated with the data is issued), and the memory system may generate and maintain a mapping between the logical address associated with the data and the physical address of the memory unit storing the data. The memory system may store the mapping between the logical address and the physical address in a map or table (e.g., a logical-to-physical (L2P) map or L2P table), which may be updated if a change is made to the logical or physical address. As an example, the host system or the memory system may assign a new logical address to the data (e.g., as part of a defragmentation operation, the memory system may relocate the logical address to a new logical address). In some such instances, the host system or the memory system may also rewrite the data to the new physical address, for example, to maintain the accuracy of the L2P table and avoid internal inconsistencies with metadata stored at the physical address of the data. However, relatively frequent rewriting of data between physical addresses may increase latency, increase power consumption, and may reduce the life of the memory system.

[0018] Thus, the techniques described in this disclosure provide a logical-to-logical (L2L) mapping or L2L table for a memory system. In addition to or as an alternative to an L2P table, a memory system may use an L2L table (e.g., an L2L mapping) to support remapping of logical addresses using a defragmentation operation. In some instances, the L2L table may be used to remap logical addresses without having to write data to new physical addresses in the memory system. For example, a memory system having an L2P table may undergo a defragmentation operation to change one or more L2P entries (e.g., L2P pointers) of the L2P table that map logical addresses (used by the host system) to physical addresses (used by the memory system). In such instances, for example, as part of a defragmentation operation performed on a file system, in response to a host command (e.g., a move command), the memory system may change the logical address of the data to a new logical address in the L2P table. The memory system may generate an entry of an L2L table that maps a first logical address to a second logical address, the first logical address being associated with information stored at the physical address before the defragmentation operation, and the second logical address being associated with information stored at the physical address after the defragmentation operation. Thus, the memory system may use the L2L table to maintain an up-to-date mapping of logical and physical addresses without having to rewrite data to a new physical address. For example, some memory systems may perform a defragmentation operation by issuing multiple read and write commands to not only move data to a new logical address, but also cause the data to be moved to a new physical address as well. Recording the changed logical address in the L2L table may enable the memory system to successfully verify metadata (e.g., using the first logical address that generated the metadata when the data was stored) without having to rewrite the data to the data's new physical address.

[0019] In some instances, a memory system may receive a command to read an L2P entry, which may point directly to a physical address or may point to an entry in an L2L table. In instances where the L2P entry points to a physical address, in some instances, the memory system may use the L2L table to verify that the metadata stored at the physical address matches the logical address. For example, an indication of the logical address associated with the physical address may be included in the metadata. If the logical address in the L2P mapping changes, the metadata may remain unchanged, which may result in a mismatch between the logical address indicated in the L2P table and the logical address indicated in the metadata. In instances where the L2P entry points to an L2L table (e.g., a reference to a physical address), the memory system may use the L2L table to verify that the metadata stored at the physical address matches the logical address. Figure 4In an example of an entry in an L2L table (described in the preceding example), the memory system can use the L2L table to identify the physical address for retrieving data and also verify the metadata (e.g., metadata that matches a previous logical address rather than the current logical address). In some cases, the memory system can use the first logical address (e.g., associated with information stored at the physical address before defragmentation) to verify the metadata. These techniques can enable the memory system to maintain an up-to-date mapping between logical and physical addresses and extend the life of the memory device, among other benefits.

[0020] In some examples, the memory system may utilize or update the L2L table during garbage collection operations. For example, the memory system may search the L2L table during garbage collection or in response to other criteria (e.g., if a mismatch in metadata is detected or during error handling). Additionally or alternatively, the memory system may maintain a bitmap of physical addresses that have been remapped from a first logical address to a second logical address (e.g., physical addresses containing entries in the L2L table). In some examples, the memory system may include a counter that indicates the number of remapped locations in a memory block (e.g., a virtual block). In such examples, the memory system may prioritize garbage collection in blocks associated with relatively high numbers indicated by the corresponding counters (e.g., the memory system may perform garbage collection in response to a counter that satisfies a threshold or indicates the highest number of remapped addresses).

[0021] The features of this disclosure are initially described in reference Figures 1 to 2 The features of the present disclosure are described in the context of systems, devices and circuits. Figures 3 to 5 These and other features of the present disclosure are described in the context of the mapping scheme and processing flow of FIG. Figures 6 to 7 The present invention is further illustrated and described in the context of device diagrams and flow charts involving logic remapping techniques.

[0022] Figure 1 An example of a system 100 supporting logic remapping techniques according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110.

[0023] The memory system 110 may be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0024] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0025] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, such coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG, but the host system 105 may be coupled to any number of memory systems 110.

[0026] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110 or otherwise supported between them. In some examples, the host system 105 may be coupled to the memory system 110 via a corresponding physical host interface of each memory device 130 included in the memory system 110, or via a corresponding physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0027] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of FIG, but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0028] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130, as well as other such operations, which can generally be referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data (e.g., in response to or otherwise associated with commands from the host system 105) with the host system 105 and one or more memory devices 130. For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0029] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0030] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0031] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that can store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, e.g., related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can serve as a cache for the memory system controller 115. For example, if the data is read from or written to the memory device 130, the data can be stored in the local memory 120, and the data can be made available within the local memory 120 to the host system 105 (e.g., with reduced latency relative to the memory device 130) for subsequent retrieval or manipulation (e.g., updating) according to the cache policy.

[0032] although Figure 1 The example of the memory system 110 in FIG. 1 has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. Generally speaking, in some cases, one or more functions attributed herein to the memory system controller 115 may alternatively be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0034] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown, memory device 130 - a may include a local controller 135 - a , and memory device 130 - b may include a local controller 135 - b .

[0035] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic device-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0036] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0037] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, as long as different blocks 170 are in different planes 165, concurrent operations may be performed on memory cells within different blocks 170. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, concurrent operations in different planes 165 may be subject to one or more restrictions, such as concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0038] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which can alternatively be referred to as a bit line).

[0039] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0040] In some cases, to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise designate the data remaining in the old block 170 as invalid or obsolete and may update the L2P mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block 170, for example, due to latency or loss considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory location of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0041] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page-level granularity, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that has become outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by the host system 105). Valid data may be the latest version of such data stored on the memory device 130. A page 175 containing no data may be a page 175 that has never been written to or has been erased.

[0042] In some cases, the memory system controller 115 or the local controller 135 may perform operations for the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that includes, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105 ).

[0043] The system 100 may include any number of non-transitory computer-readable media that support the logic remapping techniques. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if such instructions are executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), the instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0044] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a MNAND system.

[0045] System 100 may support an L2L table as described herein. For example, in addition to or in lieu of an L2P table, memory system 110 (or host system 105) may use an L2L table (e.g., an L2L map) to support remapping of logical addresses as part of a defragmentation operation, e.g., without rewriting data to new physical addresses. For example, host system 105 may update one or more logical addresses (e.g., host system 105 may perform a defragmentation operation to remap logical addresses of one or more files or data in a contiguous logical space) without rewriting the data in the physical space to new physical addresses in memory system 110, which may increase defragmentation speed and reduce media wear. In some examples, host system 105 may include or be referred to as a file system. Memory system 110 may generate an entry in an L2L table that maps a first logical address (e.g., mapped to a physical address before the update) to a second logical address (e.g., mapped to a physical address after the update). Thus, the memory system 110 can use the L2L table to maintain an up-to-date mapping of logical and physical addresses without using read and write commands to remap logical addresses. For example, recording a changed logical address in the L2L table can enable the memory system to successfully verify metadata (e.g., using the first logical address that generated the metadata when the data was stored) without having to rewrite the data to a different physical address, among other benefits. That is, an entry in the L2P table can map a second logical address to an indication of a first physical address. In some instances, the indication of the first physical address can be a pointer to an L2L table that contains a pointer to the first physical address.

[0046] Additionally or alternatively, the system 100 may maintain one or more bitmaps indicating physical addresses corresponding to remapped logical addresses, one or more counters indicating the number of remapped locations in the corresponding block 170, or any combination thereof.

[0047] Figure 2 An example of a system 200 supporting logic remapping techniques according to an example disclosed herein is shown. The system 200 may be as described in reference Figure 1 or an example of the system 100 described in its aspects. The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement the system 100 described in reference Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0048] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, for example, in response to receiving an access command from the host system 205, as described herein. The memory device 240 may include a memory device 240 as described in reference to Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0049] The memory system 210 may include a memory controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The memory controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple memory controllers 230, such as a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a method as described in reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0050] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to convert data between the host system 205 and the memory device 240, e.g., as shown by data path 250, and may be collectively referred to as data path components.

[0051] Using buffer 225 to temporarily store data during transfers allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes to be associated with commands. This can also allow bursts of commands to be processed, and once the burst stops, the buffered data can be stored or transferred (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM) or a hardware accelerator, or both, to allow for rapid storage and retrieval of data in and out of buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0052] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during the execution of an access command. That is, after an access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten with data from another access command). Furthermore, buffer 225 may be a non-cacheable buffer. That is, data cannot be directly read from buffer 225 by host system 205. For example, a read command may be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., without requiring a cache address match).

[0053] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 may be a memory system controller 215 such as that described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used for communication between system components.

[0054] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and store queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if more than one access command from host system 205 is being processed simultaneously by memory system 210. Command queue 260, buffer queue 265, and store queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively, as examples of possible implementations. However, queues, if used, may be located anywhere within memory system 210.

[0055] Data transferred between the host system 205 and the memory device 240 may take a different path within the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 via data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0056] If the host system 205 transmits an access command to the memory system 210, the command may be received by the interface 220, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). Therefore, the interface 220 may be considered the front end of the memory system 210. Upon receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 for transmission to the memory system controller 215.

[0057] The memory system controller 215 may determine that an access command has been received upon receiving a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0058] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0059] In either case, the memory system controller 215 can use the buffer 225 to temporarily store data received from or sent to the host system 205, as well as for other purposes. The buffer 225 can be considered the middle of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) can be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0060] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0061] In some cases, the buffer queue 265 can be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can contain access commands associated with the data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved to the buffer queue 265 by the memory system controller 215 and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address in the buffer 225. That is, a pointer can be maintained indicating where the data associated with each command is stored in the buffer 225. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205, and at least some of the access commands can be processed in parallel.

[0062] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 can cause the interface 220 to transmit an indication of availability (e.g., a "ready to transfer" indication) to the host system 205, for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 can use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 can obtain the location of the data stored in the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 can indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0063] Once the write data has been stored in buffer 225 via interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve the data out of buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered the back end of memory system 210. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, that the data transfer to memory device 240 has been completed.

[0064] In some cases, storage queue 270 may be used to assist in the transfer of write data. For example, memory system controller 215 may push a write command from buffer queue 265 (e.g., via bus 235) to storage queue 270 for processing. Storage queue 270 may include an entry for each access command. In some examples, storage queue 270 may additionally include: a buffer pointer (e.g., an address) that may indicate where in buffer 225 the data associated with the command is stored; and a storage pointer (e.g., an address) that may indicate the location associated with the data in memory device 240. In some cases, storage controller 230 may obtain the location within buffer 225 from which the data is obtained from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 may manage the locations within memory device 240 to store data (e.g., to perform wear leveling, garbage collection, or other operations). These entries may be added to storage queue 270, for example, by memory system controller 215. When the transfer of data is complete, the entry is removed from the store queue 270 , for example, by the memory controller 230 or the memory system controller 215 .

[0065] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0066] In some cases, the buffer queue 265 can be used to assist in buffer storage of data associated with a read command in a similar manner as discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 can indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0067] In some cases, storage queue 270 can be used to assist in the transfer of read data. For example, memory system controller 215 can push read commands to storage queue 270 for processing. In some cases, storage controller 230 can obtain the location within memory device 240 from which to retrieve data from buffer 225 or storage queue 270. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from buffer queue 265. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from storage queue 270. In some cases, memory system controller 215 can move commands processed by storage queue 270 back to command queue 260.

[0068] Once the data has been stored in the buffer 225 by the memory controller 230, the data can be transferred from the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). For example, the interface 220 can process commands from the command queue 260 and can indicate to the memory system controller 215, for example, via the bus 235, that the data transfer to the host system 205 has been completed.

[0069] The memory system controller 215 may execute the received commands in an order (e.g., a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may cause the data corresponding to the command to be moved into and out of the buffer 225, as discussed above. As the data is moved into and stored in the buffer 225, the command may remain in the buffer queue 265. If processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of the buffer 225), the command may be removed from the buffer queue 265, for example, by the memory system controller 215. If a command is removed from the buffer queue 265, the address where the data associated with the command was previously stored may be used to store data associated with a new command.

[0070] The memory system controller 215 may be further configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230, and the storage controller 230 may be omitted.

[0071] The system 200 may support an L2L table as described herein. For example, in addition to or in lieu of an L2P table, the memory system 210 (or the host system 205) may use an L2L table (e.g., an L2L mapping) to support remapping of logical addresses without rewriting the data to a different physical address. For example, the system 200 may update one or more logical addresses (e.g., the host system 205 may perform a defragmentation operation to rewrite one or more files or data in a continuous logical space) without rewriting the data in the physical space, which may increase defragmentation speed and reduce media wear. The memory system may generate an entry in the L2L table that maps a first logical address (e.g., mapped to a physical address before the update) to a second logical address (e.g., mapped to a physical address after the update). Thus, the memory system may use the L2L table to maintain an up-to-date mapping of logical and physical addresses without requiring frequent physical remapping. For example, recording changed logical addresses in the L2L table can enable the memory system to successfully verify metadata (e.g., using the first logical address that generated the metadata when the data was stored) without having to rewrite the physical address of the data, among other benefits. In some examples, the L2L table can be such as reference Figure 4 Additionally or alternatively, system 200 may maintain one or more bitmaps indicating physical addresses corresponding to remapped logical addresses, one or more counters indicating the number of remapped locations in a corresponding block, or any combination thereof.

[0072] Figure 3 An example of a mapping scheme 300 that supports logical remapping of a memory system according to an example disclosed herein is shown. The mapping scheme 300 may be as described in reference Figure 1 and 2 The mapping scheme 300 may include a user area 335 , a first L2P table 325 - a , a second L2P table 325 - b , and an L2L table 320 .

[0073] User area 335 may be an example of a physical storage device for user data (or other data) of a memory system as described herein (e.g., memory system 110). For example, user area 335 may include die 310-a, die 310-b, a set of planes 315 (e.g., Figure 3 In the example of FIG. 3 , for the corresponding die 310, represented as 0, 1, 2, and 3) and page 305, they can be as referenced herein. Figure 1 and 2 Examples of dies, planes, and pages are described in detail below. Each sector of user area 335 (e.g., an example of a sector or location may be die 0, plane 1, page 4) may correspond to a physical address of the stored information. That is, the physical address may be a physical location in user area 335 where the corresponding information is stored. The information stored in the physical address may be associated with an LBA.

[0074] In some cases, the memory system may receive an access command (e.g., a read or write command, among other examples of commands) to write or read data on an associated LBA. For example, a host system may send a write command to store data at an LBA associated with the memory system. The memory system may write the data to a physical location in the user area 335 and store the correspondence (e.g., mapping) between the LBA and the physical location in an L2P table. Thus, if the memory system receives a read command for an LBA, the memory system may refer to the L2P table to identify the physical location and, in response to the read command, retrieve the data from the indicated physical address.

[0075] In some instances, a memory system may generate metadata for information (e.g., if the information is stored as part of a write operation) and store the metadata along with the data at a physical location in the memory system. For example, the memory system may use the physical location, LBA, data, or any combination thereof to generate metadata. Metadata may be an example of an attribute associated with the stored data (e.g., the time the data was stored, the type of data, the physical or logical location of the data, etc., among other examples of metadata). A memory system may store metadata to improve the reliability of the data. For example, a memory system may read data (e.g., information) as part of a read command and compare the metadata with one or more attributes of the data. In some cases, the metadata may include a logical address associated with the data (at least initially). During a read operation, the memory system may compare the logical address included in the read command with the logical address included in the metadata as a verification check that the read data is correct. If the logical addresses do not match, the memory system may indicate to the host system that the read command failed. If the metadata matches one or more attributes (e.g., the logical or physical location of the data matches an indication of the location pointed to by the L2P table), the memory system can determine that the read data is correct (e.g., the correct location was read, the data does not contain errors or a correctable amount of errors, etc.) and can transfer the data to the host system.

[0076] In some instances, the memory system may perform operations that may result in remapping one or more entries of the L2P table. For example, the host system or the memory system may perform a defragmentation operation. Defragmentation may involve reorganizing data files in logical space (e.g., changing the logical addresses assigned to data stored at physical addresses) to have contiguous data sets, which may improve the efficiency of the host system (e.g., reduce latency) and other benefits. The host system may use the defragmentation operation to create more contiguous groups of logical addresses, thereby improving performance. In some systems, as part of the defragmentation operation, the host system may issue read and write commands. For example, if the host system wishes to remap a logical address, it may issue a read command to read data from that logical address, and then issue a write command to write the data to a different logical address. Such operations may also result in data being stored at a new physical address. The number of read and write commands as part of the defragmentation operation may take time, consume power, and may increase wear on memory cells, thereby reducing the performance of the memory system and shortening the operating life of the memory system.

[0077] Additionally or alternatively, the memory system may perform as described herein with reference to Figure 1 and 2Defragmentation may be similar to garbage collection (e.g., in that they both involve changing file storage to improve system efficiency), but garbage collection may involve removing (e.g., deleting) obsolete data to free up space at physical addresses, while defragmentation may involve reorganizing data at logical addresses, e.g., to store files contiguously in the logical address space.

[0078] As an illustrative example, as part of a defragmentation operation or some other operation, the memory system may assign new logical addresses to the data. In some cases, the memory system may also rewrite the data to a new physical address, for example, to maintain the accuracy of the L2P table 325-b and avoid inconsistencies between the L2P table 325-b and the metadata generated using the physical address. In order for the memory system to correctly perform read operations (e.g., reliably access the correct physical address after reading a command that references the corresponding logical address), the memory system may keep both the L2P map and the metadata up to date after the defragmentation operation. Updating the L2P map and metadata may involve computational overhead and, in some cases, physical wear on the memory system (e.g., due to relatively frequent rewriting of physical data). Therefore, without changing the physical addresses of the data stored on the NAND memory, the efficiency of the memory system in performing defragmentation operations may be improved.

[0079] In addition to or as an alternative to the L2P table 325, the memory system may implement the L2L table 320 as described herein. For example, the memory system may use the L2P table 325 to maintain a mapping between logical addresses and physical addresses. Figure 3 In the example of , L2P table 325-a may show an L2P table before a remapping operation (e.g., a defragmentation operation), and L2P table 325-b may show an L2P table after the remapping operation (e.g., for clarity of illustration, L2P table 325-a and L2P table 325-b may be the same L2P table shown at different times). L2P table 325 may be as shown in reference Figure 1 and 2 3. An example of an L2P table is described. For example, L2P table 325 may map LBAs to physical block addresses (PBAs) (e.g., L2P table 325 may include a pointer to a physical address at user area 335). Each entry in L2P table 325 may include a logical address and a pointer to a physical address, thereby mapping stored information to its corresponding logical and physical addresses. For example, an entry in L2P table 325-a (e.g., entry P.Ai) and an entry in L2P table 325-b (e.g., entry P.Aj) may point to the same physical address (e.g., physical block 340), but the physical address may be mapped to different logical addresses (e.g., denoted as i and j, respectively).

[0080] In some cases, the memory system may use the L2L table 320 to map logical addresses in the L2P table 325-a before a defragmentation operation (or other operation) to logical addresses in the L2P table 325-b after the defragmentation operation, or to otherwise indicate a correspondence between logical addresses in the L2P table 325-a before a defragmentation operation (or other operation) and logical addresses in the L2P table 325-b after the defragmentation operation. The L2L table 320 may support remapping of logical addresses and improve the efficiency of the memory system by recording information in an auxiliary table. Each row of the L2L table 320 (e.g., each row may be a record 345-a indicating a logical remapping) may describe a correspondence between two logical addresses or between two logical ranges.

[0081] As an example, Figure 3 The illustrated L2L table 320 may have three columns (although any other format or table layout for storing the correspondence between two logical addresses may be used). In this example, the first column (i.e., column "A") may correspond to the logical address before the remapping operation (e.g., the logical address of the L2P table 325-a before the defragmentation operation), and the second column (i.e., column "B") may correspond to the logical address after the remapping operation (e.g., the logical address of the L2P table 325-b after the defragmentation operation). In some examples, the L2L table 320 may include a third column (i.e., column "N") that indicates a length parameter associated with the corresponding record. That is, the third column may indicate the number of logical blocks between the starting logical address indicated in column "A" (e.g., the starting address of the L2P table 325-a for the logical block) and the starting logical address indicated in column "B" (e.g., the starting address of the L2P table 325-b for the logical block after the defragmentation operation). As an example, during a defragmentation operation, multiple LBAs may be moved together (e.g., from the same first starting location to the same second starting location) and, therefore, may be included together in one entry of the L2L table. Tracking this information in the N columns of the L2L table 320 may enable the memory system to compress the L2L table 320. For example, a separate entry in the L2L table is not required for each logical address that is remapped. Instead, consecutive logical addresses may be remapped as a unit to a different set of consecutive logical addresses.

[0082] In some cases, each row of L2L table 320 may be or indicate a record 345-a corresponding to a remapped logical address of user area 335. As an illustrative example, the last entry of L2P table 325-a may be remapped to the last entry of L2P table 325-b during a defragmentation operation (e.g., physical block 340 may correspond to first LBA i at a first time and second LBA j at a second time without being physically rewritten). Based on this remapping, the memory system may generate an entry of L2L table 320, such as record 345-d, indicating the remapping. For example, record 345-d may include Ai (e.g., the starting address of data stored at 340 for L2P table 325-a), Ni (e.g., the number of logical blocks or other data units stored at 340), and Bi (e.g., the starting logical address for the update of L2P table 325-b). In other words, in this example, if the host system moves a range of N logical blocks from starting address A to starting address B, an entry (eg, record 345 - d ) may be added to the list to record these three numbers.

[0083] The memory system may use one or more algorithms or operations to search the L2L table 320. In some examples, the memory system may search the L2L table 320 in response to receiving an access command (e.g., a read command). The memory system may determine whether a received logical address "X" (e.g., received as part of a read command) is included in the range of LBAs indicated by the L2L table 320. For example, for each incoming read command on LBA "X", the memory system may search the table for a record 345-a indicating that LBA X is an address that has been remapped, so the previous address (e.g., in the "A" column) can be used to verify the metadata. As an example of a search algorithm, for LBA X, the memory system may determine whether B i ≤X≤B i +N i , where B iRepresents any LBA in the "B" column, and N represents the corresponding length of the remapped logical block corresponding to the entry in the B column. If the memory system determines that the searched logical address is within the range of entries in the L2L table, the memory system may use the table to determine the logical address after the defragmentation operation. For example, the memory system may search the L2L table 320 for a record of the received logical address and may use the corresponding information (e.g., address A before the remapping operation) to verify the metadata. In some instances, during error handling and garbage collection or other instances of triggers or any combination thereof, if a mismatch between stored metadata and one or more attributes of the data is detected, an algorithmic search may be run. By running the algorithm in response to such criteria, the memory system may reduce the number of searches performed, which may improve performance (e.g., space efficiency, load time) of some types of devices (e.g., managed NAND (MNAND) devices with limited static random access memory (SRAM)).

[0084] In some cases, during garbage collection, a normalization algorithm may be used to search the L2L table 320. For example, the memory system may search the pivot table (PVT) to initiate garbage collection at a memory cell. The garbage collector may copy data from a physical source block (e.g., physical block 340) and retrieve logical address information from the metadata. In some cases, the memory system may flush the change log and may discover differences between the logical addresses of the metadata and the logical addresses of the change log.

[0085] In some cases, the memory system may use a search algorithm during garbage collection to resolve this mismatch. In some cases, if garbage collection is performed during idle time, the memory system may search the L2L table 320 for garbage collection. For example, the memory system may search the L2L table for each source block to update the mapping. In some cases, such as if garbage collection is triggered in the foreground of the memory system, the memory system may perform a search method with reduced overhead. For example, the memory system may generate and / or maintain a bitmap of remapped physical addresses, which may enable the memory system to search the L2L table 320 if the bitmap indicates that one or more addresses of a source block have been remapped.

[0086] For example, the bitmap may include one bit per PBA. In some cases, other granularities may be used, such as one bit per page, superpage, wordline, or other amount of physical memory. The memory system may use a higher-level table with pointers to virtual base (VB) bitmaps to be loaded or referenced during garbage collection. For example, the memory system may store the bitmap and table in SRAM, or in some other cache or volatile memory device. As an illustrative example of a bitmap, each page 305 of the user area 335 may correspond to a bit of the bitmap. If a page is logically remapped (e.g., physical block 340 is updated from LBA "i" in L2P table 325-a to "j" in L2P table 325-b), the memory system may store an indication (e.g., a 1 or 0) in the corresponding bit. Therefore, in response to the memory system performing garbage collection on a source block, the memory system may use the L2L table entry to update metadata in response to the bit indicating that at least a portion of the source block has been remapped.

[0087] Additionally or alternatively, the memory system may maintain a counter of the number of remapped locations. The counter may be used to prioritize garbage collection in the most frequently remapped areas of the memory. As an example, the counter may correspond to a portion of the user area (e.g., the counter may be per block, per page, per superpage, per wordline, or other amount of physical memory). The memory system may increment the counter each time a remapping of a corresponding portion of the user area 335 is remapped. If garbage collection is performed, the memory system may prioritize areas with relatively high counters. For example, if a counter meets a threshold, the memory system may perform garbage collection in response to the threshold being met, or if garbage collection is performed, the memory system may identify the highest counter or counters (e.g., relative to each counter in the source block) and update metadata or otherwise perform garbage collection on the area corresponding to the highest counter or counters.

[0088] Figure 4 An example of a mapping scheme 400 that supports logical remapping of a memory system according to an example disclosed herein is shown. The mapping scheme 400 may be as described in reference Figure 1 and 2 The mapping scheme 400 may include a user area 435 and an L2P table 425, which may be as described in reference to FIG. Figure 3 3. For example, user area 435 may include dies 405-a and 405-b, plane 410, page 415, and physical block 440, which may be Figure 3Generally, mapping scheme 400 may illustrate an example of an L2L table 420 that supports a logic remapping technique.

[0089] The user area 435 may include dies 405-a and 405-b, each of which may support a specified data storage capacity. Each memory die 405 may further include a plurality of planes 410 (e.g., memory die 405-a includes four planes 410 labeled 0-3), wherein each plane 410 may include a corresponding set of pages 415, and each page 415 may include a set of memory cells. Each block of the user area 435 (e.g., physical block 440, located at die 405-a, plane 1, page 3) may be a physical block address (PBA) of stored information. The information stored at the physical address may also be associated with an LBA. In some cases, the memory system may have a granularity of one LBA mapped to each PBA unless compression is used for physically continuous ranges.

[0090] In some cases, L2P table 425-a may point from logical address "A" to physical address "A" (e.g., the physical address of block 440). L2P table 425-a may illustrate an example of a mapping between logical and physical block addresses before the memory system performs an exemplary defragmentation operation. After such a defragmentation operation, the affected entries of L2P table 425-a may be updated to entries of L2P table 425-b. In some cases, some entries of L2P table 425-b may point directly to physical addresses. For example, if the entries are not affected by the defragmentation operation (e.g., neither the logical address nor the physical address has changed), the entries in L2P table 425-a and the entries in L2P table 425-b may be the same and may both point to the same physical block of user area 435. In some cases, some physical addresses may not be mapped to corresponding logical addresses, and therefore some entries of L2P table 425 may not contain pointers to physical blocks (e.g., "unmapped" entries).

[0091] In some cases, the memory system may store the L2P table in a fast random access memory (e.g., DRAM, 3DXPoint (3DXP), FeRAM, MRAM, SRAM). The memory system may add an indication (e.g., a pointer) of the corresponding entry of the L2L table 420 to the L2P table 425-b to avoid or reduce the computational overhead of performing the search. That is, in some cases, the pointer to the physical address from the L2P table 425-a (e.g., in Figure 4 ) may be accessed by a pointer from L2P 425-b to L2L table 420 (e.g., in Figure 4For example, after the memory system performs a defragmentation operation, in response to remapping the logical address of physical address “A” of physical block 440 from “A” to “B”, the memory system may insert a pointer to L2L table 420.

[0092] That is, instead of adjusting the entry of L2P table 425-b to include a mapping between logical address "B" and physical address "A," the memory system may insert a pointer in L2P table 425-b to an entry in L2L table 420. The entry in L2L table 420 may include the new logical address (e.g., B), the old logical address (e.g., A), and a pointer from L2L to physical address "A" (e.g., physical block 440). After following the mapping from L2P table 425-b to L2L table 420 to physical block 440, the memory system may read the information at physical block 440.

[0093] In some cases, during some processes (e.g., garbage collection, receiving access commands), the memory system can use metadata to verify whether the correct physical address has been accessed via the logical address. Although in some cases, the memory system may initially mark a mismatch between the metadata and the physical address, the memory system can use information found in the L2L table 420 to verify the metadata. By using the L2L table 420 as an intermediate mapping between the physical addresses of the user area 435 and the L2P table 425-b, the memory system can avoid performing searches to verify the metadata because it may have accessed the logical addresses before and after defragmentation. In other words, the configuration of the mapping scheme 400 enables the memory system to reference the L2L table 420 (in response to a pointer in the L2P table 425-b), which contains the correct information for metadata verification in response to a remapping operation, and for other unchanged entries of the L2P table 425-b, the memory system can avoid performing a search algorithm to save processing power and improve the latency of read operations.

[0094] Figure 5 An example of a process flow 500 for supporting logic remapping of a memory system according to an example disclosed herein is shown. The process flow 500 may be implemented by a memory system that may represent a memory system having a plurality of memory cells. Figures 1 to 4 The process flow 500 may be implemented by a memory system, for example, to generate a mapping between logical and physical block addresses of the memory system and to remap logical or physical addresses when changes occur (e.g., due to a defragmentation operation or other process). Alternative examples may be implemented below, with some steps performed in a different order or not performed at all. In addition, some steps may include additional features not described below, and some steps may be performed by different components or systems, or any combination thereof.

[0095] Aspects of process flow 500 can be implemented by a memory system, a memory device, a controller, and other components (e.g., a memory device controller, such as a MNAND die of a memory device). Additionally or alternatively, aspects of process flow 500 can be implemented as instructions in a stored memory (e.g., firmware stored in a memory coupled to a memory system). For example, if the instructions are executed by a controller (e.g., memory system controller 115), the instructions can cause the controller to perform the operations of process flow 500.

[0096] For example, as referenced in this article Figure 3 and 4 As described above, in some cases, the memory system may perform remapping by updating the L2P map after each defragmentation operation and may refer to the L2L map to verify the metadata. In some cases, the L2L map may be such as referenced Figure 4 Describes an example of L2L mapping.

[0097] At 505, an L2P map may be generated. For example, the memory system may generate the L2P map. The memory system may include information stored at physical addresses. In some cases, the memory system may receive a command (e.g., a write command) from a host system that references a logical address of some information. For example, the memory system may generate the L2P map to map the logical address referenced by the host system to the physical address of the corresponding information stored in the memory system. In some cases, the memory system may proceed with executing a command (e.g., a read command) by using the L2P map to identify the physical address associated with the logical address referenced by the host system.

[0098] At 510, a defragmentation operation may be performed. For example, the host system may perform a defragmentation operation. In some cases, the host system may determine that defragmentation may improve performance. In some instances, the host system may initiate a defragmentation operation that may include sending multiple read commands and multiple write commands to the memory system so that data is remapped to different logical addresses. In some instances, the host system may issue a defragmentation command to the memory system that causes logical addresses to be remapped without moving at least some of the data to new physical addresses. Additionally or alternatively, the memory system may initiate a defragmentation operation. The defragmentation operation may be an example of a defragmentation (e.g., remapping) operation as described herein. For example, as part of the defragmentation operation, logical addresses mapped to physical addresses may be reorganized. The memory system may receive an indication of a new logical address for information stored at the physical address. The host system may select a new organization so that the data file is stored contiguously in the logical addressing space, which may free up space at the host system and improve the efficiency of the host system when performing operations. In some cases, the physical address of the information may not change as a result of a defragmentation operation according to some of the techniques described herein.

[0099] At 515, a logical to logical mapping is generated. For example, the memory system may generate an L2L mapping. For example, the reorganization of the logical addresses that occurred at step 510 may result in an inconsistency in the L2P mapping of the information or metadata (e.g., due to not rewriting the physical address of the information to another physical address). Therefore, the memory system may generate an L2L mapping (e.g., as shown in FIG. Figure 3 and 4 In some cases, the memory system may adjust entries in the L2P map during or after a defragmentation operation. In some cases, the adjusted L2P map may be a mapping between the new logical address and the physical address. In some cases, the L2P map may include a pointer to the L2L map (e.g., a reference to the old logical address). Figure 4 L2L table described in

[15] .

[0100] At 520, a read command may be received. For example, the memory system may receive the read command from a host system. The host system may indicate a logical address in the read command. At 525, an L2P entry may be identified. For example, the memory system may identify an L2P entry or an entry in an L2L table that indicates a logical address of a physical address. If the L2P entry points to an L2L mapping, the memory system may proceed to 530. If the L2P entry points to a physical address, the memory system may proceed to 540.

[0101] At 530, a physical address may be identified. For example, the memory system may use an L2L map to identify the physical address. For example, an L2P entry may point to an entry in an L2L map. The L2L entry may include an old logical address (e.g., a logical address included in a read command from the host system) and a new logical address (e.g., an updated logical address after defragmentation). The L2L entry may also include a pointer to the physical address. The memory system may perform a read operation at the location indicated by the pointer to the physical address. For example, the memory system may use the old logical address in the L2L entry to retrieve data and verified or updated metadata from the physical address, which may reduce processing overhead for the search.

[0102] At 535, the metadata can be validated. For example, the memory system can validate that the logical address received in the command matches the logical address indicated by the metadata. For example, the memory system can compare information in the metadata with information in the L2L table to perform validation. In some cases, since the L2L entry information has already been accessed at step 530, the memory system may not perform an additional search of the L2L table. The memory system can validate that the metadata matches the logical address contained in the L2L entry.

[0103] At 540, a physical address may be identified. For example, the memory system may identify the physical address after being directed by a pointer in an L2P entry. For example, the L2P entry may directly point to a physical block address in the memory system. In some cases, the memory system may perform a read operation after accessing the pointer to the physical address. For example, the memory system may retrieve data and metadata from the physical address.

[0104] At 545, in some cases, the L2L table may be searched. For example, in some cases, the memory system may search the L2L table for an entry associated with the logical address received from the host system. For example, in some cases, the memory system may detect a mismatch between the logical address in the metadata and the logical address received in a read command from the host system. The memory system may use the L2L table to determine whether the logical address has been updated. In some cases, the L2L entry may include the old logical address (e.g., the logical address stored in the metadata) and the new logical address (e.g., the logical address included in the read command).

[0105] In some cases, the metadata can be verified at 550. For example, the memory system can verify that the logical address received in the command matches the logical address indicated by the metadata.

[0106] At 555, data transfer may be performed. For example, the memory system may transfer the data to the host system. By transferring the data, the memory system may end performing the read operation.

[0107] Figure 6 A block diagram 600 is shown of a memory system 620 (eg, a memory system) supporting logic remapping techniques according to examples disclosed herein. The memory system 620 may be a memory system such as that described in reference to FIG. Figures 1 to 5 6. The memory system 620 or its various components may be examples of devices for performing various aspects of the logical remapping techniques described herein. For example, the memory system 620 may include a write command component 625, a first mapping component 630, an L2L component 635, a third mapping component 640, a read command component 645, a retrieval component 650, a transfer component 655, a matching component 660, a transmission component 665, a garbage collection component 670, a search component 675, an update component 680, an identification component 685, a detection component 690, a verification component 695, a counting component 696, a determination component 697, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0108] The write command component 625 may be configured to or otherwise support means for receiving a write command to store information at a first logical address associated with a memory system. The first mapping component 630 may be configured to or otherwise support means for generating a first entry of a logical-to-physical mapping, the first entry mapping the first logical address to a first physical address of the memory system at which the information is stored after receiving the write command. The L2L component 635 may be configured to or otherwise support means for generating, as part of a defragmentation operation, a second entry of a logical-to-logical mapping mapping the first logical address to a second logical address associated with the information stored at the first physical address after the defragmentation operation. The third mapping component 640 may be configured to or otherwise support means for generating, as part of a defragmentation operation, a third entry of a logical-to-physical mapping mapping the second logical address to an indication of the first physical address after generating the second entry.

[0109] In some instances, a third entry of the logical-to-physical mapping includes a pointer to the first physical address. In some instances, the third entry of the logical-to-physical mapping includes a pointer to the second entry of the logical-to-logical mapping. In some instances, the second entry of the logical-to-logical mapping includes an indication of the first logical address and the first physical address.

[0110] In some examples, the read command component 645 can be configured or otherwise support means for receiving a read command to retrieve information associated with the second logical address. In some examples, the retrieval component 650 can be configured or otherwise support means for retrieving information from the first physical address of the memory system after receiving the read command.

[0111] In some examples, the identification component 685 can be configured to or otherwise support means for identifying the first physical address after reading a third entry of a logical-to-physical mapping that maps the second logical address to the first physical address of the memory system, wherein the read information is coupled with the identification.

[0112] In some examples, the identification component 685 can be configured to or otherwise support means for identifying the first physical address after reading a third entry of a logical-to-physical mapping that maps the second logical address to a second entry of the logical-to-logical mapping, the second entry of the logical-to-logical mapping indicating the first physical address, the first logical address, or both of the memory system, wherein the read information is coupled with the identification.

[0113] In some examples, the transfer component 655 may be configured to or otherwise support a device that transfers a first range of logical blocks from a first location having a first starting address to a second location having a second starting address as part of a defragmentation operation, where the second entry indicates the first starting address, the second starting address, and the number of logical blocks in the first range of logical blocks.

[0114] In some examples, the read command component 645 can be configured or otherwise support means for receiving a read command to retrieve information associated with the second logical address. In some examples, the retrieval component 650 can be configured or otherwise support means for retrieving information and metadata associated with the information from the first physical address of the memory system after receiving the read command. In some examples, the matching component 660 can be configured or otherwise support means for determining whether a third logical address stored in the metadata matches the second logical address included in the read command. In some examples, the transmission component 665 can be configured or otherwise support means for transmitting the information directly in response to the determination.

[0115] In some examples, to support determining whether a third logical address stored in the metadata matches a second logical address included in the read command, the detection component 690 can be configured to or otherwise support means for detecting a mismatch between the third logical address stored in the metadata and the second logical address included in the read command. In some examples, to support determining whether a third logical address stored in the metadata matches the second logical address included in the read command, the search component 675 can be configured to or otherwise support means for searching a logical-to-logical map for an entry associated with the third logical address stored in the metadata after detecting the mismatch. In some examples, to support determining whether a third logical address stored in the metadata matches the second logical address included in the read command, the verification component 695 can be configured to or otherwise support means for verifying information retrieved from the first physical address of the memory system after identifying an entry in the logical-to-logical map for the third logical address, wherein the sending information is coupled with the verification information.

[0116] In some instances, garbage collection component 670 may be configured as or otherwise support means for performing a garbage collection operation or an error handling operation involving the first physical address. In some instances, retrieval component 650 may be configured as or otherwise support means for retrieving information and metadata associated with the information from the first physical address of the memory system during or after performing the garbage collection operation or the error handling operation. In some instances, search component 675 may be configured as or otherwise support means for searching a logical-to-logical map for an entry associated with a third logical address stored in the metadata during or after performing the garbage collection operation or the error handling operation. In some instances, update component 680 may be configured as or otherwise support means for updating metadata associated with the information after identifying an entry in the logical-to-logical map for the third logical address.

[0117] In some examples, garbage collection component 670 can be configured as or otherwise support means for performing a garbage collection operation to transfer valid data from a source block to a target block. In some examples, update component 680 can be configured as or otherwise support means for updating metadata associated with a source block to indicate an updated logical address associated with the information after reading a logical-to-logical map containing one or more entries associated with the information.

[0118] In some examples, the search component 675 can be configured as or otherwise support means for searching the logical-to-logical mapping for one or more entries associated with the information, wherein updating metadata is coupled with the search.

[0119] In some examples, identification component 685 can be configured as or otherwise support means for identifying one or more entries after reading a bitmap that includes an indication that a source block corresponds to one or more entries of a logical to logical mapping.

[0120] In some examples, the indication that the source block corresponds to one or more entries of the logical-to-logical mapping includes bits of a page of the memory system, bits of a superpage of the memory system, bits of a word line of the memory system, bits of a physical block address of the memory system, or any combination thereof.

[0121] In some examples, the counting component 696 can be configured or otherwise support means for incrementing a counter associated with a source block after generating one or more entries associated with the source block. In some examples, the determining component 697 can be configured or otherwise support means for determining whether the number of counters is greater than a set of counters associated with other blocks. In some examples, the garbage collection component 670 can be configured or otherwise support means for performing a garbage collection operation to transfer valid data from the source block to the target block in response to the number of counters being greater than the set of counters.

[0122] Figure 7 1 is a flow chart illustrating a method 700 for supporting logic remapping techniques according to an example disclosed herein. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 6 The memory system or memory device described herein may be used to perform the functions described herein. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the functions described herein. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the functions described herein.

[0123] At 705, the method may include receiving a write command to store information at a first logical address associated with a memory system. The operations of 705 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 705 may be performed as described in reference to Figure 6 The write command component 625 described is executed.

[0124] At 710, the method may include generating a first entry of a logical-to-physical mapping, the first entry mapping a first logical address to a first physical address of a memory system where information is stored after receiving a write command. The operations of 710 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 710 may be described in detail in reference to Figure 6 The first mapping component 630 described is performed.

[0125] At 715, the method may include, as part of the defragmentation operation, generating a second entry of the logical-to-logical mapping that maps the first logical address to a second logical address, the second logical address being associated with information stored at the first physical address after the defragmentation operation. The operations of 715 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 715 may be described in detail with reference to Figure 6 The L2L component 635 described above is executed.

[0126] At 720, the method may include, as part of the defragmentation operation, in response to generating the second entry, generating a third entry of the logical-to-physical mapping that maps the second logical address to an indication of the first physical address. The operation of 720 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 720 may be as described in reference to Figure 6 The third mapping component 640 described is performed.

[0127] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a write command to store information at a first logical address associated with a memory system, generating a first entry of a logical-to-physical map that maps the first logical address to a first physical address of the memory system where the information is stored after receiving the write command, generating, as part of a defragmentation operation, a second entry of the logical-to-logical map that maps the first logical address to a second logical address associated with the information stored at the first physical address after the defragmentation operation, and generating, in response to generating the second entry, a third entry of the logical-to-physical map that maps the second logical address to an indication of the first physical address as part of the defragmentation operation.

[0128] In some examples of the method 700 and apparatus described herein, the third entry of the logical-to-physical mapping includes a pointer to the first physical address.

[0129] In some examples of the method 700 and apparatus described herein, the third entry of the logical-to-physical map includes a pointer to the second entry of the logical-to-logical map, and the second entry of the logical-to-logical map includes an indication of the first logical address and the first physical address.

[0130] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving a read command to retrieve information associated with the second logical address and retrieving information from the first physical address of the memory system upon receiving the read command.

[0131] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying the first physical address after reading a third entry of a logical-to-physical mapping that maps the second logical address to the first physical address of the memory system, wherein the reading information may be coupled with the identifying.

[0132] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying the first physical address after reading a third entry of a logical-to-physical map that maps a second logical address to a second entry of the logical-to-logical map, wherein the second entry of the logical-to-logical map indicates the first physical address, the first logical address, or both of the memory system, wherein reading the information may be coupled with the identifying.

[0133] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transferring a first range of logic blocks from a first location having a first starting address to a second location having a second starting address as part of a defragmentation operation, wherein the second entry indicates the first starting address, the second starting address, and the number of logic blocks in the first range of logic blocks.

[0134] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving a read command to retrieve information associated with a second logical address, retrieving the information and metadata associated with the information from a first physical address of a memory system after receiving the read command, determining whether a third logical address stored in the metadata matches the second logical address included in the read command, and transmitting the information upon reaching the determination.

[0135] In some examples of the method 700 and apparatus described herein, determining whether a third logical address stored in the metadata matches a second logical address included in the read command may include operations, features, circuitry, logic, means, or instructions for detecting a mismatch between the third logical address stored in the metadata and the second logical address included in the read command, upon detecting the mismatch, searching a logical-to-logical map for an entry associated with the third logical address stored in the metadata, and upon identifying the entry in the logical-to-logical map for the third logical address, verifying information retrieved from the first physical address of the memory system, wherein sending the information may be coupled to verifying the information.

[0136] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing a garbage collection operation or an error handling operation involving a first physical address, retrieving information and metadata associated with the information from the first physical address in a memory system during or after performing the garbage collection operation or the error handling operation, searching a logical-to-logical map for an entry associated with a third logical address stored in the metadata during or after performing the garbage collection operation or the error handling operation, and updating the metadata associated with the information after identifying the entry in the logical-to-logical map for the third logical address.

[0137] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing a garbage collection operation to transfer valid data from a source block to a target block and updating metadata associated with the source block to indicate an updated logical address associated with the information, the logical address being coupled to a logical-to-logical map comprising one or more entries associated with the information.

[0138] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for searching the logical-to-logical mapping for one or more entries associated with the information, wherein updating the metadata may be coupled with the searching.

[0139] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying one or more entries after reading a bitmap, the bitmap including an indication that a source block corresponds to one or more entries of a logical-to-logical mapping.

[0140] In some examples of the method 700 and apparatus described herein, the indication that a source block corresponds to one or more entries of a logical-to-logical mapping includes bits of a page of a memory system, bits of a superpage of a memory system, bits of a word line of a memory system, bits of a physical block address of a memory system, or any combination thereof.

[0141] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for, after generating one or more entries associated with a source block, incrementing a counter associated with the source block, determining whether the number of the counter is greater than a number of a set of counters associated with other blocks, and directly in response to the number of the counter being greater than a number of the set of counters, performing a garbage collection operation to transfer valid data from the source block to the target block.

[0142] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Additionally, portions from two or more of the methods described may be combined.

[0143] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0144] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, one or more intermediate components, such as a switch or transistor, may be used, for example, to interrupt the flow of signals between the connected components for a period of time.

[0145] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via conductive paths, to a closed-circuit relationship between the components in which signals can communicate between the components via conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0146] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0147] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, etc., that provides an electrically conductive path between elements or components of a memory array.

[0148] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0149] The term "in response to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0150] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring independently of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0151] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0152] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0153] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0154] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0155] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0156] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0157] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0158] Computer-readable media includes both non-transitory computer storage media and communication media, and the communication media includes any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc memory devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code devices in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Similarly, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0159] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receiving a write command to store information at a first logical address associated with the device; generating, based at least in part on receiving the write command, a first entry of a logical-to-physical mapping that maps the first logical address to a first physical address of the device storing the information; as part of a defragmentation operation, generating a second entry of a logical-to-logical mapping that maps the first logical address to a second logical address, the second logical address being associated with the information stored at the first physical address after the defragmentation operation; and As part of the defragmentation operation, based at least in part on generating the second entry, a third entry of a logical-to-physical mapping is generated that maps the second logical address with an indication of the first physical address. 2 . The apparatus of claim 1 , wherein the third entry of the logical-to-physical mapping comprises a pointer to the first physical address.

3. The apparatus according to claim 1, wherein: the third entry of the logical-to-physical map comprises a pointer to the second entry of the logical-to-logical map; and The second entry of the logical-to-logical map includes an indication of the first logical address and the first physical address.

4. The device of claim 1 , wherein the controller is further configured to cause the device to: receiving a read command to retrieve information associated with the second logical address; and Based at least in part on receiving the read command, the information is retrieved from the first physical address of the device.

5. The device of claim 4, wherein the controller is further configured to cause the device to: The first physical address is identified based at least in part on the third entry of the logical-to-physical mapping that maps the second logical address to the first physical address of the device, wherein reading the information is based at least in part on the identification.

6. The device of claim 4, wherein the controller is further configured to cause the device to: Identifying the first physical address based at least in part on the third entry of the logical-to-physical map that maps the second logical address to the second entry of the logical-to-logical map, the second entry of the logical-to-logical map indicating the first physical address, the first logical address, or both of the device, wherein reading the information is based at least in part on the identification.

7. The device of claim 1 , wherein the controller is further configured to cause the device to: As part of the defragmentation operation, a first range of logical blocks is transferred from a first location having a first starting address to a second location having a second starting address, wherein the second entry indicates the first starting address, the second starting address, and a number of logical blocks in the first range of logical blocks.

8. The device of claim 1 , wherein the controller is further configured to cause the device to: receiving a read command to retrieve information associated with the second logical address; retrieving the information and metadata associated with the information from the first physical address of the device based at least in part on receiving the read command; determining whether a third logical address stored in the metadata matches the second logical address included in the read command; and The information is communicated based at least in part on the determination.

9. The device of claim 8, wherein determining whether the third logical address stored in the metadata matches the second logical address included in the read command is further configured to cause the device to: detecting a mismatch between the third logical address stored in the metadata and the second logical address included in the read command; searching the logical-to-logical map for an entry associated with the third logical address stored in the metadata based at least in part on the detected mismatch; and Information retrieved from the first physical address of the device is validated based at least in part on the entry in the logical-to-logical mapping identifying the third logical address, wherein transmitting the information is based at least in part on validating the information.

10. The device of claim 1 , wherein the controller is further configured to cause the device to: performing a garbage collection operation or an error handling operation involving the first physical address; retrieving the information and metadata associated with the information from the first physical address of the device based at least in part on performing the garbage collection operation or the error handling operation; searching the logical-to-logical map for an entry associated with a third logical address stored in the metadata based at least in part on performing the garbage collection operation or the error handling operation; and The metadata associated with the information is updated based at least in part on the entry in the logical-to-logical mapping identifying the third logical address.

11. The device of claim 1 , wherein the controller is further configured to cause the device to: Performing garbage collection operations to transfer valid data from source blocks to destination blocks; and Metadata associated with the source block is updated to indicate an updated logical address associated with the information based at least in part on the logical-to-logical map including one or more entries associated with the information.

12. The device of claim 11, wherein the controller is further configured to cause the device to: The logical-to-logical map is searched for one or more entries associated with the information, wherein updating the metadata is based at least in part on the search.

13. The device of claim 11, wherein the controller is further configured to cause the device to: The one or more entries are identified based at least in part on a bitmap, the bitmap including an indication that the source block corresponds to the one or more entries of the logical-to-logical mapping.

14. The device of claim 13 , wherein the indication that the source block corresponds to the one or more entries of the logical-to-logical mapping comprises bits for a page of the device, bits for a superpage of the device, bits for a wordline of the device, bits for a physical block address of the device, or any combination thereof.

15. The device of claim 11, wherein the controller is further configured to cause the device to: incrementing a counter associated with the source block based at least in part on generating the one or more entries associated with the source block; determining whether the number of counters is greater than a number of a set of counters associated with other blocks; and Based at least in part on the number of the counter being higher than the number of the set of counters, performing the garbage collection operation to transfer the valid data from the source block to the target block.

16. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a write command to store information at a first logical address associated with a memory system; generating, based at least in part on receiving the write command, a first entry of a logical-to-physical mapping that maps the first logical address to a first physical address of the memory system storing the information; as part of a defragmentation operation, generating a second entry of a logical-to-logical mapping that maps the first logical address to a second logical address, the second logical address being associated with the information stored at the first physical address after the defragmentation operation; and As part of the defragmentation operation, based at least in part on generating the second entry, a third entry of a logical-to-physical mapping is generated that maps the second logical address with an indication of the first physical address.

17. The non-transitory computer-readable medium of claim 16, wherein the third entry of the logical-to-physical mapping comprises a pointer to the first physical address.

18. The non-transitory computer-readable medium of claim 16, wherein: the third entry of the logical-to-physical map comprises a pointer to the second entry of the logical-to-logical map; and The second entry of the logical-to-logical map includes an indication of the first logical address and the first physical address.

19. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving a read command to retrieve information associated with the second logical address; and Based at least in part on receiving the read command, the information is retrieved from the first physical address of the memory system.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to identify the first physical address based at least in part on the third entry of the logical-to-physical mapping that maps the second logical address to the first physical address of the memory system, wherein reading the information is based at least in part on the identification.

21. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to identify the first physical address based at least in part on the third entry of the logical-to-physical mapping that maps the second logical address to the second entry of the logical-to-logical mapping, the second entry of the logical-to-logical mapping indicating the first physical address, the first logical address, or both of the memory system, wherein reading the information is based at least in part on the identification.

22. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to transfer a first range of logical blocks from a first location having a first starting address to a second location having a second starting address as part of the defragmentation operation, wherein the second entry indicates the first starting address, the second starting address, and the number of logical blocks in the first range of logical blocks.

23. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving a read command to retrieve information associated with the second logical address; retrieving the information and metadata associated with the information from the first physical address of the memory system based at least in part on receiving the read command; determining whether a third logical address stored in the metadata matches the second logical address included in the read command; and The information is communicated based at least in part on the determination.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: detecting a mismatch between the third logical address stored in the metadata and the second logical address included in the read command; searching the logical-to-logical map for an entry associated with the third logical address stored in the metadata based at least in part on the detected mismatch; and The information retrieved from the first physical address of the memory system is validated based at least in part on the entry in the logical-to-logical map identifying the third logical address, wherein sending the information is based at least in part on validating the information.

25. A method performed by a memory system, comprising: receiving a write command to store information at a first logical address associated with the memory system; generating, based at least in part on receiving the write command, a first entry of a logical-to-physical mapping that maps the first logical address to a first physical address of the memory system storing the information; as part of a defragmentation operation, generating a second entry of a logical-to-logical mapping that maps the first logical address to a second logical address, the second logical address being associated with information stored at the first physical address after the defragmentation operation; and As part of the defragmentation operation, a third entry of the logical-to-physical mapping is generated that maps the second logical address with an indication of the first physical address based at least in part on generating the second entry.

Images