Configurable calibration level

Abstract

The present application relates to configurable check levels. A host device may determine a target reliability level for a data set stored in a memory device. The host device may transmit to the memory device a command indicating the target reliability level and a request to perform one or more error management operations for the data set based on or in response to the target reliability level. The memory device may determine the target reliability level and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the data set. The memory device may transmit to the host device an indication of the reliability level of the data set based on or in response to the command and performing a set of error management operations.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 396,443 filed by CARIELLO on August 6, 2021, entitled “CONFIGURABLE VERIFY LEVEL,” which is assigned to the present assignee and is expressly incorporated herein by reference.

[0003] The technical field relates to configurable check levels. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, and the memory cell can store either of the two possible states. In order to access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the apparatus to receive a command from a host device indicating a target reliability level associated with a data set stored in the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; determine the target reliability level from a plurality of target reliability levels based on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; perform the one or more error management operations for the data set based on the target reliability level; and transmit an indication of the reliability level associated with the data set to the host device in response to the command based on performing the one or more error management operations.

[0007] An apparatus is described. The apparatus may include a controller configured to be coupled to a memory system. The controller may be configured to cause the apparatus to determine a target reliability level associated with a data set stored in a memory device coupled to the memory system; transmit a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; and receive an indication of a reliability level associated with the data set from the memory device in response to the command based on the one or more error management operations.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to receive from a host device an indication of a target reliability level associated with a data set stored in a memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; determine the target reliability level from a plurality of target reliability levels based on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; perform the one or more error management operations for the data set based on the target reliability level; and transmit to the host device an indication of a reliability level associated with the data set in response to the command based on performing the one or more error management operations.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to determine a target reliability level associated with a data set stored in a memory device coupled to a memory system; transmit a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; and receive an indication of a reliability level associated with the data set from the memory device in response to the command based on the one or more error management operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting configurable check levels according to examples as disclosed herein is described.

[0011] Figure 2 An example of a system supporting configurable check levels according to examples as disclosed herein is described.

[0012] Figure 3 An example of a system supporting configurable check levels according to examples as disclosed herein is described.

[0013] Figure 4 An example of a flow chart supporting configurable check levels according to examples as disclosed herein is illustrated.

[0014] Figure 5 A block diagram of a memory system supporting configurable verify levels according to examples as disclosed herein is shown.

[0015] Figure 6 A block diagram of a host system supporting configurable check levels according to examples as disclosed herein is shown.

[0016] Figure 7 and 8 A flow chart illustrating one or more methods of supporting configurable check levels according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0017] In some memory systems, a host device may transmit a check command to a memory device. The check command may indicate a data set stored at the memory device, and a request to check the reliability or validity of the data set. The memory device may read the data set based on or in response to the check command to determine whether the data set is valid. In some instances, the memory device may read a logic value corresponding to the data, and compare the logic value with a threshold value to determine whether the data set is valid. The memory device may transmit a check command status response indicating whether the data set is valid to the host device. If the data set is invalid, the host device may issue read and write commands to rewrite the data set. In some instances, the host device may set an enable early recovery (EER) bit in a check error recovery mode page corresponding to the check command. The memory device may perform an error recovery process based on or in response to a duration of the EER bit value. The host device may set the EER bit based on or in response to a target reliability level of the data set. However, in some instances, the EER bit may not provide the host device with sufficient granularity to accurately indicate the target reliability level. In addition, the EER bit may indicate the duration of the error handling operation, but the EER bit may not correspond to the target reliability level of the data set. Additionally or alternatively, setting the EER bit and performing error handling operations may result in increased latency and relatively high power consumption.

[0018] Systems, devices, and techniques are described to enable a host device to indicate one or more target reliability levels and one or more corresponding error management operations via a verification command, which can provide finer granularity and reduced latency and power consumption. The host device may determine the target reliability level of the data set based on or in response to one or more commands to be executed for the data set, an operation mode corresponding to the data set, a physical stressor that the data set may experience, and the like. In some examples, the target reliability level may be selected from a set of possible target reliability levels. A bit, bit field, or attribute associated with the verification command may be configured to indicate the target reliability level. A bit, bit field, or attribute may indicate one or more error management operations associated with the target reliability level, or a memory device may be configured with a set of error management operations corresponding to each target reliability level. The memory device may read and verify the data set, and perform the indicated error management operation based on or in response to the verification command and the current reliability level of the data. Depending on the target reliability level, the error management operation may include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an error handling operation, or any combination thereof. Indicating a target reliability level and corresponding error management operations via a check command as described herein may provide reduced power consumption and reduced latency, thereby improving the reliability of the error management process and data stored at the memory device.

[0019] Initial reference Figures 1 to 3Features of the present disclosure are described in the context of systems, devices, and circuits. Figure 4 Features of the present disclosure are described in the context of flow charts. Figures 5 to 8 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow charts involving configurable check levels.

[0020] Figure 1 An example of a system 100 supporting configurable verify levels according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0022] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0023] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0024] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0025] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 Although two memory devices 130-a and 130-b are shown in the example of , the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicated with the memory devices 130 to perform operations that may generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0027] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for internal storage or computation, such as internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, if the data is read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for the host system 105 (e.g., with reduced latency relative to the memory device 130) for subsequent retrieval or manipulation (e.g., updating) according to the cache policy.

[0030] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be respectively internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may in some cases be alternatively performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some examples, the memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks included in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erasing operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 including page 175 has been erased.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations of the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in a previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105).

[0039] The system 100 may include any number of non-transitory computer-readable media that support configurable check levels. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] In some cases, the host system 105 (e.g., the host system controller 106) may transmit a verification command to the memory system 110. The verification command may indicate a data set stored at the memory device 130, and a request to check the reliability or validity of the data set. The memory system 110 (e.g., the memory system controller 115, a local controller 135 associated with the memory device 130, or some other component within the memory system 110) may read the data set based on or in response to the verification command to determine whether the data set is valid. In some examples, the memory system 110 may read a logic value corresponding to the data, and compare the logic value to a threshold value to determine whether the data set is valid. The memory system 110 may transmit a verification command status response indicating whether the data set is valid to the host system 105.

[0042] If the data set is invalid, the host system 105 may issue read and write operations to rewrite the data set. Additionally or alternatively, the host system 105 may set an EER bit in a verification error recovery mode page corresponding to the verification command. The memory system 110 performs an error recovery process, and the duration of the error recovery process may be based on or responsive to the value of the EER bit. However, setting the EER bit and performing the error recovery process may result in relatively high power consumption and latency associated with performing the verification operation. Furthermore, the EER bit may indicate the duration of the error handling operation, but the EER bit may not correspond to maintaining or ensuring a target reliability level for the data set.

[0043] Systems, devices and techniques are described to enable a host system 105 to indicate one or more target reliability levels and one or more corresponding error management operations via a check command. The host system 105 may determine a target reliability level for a data set based on or in response to one or more commands to be executed for the data set, an operation mode corresponding to the data set, a physical stressor that the data set may experience, etc. In some examples, the target reliability level may be selected from a set of possible target reliability levels. A bit, bit field or attribute associated with the check command may be configured to indicate the target reliability level. A bit, bit field or attribute may indicate one or more error management operations associated with the target reliability level, or the memory system 110 may be configured with a set of error management operations corresponding to each target reliability level.

[0044] The memory system 110 may read and verify a data set stored by the memory device 130. The memory system 110 may perform the indicated error management operation based on or in response to the verify command and the current reliability level of the data. Depending on the target reliability level, the error management operation may include an error correction operation according to a reduced error correction capability, a read margin adjustment operation, a refresh operation, an error handling operation, or any combination thereof. Indicating the target reliability level and the corresponding error management operation via a verify command as described herein may provide reduced power consumption and reduced latency, thereby improving the reliability of the error management process and the data stored at the memory device 130.

[0045] Figure 2 An example of a system 200 supporting configurable check levels according to an example disclosed herein is described. The system 200 may be as described in reference Figure 1 The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may be implemented as described in reference Figure 1 Aspects of system 100 are described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0046] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, such as in response to receiving an access command from the host system 205, as described herein. The memory device 240 may include a memory device 240 as described in reference to Figure 1For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0047] The memory system 210 may include a storage controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The storage controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single storage controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple storage controllers 230, such as a different storage controller 230 for each type of memory device 240. In some cases, the storage controller 230 may be implemented as described with reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0048] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to convert data between the host system 205 and the memory device 240, e.g., as shown by the data path 250, and may be collectively referred to as data path components.

[0049] Using buffer 225 to temporarily store data during transfer can allow data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be processed, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM) or a hardware accelerator or both to allow fast storage and retrieval of data in and out of buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0050] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during execution of an access command. That is, after an access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., may be overwritten with data from additional access commands). In addition, buffer 225 may be a non-cacheable buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without performing an operation to match an address with an address already in buffer 225 (e.g., no cache address matching or lookup operation).

[0051] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a memory system controller 215 as described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used to communicate between system components.

[0052] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As an example of a possible implementation, the command queue 260, buffer queue 265, and storage queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, the queues, if used, may be located anywhere within the memory system 210.

[0053] Data transferred between the host system 205 and the memory device 240 may take a different path than non-data information (e.g., commands, status information) in the memory system 210. For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 through data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components over the bus 235 (e.g., using a protocol specific to the memory system 210).

[0054] If the host system 205 transmits an access command to the memory system 210, the command may be received by the interface 220, for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). Therefore, the interface 220 may be considered as the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 to transmit the command to the memory system controller 215.

[0055] The memory system controller 215 may determine whether an access command has been received based on or in response to a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, it may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0056] After determining that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this can mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this can mean receiving data from the host system 205 and moving the data to the memory device 240.

[0057] In either case, the memory system controller 215 may use the buffer 225 to temporarily store data received from or sent to the host system 205, among other uses. The buffer 225 may be considered the middle of the memory system 210. In some cases, buffer address management (e.g., pointers that address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0058] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0059] In some cases, the buffer queue 265 may be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 may include access commands associated with data currently stored in the buffer 225. In some cases, commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215 and may remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 may be associated with an address at the buffer 225. That is, a pointer indicating the location in the buffer 225 where the data associated with each command is stored may be maintained. Using the buffer queue 265, multiple access commands may be received sequentially from the host system 205 and at least a portion of the access commands may be processed in parallel.

[0060] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 may transfer the data to the buffer 225 using the data path 250 for temporary storage. In some cases, the interface 220 may obtain the location within the buffer 225 where the data is to be stored from the buffer 225 or the buffer queue 265. The interface 220 may indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0061] Once the write data has been stored in the buffer 225 through the interface 220, the data may be transferred out of the buffer 225 and stored in the memory device 240. This may be accomplished using the storage controller 230. For example, the memory system controller 215 may cause the storage controller 230 to retrieve the data out of the buffer 225 using the data path 250 and transfer the data to the memory device 240. The storage controller 230 may be considered the back end of the memory system 210. The storage controller 230 may indicate to the memory system controller 215, for example, via the bus 235, that the transfer of the memory device data to the memory device 240 has been completed.

[0062] In some cases, the storage queue 270 may be used to assist in the delivery of write data. For example, the memory system controller 215 may push (e.g., via the bus 235) a write command from the buffer queue 265 to the storage queue 270 for processing. The storage queue 270 may include an entry for each access command. In some examples, the storage queue 270 may additionally include: a buffer pointer (e.g., an address) that may indicate a location in the buffer 225 where data associated with the command is stored; and a storage pointer (e.g., an address) that may indicate a location in the memory device 240 associated with the data. In some cases, the storage controller 230 may obtain the location within the buffer 225 from which the data is to be obtained from the buffer 225, the buffer queue 265, or the storage queue 270. The storage controller 230 may manage the location of the storage data within the memory device 240 (e.g., for wear leveling, garbage collection, etc.). Entries may be added to the storage queue 270, for example, by the memory system controller 215. After the transfer of data is complete, the entry may be removed from the storage queue 270 , for example, by the storage controller 230 or the memory system controller 215 .

[0063] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0064] In some cases, the buffer queue 265 may be used to assist in buffer storage of data associated with a read command in a similar manner as discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 may cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 may indicate to the memory system controller 215, for example, via the bus 235, a response to the completion of the data transfer to the buffer 225.

[0065] In some cases, the storage queue 270 may be used to assist in the delivery of read data. For example, the memory system controller 215 may push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 may obtain a location within the memory device 240 from which to retrieve data from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 may obtain a location within the buffer 225 for storing data from the buffer queue 265. In some cases, the storage controller 230 may obtain a location within the buffer 225 for storing data from the storage queue 270. In some cases, the memory system controller 215 may move the command processed by the storage queue 270 back to the command queue 260.

[0066] Once the data has been stored in the buffer 225 by the storage controller 230, the data may be transferred from the buffer 225 and sent to the host system 205. For example, the memory system controller 215 may cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). For example, the interface 220 may process commands from the command queue 260 and may indicate to the memory system controller 215, e.g., via the bus 235, that the data transfer to the host system 205 has been completed.

[0067] The memory system controller 215 may execute the received commands according to an order (e.g., a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may cause data corresponding to the command to be moved into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred from the buffer 225), the command may be removed from the buffer queue 265, such as by the memory system controller 215. If a command is removed from the buffer queue 265, the address that previously stored the data associated with the command may be used to store the data associated with the new command.

[0068] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address conversion between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230 and the storage controller 230 may be omitted.

[0069] In some cases, the host system 205 may transmit a verification command to the memory system 210. The verification command may indicate a data set stored in the memory device 240 of the memory system 210, and a request to verify the reliability of the data set. The memory system 210 may read data from the medium, and transmit a verification command status response indicating the validity of the data to the host system 205 based on or in response to the verification command. In some examples, if the data is invalid, the host system 205 may perform a read and write process to write back the data. In some examples, the host system 205 may set an EER bit in a verification error recovery mode page corresponding to the verification command. The EER bit may indicate a request for the memory system 210 to perform an error handling operation of the data set and a duration for performing the error handling operation. For example, an EER bit set to 1 may indicate a shorter duration for performing the error handling operation compared to an EER bit set to 0. The host system 205 may set the EER bit based on or in response to a target reliability level of the data set. However, in some examples, the EER bit may not provide the host system 205 with enough granularity to accurately indicate the target reliability level. Additionally or alternatively, setting the EER bit to detect marginal data may prevent the memory system 210 from recovering the data. In such cases, the host system 205 may read the data after resetting the EER bit, and write the read data back to the memory system 210 (e.g., the memory device 240 in the memory system 210) to force a refresh and restore data reliability. The additional read and write operations associated with the EER bit may result in increased latency and relatively high power consumption.

[0070] In some examples, the host system 205 may indicate a target reliability level and one or more error management operations corresponding to the target reliability level via a verification command, which may provide finer granularity, reduced latency, and reduced power consumption. The host system 205 may determine the target reliability level of the data set based on or in response to one or more commands to be executed for the data set, an operation mode corresponding to the data set, a physical stress source that the data set may experience, and the like. In some examples, the target reliability level may be selected from a set of possible target reliability levels. A bit, a bit field, or an attribute associated with the verification command may be configured to indicate the target reliability level. A bit, a bit field, or an attribute may indicate one or more error management operations associated with the target reliability level, or the memory system 210 may be configured with a set of error management operations corresponding to each target reliability level. The memory system 210 may read and verify the data set, and perform the indicated error management operation based on or in response to the verification command and the current reliability level of the data. Depending on the target reliability level, the error management operation may include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an error handling operation, or any combination thereof. Indicating a target reliability level and corresponding error management operations via a check command as described herein may provide reduced power consumption and reduced latency, thereby improving the reliability of the error management process and data stored at the memory device.

[0071] Figure 3 An example of a system 300 supporting configurable check levels according to an example disclosed herein is described. The system 300 may be as described in reference Figure 1 and 2 3. The system 300 may include a memory system 310 and a host device 305. The memory system 310 may include a command processor 315 and a memory device 330 configured to store data. The system 300 may support an interface for the host device 305 to transmit a verify command 320 (e.g., as well as other commands, such as read or write commands) to the memory system 310 and receive a status report from the memory system 310 in response to the verify command 320.

[0072] The memory system 310 may include a command processor 315 that may serve as an interface between the host device 305 and the memory system 310. The command processor 315 may be a Figure 2 2. The memory system 310 may include a memory device 330, which may be a reference device. Figure 1 and 2 Examples of memory devices are described.

[0073] The host device 305 may transmit one or more commands, such as a read command, a write command, or a verify command 320, which may indicate operations to be performed by the memory system 310. The host device 305 may transmit the commands to the command processor 315, and the command processor 315 may decode the commands and access related data stored in the memory device 330 or forward the commands to the memory device 330 (e.g., a controller of the memory device 330).

[0074] The host device 305 may transmit a check command 320 to the memory system 310 to request that the memory system 310 check for errors of data stored in the memory device 330. In some examples, the host device 305 may transmit the check command 320 to determine whether the data is corrupted by other operations performed on the memory device 330, or the host device 305 may transmit the check command 320 to identify which data of a data set that may be copied in the memory device 330 is associated with the highest reliability. The check command 320 may indicate a starting logical block address in the memory device 330, and an amount of contiguous logical data blocks (e.g., a data range or a data set) targeted for a corresponding check operation.

[0075] The command processor 315 may receive and decode the check command 320 to identify the data set. The command processor 315, the memory system 310, the memory device 330, or any combination thereof may read the indicated data set to determine the reliability level associated with the data set. In some examples, the command processor 315 may determine the reliability of the data by reading the logic level associated with the data set and comparing the logic level to a threshold level that may be referred to as a read margin. Thus, the command processor 315 may determine whether there is an error in the data set (e.g., whether the data is valid). The command processor 315 may transmit a check command status response 325 to the host device 305 to indicate whether the data set is valid. In some examples, the status response 325 may be transmitted via a UFS protocol interface unit (UPIU). Thus, the host device 305 may receive a status response 325 indicating the quality or reliability of the data set without initiating a read operation, which may reduce processing and latency.

[0076] In some examples, host device 305 may determine a target reliability level for the data set based on one or more operations to be performed on the data set before issuing verify command 320. The target reliability level may correspond to a reliability level that may provide the data set to properly retain stored information during one or more operations or other physical stressors (e.g., an over-the-air (OTA) update operation), or reprocessing on the board of memory device 330 (e.g., if the data set is subjected to an extended period of time at high temperature, soldering or other reprocessing of memory device 330, or other stressors). In some cases, if status response 325 indicates that the data set is invalid, host device 305 may initiate one or more error management processes for the data set. However, in some cases, host device 305 utilizes verify command 320 to determine whether the data set meets the target reliability level and indicates that an error management recovery process for correcting any errors in the data set may be advantageous.

[0077] In some cases, the host device 305 may utilize a check error recovery mode page corresponding to the check command 320 to indicate error recovery parameters that the memory device 330 may use when performing a check operation. The check error recovery mode page may be configured to transmit one or more error recovery parameters to the memory device 330 for use in conjunction with the check command 320. In some cases, the host device 305 may set one or more of the error recovery parameters in the check error recovery mode page based on or in response to a target reliability level for a data set. For example, the host device 305 may set an EER bit in the check error recovery mode page to high or low (e.g., 1 or 0) based on or in response to a target reliability level for a data set. The EER bit may indicate a rate of error recovery processes performed by the memory device 330 in response to the check command 320.

[0078] The error recovery process may include one or more reads of the data set by the memory device 330. If the memory device 330 recognizes that the data is not corrupted after the first read, the memory device 330 may terminate the error recovery process and indicate to the command processor 315 that the data is valid. The command processor 315 may transmit a status response 325 indicating a status of GOOD to the host device 305. If the memory device 330 recognizes an error, the memory device 330 may continue to read the data for a configured number of reads (e.g., re-read attempts) using different arrays and error correction code (ECC) settings to recover the data set. If the host device 305 sets the EER bit to low in the verify command recovery mode page, the memory device 330 will perform an error recovery process that can reduce the risk of error misdetection, which can be a relatively slow error recovery process. That is, the memory device 330 may perform each of the configured number of reads before using the ECC. If the EER bit is set to high, the memory device 330 will perform a relatively favorable error recovery process to correct the identified errors in the data. That is, the memory device 330 may not exhaust the read throughput before using ECC, which may increase the probability of error misdetection but may reduce latency and power consumption.

[0079] If host device 305 determines a relatively high target reliability level for the data set (e.g., if the data set contains critical data, or is subject to relatively high stressors, such as extended time at high temperatures, soldering or other reworking of the board, or other stressors), host device 305 may set the EER bit to high. If the data set is somewhat reliable and the EER bit is set to high, memory device 330 may refresh the data set (e.g., rewrite or correct the data set) more frequently than if the EER bit is not set. If host device 305 determines a relatively low target reliability level for the data set, host device 305 may set the EER bit to low.

[0080] If the memory device 330 identifies an error in the data set while performing a check operation based on or in response to the EER bit, the memory device 330 will indicate the error to the command processor 315. The command processor 315 may transmit a fault status response 325 (e.g., a status response CHECK CONDITION) to the host device 305. In some cases, in response to the fault status report, the host device 305 may issue a read command to retrieve the data from the memory device 330 and rewrite the data in response to the fault check command, which may further increase latency and power consumption.

[0081] Therefore, setting the EER bit in the verification command recovery mode page may result in relatively large power consumption and increased latency associated with the verification operation. In addition, the EER bit indicates the rate at which the memory device 330 will perform the error recovery process. The EER bit does not directly correspond to the reliability of the data set, or may be used to recover different error management operations of the data set in the presence of errors. That is, although the host device 305 can adjust the duration of error recovery and the power consumption associated with performing error recovery by setting the EER bit, the host device 305 may not use the EER bit to indicate the target reliability level to the memory system 310. Additionally or alternatively, the EER bit may not provide sufficient granularity for the host device 305. For example, the EER bit may not be provided to the host device 305 to indicate more than two error recovery levels.

[0082] As described herein, a command descriptor block (CDB) of a check command 320 may indicate a target reliability level for a data set, and one or more error management operations corresponding to the target reliability level. Thus, the memory device 330 may perform the indicated error management operations in response to the check command 320 to verify that the data set meets the target reliability level. By using the check command 320 to indicate different levels of check operations, the host device 305 may improve latency and power consumption associated with the check operation. For example, the host device 305 may balance reliability, power consumption, and latency by selecting a target reliability level from a set of configured target reliability levels based on or in response to one or more commands to be executed by the memory device 330, an operating mode of the memory device 330 or the memory system 310, other sources of physical stress that the memory device 330 may experience, time available to perform the check operation, reliability, or any combination thereof.

[0083] Each target reliability level may correspond to one or more error management operations, such as error correction operations, read margin adjustment operations, refresh operations, error handling operations, one or more other error management operations, or any combination thereof, according to a reduced error correction capability. The reduced error correction capability may correspond to an error correction operation performed in a configured time period. The error correction operation may represent an instance of one or more types of error correction operations that use ECC to correct errors in a data set. For example, the memory device 330 may use a low-density parity check (LDPC) code or other error handling algorithm to adjust the read margin for each read attempt of the data set. In some instances, the error correction operation may require more time to recover more marginal data than other data that is less marginal. The reduced error correction capability may indicate a configured time period for performing an error correction operation error correction operation, which may reduce the marginalization level of recoverable data. However, the configured time period may reduce the latency and power consumption associated with performing the error correction operation.

[0084] The read margin adjustment operation may correspond to the memory device 330 adjusting the read margin during one or more marginal reads to verify the data set (e.g., to check the reliability of the data set). The read margin, which may be referred to as a threshold read margin, may correspond to a reference voltage value that may indicate a logic value stored in a memory cell. For example, if the potential read from a memory cell (e.g., a single-level memory cell) is higher than the threshold read margin, the memory device 330 determines that the memory cell stores a logic 1. If the potential is lower than the threshold read margin, the memory device 330 determines that the memory cell stores a logic 0. In some examples, errors may distort the threshold voltage distribution corresponding to the voltage of each logic value, such that the potential associated with a memory cell storing a logic value of 1 may be lower than the threshold read margin, and vice versa. By performing the read margin adjustment operation, the memory device 330 may increase and / or decrease the threshold read margin of one or more reads to determine the marginality of the data set, which may indicate the reliability level of the data set.

[0085] The read margin adjustment operation may indicate the validity of the data to ensure whether the data set will be accurately stored in the future (e.g., after an operation is performed on the data set or the data is exposed to a physical stressor). The amount by which the threshold read margin may be adjusted during operation (e.g., an adjustment range in volts or millivolts) corresponds to a target reliability level. For example, a relatively higher target reliability level may correspond to more adjustment ranges than a relatively lower target reliability level. In some examples, an adjustment range may be configured for each target reliability level. Additionally or alternatively, an adjustment range for each target reliability level may be determined for the memory device 330 at design time, or based on or in response to a plurality of defined parameters or settings of the memory device 330.

[0086] The host device 305 may thus transmit a verify command 320 indicating a target reliability level from a set of target reliability levels for a verify operation to be performed on a data set in the memory device 330. The verify command 320 may indicate a request for the memory device 330 to perform one or more error management operations corresponding to the target reliability level, which may reduce latency and power consumption of the verify operation. Figure 4 Describe the verification commands and the target reliability level.

[0087] Figure 4 An example of a flowchart 400 for supporting configurable check levels according to an example as disclosed herein is illustrated. Flowchart 400 may illustrate an example of a flowchart 400 for supporting configurable check levels according to an example as disclosed herein. Figures 1 to 3 The described processes are implemented by system 100 (or one or more components thereof), system 200 (or one or more components thereof), or system 300 (or one or more components thereof). The flowcharts may illustrate processes for performing a check operation based on or in response to a configurable check command.

[0088] Aspects of flowchart 400 may be implemented by one or more controllers, as well as other components (e.g., a memory system controller of a memory system, a command processor of a memory system, a host system controller of a host system). Additionally or alternatively, aspects of flowchart 400 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a memory system). For example, if executed by a controller, the instructions may cause the controller to perform the operations of flowchart 400. Alternative examples of the following may be implemented, in which some of the processes are performed in a different order than described or not performed at all. In some cases, the operations may include features not mentioned below, or additional operations may be added.

[0089] At 405, a target reliability level for a data set stored in a memory device may be determined. In some examples, a host device may determine a target reliability level for the data set. The host device may determine the target level or reliability based on or in response to one or more commands to be executed on the data set, an operating mode associated with the memory device or a memory system including the memory device, time available for the host device to execute a check command and a corresponding verification operation, a size of the data set (e.g., a logical range), physical stressors associated with the data set, and the like. That is, the target reliability level may be based on or in response to a tradeoff between time and reliability of the data set. In some examples, the memory device may indicate a reliability level of the data set to the host device, and the host device may determine the target reliability level based on or in response to the indicated reliability level.

[0090] At 410, a command may be received. In some examples, the memory device may receive a command from a host device based on or in response to the host device determining a target reliability level. The command may be a verify command and may indicate a target reliability level for a data set. The command may indicate a request to perform an error management operation for the data set based on or in response to the target reliability level. The memory device may identify a bit, bit field, or attribute in the command (e.g., in a CDB of the command) that indicates the target reliability level. An example verify command CDB is illustrated in Table 1.

[0091]

[0092] Table 1: Example verification command CDB

[0093] As illustrated by the example check command CDB in Table 1, the check command CDB may include a set of bits configured to indicate the LBA of the data set selected for the check operation. For example, the check command CDB may indicate the least significant bit and the most significant bit corresponding to the LBA of the data set. The check command CDB may additionally or alternatively include an operation code indicating the command type and one or more reserved bit sets. In some examples, bits, bit fields, or both may be selected from the reserved bit set within the check command CDB to transmit a target reliability level and one or more error management operations for the check operation. If the target reliability level is transmitted via a bit field, each target reliability level and each error management operation may be associated with one or more bits in the bit field, and the host device may select or indicate which target level or error management operation will be performed using a bit mask to select the corresponding bit during the check operation. In other words, each target reliability level may correspond to a different bit combination in the bit field.

[0094] In some examples, a target reliability level and one or more corresponding error management operations may be indicated via attributes associated with a verify command. Example attributes specifically used to indicate a reliability level for a verify operation are illustrated in Table 2. Attributes may be provided for a host device to indicate a target reliability level and corresponding error management operations without changing or altering the verify command CDB. In some examples, the attributes may include parameters for a UFS device.

[0095]

[0096] Table 2: Instance verification command attributes

[0097] At 415, a target reliability level may be determined from a set of target reliability levels. In some examples, the memory device may determine which target reliability level of the set of target reliability levels is indicated for the data set based on or in response to a command (e.g., based on or in response to a value of a bit, a value of a bit field, or one or more parameters communicated via an attribute). The set of target reliability levels may be configured for the memory device, and each target reliability level in the set corresponds to a respective set of one or more error management operations. Additionally or alternatively, the memory device may determine the one or more error management operations based on an indication in a verify command.

[0098] The one or more error management operations may include an error correction operation based on the reduced error correction capability, a read margin adjustment operation, a refresh operation, an error handling operation, one or more other error management operations, or any combination thereof. The error management operation may refer to Figure 3 Thus, the memory device may identify, based on or in response to a command, one or more error management operations corresponding to a target reliability level for a data set.

[0099] At 420, if the target reliability level is a first target reliability level in the set of target reliability levels, one of a read margin adjustment operation or an error correction operation may be performed. In some examples, the memory device may perform one of a read margin adjustment operation or an error correction operation of the data set based on or in response to the command and the first target reliability level, wherein the first target reliability level may correspond to one of the read margin adjustment operation or the error correction operation.

[0100] At 425, if the target reliability level is a second target reliability level in the set of target reliability levels, both a read margin adjustment operation and an error correction operation may be performed. In some examples, the memory device may perform a read margin adjustment operation and an error correction operation of the data set based on or in response to the command and the second target reliability level, wherein the second target reliability level may correspond to both the read margin adjustment operation and the error correction operation.

[0101] At 430, if the target reliability level is a third target reliability level in the set of target reliability levels, one of a read margin adjustment operation or an error correction operation may be performed. In some examples, the memory device may perform one of a read margin adjustment operation or an error correction operation of the data set based on or in response to the command and the third target reliability level, wherein the third target reliability level may correspond to one of the read margin adjustment operation or the error correction operation. The third target reliability level may additionally or alternatively correspond to a threshold read margin associated with a refresh operation of the data set.

[0102] At 435, if the target reliability level is a fourth target reliability level in the set of target reliability levels, both a read margin adjustment operation and an error correction operation may be performed. In some examples, the memory device may perform a read margin adjustment operation and an error correction operation of the data set based on or in response to the command and the fourth target reliability level, wherein the fourth target reliability level may correspond to both the read margin adjustment operation and the error correction operation. The fourth target reliability level may additionally or alternatively correspond to a threshold read margin associated with a refresh operation of the data set.

[0103] At 440, it may be determined whether a read margin of the data set satisfies a threshold read margin corresponding to the third and fourth target reliability levels. In some examples, the memory device may determine whether the read margin satisfies the threshold read margin by determining whether a logic level (e.g., potential) of the data set is above or below a threshold logic level corresponding to the threshold read margin. After performing a read margin adjustment operation, an error correction operation, or both corresponding to the third or fourth target reliability level, the memory device may determine whether the read margin satisfies the threshold read margin.

[0104] At 445, if the read margin fails to meet the threshold read margin, a refresh operation may be performed for the data set. In some examples, the memory device may perform a refresh operation based on or in response to the read margin failing to meet the threshold and determining that the target reliability level is the third or fourth target reliability level. The read margin failing to meet the threshold may indicate that one or more errors are present in the data set. The refresh operation may be performed to ensure that the errors in the data set are fixed so that the data set can achieve the third or fourth target reliability level.

[0105] Although four example target reliability levels are described, it should be understood that any number of target reliability levels may be configured and indicated via the verify command. Additionally or alternatively, the target reliability level may correspond to any error management operation not shown, or any combination of error management operations. In one example, the verify command may indicate a fifth target reliability level. The fifth target reliability level may be similar to the host device setting the EER bit to low (e.g., to 0) in the verify error recovery mode page, as described in reference to FIG. Figure 3 described.

[0106] At 450, if the read margin satisfies the threshold read margin, or if the target reliability level is the first or second target reliability level, or after performing a refresh operation, an indication of the reliability level of the data set may be transmitted. In some instances, the memory device may transmit an indication of the reliability level of the data set to the host device based on or in response to a check command and performing one or more error management operations. In some instances, the indication of the reliability level may be transmitted via a response UPIU. The response UPIU may indicate a status response GOOD, BUSY, or CHECK CONDITION. The status response GOOD may indicate that the data set is valid or undamaged and that the error management operation is successfully performed. If the memory device is still processing a check command, a status response BUSY may be transmitted. The status response CHECK CONDITION may indicate that a failure occurred during the check operation. The memory device may transmit a SENSE KEY in addition to the status response CHECK CONDITION to indicate to the host device the type of failure that occurred during the check operation. Therefore, after performing a check operation and an error management operation, the check command status response may indicate the reliability level of the data set.

[0107] In some examples, the host device may determine a second target reliability level for the data set based on or in response to the indicated reliability level. In such cases, the host device may transmit a second verify command to the memory device based on or in response to the second target reliability level.

[0108] The system as described herein can therefore support a configurable verification process such that a host device can transmit a verification command to a memory device indicating a target reliability level from a set of configured target reliability levels. The memory device can perform one or more error management operations configured for the indicated target reliability level. This verification technique can be provided for a memory device to verify a data set and perform the configured error management level based on the state of the data and the target reliability level of the data. Verification operations performed according to configurable verification levels can reduce latency and power consumption and improve the reliability of stored data compared to other verification techniques where a verification command can indicate one or two operations to be performed on a data set.

[0109] Figure 5 A block diagram 500 is shown of a memory system 520 supporting configurable verify levels according to an example as disclosed herein. The memory system 520 may be as described in reference Figures 1 to 4 5. The memory system 520 or its various components may be examples of devices for performing various aspects of configurable check levels as described herein. For example, the memory system 520 may include a command component 525, a target reliability component 530, an error management component 535, a reliability component 540, a read margin component 545, a refresh component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0110] Command component 525 may be configured as or otherwise support means for receiving a command from a host device indicating a target reliability level associated with a data set stored in a memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level. Target reliability component 530 may be configured as or otherwise support means for determining a target reliability level from a set of target reliability levels based on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations. Error management component 535 may be configured as or otherwise support means for performing one or more error management operations for the data set based on the target reliability level. Reliability component 540 may be configured as or otherwise support means for transmitting an indication of a reliability level associated with the data set to the host device in response to the command based on performing the one or more error management operations.

[0111] In some examples, the target reliability component 530 may be configured as or otherwise support a device for identifying a bit, a bit field, or an attribute in a command that is configured to indicate a target reliability level, wherein determining the target reliability level from the set of target reliability levels is based on the value of the bit, the value of the bit field, or one or more parameters conveyed via the attribute.

[0112] In some examples, the command is a verify command that includes a reserved bit set within the CDB, and a bit, a bit field, or both are selected from the reserved bit set to convey a target reliability level corresponding to the verify operation.

[0113] In some examples, based on the target reliability level, the one or more error management operations include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof. In some examples, the reduced error correction capability corresponds to an error correction operation performed in a configured time period. In some examples, performing the read margin adjustment operation includes adjusting a read margin to verify the data set.

[0114] In some examples, the target reliability component 530 may be configured or otherwise support means for determining, based on the command, that the target reliability level is a first target reliability level in the set of target reliability levels, wherein the first target reliability level corresponds to a read margin adjustment operation or an error correction operation according to a reduced error correction capability. In some examples, the error management component 535 may be configured or otherwise support means for performing one of the read margin adjustment operation or the error correction operation according to the first target reliability level.

[0115] In some examples, the target reliability component 530 may be configured or otherwise support means for determining, based on the command, that the target reliability level is a second target reliability level in the set of target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation according to a reduced error correction capability. In some examples, the error management component 535 may be configured or otherwise support means for performing a read margin adjustment operation and an error correction operation according to the second target reliability level.

[0116] In some examples, the target reliability component 530 may be configured to or otherwise support means for determining, based on the command, that the target reliability level is a third target reliability level in the set of target reliability levels, wherein the third target reliability level corresponds to one of a refresh operation and a read margin adjustment operation or an error correction operation according to a reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation. In some examples, the error management component 535 may be configured to or otherwise support means for performing one of a read margin adjustment operation or an error correction operation according to the third target reliability level. In some examples, the read margin component 545 may be configured to or otherwise support means for determining, based on the third target reliability level, whether a read margin associated with the data set satisfies a threshold read margin, and performing one of a read margin adjustment operation or an error correction operation.

[0117] In some examples, refresh component 550 may be configured as or otherwise support means for performing a refresh operation of a data set based on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0118] In some examples, the target reliability component 530 may be configured to or otherwise support means for determining, based on the command, that the target reliability level is a fourth target reliability level in the set of target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation according to a reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation. In some examples, the error management component 535 may be configured to or otherwise support means for performing a read margin adjustment operation and an error correction operation according to the fourth target reliability level. In some examples, the read margin component 545 may be configured to or otherwise support means for determining, based on the fourth target reliability level, whether a read margin associated with a data set satisfies a threshold read margin, and performing a read margin adjustment operation and an error correction operation.

[0119] In some examples, refresh component 550 may be configured as or otherwise support means for performing a refresh operation of a data set based on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0120] In some examples, command component 525 may be configured or otherwise support means for receiving from the host device a second command indicating a second target reliability level associated with the data set based on the indication of the reliability level of the data set and one or more error management operations.

[0121] Figure 6A block diagram 600 is shown of a host system 620 supporting configurable check levels according to an example as disclosed herein. The host system 620 may be a Figures 1 to 4 6. The host system 620 or its various components can be examples of devices for performing various aspects of configurable check levels as described herein. For example, the host system 620 can include a target reliability component 625, a command component 630, a reliability component 635, an error management component 640, or any combination thereof. Each of these components can communicate with each other directly or indirectly (e.g., via one or more buses).

[0122] The target reliability component 625 may be configured as or otherwise support means for determining a target reliability level associated with a data set stored in a memory device coupled to the memory system. The command component 630 may be configured as or otherwise support means for transmitting a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level. The reliability component 635 may be configured as or otherwise support means for receiving an indication of a reliability level associated with the data set from the memory device in response to the command based on the one or more error management operations.

[0123] In some examples, the target reliability component 625 can be configured as or otherwise support means for transmitting in a command a bit, a bit field, or an attribute configured to indicate a target reliability level selected from a set of target reliability levels, wherein one or more parameters transmitted via a value of a bit, a value of a bit field, or via an attribute indicate the target reliability level. In some examples, the command is a check command that includes a reserved bit set within a CDB, and the bit, the bit field, or both are selected from the reserved bit set to transmit the target reliability level corresponding to the check operation.

[0124] In some examples, the target reliability level is selected from a set of target reliability levels. In some examples, based on the selected target reliability level, the one or more error management operations include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof. In some examples, the reduced error correction capability corresponds to an error correction operation performed in a configured time period. In some examples, the read margin adjustment operation corresponds to an adjustment of a read margin to verify the data set.

[0125] In some examples, to support a transfer command, command component 630 may be configured as or otherwise support means for transferring a command indicating a first target reliability level in the set of target reliability levels, wherein the first target reliability level corresponds to one of a read margin adjustment operation or an error correction operation according to a reduced error correction capability.

[0126] In some examples, to support the transfer command, command component 630 may be configured as or otherwise support means for transferring a command indicating a second target reliability level in the set of target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation according to a reduced error correction capability.

[0127] In some examples, to support a transfer command, command component 630 may be configured as or otherwise support means for transferring a command indicating a third target reliability level in the set of target reliability levels, wherein the third target reliability level corresponds to one of a refresh operation and a read margin adjustment operation or an error correction operation according to a reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation.

[0128] In some examples, to support a transfer command, command component 630 may be configured as or otherwise support a device for transferring a command indicating a fourth target reliability level in the set of target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation based on a reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation.

[0129] In some examples, command component 630 can be configured or otherwise support means for transmitting to the memory device a second command indicating a second target reliability level associated with the data set based on the indication of the reliability level of the data set and one or more error management operations.

[0130] Figure 7 Flowchart showing a method 700 of supporting configurable verification levels according to examples as disclosed herein. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 5 The described memory system performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0131] At 705, the method may include receiving a command from a host device indicating a target reliability level associated with a data set stored in a memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level. The operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be described by reference to Figure 5 The described command component 525 is executed.

[0132] At 710, the method may include determining a target reliability level from a set of target reliability levels based on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations. The operations of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 710 may be as described in reference to Figure 5 The target reliability component 530 is described as executing.

[0133] At 715, the method may include performing one or more error management operations on the data set based on the target reliability level. The operations of 715 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 715 may be as described in reference to Figure 5 The described error management component 535 performs.

[0134] At 720, the method may include transmitting an indication of a reliability level associated with the data set to the host device in response to the command based on performing one or more error management operations. The operations of 720 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 720 may be described by reference to Figure 5 The reliability component 540 performs as described.

[0135] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command from a host device for a target reliability level associated with a data set stored in a memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; determining a target reliability level from a set of target reliability levels based on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; performing the one or more error management operations for the data set based on the target reliability level; and transmitting to the host device an indication of the reliability level associated with the data set in response to the command based on performing the one or more error management operations.

[0136] Method 700 and some instances of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for identifying in a command a bit, a bit field, or an attribute configured to indicate a target reliability level, wherein determining the target reliability level from the set of target reliability levels may be based on a value of a bit, a value of a bit field, or one or more parameters conveyed via the attribute.

[0137] In some examples of method 700 and apparatus described herein, the command may be a check command including a reserved bit set within a CDB, and a bit, a bit field, or both may be selected from the reserved bit set to convey a target reliability level corresponding to the check operation.

[0138] In some examples of method 700 and apparatus described herein, according to a target reliability level, one or more error management operations include error correction operations according to reduced error correction capability, read margin adjustment operations, refresh operations, enabling early recovery operations, or any combination thereof.

[0139] In some examples of the method 700 and apparatus described herein, the reduced error correction capability corresponds to an error correction operation performed in a configured time period, and performing the read margin adjustment operation includes adjusting the read margin to verify the data set.

[0140] Method 700 and some instances of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for: determining based on the command that a target reliability level may be a first target reliability level in the set of target reliability levels, wherein the first target reliability level corresponds to a read margin adjustment operation or an error correction operation based on reduced error correction capability; and performing one of the read margin adjustment operation or the error correction operation based on the first target reliability level.

[0141] Method 700 and some instances of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for: determining based on the command that the target reliability level may be a second target reliability level in the set of target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation based on a reduced error correction capability; and performing the read margin adjustment operation and the error correction operation based on the second target reliability level.

[0142] Some instances of method 700 and the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for: determining based on the command that the target reliability level may be a third target reliability level in the set of target reliability levels, wherein the third target reliability level corresponds to a refresh operation and one of a read margin adjustment operation or an error correction operation based on reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation; performing one of the read margin adjustment operation or the error correction operation based on the third target reliability level; and determining whether the read margin associated with the data set satisfies the threshold read margin based on the third target reliability level and performing one of the read margin adjustment operation or the error correction operation.

[0143] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing a refresh operation of the data set based on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0144] Method 700 and some instances of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for: determining based on the command that the target reliability level may be a fourth target reliability level in the set of target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation based on reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation; performing a read margin adjustment operation and an error correction operation based on the fourth target reliability level; and determining whether a read margin associated with the data set satisfies a threshold read margin based on the fourth target reliability level and performing the read margin adjustment operation and the error correction operation.

[0145] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing a refresh operation of the data set based on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0146] Method 700 and some examples of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for receiving a second command from a host device indicating a second target reliability level associated with the data set based on an indication of a reliability level of the data set and one or more error management operations.

[0147] Figure 8800 according to an example disclosed herein. The operations of the method 800 may be implemented by a host system or components thereof as described herein. For example, the method 800 may be implemented by a host system or components thereof as described herein. Figures 1 to 4 The host system described in and 6 performs the operations of method 800. In some examples, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0148] At 805, the method may include determining a target reliability level associated with a data set stored in a memory device coupled to a memory system. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 805 may be described by reference to Figure 6 The target reliability component 625 performs as described.

[0149] At 810, the method may include transmitting a command indicating a target reliability level to a memory device, wherein the command indicates a request to perform one or more error management operations for a data set based on the target reliability level. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 810 may be described by reference to Figure 6 The command component 630 is described to execute.

[0150] At 815, the method may include receiving an indication of a reliability level associated with the data set from the memory device in response to the command based on the one or more error management operations. The operations of 815 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 815 may be described by reference to Figure 6 The reliability component 635 performs as described.

[0151] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining a target reliability level associated with a data set stored in a memory device coupled to a memory system; transmitting a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based on the target reliability level; and receiving an indication of the reliability level associated with the data set from the memory device in response to the command based on the one or more error management operations.

[0152] Method 800 and some instances of the apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for transmitting in a command a bit, a bit field, or an attribute configured to indicate a target reliability level selected from a set of target reliability levels, wherein the target reliability level may be indicated via a value of the bit, a value of the bit field, or one or more parameters conveyed via the attribute.

[0153] In some examples of method 800 and apparatus described herein, the command may be a check command including a reserved bit set within a CDB, and a bit, a bit field, or both may be selected from the reserved bit set to convey a target reliability level corresponding to the check operation.

[0154] In some examples of method 800 and the apparatus described herein, a target reliability level may be selected from a set of target reliability levels, and based on the selected target reliability level, one or more error management operations include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof.

[0155] In some examples of method 800 and apparatus described herein, the reduced error correction capability corresponds to an error correction operation performed in a configured time period, and the read margin adjustment operation corresponds to an adjustment of a read margin to verify the data set.

[0156] In some examples of method 800 and the apparatus described herein, a transmission command may include operations, features, circuit systems, logic, means, or instructions for transmitting a command indicating a first target reliability level in the set of target reliability levels, wherein the first target reliability level corresponds to one of a read margin adjustment operation or an error correction operation according to a reduced error correction capability.

[0157] In some examples of method 800 and the apparatus described herein, a transmission command may include operations, features, circuit systems, logic, devices, or instructions for transmitting a command indicating a second target reliability level in the set of target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation according to a reduced error correction capability.

[0158] In some examples of method 800 and the apparatus described herein, a transmission command may include operations, features, circuit systems, logic, devices, or instructions for transmitting a command indicating a third target reliability level in the set of target reliability levels, wherein the third target reliability level corresponds to one of a refresh operation and a read margin adjustment operation or an error correction operation according to a reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation.

[0159] In some examples of method 800 and the apparatus described herein, a transmission command may include operations, features, circuit systems, logic, devices, or instructions for transmitting a command indicating a fourth target reliability level in the set of target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation according to a reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation.

[0160] Method 800 and some examples of the apparatus described herein may further include operations, features, circuit systems, logic, devices, or instructions for transmitting to the memory device a second command indicating a second target reliability level associated with the data set based on the indication of the reliability level of the data set and one or more error management operations.

[0161] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0162] An apparatus is described. The apparatus may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the apparatus to receive a command from a host device indicating a target reliability level associated with a data set stored in the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; determine a target reliability level from a plurality of target reliability levels based at least in part on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; perform the one or more error management operations for the data set based at least in part on the target reliability level; and transmit to the host device an indication of the reliability level associated with the data set in response to the command based at least in part on performing the one or more error management operations.

[0163] In some cases, the controller may be further configured to cause the device to identify in the command a bit, a bit field, or an attribute configured to indicate a target reliability level, wherein determining the target reliability level from a plurality of target reliability levels is based at least in part on a value of the bit, a value of the bit field, or one or more parameters conveyed via the attribute.

[0164] In some instances of the apparatus, the command is a verify command including a reserved bit set within a command descriptor block, and a bit, a bit field, or both are selected from the reserved bit set to convey a target reliability level corresponding to the verify operation.

[0165] In some examples of the apparatus, according to the target reliability level, the one or more error management operations include an error correction operation according to a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof.

[0166] In some examples of the apparatus, the reduced error correction capability corresponds to an error correction operation performed in the configured time period, and performing the read margin adjustment operation includes adjusting the read margin to verify the data set.

[0167] In some cases, the controller may be further configured to cause the device to: determine, based at least in part on the command, that the target reliability level is a first target reliability level among multiple target reliability levels, wherein the first target reliability level corresponds to a read margin adjustment operation or an error correction operation based on reduced error correction capability; and perform one of the read margin adjustment operation or the error correction operation based on the first target reliability level.

[0168] In some cases, the controller is further configured to cause the device to: determine, at least in part based on the command, that the target reliability level is a second target reliability level among multiple target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation based on a reduced error correction capability; and perform the read margin adjustment operation and the error correction operation based on the second target reliability level.

[0169] In some cases, the controller may be further configured to cause the device to: determine, based at least in part on the command, that the target reliability level is a third target reliability level among multiple target reliability levels, wherein the third target reliability level corresponds to a refresh operation and one of a read margin adjustment operation or an error correction operation based on reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation; perform one of the read margin adjustment operation or the error correction operation based on the third target reliability level; and determine whether a read margin associated with the data set satisfies the threshold read margin based at least in part on the third target reliability level and performing one of the read margin adjustment operation or the error correction operation.

[0170] In some cases, the controller may be further configured to cause the apparatus to perform a refresh operation of the data set based at least in part on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0171] In some cases, the controller may be further configured to cause the device to: determine, based at least in part on the command, that the target reliability level is a fourth target reliability level among multiple target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation based on a reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation; perform a read margin adjustment operation and an error correction operation based on the fourth target reliability level; and determine whether a read margin associated with a data set satisfies a threshold read margin based at least in part on the fourth target reliability level and performing the read margin adjustment operation and the error correction operation.

[0172] In some cases, the controller may be further configured to cause the apparatus to perform a refresh operation of the data set based at least in part on determining that a read margin associated with the data set fails to satisfy a threshold read margin.

[0173] In some cases, the controller may be further configured to cause the apparatus to receive, from the host device, a second command indicating a second target reliability level associated with the data set based at least in part on the indication of the reliability level of the data set and the one or more error management operations.

[0174] An apparatus is described. The apparatus may include a controller configured to be coupled to a memory system. The controller may be configured to cause the apparatus to: determine a target reliability level associated with a data set stored in a memory device coupled to the memory system; transmit a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; and receive an indication of the reliability level associated with the data set from the memory device in response to the command based at least in part on the one or more error management operations.

[0175] In some cases, the controller may be further configured to cause the device to transmit in the command a bit, a bit field, or an attribute configured to indicate a target reliability level selected from a plurality of target reliability levels, wherein the target reliability level is indicated via the value of the bit, the value of the bit field, or one or more parameters transmitted via the attribute.

[0176] In some instances of the apparatus, the command is a verify command including a reserved bit set within a command descriptor block, and a bit, a bit field, or both are selected from the reserved bit set to convey a target reliability level corresponding to the verify operation.

[0177] In some instances of the apparatus, a target reliability level is selected from a plurality of target reliability levels, and based on the selected target reliability level, the one or more error management operations include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof.

[0178] In some examples of the apparatus, the reduced error correction capability corresponds to an error correction operation performed in a configured time period, and the read margin adjustment operation corresponds to an adjustment of a read margin to verify the data set.

[0179] In some instances of the device, when transmitting the command, the controller may be further configured to cause the device to transmit a command indicating a first target reliability level among a plurality of target reliability levels, wherein the first target reliability level corresponds to one of a read margin adjustment operation or an error correction operation according to a reduced error correction capability.

[0180] In some examples of the apparatus, when transmitting the command, the controller may be further configured to cause the apparatus to transmit a command indicating a second target reliability level among a plurality of target reliability levels, wherein the second target reliability level corresponds to a read margin adjustment operation and an error correction operation according to a reduced error correction capability.

[0181] In some instances of the device, when transmitting the command, the controller may be further configured to cause the device to transmit a command indicating a third target reliability level among a plurality of target reliability levels, wherein the third target reliability level corresponds to one of a refresh operation and a read margin adjustment operation or an error correction operation according to a reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation.

[0182] In some instances of the device, when transmitting the command, the controller may be further configured to cause the device to transmit a command indicating a fourth target reliability level among multiple target reliability levels, wherein the fourth target reliability level corresponds to a read margin adjustment operation, an error correction operation based on a reduced error correction capability, and a refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation.

[0183] In some examples of the apparatus, when transmitting the command, the controller may be further configured to cause the apparatus to transmit to the memory device a second command indicating a second target reliability level associated with the data set based at least in part on the indication of the reliability level of the data set and the one or more error management operations.

[0184] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0185] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0186] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components in which signals are able to communicate between components through conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0187] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. If a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0188] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0189] The term "responsive to" may refer to a condition or action that occurs at least in part, if not completely, as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0190] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to" or "directly in response to" such other condition or action.

[0191] The devices including memory arrays discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0192] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped, such as degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0193] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0194] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0195] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted by a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0196] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0197] As used herein, "or", as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0198] Computer-readable media include both non-transitory computer-readable storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. Any other non-transitory media. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of media. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0199] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receiving, from a host device, a command indicating a target reliability level associated with a data set stored in the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; determining the target reliability level from a plurality of target reliability levels based at least in part on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; performing the one or more error management operations for the data set based at least in part on the target reliability level; and An indication of a reliability level associated with the data set is transmitted to the host device in response to the command based at least in part on performing the one or more error management operations.

2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: A bit, a bit field, or an attribute configured to indicate the target reliability level is identified in the command, wherein determining the target reliability level from the multiple target reliability levels is based at least in part on a value of the bit, a value of the bit field, or one or more parameters conveyed via the attribute.

3. The apparatus of claim 2, wherein the command is a verify command including a reserved bit set within a command descriptor block, and the bit, the bit field, or both are selected from the reserved bit set to convey the target reliability level corresponding to a verify operation.

4. The apparatus of claim 1 , wherein according to the target reliability level, the one or more error management operations include an error correction operation according to a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof.

5. The apparatus according to claim 4, wherein: The reduced error correction capability corresponds to the error correction operation performed during the configured time period; and Performing the read margin adjustment operation includes adjusting a read margin to verify the data set.

6. The apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: determining, based at least in part on the command, that the target reliability level is a first target reliability level among the plurality of target reliability levels, wherein the first target reliability level corresponds to the read margin adjustment operation or the error correction operation according to the reduced error correction capability; and One of the read margin adjustment operation or the error correction operation is performed according to the first target reliability level.

7. The apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: determining, based at least in part on the command, that the target reliability level is a second target reliability level among the plurality of target reliability levels, wherein the second target reliability level corresponds to the read margin adjustment operation and the error correction operation according to the reduced error correction capability; and The read margin adjustment operation and the error correction operation are performed according to the second target reliability level.

8. The apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: determining, based at least in part on the command, that the target reliability level is a third target reliability level among the plurality of target reliability levels, wherein the third target reliability level corresponds to one of the refresh operation and the read margin adjustment operation or the error correction operation in accordance with the reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation; performing one of the read margin adjustment operation or the error correction operation according to the third target reliability level; and A determination is made whether a read margin associated with the data set satisfies the threshold read margin based at least in part on the third target reliability level and performing the one of the read margin adjustment operation or the error correction operation.

9. The apparatus of claim 8, wherein the controller is further configured to cause the apparatus to: The refresh operation of the data set is performed based at least in part on determining that the read margin associated with the data set fails to satisfy the threshold read margin.

10. The apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: determining, based at least in part on the command, that the target reliability level is a fourth target reliability level among the plurality of target reliability levels, wherein the fourth target reliability level corresponds to the read margin adjustment operation, the error correction operation in accordance with the reduced error correction capability, and the refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation; performing the read margin adjustment operation and the error correction operation according to the fourth target reliability level; and A determination is made whether a read margin associated with the data set satisfies the threshold read margin based at least in part on the fourth target reliability level and performing the read margin adjustment operation and the error correction operation.

11. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: The refresh operation of the data set is performed based at least in part on determining that the read margin associated with the data set fails to satisfy the threshold read margin.

12. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: A second command is received from the host device indicating a second target reliability level associated with the data set based at least in part on the indication of the reliability level of the data set and the one or more error management operations.

13. An apparatus comprising: a controller configured to be coupled to a memory system, wherein the controller is configured to cause the apparatus to: determining a target reliability level associated with a data set stored in a memory device coupled to the memory system; transmitting a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; and An indication of a reliability level associated with the data set is received from the memory device in response to the command based at least in part on the one or more error management operations.

14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: A bit, a bit field, or an attribute configured to indicate the target reliability level selected from a plurality of target reliability levels is transmitted in the command, wherein the target reliability level is indicated by a value of the bit, a value of the bit field, or one or more parameters conveyed via the attribute.

15. The apparatus of claim 14, wherein the command is a verify command including a reserved bit set within a command descriptor block, and the bit, the bit field, or both are selected from the reserved bit set to convey the target reliability level corresponding to a verify operation.

16. The apparatus of claim 13, wherein: selecting the target reliability level from a plurality of target reliability levels; and Depending on the target reliability level selected, the one or more error management operations include an error correction operation based on a reduced error correction capability, a read margin adjustment operation, a refresh operation, an enable early recovery operation, or any combination thereof.

17. The apparatus of claim 16, wherein: The reduced error correction capability corresponds to the error correction operation performed during the configured time period; and The read margin adjustment operation corresponds to an adjustment of a read margin to verify the data set.

18. The apparatus of claim 16, wherein when transmitting the command, the controller is further configured to cause the apparatus to: A command indicating a first target reliability level among the plurality of target reliability levels is transmitted, wherein the first target reliability level corresponds to one of a read margin adjustment operation or the error correction operation according to the reduced error correction capability.

19. The apparatus of claim 16, wherein when transmitting the command, the controller is further configured to cause the apparatus to: A command indicating a second target reliability level among the plurality of target reliability levels is transmitted, wherein the second target reliability level corresponds to the read margin adjustment operation and the error correction operation according to the reduced error correction capability.

20. The apparatus of claim 16, wherein when transmitting the command, the controller is further configured to cause the apparatus to: A command is transmitted indicating a third target reliability level among the plurality of target reliability levels, wherein the third target reliability level corresponds to one of the refresh operation and the read margin adjustment operation or the error correction operation according to the reduced error correction capability, and wherein the third target reliability level indicates a threshold read margin associated with the refresh operation.

21. The apparatus of claim 16, wherein when transmitting the command, the controller is further configured to cause the apparatus to: A command is transmitted indicating a fourth target reliability level among the plurality of target reliability levels, wherein the fourth target reliability level corresponds to the read margin adjustment operation, the error correction operation according to the reduced error correction capability, and the refresh operation, and wherein the fourth target reliability level indicates a threshold read margin associated with the refresh operation.

22. The apparatus of claim 13, wherein when transmitting the command, the controller is further configured to cause the apparatus to: A second command indicating a second target reliability level associated with the data set is transmitted to the memory device based at least in part on the indication of the reliability level of the data set and the one or more error management operations.

23. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving, from a host device, a command indicating a target reliability level associated with a data set stored in a memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; determining the target reliability level from a plurality of target reliability levels based at least in part on the command, each target reliability level corresponding to a respective one or more error management operations, wherein the target reliability level corresponds to the one or more error management operations; performing the one or more error management operations for the data set based at least in part on the target reliability level; and An indication of a reliability level associated with the data set is transmitted to the host device in response to the command based at least in part on performing the one or more error management operations.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A bit, a bit field, or an attribute configured to indicate the target reliability level is identified in the command, wherein determining the target reliability level from the multiple target reliability levels is based at least in part on a value of the bit, a value of the bit field, or one or more parameters conveyed via the attribute.

25. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: determining a target reliability level associated with a data set stored in a memory device coupled to a memory system; transmitting a command indicating the target reliability level to the memory device, wherein the command indicates a request to perform one or more error management operations for the data set based at least in part on the target reliability level; and An indication of a reliability level associated with the data set is received from the memory device in response to the command based at least in part on the one or more error management operations.

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