Memory device for performing read operations and operating method thereof

Abstract

The present application relates to a memory device for performing a read operation and an operating method thereof. The present technology relates to an electronic device. The memory device according to the present technology includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first read voltage or a second read voltage to the word line and obtain data stored in the plurality of memory cells through bit lines respectively connected to the plurality of memory cells, and a read voltage controller configured to, in response to a read command, control the operation controller to read the data stored in the plurality of memory cells by using the second read voltage and read the data stored in the plurality of memory cells by using the first read voltage according to a number of cut-off cells counted based on the data read by using the second read voltage.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an electronic device, and more particularly, to a memory device for performing a read operation and a method of operating the memory device. BACKGROUND

[0002] A memory device (semiconductor memory device) is a memory device implemented by using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Memory devices are mainly classified into volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a memory device in which stored data is lost when power is turned off. The volatile memory device includes a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like. A non-volatile memory device is a memory device that retains stored data even when power is turned off. The non-volatile memory device includes a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like. The flash memory is mainly classified into a NOR type and a NAND type. SUMMARY

[0004] According to an embodiment of the disclosure, a memory device includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first read voltage or a second read voltage to the word line, and configured to obtain data stored in the plurality of memory cells through bit lines respectively connected to the plurality of memory cells, wherein the second read voltage is higher than the first read voltage, and a read voltage controller configured to, in response to a read command input from an external controller, the read command providing an indication to read data stored in the plurality of memory cells, control the operation controller to read the data stored in the plurality of memory cells by using the second read voltage, and control the operation controller to read the data stored in the plurality of memory cells by using the first read voltage according to a number of cut cells counted based on the data read by using the second read voltage.

[0005] According to an embodiment of the disclosure, a memory device includes a plurality of memory cells connected to a word line, an operation controller configured to perform a program operation of storing a plurality of pages of data each including a plurality of bits in the plurality of memory cells, and configured to perform a read operation of obtaining the plurality of pages of data stored in the plurality of memory cells, the program operation including a first program step and a second program step, the plurality of pages of data including a plurality of logical pages, and a read voltage controller configured to, in response to a read command providing an indication of reading one logical page among the plurality of logical pages, control the operation controller to determine whether to perform the program step up to the first program step or the second program step based on a number of 0s or 1s included in sensing data obtained by sensing data stored in the plurality of memory cells by using a second read voltage, and configured to, when the program step of the plurality of memory cells is the first program step, sense the data stored in the plurality of memory cells by using a first read voltage having a lower voltage than the second read voltage.

[0006] According to an embodiment of the disclosure, a method of operating a memory device for reading data stored in a memory cell by using a first read voltage or a second read voltage includes reading the data stored in the memory cell by using the second read voltage, counting a number of cut-off cells among the memory cells by using the second read voltage, and reading the data stored in the memory cell by using a first read voltage having a lower voltage than the second read voltage based on the counted number of the cut-off cells. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 FIG. 1 is a diagram illustrating a memory system including a memory device according to an embodiment of the disclosure.

[0008] Figure 2 FIG. 2 is a diagram illustrating a configuration of the memory device of FIG. 1. Figure 1

[0009] Figure 3 FIG. 3 is a diagram illustrating a configuration of any one of a plurality of memory blocks BLK1 to BLKi of FIG. 2. Figure 2

[0010] Figure 4 FIG. 4 is a diagram illustrating a first program step according to an embodiment of the disclosure.

[0011] Figure 5 FIG. 5 is a diagram illustrating a second program step according to an embodiment of the disclosure.

[0012] Figure 6 FIG. 6 is a diagram illustrating a threshold voltage distribution of a memory cell which is changed according to a program step according to an embodiment of the disclosure. ​​

[0013] Figure 7 FIG. 1 is a diagram illustrating a programming sequence between word lines according to an embodiment of the present disclosure.

[0014] Figure 8 FIG. 2 is a diagram illustrating a threshold voltage distribution of a memory cell storing at least one bit of data according to an embodiment of the present disclosure.

[0015] Figure 9 FIG. 3 is a diagram illustrating an operation of reading data by changing a second read voltage to a first read voltage according to an embodiment of the present disclosure.

[0016] Figure 10 FIG. 4 is a diagram illustrating a voltage code corresponding to a read voltage according to an embodiment of the present disclosure.

[0017] Figure 11 FIG. 5 is a diagram illustrating an operation of moving a plurality of memory cells corresponding to a chunk to a cell counter according to an embodiment of the present disclosure.

[0018] Figure 12 FIG. 6 is a flowchart illustrating a method of changing a second read voltage to a first read voltage according to an embodiment of the present disclosure.

[0019] Figure 13 FIG. 7 is a flowchart illustrating another example of a method of changing a second read voltage to a first read voltage according to an embodiment of the present disclosure.

[0020] Figure 14 FIG. 8 is a diagram illustrating a memory controller of FIG. 1. Figure 1

[0021] Figure 15 FIG. 9 is a block diagram illustrating a memory card system to which a memory system according to an embodiment of the present disclosure is applied.

[0022] Figure 16 FIG. 10 is a block diagram illustrating a solid state drive (SSD) system to which a memory system according to an embodiment of the present disclosure is applied.

[0023] Figure 17 FIG. 11 is a block diagram illustrating a user system to which a memory system according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0024] The specific configuration or function descriptions according to the embodiments of the concept disclosed in the present specification are merely illustrated in order to describe the embodiments of the concept according to the present disclosure. The embodiments of the concept according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in the present specification.

[0025] ​Embodiments of the present disclosure provide a memory device for performing a read operation at an improved read speed and a method of operating the memory device.

[0026] According to embodiments of the present disclosure, a memory device for performing a read operation at an improved read speed and a method of operating the memory device are provided.

[0027] Figure 1 FIG. 1 is a diagram illustrating a memory system including a memory device according to embodiments of the present disclosure.

[0028] Referring to Figure 1 The memory system 50 can include a memory device 100 and a memory controller 200. The memory system 50 can be a device that stores data based on an instruction of a host 300 such as a cellular phone, a smart phone, an MP3 player, a notebook computer, a desktop computer, a game machine, a TV, a tablet PC, or a car infotainment system.

[0029] The memory system 50 can be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the memory system 50 can be configured as any one of various types of storage devices such as an SSD, a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI-express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0030] The memory system 50 can be manufactured as any one of various types of packages. For example, the memory system 50 can be manufactured as any one of various types of package types such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level chip scale package (WSP).

[0031] The memory device 100 can store data. The memory device 100 operates based on the memory controller 200. The memory device 100 can include a memory cell array (not shown) having a plurality of memory cells that store data.

[0032] Each of the memory cells can be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) capable of storing four bits of data.

[0033] The memory cell array (not shown) can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. One memory block can include a plurality of pages. In an embodiment, a page can be a unit for storing data in or reading data stored in the memory device 100. A memory block can be a unit for erasing data.

[0034] In an embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin-transfer torque random access memory (STT-RAM), or the like. In the present specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

[0035] The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a region selected by the address in the memory cell array. The command can instruct the memory device 100 to perform an operation on the region selected by the address. For example, the memory device 100 can perform a write operation (a program operation), a read operation, and an erase operation. During the write operation, the memory device 100 can program data in the region selected by the address. During the read operation, the memory device 100 can read data from the region selected by the address. During the erase operation, the memory device 100 can erase data stored in the region selected by the address.

[0036] In an embodiment, the memory device 100 can include an operation controller 140 and a read voltage controller 150.

[0037] The operation controller 140 can control a program operation and a read operation of the memory device 100. The program operation can be an operation of storing data in a memory cell included in the memory device 100. The read operation can be an operation of obtaining data stored in the memory cell.

[0038] Specifically, the programming operation can be an operation of increasing a threshold voltage of the memory cell according to data to be stored in the memory cell. In this specification, the present disclosure is described under the assumption that the memory cell is programmed in TLC storing three-bit data. When the programming operation is performed, each memory cell can have a threshold voltage corresponding to any one of an erased state and first to seventh programmed states. The threshold voltage of the memory cell after the programming operation is performed can be determined according to data to be stored in the memory cell. According to the data to be stored, each memory cell can have any one of the erased state and the first to seventh programmed states as a target programmed state.

[0039] In an embodiment, the programming operation can include a first programming step and a second programming step. The memory cell can be programmed to have a threshold voltage corresponding to any one of an erased state or an intermediate state through the first programming step. Thereafter, each memory cell can be programmed to have a threshold voltage corresponding to a target programmed state through the second programming step.

[0040] In an embodiment, when each memory cell is programmed in TLC storing three-bit data, data stored in one page can be multi-page data. For example, the multi-page data can include a plurality of logical pages. Specifically, the plurality of logical pages can include a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page.

[0041] In an embodiment, the read operation can be an operation of applying a read voltage to the memory cell in which data is stored and sensing data stored in the memory cell in a state in which the read voltage is applied. The read operation can be an operation of obtaining data stored in the memory cell. Since the threshold voltage of the memory cell is determined according to the stored data, the read operation can be an operation of identifying a state of the threshold voltage of each memory cell. For example, when the memory cell is programmed in TLC, seven read voltages can be applied to identify a state corresponding to the threshold voltage among the erased state and the first to seventh programmed states.

[0042] Among the memory cells to which the read voltage is applied, the memory cell having a threshold voltage lower than the read voltage can be read as an on cell. The on cell can correspond to a logical value "1". Among the memory cells to which the read voltage is applied, the memory cell having a threshold voltage higher than the read voltage can be read as an off cell. The off cell can correspond to a logical value "0".

[0043] In an embodiment, the first programming step and the second programming step can be performed individually for each of a plurality of word lines connecting a plurality of memory cells. For example, a plurality of memory cells connected to a selected word line among the plurality of word lines can be programmed to the first programming step. Thereafter, a plurality of memory cells connected to a next word line of the selected word line can be programmed to the first programming step. Next, a plurality of memory cells connected to the selected word line can be programmed to the second programming step. The programming operation of the plurality of memory cells connected to the selected word line can be completed through the above-described sequence. However, the plurality of memory cells connected to the next word line of the selected word line can not be programmed to the second programming step. In addition, the programming operation can be performed simultaneously for each of a plurality of memory blocks having a plurality of memory cells. Accordingly, the plurality of memory cells included in each of the memory blocks can exist in a state of being programmed only the first programming step or exist in a state of performing the programming step up to the second programming step, a mixture of the memory cells in the first programming step and the memory cells in the second programming step.

[0044] In an embodiment, the operation controller 140 can generate the first read voltage or the second read voltage and can apply the first read voltage or the second read voltage to a word line to which a plurality of memory cells are connected. The first read voltage can be a voltage for reading data stored in a plurality of memory cells programmed to the first programming step. The second read voltage can be a voltage for reading any one of a plurality of logical pages stored in a plurality of memory cells programmed to the second programming step. For example, the second read voltage can be a voltage for reading an LSB page among a plurality of logical pages.

[0045] In an embodiment, the second programming step can be performed on a memory cell on which only the first programming step is performed. At this time, a voltage applied to obtain data stored in a memory cell on which only the first programming step is performed can be the first read voltage. In addition, when the second read voltage is applied to a plurality of memory cells, the number of memory cells on which only the first programming step is performed and the number of memory cells on which programming up to the second programming step is performed can be different. Accordingly, the performed programming step can be determined based on the number of memory cells to which the second read voltage is applied.

[0046] In an embodiment, the operation controller 140 can read data stored in a plurality of memory cells by using the second read voltage. In addition, the operation controller 140 can provide the read data to the read voltage controller 150 by using the second read voltage.

[0047] In an embodiment, the read voltage controller 150 can control the operation controller 140 to change a read voltage to be applied to a word line connected to a plurality of memory cells. For example, a memory cell programmed only with a first programming step can have to perform a read operation through a first read voltage.

[0048] In an embodiment, the read voltage controller 150 can control the operation controller 140 to change the second read voltage to the first read voltage based on the number of cut-off cells among the plurality of memory cells read by using the second read voltage and information about a reference cut-off cell number. The information about the reference cut-off cell number can be information compared with the number of cut-off cells among the plurality of memory cells read by using the second read voltage and a criterion for determining whether the number of cut-off cells among the plurality of memory cells read by using the second read voltage exceeds the reference cut-off cell number. The information about the reference cut-off cell number can include a first reference cut-off cell number and a second reference cut-off cell number. For example, when the number of cut-off cells among the plurality of memory cells to which the second read voltage is applied is equal to or less than a preset first reference cut-off cell number, the read voltage controller 150 can control the operation controller 140 to change the second read voltage to the first read voltage.

[0049] The memory controller 200 can control overall operations of the memory system 50.

[0050] When power is applied to the memory system 50, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) can include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0051] In an embodiment, the memory controller 200 can receive data and a logical block address (LBA) from the host 300, and can convert the LBA to a physical block address (PBA) indicating an address of a memory cell in which data included in the memory device 100 is to be stored. In this specification, the LBA and "logical address" or "logical's address" can be used as the same meaning. In this specification, the PBA and "physical address" can be used as the same meaning.

[0052] The memory controller 200 can control the memory device 100 to perform a write operation, a read operation, an erase operation, etc. according to a request of the host 300. During the write operation, the memory controller 200 can provide a write command, a PBA, and data to the memory device 100. During the read operation, the memory controller 200 can provide a read command and a PBA to the memory device 100. During the erase operation, the memory controller 200 can provide an erase command and a PBA to the memory device 100.

[0053] In an embodiment, the memory controller 200 can independently generate a command, an address, and data regardless of a request from the host 300, and can transmit the command, the address, and the data to the memory device 100. For example, the memory controller 200 can provide the command, the address, and the data for performing a read operation and a write operation accompanying wear leveling, read recycling, garbage collection, etc. to the memory device 100.

[0054] In an embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method can be a method of controlling operations of at least two memory devices 100 to overlap each other.

[0055] The host 300 can communicate with the memory system 50 by using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), a PCI-express (PCIe), a non-volatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a DIMM with register (RDIMM), and a load-reduced DIMM (LRDIMM).

[0056] Further, in the related art, the memory controller 200 controls the memory device 100 to determine up to which programming step is performed on a plurality of memory cells. This can take a longer time than a time of determining up to which programming step is performed on a plurality of memory cells in the memory device 100.

[0057] Accordingly, according to an embodiment of the disclosure, data can be read at an improved speed by determining a programming step based on the number of cut-off cells among the plurality of memory cells in the memory device 100 by using a second read voltage.

[0058] Figure 2is illustrated Figure 1 a diagram illustrating a structure of a memory device of the present disclosure.

[0059] Referring to Figure 2 , the memory device 100 can include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

[0060] The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz can be connected to an address decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz can be connected to a page buffer bank 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells. As an embodiment, the plurality of memory cells can be non-volatile memory cells. Memory cells among the plurality of memory cells connected to the same word line can be defined as a page. That is, the memory cell array 110 can be configured by a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 can include a plurality of dummy cells. At least one of the dummy cells can be connected in series between a drain select transistor and a memory cell and between a source select transistor and a memory cell.

[0061] Each memory cell of the memory device 100 can be configured as an SLC storing one bit of data, an MLC storing two bits of data, a TLC storing three bits of data, or a QLC capable of storing four bits of data.

[0062] The peripheral circuit 120 can include the address decoder 121, a voltage generator 122, the page buffer bank 123, a data input / output circuit 124, and a sensing circuit 125.

[0063] The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation. As Figure 1 The operation controller 140 as illustrated can be implemented as a configuration of the peripheral circuit 120. Figure 2

[0064] The address decoder 121 can be connected to the memory cell array 110 through row lines RL. The row lines RL can include a drain select line, a word line, a source select line, and a common source line. According to an embodiment of the present disclosure, the word line can include a normal word line and a dummy word line. According to an embodiment of the present disclosure, the row lines RL can further include a tube select line.

[0065] ​The address decoder 121 can be configured to operate in response to control of the control logic 130. The address decoder 121 can receive the address ADDR from the control logic 130.

[0066] The address decoder 121 can be configured to decode a block address in the received address ADDR. The address decoder 121 can select at least one storage block among the storage blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 can be configured to decode a row address RADD in the received address ADDR. The address decoder 121 can select at least one word line of the selected storage block by applying a voltage provided from the voltage generator 122 to the at least one word line according to the decoded row address RADD.

[0067] During a program operation, the address decoder 121 can apply a program voltage to the selected word line and can apply a pass voltage having a level lower than that of the program voltage to the unselected word line. During a program verify operation, the address decoder 121 can apply a verify voltage to the selected word line and can apply a verify pass voltage having a level greater than that of the verify voltage to the unselected word line.

[0068] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and can apply a read pass voltage having a level greater than that of the read voltage to the unselected word line.

[0069] An erase operation of the memory device 100 can be performed in units of storage blocks. An address ADDR input to the memory device 100 during the erase operation can include a block address. The address decoder 121 can decode the block address and select one storage block according to the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line to be input to the selected storage block.

[0070] According to an embodiment of the disclosure, the address decoder 121 can be configured to decode a column address in the transmitted address ADDR. The decoded column address can be transmitted to the page buffer group 123. As an example, the address decoder 121 can include components such as a row decoder, a column decoder, and an address buffer.

[0071] The voltage generator 122 can be configured to generate a plurality of operating voltages Vop by using an external power supply voltage provided to the memory device 100. The voltage generator 122 can operate in response to the control logic 130.

[0072] As an example, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as an operating voltage of the memory device 100.

[0073] As an implementation, the voltage generator 122 can generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage generator 122 can be configured to generate various voltages required for the memory device 100. For example, the voltage generator 122 can generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0074] To generate a plurality of operating voltages Vop having various voltage levels, the voltage generator 122 can include a plurality of pump capacitors that receive an internal voltage, and selectively activate the plurality of pump capacitors to generate the plurality of operating voltages Vop in response to the control logic 130.

[0075] The generated plurality of operating voltages Vop can be provided to the memory cell array 110 by the address decoder 121.

[0076] The page buffer set 123 includes a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm can be connected to the memory cell array 110 through a first bit line BL1 to an m-th bit line BLm, respectively. The first page buffer PB1 to the m-th page buffer PBm operate in response to a control of the control logic 130.

[0077] The first page buffer PB1 to the m-th page buffer PBm can communicate data DATA with the data input / output circuit 124. At the time of programming, the first page buffer PB1 to the m-th page buffer PBm can receive data DATA to be stored through the data input / output circuit 124 and a data line DL.

[0078] During a program operation, when a program pulse is applied to a selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer data DATA to be stored, i.e., data DATA received through the input / output circuit 124, to the selected memory cells through the bit lines BL1 to BLm. The memory cells of the selected page can be programmed according to the transferred data DATA. The memory cells connected to the bit line to which a program enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit line to which a program inhibit voltage (e.g., a power supply voltage) is applied can be maintained. During a program verify operation, the first page buffer PB1 to the m-th page buffer PBm can read data DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

[0079] During a read operation, the page buffer set 123 can read data DATA from the memory cells of the selected page through the bit line BL, and can store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0080] During an erase operation, the page buffer set 123 can float the bit line BL. As an embodiment, the page buffer set 123 can include a column selection circuit.

[0081] In an embodiment, while data stored in some of the plurality of page buffers included in the page buffer set 123 is being programmed into the memory cell array 110, other page buffers can receive and store new data from the memory controller 200.

[0082] The data input / output circuit 124 can be connected to the first to m-th page buffers PB1 to PBm through the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0083] The data input / output circuit 124 can include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 can receive data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 can output data DATA transferred from the first to m-th page buffers PB1 to PBm included in the page buffer set 123 to the external controller.

[0084] During a read operation or a verify operation, the sensing circuit 125 can generate a reference current in response to a signal of an enable bit VRYBIT generated by the control logic 130, and can compare a sensing voltage VPB received from the page buffer set 123 with a reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.

[0085] The control logic 130 can be connected to the address decoder 121, the voltage generator 122, the page buffer set 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 can be configured to control all operations of the memory device 100. The control logic 130 can operate in response to a command CMD transferred from an external device.

[0086] The control logic 130 can generate various signals in response to the command CMD and the address ADDR to control the peripheral circuit 120. For example, the control logic 130 can generate an operation signal OPSIG, a row address RADD, page buffer control signals PBSIGNALS, and a pass bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 can output the operation signal OPSIG to the voltage generator 122, the row address RADD to the address decoder 121, the page buffer control signals PBSIGNALS to the page buffer group 123, and the pass bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 can determine whether the verify operation is passed or failed in response to a pass signal PASS or a fail signal FAIL output by the sensing circuit 125. Figure 1 The illustrated read voltage controller 150 can be implemented as Figure 2 One configuration of the control logic 130 illustrated. In an embodiment, the control logic 130 can control the peripheral circuit 120 to change the second read voltage to the first read voltage and can apply the first read voltage to the plurality of memory cells.

[0087] Figure 3 is a diagram illustrating a configuration of an arbitrary one of the plurality of memory blocks BLK1 to BLKi of Figure 2

[0088] The memory block BLKi is an arbitrary one of the memory blocks BLK1 to BLKz of Figure 2

[0089] Referring to Figure 3 , a plurality of word lines arranged in parallel to each other can be connected between a first selection line and a second selection line. Here, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically, the memory block BLKi can include a plurality of strings ST connected between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn can be connected to the strings ST, respectively, and the source line SL can be commonly connected to the strings ST. Since the strings ST can be identically configured to each other, the string ST connected to the first bit line BL1 can be specifically described as an example.

[0090] The string ST can include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. However, the number of the source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 to MC16 can vary based on an embodiment.

[0091] ​​The source of the source select transistor SST can be connected to a source line SL, and the drain of the drain select transistor DST can be connected to a first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to a source select line SSL, the gates of the drain select transistors DST can be connected to a drain select line DSL, and the gates of the memory cells MC1 to MC16 can be connected to a plurality of word lines WL1 to WL16. A group of memory cells included in different strings ST, connected to the same word line, can be referred to as a page PG. Accordingly, the memory block BLKi can include a number of pages PG of the word lines WL1 to WL16.

[0092] In an embodiment, one memory cell can store three bits of data. In this case, one physical page PG can store three logical page (LPG) data. One logical page (LPG) data can include the same number of bits of data as the cells included in one physical page PG.

[0093] Figure 4 FIG. 1 is a diagram illustrating a first program step according to an embodiment of the disclosure.

[0094] Referring to Figure 4 The first program step can be a step of applying a first step program voltage 1S_Vpgm and a first step verify voltage 1S_V_vfy to the memory cells in the initial state. The first program step can include a program voltage application step PGM Step and a program verify step Verify Step.

[0095] In the program voltage application step PGM Step, a program voltage can be applied to a selected word line connected to a selected memory cell. In the program voltage application step PGM Step, each selected memory cell can be programmed from the initial state to an intermediate program state.

[0096] In the program verify step Verify Step, a verify voltage can be applied to the selected word line. Whether the selected memory cell is programmed to the intermediate program state via a bit line respectively connected to the selected memory cell can be determined in a state where the verify voltage is applied to the selected word line. However, the program verify step Verify Step can be omitted in the first program step.

[0097] In an embodiment, when the first programming step is performed, the first step verify voltage 1S_V_vfy can be applied after the first step program voltage 1S_Vpgm is applied to the selected word line. The first step program voltage 1S_Vpgm can have a voltage level higher than a voltage level of the first program voltage applied to the selected word line in the second programming step. The memory cells, which are determined to have passed the program verify operation by the first step verify voltage 1S_V_vfy, can have an intermediate program state.

[0098] Figure 5 FIG. 2 is a diagram illustrating a second programming step according to an embodiment of the disclosure.

[0099] Referring to Figure 5 , the second programming step can be a step of applying program voltages 2S_Vpgm1 to 2S_Vpgmn (n is a natural number equal to or greater than 1) and verify voltages 2S_V_vfy1 to 2S_V_vfy7 to the memory cells to which the first programming step is performed. The second programming step can include a plurality of program loops PL1 to PLn. The memory device 100 can perform a program operation by performing the plurality of program loops PL1 to PLn so that the selected memory cells have a target program state among final program states. Each of the plurality of program loops can include a program voltage application step PGM Step and a program verify step Verify Step.

[0100] In the program voltage application step PGM Step, a program voltage can be applied to the selected word line connected to the selected memory cell. In the program voltage application step PGM Step, each of the selected memory cells can be programmed to a target program state among the final program states. The target program state can be determined according to data to be programmed to the selected memory cell.

[0101] In the program verify step Verify Step, a verify voltage can be applied to the selected word line. Whether the selected memory cell is programmed to the target program state via the bit line connected to the selected memory cell, respectively, can be determined in a state in which the verify voltage is applied to the selected word line.

[0102] In an embodiment, the program voltages can be determined according to an incremental step pulse programming (ISPP) method. The levels of the program voltages can gradually increase or decrease as the program loops PL1 to PLn are repeated. The number of times of application, the voltage level, the voltage application time, etc. of the program voltages used in each of the program loops can be determined in various forms according to the memory controller 200.

[0103] A pass voltage can be applied to unselected word lines (the remaining word lines other than the selected word line). In an embodiment, the pass voltage can be applied to the unselected word lines with the same level. In an embodiment, the pass voltage can have different levels according to the position of the word line.

[0104] A ground voltage can be applied as a program enable voltage to the selected bit line connected to the memory cell to be programmed. A program inhibit voltage can be applied to the unselected bit line, which is a bit line connected to the memory cell other than the memory cell to be programmed.

[0105] In the program verify step Verify Step, the memory device 100 can apply a verify voltage to the selected word line and can apply a verify pass voltage to the unselected word line. The memory device 100 can sense a voltage or a current outputted through the bit line connected to the memory cell connected to the selected word line, respectively, and can determine whether the program verify step Verify Step is passed or failed based on the sensing result.

[0106] In the program voltage application step PGM Step, the selected memory cell can be programmed to any one of the final program states.

[0107] For example, when the memory cell is programmed in TLC, the selected memory cell can be programmed to any one of the erased state and the first to seventh program states. However, the number of data bits stored in the memory cell is not limited to the present embodiment.

[0108] In the program verify step Verify Step, it can be determined whether the selected memory cell is programmed to a target program state among the final program states. In the program verify step Verify Step, a verify voltage corresponding to the target program state can be applied to the selected memory cell. For example, when the selected memory cell is read as a cut-off cell by the verify voltage corresponding to the target program state among the final program states, the program verify step Verify Step can be passed.

[0109] In the embodiment, when the first programming loop PL1 is executed, the first verification voltage 2S_V_vfy1 to the seventh verification voltage 2S_V_vfy7 can be sequentially applied after the first programming voltage 2S_Vpgm1 is applied to the selected word line. At this time, the memory cell whose target programming state is the first programming state can perform the programming verification step Verify Step by using the first verification voltage 2S_V_vfy1. The memory cell whose target programming state is the second programming state can perform the programming verification step Verify Step by using the second verification voltage 2S_V_vfy2. The memory cell whose target programming state is the third programming state can perform the programming verification step Verify Step by using the third verification voltage 2S_V_vfy3. The memory cell whose target programming state is the fourth programming state can perform the programming verification step Verify Step by using the fourth verification voltage 2S_V_vfy4. The memory cell whose target programming state is the fifth programming state can perform the programming verification step Verify Step by using the fifth verification voltage 2S_V_vfy5. The memory cell whose target programming state is the sixth programming state can perform the programming verification step Verify Step by using the sixth verification voltage 2S_V_vfy6. The memory cell whose target programming state is the seventh programming state can perform the programming verification step Verify Step by using the seventh verification voltage 2S_V_vfy7. The number of verification voltages is not limited to the embodiment.

[0110] The memory cell that passed the programming verification step Verify Step performed by each of the verification voltages 2S_V_vfy1 to 2S_V_vfy7 can be determined to have the target programming state. Thereafter, the memory cell that passed the programming verification step Verify Step can be inhibited from programming in the second programming loop PL2. The programming inhibition voltage can be applied to the bit line connected to the memory cell inhibited from programming.

[0111] The memory cell that failed the programming verification step Verify Step performed by each of the verification voltages 2S_V_vfy1 to 2S_V_vfy7 can be determined to not reach the target programming state. Thereafter, the memory cell that failed the programming verification step Verify Step can perform the second programming loop PL2.

[0112] The second programming voltage 2S_Vpgm2 that is higher than the first programming voltage 2S_Vpgm1 by a unit voltage Δ2S_Vpgm can be applied to the selected word line in the second programming loop PL2. Thereafter, the programming verification step Verify Step can be performed in the same manner as the programming verification step Verify Step in the first programming loop PL1.

[0113] Thereafter, the second programming step can perform the next programming loop for a preset number of times identical to the second programming loop PL2.

[0114] In an embodiment, the programming operation can fail when the programming operation is not completed within a preset number of programming loops. The programming operation can pass when the programming operation is completed within the preset number of programming loops. Whether the programming operation is completed can be determined via whether all programming verify steps pass for the selected memory cell. When all programming verify steps pass, the next programming loop can not be performed.

[0115] Figure 6 FIG. 1 is a diagram illustrating a threshold voltage distribution of a memory cell according to an embodiment of the disclosure.

[0116] Referring to Figure 6 The threshold voltage distribution of the memory cell can change according to the programming operation in the order of an initial state, an intermediate programming state, and a final programming state.

[0117] The initial state can be a state in which the programming operation is not performed, and the threshold voltage distribution of the memory cell can be an erase state E.

[0118] The intermediate programming state can be a programming state of the memory cell in which the first programming step is performed. The threshold voltage of the memory cell can change to the erase state E or an intermediate state MID PV according to the first programming step. For example, the memory cell having the threshold voltage of the erase state E in the initial state can have the threshold voltage corresponding to the erase state E or the intermediate state MID PV according to the first programming step.

[0119] The final programming state can be a programming state of the memory cell in which the second programming step is performed. The threshold voltage of the memory cell can change to the erase state E and the first programming state PV1 to the seventh programming state PV7 according to the second programming step. For example, the memory cell having the threshold voltage of the erase state E in the intermediate programming state can have the threshold voltage corresponding to the erase state E, the first programming state PV1, the second programming state PV2, and the third programming state PV3 according to the second programming step. The memory cell having the threshold voltage of the intermediate state MID PV in the intermediate programming state can have the threshold voltage corresponding to the fourth programming state PV4, the fifth programming state PV5, the sixth programming state PV6, and the seventh programming state PV7 according to the second programming step.

[0120] Each memory cell can have the erase state E and any one of the first to seventh program states PV1 to PV7 as a target program state. The target program state can be determined according to data to be stored in the memory cell. The memory cell can have a threshold voltage corresponding to the target program state among the final program states according to the first program step and the second program step.

[0121] Figure 7 FIG. 1 is a diagram illustrating a program order between word lines according to an embodiment of the present disclosure.

[0122] Referring to Figure 7 The memory device 100 can perform a program operation on the memory cells connected to the word lines WL1 to WL4 in the storage block BLKz. The program operation can be performed by being divided into the first program step and the second program step.

[0123] In an embodiment, the first program step can be performed on the first word line WL1. Thereafter, the first program step can be performed on the second word line WL2. Thereafter, the second program step can be performed on the first word line WL1. Accordingly, the program operation of the first word line WL1 can be completed. For example, each memory cell connected to the first word line WL1 can be programmed to a target program state among the final program states. Thereafter, the order of the first program step and the second program step to be performed on the word lines can be performed in the same as the program order of the first word line WL1.

[0124] As described above, with regard to the program order according to the present disclosure, the first program step can be performed on a selected word line, the first program step can be performed on a word line to be selected next, and the second program step can be performed on the selected word line. Such a program method can reduce a phenomenon of interference between adjacent word lines, compared to a method of performing a program operation on a selected word line without dividing program steps.

[0125] Figure 8 FIG. 2 is a diagram illustrating a threshold voltage distribution of a memory cell storing at least one bit of data according to an embodiment of the present disclosure.

[0126] Referring to Figure 8 The intermediate program state can be a program state of a memory cell on which the first program step is performed. In the intermediate program state, one memory cell can have a threshold voltage corresponding to any one of the erase state E and the intermediate state MID PV. In the intermediate program state, one memory cell can store one bit of data.

[0127] The first read voltage V1_R can be a read voltage for distinguishing the erase state E and the intermediate state MID PV of the memory cell in the intermediate programming state. The memory cell having the erase state E in the intermediate programming state can be read as an on cell. The on cell can correspond to a logic value of "1". The memory cell having the intermediate state MID PV in the intermediate programming state can be read as an off cell. The off cell can correspond to a logic value of "0".

[0128] The final programming state can be a programming state of the memory cell to which the second programming step is performed. In the final programming state, one memory cell can have any one of the erase state E and the first to seventh programming states PV1 to PV7. In the final programming state, one memory cell can store a plurality of bits of data. In an embodiment, when one memory cell is programmed in TLC, the data stored in one page can be multi-page data. For example, the multi-page data can include a plurality of logical pages. Specifically, the plurality of logical pages can include an LSB page, a CSB page, and an MSB page.

[0129] The second read voltage V2_R can be a read voltage for distinguishing the erase state E, the first to third programming states PV1 to PV3, and the fourth to seventh programming states PV4 to PV7 of the memory cell in the final programming state. At this time, the memory cell corresponding to the erase state E and the first to third programming states PV1 to PV3 in the LSB page can be read as an on cell. The memory cell corresponding to the fourth to seventh programming states PV4 to PV7 in the LSB page can be read as an off cell.

[0130] Figure 9 FIG. 1 is a diagram illustrating an operation of reading data by changing a second read voltage to a first read voltage according to an embodiment of the disclosure.

[0131] Referring to Figure 9 , the operation controller 140 can include a voltage generator 141 and a read data storage 142. The read voltage controller 150 can include a voltage change controller 151, a read voltage code storage 152, and a cell counter 153. Figure 9 The voltage generator 141 illustrated can be implemented as Figure 2 one configuration of the voltage generator 122 illustrated.

[0132] The memory controller 200 can provide the read command R_CMD to the voltage change controller 151, the read command R_CMD providing an indication to read data stored in a plurality of memory cells.

[0133] The read voltage code storage 152 can provide the voltage code V_CODE corresponding to the second read voltage to the voltage change controller 151.

[0134] The voltage change controller 151 can provide a control signal V_CTRL to the voltage generator 141 so that the voltage generator 141 generates the second read voltage in response to the read command R_CMD.

[0135] The voltage generator 141 can generate the second read voltage and apply the second read voltage to the plurality of memory cells in the memory cell array 110.

[0136] Thereafter, the read data storage 142 can store data R_DATA read by applying the second read voltage to the plurality of memory cells. The read data R_DATA can include a plurality of data pieces. In an embodiment, the read data storage 142 can provide the read data R_DATA to the cell counter 153. In another embodiment, the read data storage 142 can provide only one data piece among the plurality of data pieces included in the read data to the cell counter 153.

[0137] The cell counter 153 can receive the read data R_DATA and count the number of cut cells among the plurality of memory cells to which the second read voltage is applied. In an embodiment, the cell counter 153 can count only the number of cut cells of the memory cells among the plurality of memory cells to which the second read voltage is applied, which correspond to the piece. In an embodiment, the cell counter 153 can count the number of 0s included in the read data R_DATA. In another embodiment, the cell counter 153 can count the number of 1s included in the read data R_DATA. The cell counter 153 can provide the counted number of cut cells CNT_NUM to the voltage change controller 151.

[0138] The voltage change controller 151 can receive the voltage code V_CODE corresponding to each of the first read voltage and the second read voltage and information on the reference cut cell number from the read voltage code storage 152. The information on the reference cut cell number can include the first reference cut cell number and the second reference cut cell number.

[0139] The voltage change controller 151 can determine whether the counted number of cut cells CNT_NUM exceeds a first reference cut cell number. When the counted number of cut cells CNT_NUM exceeds the preset first reference cut cell number, the voltage change controller 151 can provide the read data R_DATA to the memory controller 200. In contrast, when the counted number of cut cells CNT_NUM is equal to or less than the preset first reference cut cell number, the voltage change controller 151 can change the voltage code corresponding to the second read voltage to a voltage code corresponding to the first read voltage. Thereafter, the voltage change controller 151 can provide the control signal V_CTRL for generating the first read voltage by the voltage code corresponding to the first read voltage to the voltage generator 141.

[0140] In an embodiment, the voltage change controller 151 can determine whether the number of cut cells in the memory cell corresponding to the chip among the plurality of memory cells read by applying the second read voltage exceeds a second reference cut cell number. For example, when the number of cut cells in the memory cell corresponding to the chip is equal to or less than the second reference cut cell number, the voltage change controller 151 can change the voltage code corresponding to the second read voltage to a voltage code corresponding to the first read voltage. Thereafter, the voltage change controller 151 can provide the control signal V_CTRL for generating the first read voltage by the voltage code corresponding to the first read voltage to the voltage generator 141.

[0141] The voltage generator 141 can generate the first read voltage and apply the first read voltage to the plurality of memory cells in the memory cell array 110. The read data storage 142 can store the data R_DATA read by applying the first read voltage to the plurality of memory cells. Thereafter, the read data R_DATA can be provided to the memory controller 200 through the cell counter 153 and the voltage change controller 151.

[0142] In the present specification, an operation of changing the second read voltage to the first read voltage based on the number of cut cells or the number of logical values "0" among the plurality of memory cells read by applying the second read voltage is described. However, a basis for changing the read voltage is not limited to the number of cut cells or the number of logical values "0". Alternatively, the second read voltage can be changed to the first read voltage based on the number of on cells or the number of logical values "1".

[0143] Figure 10 FIG. 1 is a diagram illustrating a voltage code corresponding to a read voltage according to an embodiment of the present disclosure.

[0144] Referring to Figure 10The read voltage code storage 152 can store a voltage code corresponding to each of the first read voltage and the second read voltage, and information about the reference cut-off cell number. The information about the reference cut-off cell number can include a first reference cut-off cell number and a second reference cut-off cell number. The read voltage code storage 152 can provide the voltage code corresponding to each of the first read voltage and the second read voltage and the information about the reference cut-off cell number to the voltage change controller 151. In an embodiment, the voltage code corresponding to each of the first read voltage and the second read voltage can be a binary code. Figure 9 The voltage generator 141 illustrated in FIG. 1 can generate a read voltage level.

[0145] The voltage change controller 151 can receive the voltage code corresponding to each of the first read voltage and the second read voltage and the information about the reference cut-off cell number. Thereafter, the voltage change controller 151 can change the voltage code corresponding to the second read voltage to the voltage code corresponding to the first read voltage. For example, when the number of cut-off cells among the plurality of memory cells read by applying the second read voltage is equal to or less than the first reference cut-off cell number, the voltage change controller 151 can change the voltage code corresponding to the second read voltage to the voltage code corresponding to the first read voltage. As another example, when the number of cut-off cells corresponding to a chip among the plurality of memory cells read by applying the second read voltage is equal to or less than the second reference cut-off cell number, the voltage change controller 151 can change the voltage code corresponding to the second read voltage to the voltage code corresponding to the first read voltage.

[0146] Figure 11 FIG. 1 is a diagram illustrating an operation of moving a plurality of memory cells corresponding to a chip to a cell counter according to an embodiment of the disclosure.

[0147] Referring to Figure 11 The read data storage 142 can store data R_DATA read by applying the second read voltage to the plurality of memory cells. The read data R_DATA can include a plurality of pieces of data. The read data storage 142 can provide the read data R_DATA to the cell counter 153. In an embodiment, the read data storage 142 can provide only one piece of data among the plurality of pieces of data included in the read data to the cell counter 153. Thereafter, the read data storage 142 can provide the memory cell corresponding to the piece among the plurality of memory cells to which the second read voltage is applied to the cell counter 153. The size of the piece can be set in various ways. For example, the cell counter 153 can count only the number of cut-off cells among the memory cell corresponding to the piece.

[0148] Figure 12is a flowchart illustrating a method of changing a second read voltage to a first read voltage according to an embodiment of the disclosure.

[0149] Figure 12 The illustrated method can be performed by, for example Figure 1 by the memory device 100 illustrated.

[0150] Referring to Figure 12 In step S1201, the memory device 100 can apply a second read voltage to a word line connected to a plurality of memory cells. For example, the operation controller 140 can store data read by applying the second read voltage to the plurality of memory cells in the read data storage 142.

[0151] In step S1203, the memory device 100 can determine whether the number of cut cells among the plurality of memory cells to which the second read voltage is applied exceeds a first reference cut cell number. For example, when the number of cut cells among the plurality of memory cells exceeds the first reference cut cell number, step S1205 can be performed. Alternatively, when the number of cut cells among the plurality of memory cells is equal to or less than the first reference cut cell number, step S1207 can be performed.

[0152] In step S1205, the memory device 100 can output data read by applying the second read voltage to the plurality of memory cells to the memory controller 200.

[0153] In step S1207, when the number of cut cells among the plurality of memory cells is equal to or less than the first reference cut cell number, the memory device 100 can change the second read voltage to a first read voltage and apply the first read voltage to the word line. Thereafter, the memory device 100 can output data read by applying the first read voltage to the plurality of memory cells to the memory controller 200.

[0154] Figure 13 is a flowchart illustrating another example of a method of changing a second read voltage to a first read voltage according to an embodiment of the disclosure.

[0155] Figure 13 The illustrated method can be performed by, for example Figure 1 by the memory device 100 illustrated.

[0156] Referring to Figure 13 In step S1301, the memory device 100 can apply a second read voltage to a word line connected to a plurality of memory cells. For example, the operation controller 140 can store data read by applying the second read voltage to the plurality of memory cells in the read data storage 142.

[0157] In step S1303, the memory device 100 can determine whether the number of cut cells among the memory cells corresponding to the chip among the plurality of memory cells to which the second read voltage is applied exceeds a second reference cut cell number. For example, when the number of cut cells among the memory cells corresponding to the chip exceeds the second reference cut cell number, step S1305 can be performed. Alternatively, when the number of cut cells among the memory cells corresponding to the chip is equal to or less than the second reference cut cell number, step S1307 can be performed.

[0158] In step S1305, the memory device 100 can output data read by applying the second read voltage to the plurality of memory cells to the memory controller 200.

[0159] In step S1307, when the number of cut cells among the memory cells corresponding to the chip is equal to or less than the second reference cut cell number, the memory device 100 can change the second read voltage to the first read voltage and can apply the first read voltage to the word line. Thereafter, the memory device 100 can output data read by applying the first read voltage to the plurality of memory cells to the memory controller 200.

[0160] Figure 14 is a diagram illustrating a memory controller of Figure 1 .

[0161] Figure 14 The memory controller 1400 of Figure 1 may denote the memory controller 200 of

[0162] Referring to Figure 14 , the memory controller 1400 can include a processor 1430, a RAM 1420, an error correction circuit 1430, a host interface 1440, a ROM 1450, and a flash memory interface 1460.

[0163] The processor 1410 can control overall operations of the memory controller 1400. The RAM 1420 can serve as a buffer memory, a cache memory, an operating memory, etc. of the memory controller 1400.

[0164] The error correction circuit 1430 can perform error correction. The error correction circuit 1430 can perform error correction coding (ECC coding) based on data to be written to the memory device through the flash memory interface 1460. The error correction coded data can be transmitted to the memory device through the flash memory interface 1460. The error correction circuit 1430 can perform error correction decoding (ECC decoding) on data received from the memory device 100 through the flash memory interface 1460. For example, the error correction circuit 1430 can be included in the flash memory interface 1460 as a component of the flash memory interface 1460.

[0165] The ROM 1450 can store various information required for the operation of the memory controller 1400 in the form of firmware.

[0166] The memory controller 1400 can communicate with an external device (e.g., the host 300, an application processor, etc.) through the host interface 1440.

[0167] The memory controller 1400 can communicate with the memory device 100 through the flash memory interface 1460. The memory controller 1400 can transmit a command, an address, a control signal, etc. to the memory device 100 through the flash memory interface 1460 and receive data through the flash memory interface 1460. For example, the flash memory interface 1460 can include a NAND interface.

[0168] Figure 15 FIG. 2 is a block diagram illustrating a memory card system to which embodiments of the present disclosure are applied.

[0169] Referring to Figure 15 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0170] The memory controller 2100 can be connected to the memory device 2200. The memory controller 2100 can be configured to access the memory device 2200. For example, the memory controller 2100 can be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 2200. The memory controller 2100 can be configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 can be configured to drive firmware for controlling the memory device 2200. The memory controller 2100 can be implemented identically to the memory controller 200 described with reference to Figure 1 . The memory device 2200 can be implemented identically to the memory device 100 described with reference to Figure 1 .

[0171] For example, the memory controller 2100 can include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0172] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 can be configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined in at least one of the various communication standards described above.

[0173] For example, the memory device 2200 can be configured with various nonvolatile memory elements such as Electrically Erasable Programmable ROM (EEPROM), NAND flash, NOR flash, Phase-Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0174] The memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash card (CF), a Smart Media card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, micro-SD, or eMMC), an SD card (SD, mini-SD, micro-SD, or SDHC), and a Universal Flash Storage (UFS).

[0175] Figure 16 is a block diagram illustrating a solid state drive (SSD) system to which a memory system according to an embodiment of the disclosure is applied.

[0176] Referring to Figure 16 The SSD system 3000 can include a host 3100 and an SSD 3200. The SSD 3200 can exchange a signal SIG with the host 3100 through a signal connector 3001 and can receive a power supply through a power supply connector 3002. The SSD 3200 can include an SSD controller 3210, a plurality of flash memories 3221 through 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0177] According to an embodiment of the disclosure, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to Figure 1 FIG. 1.

[0178] The SSD controller 3210 can control the plurality of flash memories 3221 through 322n in response to a signal received from the host 3100. For example, the signal can be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal can be a signal defined through at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0179] The auxiliary power supply device 3230 can be connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 can receive power from the host 3100 and can charge the power. The auxiliary power supply device 3230 can supply power to the SSD 3200 when the power from the host 3100 is not smooth. For example, the auxiliary power supply device 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located on a main board and can supply auxiliary power to the SSD 3200.

[0180] The buffer memory 3240 can operate as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 through 322n, or can temporarily store metadata (for example, a mapping table) of the flash memories 3221 through 322n. The buffer memory 3240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0181] Figure 17 FIG. 4 is a block diagram illustrating a user system to which a memory system according to an embodiment of the disclosure is applied.

[0182] Referring to Figure 17 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0183] The application processor 4100 can drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 can include a controller, an interface, a graphic engine, etc. that control the components included in the user system 4000. The application processor 4100 can be provided as a system on chip (SoC).

[0184] The memory module 4200 can be used as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package on package (POP) and provided as one semiconductor package.

[0185] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0186] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented as a non-volatile semiconductor memory element such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, and three-dimensional NAND flash. For example, the storage module 4400 can be provided as a removable storage device (a removable drive) such as a memory card of the user system 4000 and an external drive.

[0187] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate identically to the memory device 100 described with reference to Figure 1 For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate identically to the memory device 100 described with reference to Figure 1The described memory system 50 operates equivalently.

[0188] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or an interface for outputting data to an external device. For example, the user interface 4500 can include a user input interface such as a keypad, a key pad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 can include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0189] Cross Reference to Related Applications

[0190] This application claims priority to Korean Patent Application No. 10-2021-0101750, filed on August 3, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: a plurality of memory cells connected to a word line; an operation controller that applies a first read voltage or a second read voltage to the word line and obtains data stored in the plurality of memory cells through bit lines respectively connected to the plurality of memory cells, wherein the second read voltage is higher than the first read voltage; and a read voltage controller that, in response to a read command input from an external controller that provides an instruction to read the data stored in the plurality of memory cells, controls the operation controller to read the data stored in the plurality of memory cells by using the second read voltage, and, according to a number of cut-off cells having a threshold voltage higher than the second read voltage counted based on the data read by using the second read voltage, controls the operation controller to change the second read voltage to the first read voltage and read the data stored in the plurality of memory cells by using the first read voltage.

2. The memory device of claim 1, wherein, each of the plurality of memory cells is programmed to store a plurality of bits, and wherein the data stored in the plurality of memory cells includes a plurality of logical pages.

3. The memory device of claim 2, wherein, the second read voltage is a voltage for reading one logical page among the plurality of logical pages.

4. The memory device of claim 3, wherein, the one logical page is a least significant bit page.

5. The memory device of claim 1, wherein, the read voltage controller includes: a cell counter that counts the number of cut-off cells; a read voltage code storage that stores information about a reference number of cut-off cells; and a voltage change controller that, based on the counted number of cut-off cells and the information about the reference number of cut-off cells, controls the operation controller to change the second read voltage to the first read voltage.

6. The memory device of claim 5, wherein, the operation controller further includes: a voltage generator that generates the first read voltage or the second read voltage; and a read data storage that stores data read by using the first read voltage or the second read voltage.

7. The memory device of claim 6, wherein, the information about the reference number of cut-off cells includes a first reference number of cut-off cells and a second reference number of cut-off cells, the second reference number of cut-off cells is smaller than the first reference number of cut-off cells, and wherein, when the number of cut-off cells is equal to or smaller than the first reference number of cut-off cells, the voltage change controller controls the operation controller to change the second read voltage to the first read voltage and read the data stored in the plurality of memory cells by using the first read voltage.

8. The memory device of claim 5, wherein, the data read by using the second read voltage includes a plurality of data pieces, and wherein the cell counter counts the number of cut-off cells in a memory cell corresponding to any one of the plurality of data pieces.

9. The memory device of claim 8, wherein, The information about the number of the reference cut cells includes a first reference number of cut cells and a second reference number of cut cells, the second reference number of cut cells is smaller than the first reference number of cut cells, and wherein, when the number of cut cells in the memory cells corresponding to any one of the plurality of data pieces is equal to or smaller than the second reference number of cut cells, the operation controller is controlled to change the second read voltage to the first read voltage, and to read data stored in the plurality of memory cells by using the first read voltage.

10. A memory device, comprising: a plurality of memory cells connected to a word line; an operation controller that performs a program operation of storing a plurality of pages of data each including a plurality of bits in the plurality of memory cells, and performs a read operation of obtaining the plurality of pages of data stored in the plurality of memory cells, the program operation including a first program step and a second program step, the plurality of pages of data including a plurality of logical pages; and a read voltage controller that, in response to a read command that provides an instruction to read one of the plurality of logical pages, controls the operation controller to determine whether to perform the program step up to the first program step or the second program step on the plurality of memory cells based on a number of 0s or Is included in sensing data obtained by sensing data stored in the plurality of memory cells by using a second read voltage, and when the program step of the plurality of memory cells is the first program step, changes the second read voltage to a first read voltage having a lower voltage than the second read voltage and senses data stored in the plurality of memory cells by using the first read voltage.

11. The memory device of claim 10, wherein, In the first program step, threshold voltages of the plurality of memory cells are increased to threshold voltages corresponding to each of an erased state and an intermediate state.

12. The memory device of claim 11, wherein, In the second program step, among the threshold voltages of the plurality of memory cells on which the first program step is performed, threshold voltages of the plurality of memory cells corresponding to the erased state are increased to threshold voltages corresponding to the erased state and each of a first program state to a third program state, and threshold voltages of the plurality of memory cells corresponding to the intermediate state are increased to threshold voltages corresponding to a fourth program state to a seventh program state.

13. The memory device of claim 12, wherein, The logical page is a least significant bit page.

14. The memory device of claim 10, wherein, When the number of 0s or Is included in the sensing data is equal to or smaller than a first reference number, the read voltage controller determines to perform the program step up to the first program step on the plurality of memory cells.

15. The memory device of claim 10, wherein, The sensing data includes a plurality of data pieces, and wherein, when the number of 0s or Is included in the sensing data corresponding to a piece among the plurality of data pieces is equal to or smaller than a second reference number, the read voltage controller determines to perform the program step up to the first program step on the plurality of memory cells.

16. A method of operating a memory device for reading data stored in memory cells by using a first read voltage or a second read voltage, the method comprising the steps of: reading the data stored in the memory cells by using the second read voltage; counting a number of snapback cells having a threshold voltage higher than the second read voltage among the memory cells by using the second read voltage; and changing the second read voltage to the first read voltage having a lower voltage than the second read voltage based on the counted number of snapback cells and reading the data stored in the memory cells by using the first read voltage.

17. The method of claim 16, wherein, each of the memory cells is programmed to store a plurality of bits, and wherein the data stored in the memory cells includes a plurality of logical pages.

18. The method of claim 17, wherein, the second read voltage is used to read one logical page among the plurality of logical pages.

19. The method of claim 18, wherein, the step of reading the data stored in the memory cells by using the first read voltage includes the step of reading the data stored in the memory cells by using the first read voltage in response to the number of snapback cells being equal to or smaller than a reference snapback cell number.

20. The method of claim 19, wherein, the number of snapback cells is a number of snapback cells in memory cells corresponding to a chip among the memory cells to which the second read voltage is applied.

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