Tracking RC time constants through word lines in memory devices

Abstract

The present disclosure relates to tracking RC time constants through word lines in a memory device. A memory device includes a memory array comprising a plurality of word lines, and control logic operably coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of word lines of the memory array, and determines respective threshold voltages stored in a plurality of memory cells associated with each of the plurality of word lines. The control logic further determines a difference between the respective threshold voltages based on a location of the plurality of memory cells within each word line, and determines a respective resistance-capacitance, RC, time constant for each of the plurality of word lines in view of the difference between the respective threshold voltages.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to tracking RC time constants via word lines in a memory device within a memory subsystem. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] One aspect of this disclosure relates to a memory device comprising: a memory array including a plurality of word lines; and control logic operatively coupled to the memory array to perform operations including: sequentially applying measurement programming pulses to each of the plurality of word lines of the memory array; determining a corresponding threshold voltage stored in a plurality of memory cells associated with each of the plurality of word lines; determining a difference between the corresponding threshold voltages based on the position of the plurality of memory cells within each word line; and determining a corresponding resistance-capacitance RC time constant for each of the plurality of word lines in view of the difference between the corresponding threshold voltages.

[0004] Another aspect of this disclosure relates to a method comprising: sequentially applying measurement programming pulses to each of a plurality of word lines of a memory array of a memory device; determining a corresponding threshold voltage stored in a plurality of memory cells associated with each of the plurality of word lines; determining a difference between the corresponding threshold voltages based on the position of the plurality of memory cells within each word line; and determining a corresponding resistance-capacitance RC time constant for each of the plurality of word lines in view of the difference between the corresponding threshold voltages.

[0005] This disclosure also relates to a memory device comprising: a memory array including a plurality of word lines; and control logic operatively coupled to the memory array to perform operations including: applying a measurement programming pulse to one of the plurality of word lines of the memory array; determining a corresponding threshold voltage stored in a plurality of memory cells associated with the word line; determining a difference between the corresponding threshold voltages based on the positions of the plurality of memory cells within the word line; and determining a resistance-capacitance (RC) time constant of the word line in view of the difference between the corresponding threshold voltages. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A An exemplary computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2 This is a schematic block diagram of a portion of a memory device comprising a memory array having strings of memory cells and associated selection circuitry and selection lines, according to some embodiments.

[0010] Figure 3 According to some embodiments Figure 2 A side view of the structure of a portion of a memory device.

[0011] Figure 4 This is a flowchart of an exemplary method for tracking the RC time constant through word lines in a memory device of a memory subsystem, according to some embodiments of the present disclosure.

[0012] Figure 5A This is a diagram of an exemplary memory array of a memory device according to some embodiments of the present disclosure.

[0013] Figure 5B This is a diagram of exemplary word lines of a memory array according to some embodiments of the present disclosure.

[0014] Figure 6 This is a block diagram of an exemplary computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0015] Various aspects of this disclosure relate to tracking the RC time constant via word lines in a memory device through a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of both. The following is in conjunction with… Figure 1A Describe examples of storage devices and memory modules. Typically, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0016] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1AOther examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​such as “0” and “1”, or combinations of such values.

[0017] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain a group of memory cells, a group of word lines, a word line, or a single memory cell.

[0018] The performance of memory devices (such as NAND memory devices) depends heavily on the resistance of the NAND circuitry. There is inherent resistance in the conductive material chosen for the circuitry, and resistance also exists due to the circuitry's configuration. While low-resistance metals can be chosen for conductors, the size of the conductor's cross-section also affects its resistivity, and adjacent structures can create capacitance, which leads to additional resistance in the conductor. The combination of these effects in the circuitry can be measured by a constant known as the resistance-capacitance (RC) time constant. Lower resistance in the circuitry results in a lower RC time constant value, and faster memory device performance. The RC time constant is particularly affected by word line design due to the length of word lines and their small size, when they are integrated into access transistors. Furthermore, because word lines intersect with the vertical pillars of the memory array to form memory cells, the RC time constant of a given word line can be affected by the geometry of those intersections. In some memory devices, the pillars can have a tapered shape, containing one or more steps where the width of the pillars changes significantly. Therefore, since the surface area intersecting the pillars varies with each word line, the RC constant of each word line can also vary. For example, word lines that intersect with columns (where the columns are thicker) can have higher resistivity and a higher RC time constant.

[0019] Knowing the RC time constant of a given word line in a memory array has many benefits. For example, the RC time constant of a word line can be used to monitor word line degradation due to program / erase cycles, detect defects in a word line (e.g., electrical short circuits with adjacent word lines), optimize overdrive and underdrive performance of word lines, optimize programming time while maintaining a sufficient read window between the threshold distributions of word lines, and other potential benefits. However, measuring the RC time constant of a given word line is challenging. For example, on some memory dies, only one block can contain probe pads that allow the connection of external measurement circuitry. Therefore, the measurement of the RC time constant can only be applied to a small fraction of all word lines in the memory array on those dies. Because the RC time constant can vary significantly between word lines in a memory array as described above, the RC time constant of most word lines is unknown, and the advantages associated with knowing the RC time constant of those word lines cannot be realized.

[0020] This disclosure addresses the aforementioned and other problems by allowing the tracking of RC time constants along word lines in a memory device within a memory subsystem. In one embodiment, the control logic of the memory device internally performs a measurement process that determines the RC time constant of each individual word line of the memory array. In one embodiment, the control logic sequentially applies a measurement programming pulse to each word line of the memory array and subsequently reads the threshold voltages of multiple memory cells programmed to different points along each word line. Due to resistance along the length of each word line, the threshold voltage can decrease as the memory cell moves further away from the proximal end of the word line where the measurement programming pulse was applied. By measuring the threshold voltages of at least a subset of the cells along each word line, the control logic can determine the corresponding slope of the cell threshold voltage for each word line (i.e., the amount of change in the threshold voltage across the corresponding memory cell). In one embodiment, the control logic may utilize a lookup table or other data structure containing multiple entries, each entry associating a specific slope of the cell threshold voltage with a corresponding RC time constant. In one embodiment, after determining the corresponding RC time constant, the control logic can program the indication of the RC time constant to one or more memory cells for each corresponding word line, making the RC time constant readily available for future use.

[0021] The advantages of this method include, but are not limited to, improved performance of the memory device. The RC time constant tracking technique described herein allows for the easy determination of the corresponding RC time constant for each individual word line of the memory array of the memory device. Once known and stored, control logic can use the RC time constant of each word line to improve the performance of the memory device, such as by monitoring word line degradation due to programming / erasing cycles based on changes in the RC time constant over time, detecting defects in word lines (e.g., electrical short circuits with adjacent word lines) based on sudden changes in the RC time constant, optimizing overdrive and underdrive performance of word lines based on the RC time constant, optimizing programming time based on the RC time constant, while maintaining a sufficient read window between the threshold distributions of word lines, or other performance improvements.

[0022] Figure 1A An exemplary computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing power.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1AAn example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize NVM High Speed ​​(NVMe) interfaces, Open NAND Flash Interface (ONFI) interfaces, or some other interfaces to access components (e.g., memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components, such as 3D cross-dot arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A The exemplary memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0035] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to implement the required access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 from an external source (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices (such as memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands, such as programming commands, read commands, or other commands, to memory device 130 in response to requests received from host system 120. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. In some embodiments, memory subsystem controller 115 includes at least a portion of memory interface 113. For example, memory subsystem controller 115 may include processor 117 (e.g., processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, memory interface component 113 is part of host system 110, an application, or an operating system.

[0039] In one embodiment, memory device 130 includes a local media controller 135, which itself includes an RC time constant tracking component 137. As described herein, the RC time constant tracking component 137 internally performs a measurement process within memory device 130 to determine the RC time constant of each individual word line of the memory array of memory device 130. Further details regarding the operation of the local media controller 135 and the RC time constant tracking component 137 are described below.

[0040] Figure 1B According to the embodiment, a first device in the form of a memory device 130 and a memory subsystem (e.g., Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0041] Memory device 130 includes an array 150 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 150 (in...) Figure 1B(not shown) can be programmed to be one of at least two target data states.

[0042] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded for access to the memory cell array 150. The memory device 130 also includes an input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 114 communicates with the I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 109 to latch address signals before decoding. A command register 124 communicates with the I / O control circuitry 112 and the local media controller 135 to latch input commands.

[0043] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 150 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 150. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to addresses.

[0044] The local media controller 135 also communicates with cache register 142. Cache register 142 latches input or output data as instructed by the local media controller 135 to temporarily store data while the memory cell array 150 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 142 to data register 144 for transfer to the memory cell array 150; then new data can be latched in cache register 142 from I / O control circuitry 112. During read operations, data can be transferred from cache register 142 to I / O control circuitry 112 for output to memory subsystem controller 115; then new data can be transferred from data register 144 to cache register 142. Cache register 142 and / or data register 144 may form a page buffer of memory device 130 (e.g., may form a portion thereof). The page buffer may further include sensing devices (in...) Figure 1B(Not shown in the diagram) to sense the data status of memory cells in the memory cell array 150, for example, by sensing the status of data lines connected to the memory cells. Status register 122 can communicate with I / O control circuitry system 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115. As described herein, memory device 130 may include multiple status registers, including a separate status register associated with each corresponding partition (e.g., plane) of memory device 130, and a die-level status register for memory device 130.

[0045] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be further received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0046] In one embodiment, the local media controller 135 includes an RC time constant tracking component 137 that sequentially applies a measurement programming pulse to each word line of the memory array 150, and subsequently reads a threshold voltage programmed to a plurality of memory cells at different points along each word line. Due to the resistance along the length of each word line, as the memory cells move further away from where the measurement programming pulse is applied (e.g., via...), the threshold voltage is read. Figure 1BWhen the threshold voltage is near the word line of one or more signal drivers (not shown), the threshold voltage can decrease. By measuring the threshold voltage of at least a subset of cells along each word line, the RC time constant tracking component 137 can determine the corresponding slope of the cell threshold voltage for each word line (i.e., the amount of change in the threshold voltage across the corresponding memory cell). In one embodiment, the RC time constant tracking component 137 utilizes a lookup table 139 or other data structure to determine the corresponding RC time constant for each word line. According to an embodiment, the lookup table 139 may be part of a local media controller 135, part of a memory array 150, or located elsewhere on the memory device 130. The lookup table 139 may contain multiple entries, each associated with a specific slope of the cell threshold voltage with a corresponding RC time constant. For example, the RC time constant tracking component 137 can identify an entry in the lookup table 139 containing an indication of the determined slope and determine the corresponding RC time constant from that entry. The entries in the lookup table 139 may be populated prior to operation of the memory device 130, wherein the values ​​in the entries are determined by a testing process performed during device manufacturing. In one embodiment, after determining the corresponding RC time constant, the RC time constant tracking unit 137 can make the indication of the RC time constant programmed into one or more memory cells for each corresponding word line, so that the RC time constant is easy to use for future purposes.

[0047] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or via input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 142. This data can then be written to data register 144 for programming memory cell array 150.

[0048] In one embodiment, cache register 142 can be omitted, and data can be written directly to data register 144. Data can also be output via input / output (I / O) pins [7:0] for an 8-bit device, or via input / output (I / O) pins [15:0] for a 16-bit device. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0049] Those skilled in the art will understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1B The memory device 130. It should be recognized that, reference... Figure 1B The functionality of the various block components described may not necessarily be separated into different parts or component portions of the integrated circuit device. For example, a single part or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 2 This is a schematic block diagram of a portion of a memory device 200 including a memory array 201 having strings of memory cells and associated selection circuitry and select lines, according to some embodiments. The memory device 200 may correspond to... Figure 1A-1B The memory device 130. For example, the memory array 201 can be formed Figure 1B It is part of the memory cell array 104.

[0051] like Figure 2 As shown, memory device 200 may contain blocks (memory cell blocks) BLK0, BLK1 to BLKi. Three blocks are shown as an example. Memory device 200 may contain many blocks (e.g., up to thousands or more blocks). In the physical structure of memory device 200, blocks may be arranged (e.g., formed) one block after another, such that each block may have adjacent blocks. Adjacent blocks are blocks positioned close together (e.g., adjacent to) each other. For example, in the physical structure of memory device 200, blocks BLK0 and BLK1 may be adjacent blocks.

[0052] Each of the blocks BLK0, BLK1 through BLKi in the memory device 200 may contain sub-blocks (e.g., may be divided into sub-blocks). For example, each of blocks BLK0 and BLK1 may contain sub-blocks SB0 and SB1. Block BLKi may contain sub-block SB0 (and sub-block SB1, which is not shown). Blocks BLK0, BLK1 through BLKi may contain the same number of sub-blocks. Figure 2An example is shown where each of blocks BLK0, BLK1 through BLKi can contain two sub-blocks (e.g., SB0 and SB1). However, each of blocks BLK0, BLK1 through BLKi can have more than two blocks (e.g., SB0, SB1, SB2, SB3, etc.).

[0053] like Figure 2 As shown, each sub-block (e.g., SB0 or ​​SB1) has its own memory cell string, and each memory cell string may be associated with (e.g., coupled to) selection circuitry. For example, sub-block SB0 of block BLK0 has memory cell strings 231a, 232a, and 233a and associated selection circuitry (e.g., drain selection circuitry) 241a, 242a, and 243a, as well as selection circuitry (e.g., source selection circuitry) 241′a, 242′a, and 243′a. Sub-block SB1 of block BLK0 has memory cell strings 234a, 235a, and 236a and associated selection circuitry (e.g., drain selection circuitry) 244a, 245a, and 246a, as well as selection circuitry (e.g., source selection circuitry) 244′a, 245′a, and 246′a.

[0054] Sub-block SB0 of block BLK1 has memory cell strings 231b, 232b, and 233b, and associated selection circuits (e.g., drain selection circuits) 241b, 242b, and 243b, and selection circuits (e.g., source selection circuits) 241′b, 242′b, and 243′b. Sub-block SB1 of block BLK1 has memory cell strings 234b, 235b, and 236b, and associated selection circuits (e.g., drain selection circuits) 244b, 245b, and 246b, and selection circuits (e.g., source selection circuits) 244′b, 245′b, and 246′b.

[0055] Sub-block SB0 of BLKi has memory cell strings 231c, 232c, and 233c, and associated selection circuits (e.g., drain selection circuits) 241c, 242c, and 243c, and selection circuits (e.g., source selection circuits) 241′c, 242′c, and 243′c. Sub-blocks of blocks of memory device 200 (e.g., blocks BLK0, BLK1 to BLKi) may have the same number of memory cell strings and associated selection circuits.

[0056] Figure 2An example of three memory cell strings and their associated circuitry in a sub-block (e.g., sub-block SB0) is shown. The number of memory cell strings and their associated selection circuitry in each sub-block of blocks BLK0, BLK1 through BLKi can vary. Memory device 200 may include data lines 270, 271, and 272 carrying signals BL0, BL1, and BL2, respectively. Each of data lines 270, 271, and 272 may be constructed as a conductive line (containing a conductive material). The memory cell strings of blocks BLK0, BLK1 through BLKi may share data lines 270, 271, and 272.

[0057] For example, memory cell strings 231a and 234a (of block BLK0), memory cell strings 231b and 234b (of block BLK1), and memory cell string 231c (of block BLKi) can share data line 270. Memory cell strings 232a and 235a (of block BLK0), memory cell strings 232b and 235b (of block BLK1), and memory cell string 232c (of block BLKi) can share data line 271. Memory cell strings 233a and 236a (of block BLK0), memory cell strings 233b and 236b (of block BLK1), and memory cell string 233c (of block BLKi) can share data line 272. As an example, Figure 2 Three data lines, 270, 271, and 272, are shown. The number of data lines can vary.

[0058] Memory device 200 may include a line 299 capable of carrying a signal SRC (e.g., a source line signal). Line 299 may be configured as a conductive line (containing a conductive material) and may form part of a source (e.g., a source line) of memory device 200. Blocks BLK0, BLK1 through BLKi may share line 299. Alternatively, each of blocks BLK0, BLK1 through BLKi may have its own line (e.g., a source) similar to line 299.

[0059] Memory device 200 may include access lines in blocks BLK0, BLK1 to BLKi, wherein the access lines are electrically isolated from each other within the same block and electrically isolated between blocks. For example... Figure 2 As shown, each of blocks BLK0, BLK1, BLK2, and BLK3 may include its own access lines associated with signals (e.g., word line signals) WL0, WL1, WL2, and WL3. For example, in block BLK0, memory device 200 includes access lines (which may be or may include word lines) 2200, 2210, 2220, and 2230 (e.g., a set of access lines), which may carry corresponding signals (e.g., word line signals) WL00, WL10, WL20, and WL30, respectively.

[0060] In block BLK1, memory device 200 includes access lines (which may or may include word lines) 2201, 2211, 2221, and 2231 (e.g., a set of access lines), which may carry corresponding signals (e.g., word line signals) WL01, WL11, WL21, and WL31, respectively. In block BLKi, memory device 200 includes access lines (which may or may include word lines) 2201, 2211, 2221, and 2231. i 221 i 222 i and 223 i It can carry corresponding signals (e.g., word line signals) WL0 i WL1 i WL2 i and WL3 i .

[0061] Access lines 2200 to 2230, 2201 to 2231 and 220 i Up to 223 i These can be configured as conductive access lines (containing a conductive material), which can form part of a corresponding access line of the memory device 200 for accessing memory cells in a corresponding block. As an example, Figure 2 The diagram shows four access lines (2200 to 2230, 2201 to 2231, or 220) in each of blocks BLK0, BLK1 to BLKi. i Up to 223 i The number of access lines can vary.

[0062] In subblock SB0 of block BLK0, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820, and 2830 that can be shared by select circuits 241a, 242a, and 243a. In subblock SB1 of block BLK0, memory device 200 includes select lines (e.g., drain select lines) 2801, 2811, 2821, and 2831 that can be shared by select circuits 244a, 245a, and 246a. Block BLK0 may include select lines (e.g., source select lines) 284, 285, and 286 that can be shared by select circuits 241′a, 242′a, 243′a, 244′a, 245′a, and 246′a.

[0063] In sub-block SB0 of block BLK1, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820, and 2830 that can be shared by select circuits 241b, 242b, and 243b. In sub-block SB1 of block BLK1, memory device 200 includes select lines (e.g., drain select lines) 2801, 2811, 2821, and 2831 that can be shared by select circuits 244b, 245b, and 246b. Block BLK1 may include select lines (e.g., source select lines) 284, 285, and 286 that can be shared by select circuits 241′b, 242′b, 243′b, 244′b, 245′b, and 246′b. In the sub-block SB0 of block BLKi, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820 and 2830 that can be shared by select circuits 241c, 242c and 243c; and select lines (e.g., source select lines) 284, 285 and 286 that can be shared by select circuits 241′c, 242′c and 243′c.

[0064] Figure 2 An example is shown in which the memory device 200 includes four drain select lines (e.g., 2800, 2810, 2820, and 2830) associated with drain select circuitry (e.g., 241a, 242a, or 243a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include fewer or more than four drain select lines associated with drain select circuitry. Similarly, Figure 2 An example is shown in which the memory device 200 includes three source select lines (e.g., 284, 285, and 286) associated with a source select circuit (e.g., 241′a, 242′a, or 243′a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include fewer or more than three source select lines associated with the source select circuit.

[0065] The memory device 200 may include connectors 280′0, 281′0, 282′0, 283′0, 280′1, 281′1, 282′1, and 283′1, wherein each connector may be electrically connected to two corresponding select lines. Figure 2 Connectors 280′0, 281′0, 282′0, 283′0, 280′1, 281′1, 282′1, and 283′1 are shown separately to avoid congestion. Figure 2 The components shown. Figure 2Connector 280'0 is shown to indicate that select line 2800 (sometimes referred to as select line 2800 / SB0 / BLK0) of sub-block SB0 of block BLK0 and select line 2800 (sometimes referred to as select line 2800 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through connector 280'0. Therefore, in memory device 200, select lines 2800 / SB0 / BLK0 and 2800 / SB0 / BLK1 can provide (e.g., apply) the same signal. This also means that select lines 2800 / SB0 / BLK0 and 2800 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0066] Figure 2 Connector 281'0 is shown to indicate that select line 2810 (sometimes referred to as select line 2810 / SB0 / BLK0) of sub-block SB0 of block BLK0 and select line 2810 (sometimes referred to as select line 2810 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through connector 281'0. Therefore, in memory device 200, select lines 2810 / SB0 / BLK0 and 2810 / SB0 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2810 / SB0 / BLK0 and 2810 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0067] Figure 2 Connector 282'0 is shown to indicate that select line 2820 (sometimes referred to as select line 2820 / SB0 / BLK0) of sub-block SB0 of block BLK0 and select line 2820 (sometimes referred to as select line 2820 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through connector 282'0. Therefore, in memory device 200, select lines 2820 / SB0 / BLK0 and 2820 / SB0 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2820 / SB0 / BLK0 and 2820 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0068] Figure 2Connector 283'0 is shown to indicate that select line 2830 (sometimes referred to as select line 2830 / SB0 / BLK0) of sub-block SB0 of block BLK0 and select line 2830 (sometimes referred to as select line 2830 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through connector 283'0. Therefore, in memory device 200, select lines 2830 / SB0 / BLK0 and 2830 / SB0 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2830 / SB0 / BLK0 and 2830 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0069] Figure 2 Connector 280′1 is shown to indicate that select line 2801 (sometimes referred to as select line 2801 / SB1 / BLK0) of sub-block SB1 of block BLK0 and select line 2801 (sometimes referred to as select line 2801 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through connector 280′1. Therefore, in memory device 200, select lines 2801 / SB1 / BLK0 and 2801 / SB1 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2801 / SB1 / BLK0 and 2801 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0070] Figure 2 Connector 281′1 is shown to indicate that select line 2811 (sometimes referred to as select line 2811 / SB1 / BLK0) of sub-block SB1 of block BLK0 and select line 2811 (sometimes referred to as select line 2811 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through connector 281′1. Therefore, in memory device 200, select lines 2811 / SB1 / BLK0 and 2811 / SB1 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2811 / SB1 / BLK0 and 2811 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0071] Figure 2Connector 282'1 is shown to indicate that select line 2821 (sometimes referred to as select line 2821 / SB1 / BLK0) of sub-block SB1 of block BLK0 and select line 2821 (sometimes referred to as select line 2821 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through connector 282'1. Therefore, in memory device 200, select lines 2821 / SB1 / BLK0 and 2821 / SB1 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2821 / SB1 / BLK0 and 2821 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0072] Figure 2 Connector 283'1 is shown to indicate that select line 2831 (sometimes referred to as select line 2831 / SB1 / BLK0) of sub-block SB1 of block BLK0 and select line 2831 (sometimes referred to as select line 2831 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through connector 283'1. Therefore, in memory device 200, select lines 2831 / SB1 / BLK0 and 2831 / SB1 / BLK1 can be provided (applied) with the same signal. This also means that select lines 2831 / SB1 / BLK0 and 2831 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0073] In the structure of memory device 200, each of connectors 280′0, 281′0, 282′0, 283′0, 280′1, 281′1, 282′1, and 283′1 may contain a conductive material formed to make electrical contact with the material of two corresponding select lines. For example, connector 283′0 may contain a conductive material formed to make electrical contact with the material forming select line 2830 / SB0 / BLK0 and the material forming select line 2831 / SB1 / BLK0. In another example, connector 282′0 may contain a conductive material formed to make electrical contact with the material forming select line 2820 / SB0 / BLK0 and the material forming select line 2821 / SB1 / BLK0.

[0074] The material (or multiple materials) of each of connectors 280′0, 281′0, 282′0, 283′0, 280′1, 281′1, 282′1, and 283′1 may comprise metal, doped polysilicon, or other conductive materials. Each drain select circuit of memory device 200 may include multiple drain select gates (e.g., four transistors connected in series) connected in series between a corresponding data line and a corresponding memory cell string. The drain select gates may be controlled by the corresponding drain select line (e.g., turned on or off) based on the voltage of a signal provided to the corresponding drain select line. Each source select circuit of memory device 200 may include multiple source select gates connected in series between line 299 and a corresponding memory cell string. The source select gates may be controlled by the corresponding source select line (e.g., turned on or off) based on the voltage of a signal provided to the corresponding source select line.

[0075] exist Figure 2 In this memory device 200, each memory cell string has memory cells arranged in a string (e.g., coupled in series with each other) to store information. During operation of the memory device 200 (e.g., read, write, or erase operation), a memory cell string can be individually selected to access memory cells within the selected memory cell string in order to store information in or read information from the selected memory cell string. Depending on which operation the memory device 200 performs on the selected memory cell string, one or two selection circuits (drain selection circuit and source selection circuit) associated with the selected memory cell string can be activated (e.g., by turning on the selection gate (e.g., transistor) in the selection circuit (or selection circuit)).

[0076] During operation of the memory device 200, activating a specific selection circuit in the selection circuitry of the memory device 200 may include providing (e.g., applying) a voltage of a specific value to a signal on a selection line associated with that specific selection circuit. When a specific drain selection circuit of the memory device 200 is activated, it can electrically connect a selected memory cell string associated with that specific selection circuit to a corresponding data line (e.g., one of data lines 270, 271, or 272) (e.g., forming a current path from the selected memory cell string associated with that specific selection circuit to the corresponding data line (e.g., one of data lines 270, 271, or 272). When a specific source selection circuit is activated, it can electrically connect a selected memory cell string associated with that specific selection circuit to a source (e.g., line 299) (e.g., forming a current path from the selected memory cell string associated with that specific selection circuit to the source (e.g., line 299).

[0077] Figure 3 According to some embodiments Figure 2 A side view of the structure of a portion of the memory device 200. (See attached image.) Figure 3 As shown, the memory device 200 may include a substrate 390 on which memory cells 210, 211, 212, and 213 of corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1 may be formed (e.g., formed perpendicularly in the z-direction relative to line 299 and substrate 390). The memory device 200 includes different levels 307 to 317 relative to the z-direction. Levels 307 to 317 are internal device levels between the substrate 390 and the data line 270.

[0078] The substrate 390 of the memory device 200 may comprise a monocrystalline semiconductor material. For example, the substrate 390 may comprise monocrystalline silicon. The monocrystalline semiconductor material of the substrate 390 may contain impurities, allowing the substrate 390 to have a specific conductivity type (e.g., n-type or p-type).

[0079] The memory device 200 may include a drive circuit system 319 to provide signals (e.g., drain select line signal and source select line signal) to corresponding select lines of the memory device 200. The drive circuit system 319 may correspond to... Figure 1A-1B The local media controller 135 is either included within it. Although in Figure 3 Not shown, but substrate 390 may contain circuitry that can be located directly below line 299. Such circuitry may include sense amplifiers, buffers (e.g., page buffers), decoders, and other circuitry components of memory device 200. Figure 3 As shown, the drive circuit system 319 may include drivers (driver circuits) 380, 381, 382, ​​and 383 that provide corresponding signals (e.g., drain select line signals SGD0, SGD1, SGD2, and SGD3), and drivers (driver circuits) 384, 385, and 386 that provide corresponding signals (e.g., source select line signals SGS0, SGS1, and SGS2). Figure 3 For simplicity, only some drain selection signals and source selection signals are shown in the diagram.

[0080] exist Figure 3 In this context, each of drivers 380 to 386 may contain two transistors: an N-channel transistor (e.g., an NMOS) and a P-channel transistor (e.g., a p-channel MOS (PMOS)). For simplicity, in Figure 3Details of only one of drivers 380 to 384 are shown in the diagram. Each of drivers 380 to 386 may include an output node, for example, a node located between and electrically connected to transistors N and P, to provide (e.g., drive) a corresponding signal (e.g., a drain select line signal or a source select line signal). The output node of each of drivers 380 to 386 may be coupled (e.g., electrically connected) to (e.g., electrically connected to) a corresponding drain select line or a corresponding source select line of memory device 200. This allows drain select line signals and source select line signals (e.g., SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, and SGS2) from drive circuitry system 319 to the corresponding drain select line and source select line of memory device 200, as referenced above. Figure 2 and Figure 3 As stated above.

[0081] Figure 3 Examples are shown in which each of drivers 380 to 386 may have two transistors of different transistor types (e.g., NMOS and PMOS) coupled in a complementary MOS (CMOS) connection. However, each of drivers 380 to 386 may have two transistors of the same type (e.g., two NMOS transistors or two PMOS transistors) and two separate transistor gate signals. Furthermore, the number of transistors in each of drivers 380 to 386 may be different from two.

[0082] like Figure 3 As shown, the data line 270 can have a length extending in the y direction (e.g., Figure 3 As shown), the y-direction is perpendicular to both the z-direction and the x-direction. Data line 270 may contain a conductive material (e.g., conductive-doped polysilicon, metal, or other conductive material). Furthermore, line 299 may contain a conductive material and may have a length extending in the y-direction. Figure 3 An example is shown in which line 299 (e.g., a source) may be formed on a portion of substrate 390 (e.g., by depositing a conductive material on substrate 390). Alternatively, line 299 may be formed in or on a portion of substrate 390 (e.g., by doping a portion of substrate 390).

[0083] In at least some embodiments, the selection lines (e.g., drain selection lines) 2800, 2810, 2820, and 2830 for each of blocks BLK0 and BLK1 may be located in corresponding levels 314, 315, 316, and 317. The selection lines (e.g., drain selection lines) 2801, 2811, 2821, and 2831 for each of blocks BLK0 and BLK1 may be located in corresponding levels 314, 315, 316, and 317.

[0084] In at least some embodiments, memory cells 210, 211, 212, and 213 of memory cell strings 231a, 234a, 231b, and 234b may be located in levels 310, 311, 312, and 313, respectively. Access lines 2200, 2210, 2220, and 2230 of block BLK0 (associated with memory cells 210, 211, 212, and 213, respectively) may be located in levels 310, 311, 312, and 313, respectively. Access lines 2201, 2211, 2221, and 2231 of block BLK1 (associated with memory cells 210, 211, 212, and 213, respectively) may be located in levels 310, 311, 312, and 313, respectively.

[0085] The selection lines (e.g., source selection lines) 284, 285, and 286 of each of blocks BLK0 and BLk1 can be located in different layers (e.g., layers 307, 308, and 309, respectively) between the substrate 390 and the memory cell strings 231a, 232a, and 233a. The memory device 200 may also include dielectric materials interleaved with other elements in the different layers of the memory device 200. Figure 3 (Not shown in the diagram). For example, memory device 200 may include a dielectric material (e.g., silicon dioxide) located between layers 314 and 317 and intersecting (in the spaces between) the select lines 2800, 2810, 2820, and 2830 of each of blocks BLK0 and BLK1. In another example, memory device 200 may include a set of dielectric materials (e.g., silicon dioxide) located between layers 310 and 313 and intersecting (in the spaces between) the access lines 2200, 2210, 2220, and 2230 of block BLK0. In yet another example, memory device 200 may include a set of dielectric materials (e.g., silicon dioxide) located between layers 310 and 313 and intersecting (in the spaces between) the access lines 2201, 2211, 2221, and 2231 of block BLK1.

[0086] In another example, memory device 200 includes a dielectric material (e.g., silicon dioxide) located between layers 307 and 309 and intersecting (located in the space between) select lines 284, 285, and 286. The material of select lines 2800, 2810, 2820, 2830, 2801, 2811, 2821, 2831, 284, 285, and 286 may comprise conductive-doped polysilicon, metal, or other conductive materials, and may be the same as the conductive material of access lines 2200, 2210, 2220, 2230, 2201, 2211, 2221, and 2231. Figure 3As shown, the memory device 200 may include pillars (conductive pillars) 341, 342, 343, and 344 in corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1. Each of the pillars 341, 342, 343, and 344 may have an outwardly extending length (e.g., extending vertically in the z-direction and perpendicular to the y-direction). Each of the pillars 341, 342, 343, and 344 may contact a conductive region of the material forming a portion of data line 270 and a conductive region of the material forming a portion of line 299.

[0087] Each of pillars 341, 342, 343, and 344 may contain one (or more) materials to form a conductive path (e.g., a channel) between data line 270 and line 299. Such materials (e.g., undoped or doped polysilicon) in each of pillars 341, 342, 343, and 344 may be channels (in the respective pillars of pillars 341, 342, 343, and 344) Figure 3 (Not shown in the image)

[0088] like Figure 3 As shown, memory device 200 may include a structure 330 adjacent to and continuously extending along the length of the respective pillars 341, 342, 343, and 344. Structure 330 is also adjacent to portions of the respective access lines (2200, 2210, 2220, and 2230, or access lines 2201, 2211, 2221, and 2231). The structure 330 adjacent to the respective pillars is located between the respective pillars and portions of the respective access lines (access lines 2200, 2210, 2220, and 2230, or access lines 2201, 2211, 2221, and 2231). Structure 330 may include portions 301, 302, and 303. A portion of structure 330 along a particular pillar may form a portion of each memory cell in a string of memory cells adjacent to that particular pillar. For example, the structure 330 adjacent to pillar 342 can form a portion of each of the memory cells 210, 211, 212, and 213 of the memory cell string 234a. Therefore, each of the memory cells 210, 211, 212, and 213 of the memory cell string can include a portion of the structure 330 (a portion of each of portions 301, 302, and 303) directly located between one of the access lines (one of access lines 2200, 2210, 2220, 2230, 2201, 2211, 2221, and 2231) and the corresponding pillar. For example, memory cell 212 (adjacent to pillar 342) of the memory cell string 243a can include a portion of each of portions 301, 302, and 303 directly located between access line 2220 and pillar 342.

[0089] Structure 330 may be part of a TANOS (TaN, Al2O3, Si3N4, SiO2, Si) structure. For example, portion 301 (e.g., interpoly dielectrics) may contain one or more charge-blocking materials (e.g., dielectric materials such as TaN and Al2O3) capable of blocking charge tunneling. Portion 302 may contain charge storage elements (e.g., one or more charge storage materials, such as Si3N4) that can provide charge storage functionality (e.g., charge trapping) to represent the value of information stored in memory cells 210, 211, 212, or 213. Portion 303 may contain dielectrics, such as one or more tunneling dielectric materials (e.g., SiO2) capable of allowing the tunneling of charges (e.g., electrons). As an example, portion 303 may allow electrons to tunnel from portion 304 to portion 302 during a write operation and from portion 302 to portion 304 during an erase operation of the memory device 200. Furthermore, portion 303 may allow holes to tunnel from portion 304 to portion 302, compensating for trapped electron recombination during erase operations of the memory device 200. In an alternative arrangement of the memory device 200, structure 330 may be part of a SONOS (Si, SiO2, Si3N4, SiO2, Si) structure. In another alternative arrangement, structure 330 may be part of a floating gate structure (e.g., portion 302 may be polysilicon, and each of portions 301 and 303 may be a dielectric (e.g., SiO2)).

[0090] like Figure 3 As shown, the select line (e.g., 2800) is a sheet (e.g., a single layer) of conductive material (e.g., polysilicon, metal, or other conductive material). As described above, the select line may carry a signal (e.g., signal SGD10), but it does not function as a switch (e.g., a transistor). The select gate (e.g., 260) may include a portion of the corresponding select line (e.g., a portion of the conductive material sheet forming the corresponding select line) and additional structures that perform a function (e.g., the function of a transistor). For example, in Figure 3 In one embodiment, the selection gate 260 of sub-block SB0 of block BLK0 may include a portion of the selection line 2800 of sub-block SB0 of block BLK0 and a portion of the structure 330 adjacent to the selection line 2800 of sub-block SB0 of block BLK0 (along pillar 341). In another embodiment, the selection gate 261 of sub-block SB0 of block BLK0 may include a portion of the selection line 2810 of sub-block SB0 of block BLK0 and a portion of the structure 330 adjacent to the selection line 2810 of sub-block SB0 of block BLK0 (along pillar 341).

[0091] Figure 3 An example is shown in which select gates 261 to 266 have the same structure (e.g., a TANOS structure) as memory cells 210, 211, 212, and 213. Alternatively, select gates 260, 261, 262, and 263 (e.g., drain select gates), select gates 264, 265, and 266 (e.g., source select gates), or select gates 260 to 266 may have different structures, such as FET structures. As known to those skilled in the art, an FET typically includes a transistor gate, a transistor body channel, and a gate oxide between the transistor gate and the transistor body channel, the gate oxide being in direct contact with the transistor gate and the transistor body channel.

[0092] Figure 4 This is a flowchart of an exemplary method for tracking an RC time constant via word lines in a memory device through a memory subsystem, according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is executed by the RC time constant tracking component 137 of FIG1. ​​Although shown in a specific order or sequence, the order of processes may be modified unless otherwise stated. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0093] In operation 405, programming pulses are applied. For example, processing logic (e.g., RC time constant tracking unit 137) may cause the programming pulses to be sequentially applied to each of the multiple word lines of the memory array 150 of the memory device 130. In one embodiment, as... Figure 5A As shown, the memory array 150 can contain multiple word lines (WLn-1, WLn..., top of WL), which can be referenced above. Figure 2 and Figure 3One implementation of the described word line. Each word line in memory array 150 may intersect with multiple vertical pillars (pillar 0, pillar 1, ..., pillar M) to form a memory cell. The RC time constant of a given word line may be affected by the geometry of those intersections. For example, in memory array 150, the pillars may have a tapered shape, including one or more steps in which the width of the pillars varies significantly. Therefore, since the surface area of ​​the intersections with the pillars varies with each word line, the RC constant of each word line may also vary. Word lines intersecting with pillars (where the pillars are thicker) may have higher resistivity and higher RC time constants. In one embodiment, in response to a trigger event, RC time constant tracking component 137 may cause a measurement programming pulse to be sequentially applied to each word line in memory array 150. For example, RC time constant tracking component 137 may first cause a measurement programming pulse to be applied to WLn-1, then subsequently to WLn, and so on, until the top of WL. In one embodiment, the RC time constant tracking component 137 applies a control signal to the signal driver, such as... Figure 5B The driver 510 is configured such that a signal driver coupled to a first end of a given word line 500 (e.g., WLn) applies a measurement programming pulse. In one embodiment, the measurement programming pulse is a relatively short voltage pulse (i.e., shorter than a typical programming pulse) having an amplitude determined by testing, targeting the average threshold voltage of the memory cell along word line 500.

[0094] Refer again Figure 4 In operation 410, a threshold voltage is determined. For example, the processing logic may determine a corresponding threshold voltage stored in a plurality of memory cells associated with each of the plurality of word lines. In operation 415, a difference is determined. For example, the processing logic may determine a difference between the corresponding threshold voltages based on the location of the plurality of memory cells within each word line. In one embodiment, RC time constant tracking component 137 may read the voltage programmed into the plurality of memory cells. Depending on the embodiment, the number of memory cells may include all memory cells associated with a word line such as word line 500, or a subset of memory cells associated with a word line. Due to resistance along the length of the word line, the threshold voltage may decrease as the memory cells move further away from the end of the word line where the measurement programming pulse is applied (i.e., where the signal driver 510 is connected). For example, the threshold voltage vnear may be higher than Figure 5B The threshold voltages vfar1, vfar2, vfar3, and vfar4 are shown.

[0095] In one embodiment, the RC time constant tracking component 137 can perform a program verification operation on each word line of the memory array 150, such that a program verification voltage is applied to each word line. As part of the program verification operation, the RC time constant tracking component 137 can identify a first group of memory cells (i.e., "near" memory cells) within a threshold distance from a first end of each word line and a second group of memory cells (i.e., "far" memory cells) beyond the threshold distance from the first end of each word line. The RC time constant tracking component 137 can determine a first number of memory cells in the first group having a threshold voltage below the program verification level (e.g., associated with the program verification voltage) and a second number of memory cells in the second group having a threshold voltage below the program verification level. The RC time constant tracking component 137 can further determine a difference between the first number of memory cells and the second number of memory cells, wherein the difference represents the amount of change in the threshold voltage of the memory cells along word line 500.

[0096] Refer again Figure 4 In operation 420, the RC time constant is determined. For example, given the difference between corresponding threshold voltages, the control logic can determine the corresponding RC time constant for each of the multiple word lines. In one embodiment, the RC time constant tracking component 137 utilizes a lookup table 139 or other data structure to determine the corresponding RC time constant for each word line. The lookup table 139 may contain multiple entries, each entry associating a specific slope of the cell threshold voltage (i.e., the difference between corresponding threshold voltages based on location) with the corresponding RC time constant. For example, the RC time constant tracking component 137 can identify entries in the lookup table 139 that contain an indication of the determined slope and determine the corresponding RC time constant from that entry. The entries in the lookup table 139 may be populated prior to operation of the memory device 130, wherein the values ​​in the entries are determined through a testing process performed during device manufacturing.

[0097] In operation 425, data is stored. For example, the control logic may cause an indication of the corresponding RC time constant to be stored in at least one memory cell associated with each corresponding word line. In one embodiment, the RC time constant tracking component 137 may cause the indication (such as...) Figure 5B The “flag byte” shown is written to at least one memory cell of word line 500. As an indication of the RC time constant of word line 500 is stored in the memory cell of word line 500, the RC time constant can be easily accessed for future use, such as to optimize the operation of memory array 150.

[0098] As described above, operations 405-425 can be performed sequentially for each word line of memory array 150 or for any subset of one or more word lines of memory array 150. For example, each of operations 405-425 can be performed once for a first word line (e.g., WLn-1). Subsequently, each of operations 405-425 can be performed once for a second word line (e.g., WLn), and so on. In one embodiment, one or more specific operations can be performed on the word lines before performing one or more subsequent operations on the word lines. For example, operations 405-410 can be performed on the word lines before performing operations 415-425 on any word line.

[0099] Once operations 405-425 have been performed on one or more word lines of memory array 150, additional operations 430-440 can be performed to improve the operation of memory device 130 using RC time constants. In one embodiment, these additional operations are performed by RC time constant tracking unit 137. However, in other embodiments, these additional operations can be performed by other units, such as the memory subsystem controller 115 of FIG1. ​​The additional operations 430-440 are independent and can be performed independently of each other. Furthermore, multiple operations in operations 430-440 can be performed sequentially or in parallel on memory device 130.

[0100] In operation 430, a defect is detected. For example, the control logic may detect a defect in at least one word line based on the change in the corresponding RC time constant of at least one of multiple word lines over time. In one embodiment, the control logic may determine the RC time constant of a given word line 500 according to the steps of operations 405-420 described above. After determining the RC time constant, the control logic may compare the determined RC time constant with an indication of the RC time constant stored after a previous determination (e.g., from a “flag byte”). If there is a change in the RC time constant (e.g., if the most recently determined RC time constant is lower than the stored RC time constant by more than a threshold amount), the control logic may detect word line degradation or the presence of some other defect. For example, such degradation may be caused by an excessive number of program / erase cycles, or the defect may be an electrical short circuit, delamination, or other defects. Depending on the embodiment, the control logic may optionally update the stored indication of the RC time constant with the most recently determined RC constant.

[0101] In operation 435, the voltage is regulated. For example, the control logic may adjust at least one of the overdrive or underdrive voltages of one of a plurality of word lines based on a corresponding RC time constant. During a memory access operation (e.g., a programming operation) performed on memory device 130, the control logic may cause a specific voltage signal to be applied to the word lines of memory array 150. The control logic may cause the voltage signal to be applied to the word line associated with the memory cell in the form of one or more pulses (referred to as programming pulses). The amplitude of the voltage and the width of each pulse may determine the amount of charge to be stored in the memory cell associated with the word line, and thus program the state of the memory cell. A series of pulses may be applied to the word line to gradually raise the memory cell to a target threshold voltage (Vt) without overprogramming the memory cell. In some solutions for evolving specifications and requirements, the pump regulator circuitry of the local media controller may be adapted to provide a measurement of overdrive or underdrive voltage applied to the word line when necessary. The overdrive voltage may contain a higher voltage than the normally applied voltage, so that the memory cell of the word line can reach the target threshold voltage in a shorter time. Underdrive voltage can include a voltage lower than the normally applied voltage, allowing the memory cells of the word line to reach the target threshold voltage in a shorter time. In one embodiment, a specific amount of overdrive or underdrive voltage can be determined based on a determined RC time constant for a given word line. For example, control logic can utilize a lookup table comprising multiple entries, each entry having an associated RC time constant and a set of one or more fine-tuning settings (e.g., corresponding overdrive and / or underdrive voltages). Thus, control logic can identify the entry corresponding to the determined RC time constant, determine the associated overdrive or underdrive voltage, and cause the determined overdrive or underdrive voltage to be applied to the word line during memory access operations.

[0102] In operation 440, the programming step size is adjusted. For example, the control logic may adjust the step size between programming pulses used for programming operations performed on one of multiple word lines based on a corresponding RC time constant. In one embodiment, data is programmed into memory cells of memory array 150 using a sequence of programming pulses with a specific programming step size (i.e., the amount by which the amplitude of the programming voltage increases between each successive programming pulse). The control logic may be pre-configured to use a default programming step size (e.g., an initial voltage value), but this programming step size is a configurable parameter. In one embodiment, the control logic may adjust the step size based on the RC time constant of a given word line (e.g., increasing or decreasing the amount by which subsequent programming pulses exceed previous programming pulses). For example, the control logic may utilize a lookup table comprising multiple entries, each entry having an associated RC time constant and a set of one or more fine-tuning settings (e.g., a corresponding programming step size). Thus, the control logic may identify the entry corresponding to the determined RC time constant, determine the associated programming step size, and cause the determined programming step size to be used in a series of programming pulses applied to the word line during a memory access operation.

[0103] Figure 6 An exemplary machine of computer system 600 is shown, in which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1A (Operation of the RC time constant tracking component 137). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0104] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the action the machine should take. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0105] An exemplary computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0106] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0107] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein are stored. During execution by computer system 600, the instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A The memory subsystem 110.

[0108] In one embodiment, instruction 626 includes implementation and Figure 1A The RC time constant tracking component 137 corresponds to the functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0109] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this paper, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0110] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0111] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0112] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0113] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0114] In the foregoing description, embodiments of this disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory array, the memory array comprising multiple word lines; as well as Control logic, operatively coupled to the memory array, to perform operations including: The measurement programming pulses are sequentially applied to each of the plurality of word lines of the memory array; Determine the corresponding threshold voltage stored in a plurality of memory cells associated with each of the plurality of word lines; The difference between the corresponding threshold voltages is determined based on the position of the plurality of memory cells within each word line; as well as The corresponding resistance-capacitance RC time constant for each of the plurality of word lines is determined based on the difference between the corresponding threshold voltages.

2. The memory device of claim 1, wherein the control logic performs operations further including: The indication of the corresponding RC time constant is stored in at least one of the memory cells associated with each corresponding word line.

3. The memory device of claim 1, wherein sequentially applying the measurement programming pulse to each of the plurality of word lines of the memory array comprises applying the measurement programming pulse to a signal driver coupled to a first end of each of the plurality of word lines.

4. The memory device of claim 3, wherein determining the difference between the respective threshold voltages based on the positions of the plurality of memory cells within each word line includes determining how much the respective threshold voltage decreases as the distance of the memory cell from the first end of each word line increases.

5. The memory device of claim 3, wherein determining the difference between the corresponding threshold voltages based on the positions of the plurality of memory cells within each word line comprises: Identify a first group of memory cells within a threshold distance from the first end of each word line and a second group of memory cells beyond the threshold distance from the first end of each word line; A first number of memory cells in the first group having a threshold voltage lower than the programming verification level and a second number of memory cells in the second group having a threshold voltage lower than the programming verification level are determined. as well as Determine the difference between the first number of memory cells and the second number of memory cells.

6. The memory device of claim 1, wherein determining the corresponding RC time constant of each of the plurality of word lines comprises identifying a corresponding entry in an identification data structure, each entry comprising an indication of the difference between the corresponding threshold voltages and an indication of the corresponding RC time constant.

7. The memory device of claim 1, wherein the control logic performs operations further including: Defects in the at least one word line are detected based on the change of the corresponding RC time constant of at least one of the multiple word lines over time.

8. The memory device of claim 1, wherein the control logic performs operations further including: Based on the corresponding RC time constant, adjust at least one of the overdrive voltage or underdrive voltage of one of the multiple word lines.

9. The memory device of claim 1, wherein the control logic performs the following operations: Based on the corresponding RC time constant, the step size between programming pulses used for programming operations performed on one of the plurality of word lines is adjusted.

10. A method comprising: This causes measurement programming pulses to be sequentially applied to each of the multiple word lines of the memory array of the memory device; Determine the corresponding threshold voltage stored in a plurality of memory cells associated with each of the plurality of word lines; The difference between the corresponding threshold voltages is determined based on the position of the plurality of memory cells within each word line; as well as The corresponding resistance-capacitance RC time constant for each of the plurality of word lines is determined based on the difference between the corresponding threshold voltages.

11. The method of claim 10, further comprising: The indication of the corresponding RC time constant is stored in at least one of the memory cells associated with each corresponding word line.

12. The method of claim 10, wherein sequentially applying the measurement programming pulse to each of the plurality of word lines of the memory array comprises applying the measurement programming pulse to a signal driver coupled to a first end of each of the plurality of word lines.

13. The method of claim 12, wherein determining the difference between the respective threshold voltages based on the positions of the plurality of memory cells within each word line includes determining how much the respective threshold voltage decreases as the distance of the memory cell from the first end of each word line increases.

14. The method of claim 12, wherein determining the difference between the corresponding threshold voltages based on the positions of the plurality of memory cells within each word line comprises: Identify a first group of memory cells within a threshold distance from the first end of each word line and a second group of memory cells beyond the threshold distance from the first end of each word line; A first number of memory cells in the first group having a threshold voltage lower than the programming verification level and a second number of memory cells in the second group having a threshold voltage lower than the programming verification level are determined. as well as Determine the difference between the first number of memory cells and the second number of memory cells.

15. The method of claim 10, wherein determining the corresponding RC time constant of each of the plurality of word lines comprises identifying a corresponding entry in an identification data structure, each entry comprising an indication of the difference between the corresponding threshold voltages and an indication of the corresponding RC time constant.

16. The method of claim 10, further comprising: Defects in the at least one word line are detected based on the change of the corresponding RC time constant of at least one of the multiple word lines over time.

17. The method of claim 10, further comprising: Based on the corresponding RC time constant, adjust at least one of the overdrive voltage or underdrive voltage of one of the multiple word lines.

18. The method of claim 10, further comprising: Based on the corresponding RC time constant, the step size between programming pulses used for programming operations performed on one of the plurality of word lines is adjusted.

19. A memory device comprising: A memory array, the memory array comprising multiple word lines; as well as Control logic, operatively coupled to the memory array, to perform operations including: The measurement programming pulse is applied to one of the multiple word lines of the memory array; Determine the corresponding threshold voltages stored in the plurality of memory cells associated with the word line; The difference between the corresponding threshold voltages is determined based on the positions of the plurality of memory cells within the word line; as well as The resistance-capacitance RC time constant of the word line is determined based on the difference between the corresponding threshold voltages.

20. The memory device of claim 19, wherein the control logic performs the following operations: The indication of the RC time constant is stored in at least one of the memory cells associated with the word line.

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