Memory devices and methods of testing memory devices with repair signal maintenance mechanisms

Abstract

The present application provides a memory test circuit with a repair signal maintaining mechanism. The repair control circuit controls a built-in self-repair procedure of a memory built-in self-repair circuit on a memory circuit, and includes a remapping temporary storage circuit and a latch temporary storage circuit. When the built-in self-repair procedure is completed, the remapping temporary storage circuit receives and temporarily stores a repair signal generated from the memory built-in self-repair circuit. The latch temporary storage circuit is electrically coupled between the remapping temporary storage circuit and a remapping circuit corresponding to the memory circuit, receives and saves the repair signal from the remapping temporary storage circuit, so that when the remapping temporary storage circuit is scanned according to a scan chain, the remapping circuit accesses the repair signal, and remaps the memory circuit according to the repair signal and a redundancy structure to repair the memory circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to memory testing technology, and in particular, to a memory device and a memory testing circuit and method thereof with a repair signal maintaining mechanism. BACKGROUND

[0002] Circuit chips are tested before being shipped to ensure that the chips are functioning properly. For example, scan testing through scan chains can eliminate chips with defects such as stuck-at faults and delay faults. Memory built-in self-test (MBIST) circuitry can be used to eliminate chips with defective memories. Test data is generated using automatic test patterns and read and written to the memory through scan chains for multiple cycles to test for delay faults in the paths between functional registers and the memory.

[0003] However, in scan testing, the data of all shift registers located in the scan chains will be lost due to shifting. At this time, if some of the registers have data for repairing the memory, the memory cannot be repaired correctly, resulting in incorrect test results. SUMMARY

[0004] In view of the problems of the prior art, one object of the present application is to provide a memory device and a memory testing circuit and method thereof with a repair signal maintaining mechanism to improve the prior art.

[0005] The present application includes a memory testing circuit with a repair signal maintaining mechanism, which includes a memory built-in self-repair (MBISR) circuit and a repair control circuit. The repair control circuit is configured to control the MBISR circuit to perform a built-in self-repair procedure on a memory circuit with a redundancy structure and includes a remapping register circuit and a latch register circuit. The remapping register circuit is disposed in a scan chain and is configured to store a repair signal generated from the MBISR circuit after the built-in self-repair procedure is completed. The latch register circuit is electrically coupled between the remapping register circuit and a remapping circuit corresponding to the memory circuit and is configured to receive and save the repair signal from the remapping register circuit to enable the remapping circuit to access the repair signal and remap the memory circuit for repair according to the repair signal and the redundancy structure when the remapping register circuit is scanned according to the scan chain.

[0006] The present application also includes a memory device, which comprises a memory circuit and a memory test circuit. The memory circuit has a redundancy structure. The memory test circuit comprises a memory built-in self-repair circuit and a repair control circuit. The repair control circuit is configured to control the memory built-in self-repair circuit to perform a built-in self-repair procedure on the memory circuit, and comprises a remapping temporary storage circuit and a latch temporary storage circuit. The remapping temporary storage circuit is disposed in a scan chain and configured to store a repair signal generated from the memory built-in self-repair circuit after the built-in self-repair procedure is completed. The latch temporary storage circuit is electrically coupled between the remapping temporary storage circuit and a remapping circuit corresponding to the memory circuit, and configured to receive and save the repair signal from the remapping temporary storage circuit, so as to enable the remapping circuit to access the repair signal and perform a repair remapping on the memory circuit according to the repair signal and the redundancy structure when the remapping temporary storage circuit is scanned according to the scan chain.

[0007] The present application also includes a memory test method with a repair signal maintaining mechanism, which comprises: controlling, by a repair control circuit, a memory built-in self-repair circuit to perform a built-in self-repair procedure on a memory circuit with a redundancy structure; storing, by a remapping temporary storage circuit of the repair control circuit, a repair signal generated from the memory built-in self-repair circuit after the built-in self-repair procedure is completed, wherein the remapping temporary storage circuit is disposed in a scan chain; receiving and saving, by a latch temporary storage circuit of the repair control circuit, the repair signal from the remapping temporary storage circuit, wherein the latch temporary storage circuit is electrically coupled between the remapping temporary storage circuit and a remapping circuit corresponding to the memory circuit; and enabling, by the latch temporary storage circuit, the remapping circuit to access the repair signal and perform a repair remapping on the memory circuit according to the repair signal and the redundancy structure when the remapping temporary storage circuit is scanned according to the scan chain.

[0008] The features, implementations and effects of the present application will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A module diagram of a memory device according to an embodiment of the present application;

[0010] Figure 2 A circuit diagram of partial elements included in a repair control circuit according to an embodiment of the present application; and

[0011] Figure 3 A flowchart of a memory test method with a repair signal maintaining mechanism according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] One object of the present application is to provide a memory device and a memory testing circuit and method with a repair signal maintaining mechanism to correctly save repair signals and provide memory circuits with repair, avoiding the situation that the memory circuits cannot be repaired due to the loss of repair signals in scan testing in some technologies, and obtaining incorrect test results.

[0013] Please refer to Figure 1 . Figure 1 A block diagram of a memory device 100 according to an embodiment of the present application is shown. The memory device 100 includes a memory circuit 110 and a memory testing circuit 120.

[0014] In an embodiment, the memory circuit 110 has a redundancy structure. In different embodiments, the redundancy structure can be at least one redundant row, at least one redundant column, or at least one redundant input / output port.

[0015] For example, the memory circuit 110 can be a static random access memory (SRAM) with 8192x64 memory cells and a structure with one redundant input / output port. Therefore, the memory circuit 110 actually has 8192x65 memory cells. It should be noted that the above structure and values are only an example, and the present application is not limited thereto.

[0016] The memory testing circuit 120 is configured to perform built-in self-test and analysis on the memory circuit 110 to feed in test data and read test results, and accordingly generate repair signals RI. In an embodiment, the memory device 100 is provided with a remapping circuit 130 corresponding to the memory circuit 110, which is configured to receive the repair signals RI and perform remapping on the memory circuit 110 to repair the memory circuit 110. In more detail, the remapping circuit 130 can determine whether the bits at specific positions of the memory circuit 110 need to be replaced by the bits in the redundancy structure according to the repair signals RI due to defects.

[0017] It should be noted that in Figure 1 , the remapping circuit 130 shown is in a form independent of the memory circuit 110. In implementation, the remapping circuit 130 can be arranged in the memory circuit 110 to become a part of the memory circuit 110.

[0018] Therefore, when the data of the memory circuit 110 is incorrect due to defective bits, the mechanism for data repair can be implemented according to the repair signals RI and the redundancy structure.

[0019] The memory testing circuit 120 includes a memory built-in self-repair circuit 140 and a repair control circuit 150.

[0020] The memory built-in self-repair circuit 140 includes, for example, but not limited to, a built-in self-test circuit and a built-in self-analysis circuit (not shown). The repair control circuit 150 is configured to control the memory built-in self-repair circuit 140 to feed test data to the memory circuit 110 to perform a built-in self-repair procedure including built-in self-test and analysis.

[0021] Please refer to Figure 2 . Figure 2 A circuit diagram of the repair control circuit 150 according to an embodiment of the present application.

[0022] In an embodiment, the repair control circuit 150 includes a multiplexer 200, a remapping buffer circuit 210 and a latch buffer circuit 220.

[0023] The multiplexer 200 includes a first input terminal IN1, a second input terminal IN2 and an output terminal O. The first input terminal IN1 is electrically coupled to the memory built-in self-repair circuit 140 in the memory system 100, and the second input terminal IN2 and the output terminal O are electrically coupled to the remapping buffer circuit 210. Figure 1

[0024] In an embodiment, the multiplexer 200 is configured to receive a selection signal HR and switch the selected input terminal according to the selection signal HR. The selection signal HR can be generated by, for example, but not limited to, a control circuit (not shown) included in the memory built-in self-repair circuit 140 according to the mode required to be performed by the remapping buffer circuit 210. For example, when the selection signal HR is in a first state, the multiplexer 200 operates in a receiving mode and selects the first input terminal IN1 as the input terminal to receive the signal transmitted by the memory built-in self-repair circuit 140. When the selection signal HR is in a second state, the multiplexer 200 operates in a latching mode and selects the second input terminal IN2 as the input terminal to receive the signal buffered by the remapping buffer circuit 210, so that the signal buffered by the remapping buffer circuit 210 is maintained by the loop formed by the remapping buffer circuit 210 and the multiplexer 200.

[0025] The remapping buffer circuit 210 is configured to buffer the repair signal RI generated by the memory built-in self-repair circuit 140 after the completion of the built-in self-repair procedure.

[0026] In detail, after the completion of the built-in self-repair procedure, the multiplexer 200 will operate in the receiving mode according to the selection signal HR in the first state, select the first input terminal IN1 as the input terminal, receive the repair signal RI generated by the memory built-in self-repair circuit 140, and transmit the repair signal RI to the remapping buffer circuit 210 through the output terminal O for buffering.

[0027] ​In one embodiment, the remapping latch circuit 210 includes a latch input terminal DL and a latch output terminal QL. The latch input terminal DL is electrically coupled to the output terminal O of the multiplexer 200 to receive the repair signal RI. The latch output terminal QL is electrically coupled to the second input terminal IN2 of the multiplexer 200 and the latch remapping circuit 220 to output the repair signal RI. It is noted that the remapping latch circuit 210 can include more terminals, such as a clock signal terminal CLK, a serial input terminal SI, a scan enable terminal SE, and the like, to receive corresponding signals and perform corresponding functions.

[0028] In addition to being disposed in the repair control circuit 150, the remapping latch circuit 210 is also located on a scan chain (not shown) in an electronic system associated with the memory device 100, where the scan chain includes a plurality of shift latches connected in series. When the electronic system performs a scan test on the memory circuit 110, the remapping latch circuit 210 can operate with other shift latches on the scan chain to shift test data fed into the scan chain, thereby achieving the purpose of the scan test.

[0029] The latch remapping circuit 220 is electrically coupled to the latch output terminal QL of the remapping latch circuit 210 and the repair circuit 130 to receive and store the repair signal RI from the remapping latch circuit 210, so that the repair circuit 130 can access the repair signal RI and remap the memory circuit 110 according to the repair signal RI and the redundancy structure when the remapping latch circuit 210 performs a scan test according to the scan chain. Figure 1 In one embodiment, the latch remapping circuit 220 includes a latch input terminal DL, a latch output terminal QL, and a control terminal GL. The latch input terminal DL is electrically coupled to the latch output terminal QL of the remapping latch circuit 210, the latch output terminal QL is electrically coupled to the repair circuit 130, and the control terminal GL is configured to receive a mode control signal MC. The mode control signal MC can be a signal related to the aforementioned scan test, and the memory test circuit 120 mainly operates in a non-scan test mode. After the memory test circuit 120 obtains the repair signal RI, the memory test circuit 120 switches to the scan test mode. Generally, the scan test and the memory test can be independent tests, so the control of the mode control signal MC can be transmitted by, for example, but not limited to, a register or a pad outside the memory test circuit 120, to control the mode required to be executed by the remapping latch circuit 210.

[0030] Figure 1

[0031] ​​In one embodiment, the latch register 220 is configured to operate in a pass-through mode before the completion of the built-in self-repair procedure according to the mode control signal MC, and to become a bypass state. Also, the latch register 220 is configured to operate in a save mode after the completion of the built-in self-repair procedure, to receive and save the repair signal RI from the remapping register 210.

[0032] In one embodiment, the latch register 220 receives the mode control signal MC through the inverter 230 to operate in the pass-through mode when the mode control signal MC is in the first state, and to operate in the save mode when the mode control signal MC is in the second state. However, the present application is not limited thereto.

[0033] After saving the repair signal RI, the latch register 220 is configured to allow the remapping circuit 130 to access the repair signal RI, so as to remap and repair the memory circuit 110 according to the scan chain, for example, but not limited to, when the remapping register 210 receives the automatic test pattern generation (ATPG) test data for scan testing through the input terminal SE. Figure 1

[0034] In some technologies, when the electronic system in which the memory device 100 is located performs scan testing, for example, but not limited to, delay fault scan testing, the remapping register 210 will be located in the scan chain, so that the content of the register will be shifted to other shift registers in the scan chain, and the repair signal RI cannot be maintained. In this case, the memory circuit 110 will not be able to complete the repair according to the repair signal RI, so that the read result of the scan testing will be read in the un-repaired state, resulting in errors in the defective bits.

[0035] The memory device 100 of the present application can first perform built-in self-test and analysis on the memory circuit 110 by the memory test circuit 120 to generate the repair signal RI, and then transmit the repair signal RI to the latch register 220 for saving after being received by the remapping register 210. The remapping register 210 located in the scan chain can continue to perform scan testing, and the repair signal RI provided by the latch register 220 can be used to repair the memory circuit 110. Therefore, the scan testing related to the memory circuit 110 can obtain correct test results.

[0036] Please refer to Figure 3 . Figure 3 A flowchart of a memory testing method 300 with a repair signal maintaining mechanism according to one embodiment of the present application is shown.

[0037] ​In addition to the aforementioned device, the present application also discloses a memory testing method 300 with a repair signal maintaining mechanism, which is applied to, for example, but not limited to Figure 1 the memory testing circuit 120. An embodiment of the memory testing method 300, as shown in Figure 3 FIG. 3, includes the following steps:

[0038] Step S310, the memory built-in self-repair circuit 140 is controlled by the repair control circuit 150 to test the memory circuit 110 with a redundancy structure, and to perform a built-in self-repair procedure according to the redundancy structure.

[0039] Step S320, the remapping temporary storage circuit 210 of the repair control circuit 150 receives and temporarily stores the repair signal RI generated from the memory built-in self-repair circuit 140 through the temporary storage input terminal DR after the built-in self-repair procedure is completed, wherein the remapping temporary storage circuit 210 is arranged in a scan chain.

[0040] Step S330, the repair signal RI is received and saved by the latch temporary storage circuit 220 in the repair control circuit 150 from the remapping temporary storage circuit 210.

[0041] Step S340, the remapping circuit 130 is accessed by the latch temporary storage circuit 220 to remap and repair the memory circuit 110 according to the repair signal RI when the remapping temporary storage circuit 210 is scanned according to the scan chain.

[0042] It is noted that the above-mentioned embodiment is only an example. In other embodiments, those skilled in the art can make changes and modifications without departing from the spirit of the present application.

[0043] In summary, the memory device and the memory testing circuit and method with a repair signal maintaining mechanism of the present application can correctly save the repair signal and provide the memory circuit for repair, thereby avoiding the loss of the repair signal in the scan test to cause the memory circuit to be unable to repair and to obtain an incorrect test result in some technologies.

[0044] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the content explicitly or implicitly disclosed in the present application, and these changes can all fall within the scope of the patent protection required by the present application. In other words, the scope of the patent protection of the present application should be based on the definition in the claims of the present application.

[0045] Legend of reference signs:

[0046] 100: memory device

[0047] 110: memory circuit

[0048] 120: memory test circuit

[0049] 130: remapping circuit

[0050] 140: memory built-in self-repair circuit

[0051] 150: repair control circuit

[0052] 200: multiplexer

[0053] 210: remapping temporary storage circuit

[0054] 220: latch temporary storage circuit

[0055] 230: inverter

[0056] 300: memory test method

[0057] S310-S340: steps

[0058] CLK, SI, SE: input terminals

[0059] DL: latch input terminal

[0060] DR: temporary storage input terminal

[0061] GL: control terminal

[0062] HR: selection signal

[0063] IN1: first input terminal

[0064] IN2: second input terminal

[0065] MC: mode control signal

[0066] O: output terminal

[0067] QR: temporary storage output terminal

[0068] QL: latch output terminal

[0069] RI: repair signal

Claims

1. A memory test circuit with repair signal maintenance mechanism, comprising: a memory built-in self-repair circuit; and a repair control circuit configured to control the memory built-in self-repair circuit to perform a built-in self-repair procedure on a memory circuit with a redundancy structure, and comprising: a remapping temporary storage circuit disposed in a scan chain and configured to receive and temporarily store a repair signal generated from the memory built-in self-repair circuit after the built-in self-repair procedure is completed; and a latch temporary storage circuit electrically coupled between the remapping temporary storage circuit and a remapping circuit corresponding to the memory circuit and configured to receive and save the repair signal from the remapping temporary storage circuit, so that the remapping circuit accesses the repair signal and remaps the memory circuit according to the repair signal and the redundancy structure when the remapping temporary storage circuit performs a scan test according to the scan chain. The repair control circuit further comprises a multiplexer comprising a first input, a second input and an output, the first input is electrically coupled to the memory built-in self-repair circuit to receive the repair signal, the second input and the output are electrically coupled to the remapping temporary storage circuit, wherein the multiplexer is configured to receive a selection signal and select the first input to receive the repair signal from the memory built-in self-repair circuit in a receiving mode and select the second input to receive the repair signal temporarily stored by the remapping temporary storage circuit in a latching mode.

2. The memory test circuit of claim 1, wherein, The latch temporary storage circuit is configured to receive a mode control signal and operate in a pass-through mode before the built-in self-repair procedure is completed and operate in a saving mode after the built-in self-repair procedure is completed to receive and save the repair signal from the remapping temporary storage circuit.

3. The memory test circuit of claim 1, wherein, 4. A memory device, comprising: a memory circuit with a redundancy structure; and a memory test circuit, comprising: a memory built-in self-repair circuit; a repair control circuit configured to control the memory built-in self-repair circuit to perform a built-in self-repair procedure on the memory circuit, and comprising: a remapping temporary storage circuit disposed in a scan chain and configured to receive and temporarily store a repair signal generated from the memory built-in self-repair circuit after the built-in self-repair procedure is completed; and a latch temporary storage circuit electrically coupled between the remapping temporary storage circuit and a remapping circuit corresponding to the memory circuit and configured to receive and save the repair signal from the remapping temporary storage circuit, so that the remapping circuit accesses the repair signal and remaps the memory circuit according to the repair signal and the redundancy structure when the remapping temporary storage circuit performs a scan test according to the scan chain. The redundancy structure of the memory circuit is at least one redundant column, at least one redundant row or at least one redundant input / output port. ​ 5. The memory device of claim 4, wherein, ​ 6. The memory device of claim 4, wherein, The repair control circuit further includes a multiplexer including a first input electrically coupled to the memory built-in self-repair circuit to receive the repair signal, a second input and an output electrically coupled to the remapping temporary circuit, wherein the multiplexer is configured to receive a selection signal and select the first input to receive the repair signal from the memory built-in self-repair circuit in a receive mode and select the second input to receive the repair signal temporarily stored by the remapping temporary circuit in a latch mode.

7. The memory device of claim 4, wherein, The latch temporary circuit is configured to receive a mode control signal and operate in a pass-through mode before the built-in self-repair procedure is completed and operate in a save mode after the built-in self-repair procedure is completed to receive and save the repair signal from the remapping temporary circuit.

8. A memory testing method having a repair signal maintaining mechanism, comprising: controlling, by a repair control circuit, a memory built-in self-repair circuit to perform a built-in self-repair procedure on a memory circuit having a redundancy structure; temporarily storing, by a remapping temporary circuit of the repair control circuit, a repair signal generated from the memory built-in self-repair circuit after the built-in self-repair procedure is completed, wherein the remapping temporary circuit is disposed in a scan chain; receiving and saving, by a latch temporary circuit of the repair control circuit, the repair signal from the remapping temporary circuit, wherein the latch temporary circuit is electrically coupled between the remapping temporary circuit and a remapping circuit; and enabling, by the latch temporary circuit, the remapping circuit corresponding to the memory circuit to access the repair signal and to remap the memory circuit according to the repair signal and the redundancy structure when the remapping temporary circuit is performing a scan test according to the scan chain.

9. The memory test method of claim 8, wherein, The repair control circuit further includes a multiplexer including a first input electrically coupled to the memory built-in self-repair circuit to receive the repair signal, a second input and an output electrically coupled to the remapping temporary circuit, wherein the multiplexer is configured to receive a selection signal and select the first input to receive the repair signal from the memory built-in self-repair circuit in a receive mode and select the second input to receive the repair signal temporarily stored by the remapping temporary circuit in a latch mode. The latch temporary circuit is configured to receive a mode control signal and operate in a pass-through mode before the built-in self-repair procedure is completed and operate in a save mode after the built-in self-repair procedure is completed to receive and save the repair signal from the remapping temporary circuit.

10. The memory testing method of claim 8, wherein, ​ ​

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