Semiconductor Structure and Method of Manufacturing the Same

Abstract

Embodiments of the present application disclose a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate; a first metal layer located on the surface of the semiconductor substrate; a second metal layer located above the surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer for isolating the first metal layer and the second metal layer; at least four through holes located in the insulating layer, and the at least four through holes are filled with a conductive material for connecting the first metal layer and the second metal layer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor manufacturing technologies, including but not limited to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] For semiconductor devices such as memories and chips, a multi-layer structure is usually adopted on a semiconductor substrate. Electrical connections between layers on the surface of the semiconductor substrate are realized by metal wires, and metal wires of different layers are connected through vias. The resistance value of the via is an important parameter affecting the connection performance. Therefore, test units (Test-key) are usually formed during the manufacturing process for resistance testing of the vias.

[0003] However, the test unit is located on the periphery of the device, and there are no other patterns around it, which easily causes deformation of the vias, resulting in the test results being difficult to reflect the actual resistance value of the vias inside the device. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof to solve at least one problem existing in the prior art.

[0005] In a first aspect, the semiconductor structure provided by embodiments of the present application includes:

[0006] A semiconductor substrate;

[0007] A first metal layer located on the surface of the semiconductor substrate;

[0008] A second metal layer located above the surface of the first metal layer;

[0009] An insulating layer located between the first metal layer and the second metal layer for isolating the first metal layer and the second metal layer;

[0010] At least four vias located in the insulating layer, and the at least four vias have a conductive material for connecting the first metal layer and the second metal layer.

[0011] In some embodiments, the first metal layer includes: a plurality of bottom metal wires parallelly distributed along a first direction;

[0012] The second metal layer includes: a plurality of top metal wires parallelly distributed along a second direction; wherein, the second direction is perpendicular to the first direction.

[0013] In some embodiments, the at least four vias are located at the overlapping positions of at least two of the bottom metal wires in the first metal layer and at least two of the top metal wires in the second metal layer.

[0014] In some embodiments, the at least four through-holes include four test through-holes; wherein, the four test through-holes are respectively located at four overlapping positions of two top metal lines and two bottom metal lines.

[0015] In some embodiments, there is a spaced top metal line between the two top metal lines connected to the test through-holes; and there is a spaced bottom metal line between the two bottom metal lines connected to the test through-holes.

[0016] In some embodiments, the at least four through-holes further include at least a pair of auxiliary through-holes, wherein the at least a pair of auxiliary through-holes are connected to the spaced top metal line or the spaced bottom metal line, and the distance between a pair of the auxiliary through-holes is greater than the distance between any two of the test through-holes.

[0017] In some embodiments, the two top metal lines connected to the test through-holes are connected through a test pad; the two bottom metal lines connected to the test through-holes are connected through a test pad.

[0018] In some embodiments, the semiconductor structure further includes:

[0019] At least two dummy through-holes, the dummy through-holes penetrate through the insulating layer and are connected to any one of the first metal layer or the second metal layer; the distribution positions of the at least two dummy through-holes and the at least four through-holes form a centrosymmetric or axisymmetric figure.

[0020] In some embodiments, the dummy through-holes are filled with an insulating material.

[0021] In some embodiments, the at least four through-holes are used for resistance testing by the Kelvin four-wire detection method.

[0022] In a second aspect, an embodiment of the present application provides a manufacturing method of a semiconductor structure, including:

[0023] Form a first metal layer on the surface of a semiconductor substrate;

[0024] Cover an insulating layer on the first metal layer;

[0025] Form at least four through-holes that penetrate through the insulating layer and are connected to the first metal layer;

[0026] Fill a conductive material in the at least four through-holes;

[0027] Form a second metal layer on the insulating layer and the at least four through-holes;

[0028] The conductive material in the at least four through-holes is used to connect the first metal layer and the second metal layer.

[0029] In some embodiments, forming the first metal layer on the surface of the semiconductor substrate includes:

[0030] Forming a plurality of underlying metal lines parallelly distributed along a first direction on the semiconductor surface;

[0031] Forming the second metal layer on the insulating layer and the at least four through-holes includes:

[0032] Forming a plurality of top metal lines parallelly distributed along a second direction on the insulating layer and the at least four through-holes; wherein, the second direction is perpendicular to the first direction.

[0033] In some embodiments, forming the at least four through-holes penetrating the insulating layer and connecting the first metal layer includes:

[0034] Forming four test through-holes penetrating the insulating layer and connecting the underlying metal lines at four target positions of two of the underlying metal lines; each of the underlying metal lines includes two target positions distributed along the second direction, and the adjacent two target positions of the two underlying metal lines are distributed along the first direction;

[0035] Forming a plurality of top metal lines parallelly distributed along a second direction on the insulating layer and the at least four through-holes includes:

[0036] Forming top metal lines above two target positions distributed along the first direction, where the target positions are the overlapping positions of two of the top metal lines and two of the underlying metal lines.

[0037] In some embodiments, forming the at least four through-holes penetrating the insulating layer and connecting the first metal layer further includes:

[0038] Forming at least a pair of auxiliary through-holes penetrating the insulating layer and respectively connecting different underlying metal lines on one of the top metal lines between two of the top metal lines, wherein the distance between the pair of auxiliary through-holes is greater than the distance between any two of the test through-holes.

[0039] In some embodiments, the method further includes:

[0040] Forming at least two dummy through-holes, the dummy through-holes penetrating the insulating layer and connecting any one of the first metal layer or the second metal layer; the distribution positions of the at least two dummy through-holes and the at least four through-holes form a centrosymmetric or axisymmetric figure.

[0041] In some embodiments, the method further includes:

[0042] Filling insulating materials in the at least two dummy through-holes.

[0043] In some embodiments, the dummy vias are connected to the first metal layer, and the method further includes:

[0044] Forming a covering layer that fills between the top metal lines and covers the dummy vias.

[0045] Through the technical solution of the embodiments of the present application, at least four vias are used to connect the first metal layer and the second metal layer. On the one hand, there are other structures such as vias around each via to provide support, which can reduce the situation of inaccurate testing caused by via deformation; on the other hand, multiple vias also facilitate flexible testing, making the test results closer to the actual resistance value of the vias inside the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of a semiconductor structure provided by an embodiment of the present application Figure 1 ;

[0047] Figure 2 Schematic diagram of a semiconductor structure in one embodiment;

[0048] Figure 3 Schematic diagram of a semiconductor structure provided by an embodiment of the present application Figure 2 ;

[0049] Figure 4 Schematic diagram of a semiconductor structure provided by an embodiment of the present application Figure 3 ;

[0050] Figure 5A Schematic diagram of the first metal layer in a semiconductor structure provided by an embodiment of the present application;

[0051] Figure 5B Schematic diagram of the first metal layer in a semiconductor structure in one embodiment;

[0052] Figure 6 Schematic diagram of a semiconductor structure provided by an embodiment of the present application Figure 4 ;

[0053] Figure 7 Flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present application;

[0054] Figure 8A Schematic diagram of simultaneously forming multiple vias in a manufacturing method of a semiconductor structure provided by an embodiment of the present application;

[0055] Figure 8B Schematic diagram of forming one via in one embodiment;

[0056] Figure 9Schematic diagram of a semiconductor structure in an embodiment;

[0057] Figure 10 Schematic diagram five of a semiconductor structure provided by an embodiment of the present application;

[0058] Figure 11 Cross-sectional view of the position of dummy vias in a semiconductor structure provided by an embodiment of the present application. Detailed implementation manners

[0059] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0061] An embodiment of the present application provides a semiconductor structure, as Figure 1 shown, the semiconductor structure 100 includes:

[0062] A semiconductor substrate 110;

[0063] A first metal layer 120, located on the surface of the semiconductor substrate 110;

[0064] A second metal layer 130, located above the surface of the first metal layer 120;

[0065] An insulating layer 140, located between the first metal layer 120 and the second metal layer 130, for isolating the first metal layer 120 and the second metal layer 130;

[0066] At least four vias 150, located in the insulating layer 140, and the at least four vias 150 are filled with a conductive material for connecting the first metal layer 120 and the second metal layer 130.

[0067] In the embodiments of the present application, the above semiconductor structure may be a test structure for testing located around a semiconductor device, or is also referred to as a test unit. This semiconductor structure can be formed synchronously with semiconductor devices during the process of fabricating various semiconductor devices (such as memories, chips, etc.) using a wafer. Since this semiconductor structure is separated from the semiconductor device, it does not affect the performance of the semiconductor device.

[0068] This semiconductor structure can be used for testing during the manufacturing process of semiconductor devices, thereby realizing the process monitoring of semiconductor devices. When the manufacturing of semiconductor devices is completed, the area where the above semiconductor structure is located can be cut off, and only the semiconductor devices are retained and packaged separately. Of course, the above semiconductor structure can also be retained and packaged together with the semiconductor device, so as to facilitate the testing of the product.

[0069] The above first metal layer and second metal layer are metal layers formed synchronously with different metal layers in the semiconductor device. Both the first metal layer and the second metal layer can have patterns formed by etching or the like, for example, linear or mesh-shaped. The first metal layer and the second metal layer are isolated from each other by an insulating layer, and the insulating layer can be made of insulating materials such as silicon oxide or silicon nitride.

[0070] The first metal layer and the second metal layer can be connected to each other through through-holes. The through-holes penetrate the insulating layer and are connected to the first metal layer and the second metal layer. The through-holes can have conductive materials such as metal, and the electrical connection between the first metal layer and the second metal layer is realized through the conductive materials.

[0071] In the embodiments of the present application, the number of through-holes is at least four. These through-holes can be distributed at intervals in different positions and are respectively connected to the first metal layer and the second metal layer.

[0072] Since there are multiple through-holes in the entire semiconductor structure, therefore, compared with the test structure in the semiconductor structure 200 shown in Figure 2 which has only one through-hole 201, each through-hole in the embodiments of the present application has the support of other through-hole and other structures nearby. In this way, on the one hand, the situation where inaccurate testing is caused by through-hole deformation can be reduced; on the other hand, multiple through-holes are also convenient for flexible testing, making the test results closer to the actual resistance value of the through-holes inside the device.

[0073] In some embodiments, the first metal layer includes: a plurality of bottom metal lines parallelly distributed along a first direction;

[0074] The second metal layer includes: a plurality of top metal lines parallelly distributed along a second direction; wherein, the second direction is perpendicular to the first direction.

[0075] In an embodiment of the present application, the first metal layer may be a linear metal wire and may include a plurality of metal wires distributed side by side. Since the first metal layer is the metal layer close to the substrate surface, these metal wires may be referred to as bottom metal wires. Here, the plurality of bottom metal wires may be all parallelly distributed along a first direction, and the first direction may be any direction parallel to the substrate surface, and may be subject to a manner that is convenient to implement in the actual manufacturing process.

[0076] In an embodiment of the present application, the second metal layer may be a plurality of parallelly distributed metal wires similar in structure to the first metal layer. Relative to the first metal layer, the second metal layer is far from the substrate surface, so it may be referred to as top metal wires. The plurality of top metal wires are parallelly distributed along a second direction. The second direction may be perpendicular to the first direction, so that the structure can be more stable.

[0077] In some embodiments, as Figure 3 shown, the at least four vias 150 are located at the overlapping positions of at least two of the bottom metal wires 121 in the first metal layer 120 and at least two of the top metal wires 131 in the second metal layer 130.

[0078] The metal wires of the above-mentioned first metal layer and the second metal layer are perpendicular to each other. Therefore, each of the bottom metal wires of the first metal layer and each of the top metal wires of the second metal layer respectively have overlapping positions. These overlapping positions are on the same straight line in the direction perpendicular to the substrate surface. Therefore, the at least four vias can be formed at these overlapping positions, so as to realize the connection between the first metal layer and the second metal layer.

[0079] Since both the first metal layer and the second metal layer have a plurality of metal wires, there can be a plurality of overlapping positions. Each overlapping position can form a via, and the plurality of vias can be respectively located at different overlapping positions.

[0080] In some embodiments, the at least four vias include four test vias; wherein, the four test vias are respectively located at the four overlapping positions of two top metal wires and two bottom metal wires.

[0081] In an embodiment of the present application, the above-mentioned semiconductor structure may include four test vias, and these test vias are used for resistance testing. Therefore, the metal wires where these test vias are located can be connected to an external test circuit. Of course, during testing, it is also possible to use a probe to directly contact the via position or the metal wire for testing.

[0082] Four test vias can be located at the four overlapping positions of two top metal lines and two bottom metal lines. Since two vias are connected to each metal line, and these two vias are connected to different metal lines on another layer, in this way, the four test vias can connect different combinations of these four metal lines. During testing, four groups of test data can be obtained, facilitating sufficient data processing and improving the reliability of the test.

[0083] In some embodiments, there is a spaced top metal line between the two top metal lines connected with the test vias; and there is a spaced bottom metal line between the two bottom metal lines connected with the test vias.

[0084] The two top metal lines and the two bottom metal lines connected with the test vias can both not be two adjacent top metal lines side by side, that is, there can be one or more top metal lines between the two top metal lines connected with the test vias. Here, there is a spaced metal line between the two top metal lines and the two bottom metal lines connected with the test vias respectively.

[0085] In this way, on the one hand, it can make there be a certain distance between the test vias, improving the stability of the overall structure, and on the other hand, it can reduce the interference between the vias during testing.

[0086] In some embodiments, as Figure 4 shown, among the at least four vias, there are also at least a pair of auxiliary vias 151 and at least four test vias 152. Among them, the at least a pair of auxiliary vias 151 are connected to the spaced top metal line 131 or the spaced bottom metal line 121, and the distance between a pair of the auxiliary vias 151 is greater than the distance between any two of the test vias 152.

[0087] In some embodiments, auxiliary vias can be arranged at the center of the semiconductor structure.

[0088] The distances between the above four vias can be equal to each other in pairs, thus having a stable structure and being convenient for testing. In addition, there are also spaced metal lines between the metal lines where the vias are located. Therefore, auxiliary vias can be formed on the spaced metal lines to facilitate auxiliary testing. The auxiliary vias appear in pairs and are connected to the same top metal line or bottom metal line. The distance between the auxiliary vias can be greater than the distance between the above test vias, so as not to affect the test vias.

[0089] In some embodiments, the two top metal lines connected with the test vias are connected through test pads; the two bottom metal lines connected with the test vias are connected through test pads.

[0090] That is to say, the top metal lines for testing via connections are interconnected through test pads, and the bottom metal lines are also connected through test pads (as Figure 5A shown, test pad 501 connects two bottom metal lines 502), enabling the test vias to be interconnected through the respective metal lines. In this way, the resistance can be tested through an external set of test paths. Since the test vias are interconnected with each other, the average resistance value of each via can be calculated from the test data obtained. Compared with the case where, as Figure 5B shown, test pad 503 only connects one bottom metal line 504, the resistance values of the vias in the semiconductor device can be estimated more accurately, thereby determining whether the device may fail.

[0091] It should be noted that the metal lines connected to the auxiliary vias are not connected to the metal lines connected to the test vias, so they can be tested separately. In this way, auxiliary test data can be provided during the test, facilitating the verification of the test reliability.

[0092] In some embodiments, as Figure 6 shown, the semiconductor structure 100 further includes:

[0093] At least two dummy vias 160 that penetrate the insulating layer and are connected to either the first metal layer 120 or the second metal layer 130; the distribution positions of the at least two dummy vias 160 and the at least four vias 150 form a centrosymmetric or axisymmetric figure.

[0094] In the embodiments of the present application, a dummy via is a via that has a similar structure to a test via or an auxiliary via and penetrates the insulating layer. The dummy via may also contain conductive materials such as metal, but it does not function to connect the first metal layer and the second metal layer. That is to say, the dummy via can be connected to only the first metal layer or only the second metal layer.

[0095] The dummy vias can be used to support the entire semiconductor structure. For example, the positional distribution of the dummy vias and other vias can be centrosymmetric or axisymmetric, making the semiconductor structure more stable. In addition, the dummy vias can also jointly form a structure that simulates the actual vias in the semiconductor device with the test vias and auxiliary vias, making the test data of the test vias closer to the data of the actual vias in the semiconductor device.

[0096] In some embodiments, the test vias form a first axisymmetric distribution with the center line of the semiconductor structure as the axis, and the distances from the test vias of the first axisymmetric distribution to the center of the semiconductor structure may be different. The auxiliary vias and dummy vias together form a second axisymmetric distribution with the center line of the semiconductor structure as the axis, and the distances from the vias of the second axisymmetric distribution to the center of the semiconductor structure may be different. The ratio of the distance between any two test vias in the first axisymmetric distribution to the distance from any test via to the center of the semiconductor structure ranges from 1.5 to 3. The ratio of the distance from the vias in the second axisymmetric distribution to the center of the semiconductor structure to the distance from the vias in the first axisymmetric distribution to the center of the semiconductor structure is greater than 3.

[0097] In some embodiments, the test vias form a first centrosymmetric distribution centered on the center of the semiconductor structure, and the distances from the test vias of the first centrosymmetric distribution to the center of the semiconductor structure are the same. The auxiliary vias and dummy vias together form a second centrosymmetric distribution centered on the center of the semiconductor structure, and the distances from the vias of the second centrosymmetric distribution to the center of the semiconductor structure are the same.

[0098] In some embodiments, the dummy vias are filled with an insulating material.

[0099] In this way, the dummy vias can play a supporting role, prevent other vias from deforming, and prevent the dummy vias from causing electrical interference to the first metal layer, the second metal layer or other vias.

[0100] In some embodiments, the at least four vias are used for resistance testing by the Kelvin four-wire detection method.

[0101] The Kelvin four-wire detection method is also known as four-terminal detection or four-point probe method. This method can eliminate the impedance of wiring and contact resistance by separating the current and voltage electrodes, thereby achieving accurate resistance testing. In the embodiments of the present application, the metal wires connected to the above at least four vias can be respectively connected to different detection ends to achieve four-wire detection. Compared with the single-point testing method, the accuracy of detection can be improved.

[0102] As Figure 7 shown, the embodiments of the present application also provide a manufacturing method of a semiconductor structure, including:

[0103] Step S101, forming a first metal layer on the surface of the semiconductor substrate;

[0104] Step S102, covering an insulating layer on the first metal layer;

[0105] Step S103, forming at least four vias penetrating the insulating layer and connecting the first metal layer;

[0106] Step S104: Fill the at least four through-holes with a conductive material;

[0107] Step S105: Form a second metal layer on the insulating layer and the at least four through-holes; the conductive material in the at least four through-holes is used to connect the first metal layer and the second metal layer.

[0108] Since the above semiconductor structure can be a test structure for testing located around a semiconductor device, the manufacturing process of this semiconductor structure is carried out synchronously during the process of manufacturing a semiconductor device product. The above first metal layer, second metal layer, and insulating layer are all formed corresponding to and synchronously with the respective layers in the semiconductor device.

[0109] The above at least four through-holes are also carried out synchronously with the process of forming through-holes in the semiconductor device. As Figure 8A shown, after the first metal layer 801 is formed and covers the insulating layer (not shown in the figure), a plurality of through-holes 802 are synchronously formed at a plurality of target positions, and then subsequent related processes such as the second metal layer are carried out. Compared with the method of forming only one through-hole 812 on the first metal layer 811 as Figure 8B shown, it can make the whole structure more stable and closer to the structure of an actual semiconductor device, so that the quality of the entire manufacturing process can be reflected by these through-holes.

[0110] In some embodiments, forming the first metal layer on the surface of the semiconductor substrate includes:

[0111] Forming a plurality of bottom metal lines parallelly distributed along a first direction on the semiconductor surface;

[0112] Forming the second metal layer on the insulating layer and the at least four through-holes includes:

[0113] Forming a plurality of top metal lines parallelly distributed along a second direction on the insulating layer and the at least four through-holes; wherein, the second direction is perpendicular to the first direction.

[0114] Here, a metal layer can be first formed on the surface of the semiconductor substrate, and then a plurality of metal lines can be formed by means of patterning etching; alternatively, a patterned mask layer can be first formed on the semiconductor substrate, and then metal is deposited in the areas not covered by the mask layer to form a plurality of metal lines, and then the mask layer is removed, so as to form a first metal layer with a plurality of bottom metal lines.

[0115] After forming the first metal layer, an insulating material can be deposited thereon to form an isolation layer.

[0116] In some embodiments, forming the at least four through-holes penetrating the insulating layer and connecting the first metal layer includes:

[0117] At four target positions of the two underlying metal lines, four test vias are formed through the insulating layer and connected to the underlying metal lines; each of the underlying metal lines includes two target positions distributed along the second direction, and the adjacent two target positions of the two underlying metal lines are distributed along the first direction;

[0118] On the insulating layer and the at least four vias, a plurality of top metal lines parallel to each other along the second direction are formed, including:

[0119] Top metal lines are formed above the two target positions distributed along the first direction, and the target positions are the overlapping positions of the two top metal lines and the two underlying metal lines.

[0120] After forming the insulating layer, the insulating layer can be perforated at the target positions by etching or other methods to form the above four test vias, and the depth of the vias is the thickness of the insulating layer. Through the vias penetrating the insulating layer, the surface of the insulating layer can be connected to the underlying metal lines. Then, a conductive material such as a metal dock, copper, or other compound conductive material can be filled in the vias or coated on the inner walls of the vias. The conductive material is connected to the underlying metal lines through the vias and is connected to the top of the insulating layer.

[0121] The above top metal lines can be continuously formed on the top of the insulating layer. The top metal lines and the underlying metal lines are perpendicularly distributed to each other, so there is an overlapping position between each metal line on the top and the bottom. The above test vias can penetrate the insulating layer at the overlapping position, so as to connect the top metal layer and the underlying metal layer.

[0122] In some embodiments, forming at least four vias through the insulating layer and connected to the first metal layer further includes:

[0123] At least a pair of auxiliary vias are formed through the insulating layer and respectively connected to different underlying metal lines in one top metal line between the two top metal lines, wherein the distance between the pair of auxiliary vias is greater than the distance between any two of the test vias.

[0124] In the embodiments of the present application, before forming the top metal lines, auxiliary vias can also be formed at the corresponding positions of one top metal line between the corresponding positions of the top metal lines where the above test vias are located (not yet formed at this time) and connected to the underlying metal lines. The underlying metal lines connected by the auxiliary vias are also located between the two underlying metal lines connected by the above test vias, and the underlying metal lines connected by the auxiliary vias are not connected to other underlying metal lines. Therefore, the auxiliary vias can be used for separate testing to provide data for auxiliary judgment of the resistance value of the vias.

[0125] After forming the above-mentioned test vias and auxiliary vias, a top metal wire can be formed on the insulating layer, and the top metal wire can be connected to the test vias and the auxiliary vias respectively.

[0126] In some embodiments, the method further includes:

[0127] Forming at least two dummy vias that penetrate the insulating layer and connect to either the first metal layer or the second metal layer; the distribution positions of the at least two dummy vias and the at least four vias form a figure that is centrosymmetric or axially symmetric.

[0128] In the embodiments of the present application, after forming the insulating layer and before forming the top metal wire, dummy vias that penetrate the insulating layer can also be formed. The position where the dummy vias are located is not the overlapping position of the bottom metal wire and the top metal wire. That is to say, one end of the dummy via can be connected to the bottom metal wire, but the other end will not be connected to the top metal wire, or one end of the dummy via can be connected to the top metal wire, but the other end will not be connected to the bottom metal wire. Therefore, the top metal wire and the bottom metal wire will not be electrically connected.

[0129] In some embodiments, the method further includes:

[0130] Filling an insulating material in the at least two dummy vias.

[0131] The dummy vias can be used to provide support, enabling the entire semiconductor structure to simulate the structure inside a semiconductor device, reducing the probability of deformation of the test vias, and thus improving the test performance of the test vias. Since the dummy vias do not need to achieve electrical connection, an insulating material can be filled inside the dummy vias. The type of the insulating material can be materials such as silicon oxide, silicon nitride, or other organic materials.

[0132] In some embodiments, when the dummy vias are connected to the first metal layer, the method further includes:

[0133] Forming a cover layer that fills between the top metal wires and covers the dummy vias.

[0134] One end of the above-mentioned dummy via can be connected to the first metal layer, that is, connected to at least one bottom metal wire, and penetrates the insulating layer. The other end of the dummy via is exposed at the top of the insulating layer and is located between the top metal wires.

[0135] In the embodiments of the present application, a cover layer can be formed after the second metal layer is formed to cover the dummy vias exposed at the top of the insulating layer and fill between the top metal wires of the second metal layer, so that the top metal wires are isolated from each other through the cover layer.

[0136] The material of the covering layer is an insulating material, which can be silicon oxide, silicon nitride or other organic material, etc.

[0137] The embodiments of the present application also provide the following examples:

[0138] For the back-end-of-line (BEOL) processes of MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices and other devices, each layer of metal is connected through vias. The traditional ISO Test-key (Isolation Test-key) generally tests the resistance value of a single via.

[0139] As Figure 9 shown, the test structure of a single via includes a bottom metal line 901, a top metal line 902, and a test via 903 located at the overlapping position of these two metal lines and connecting these two metal lines. The via of this structure is easily affected by the surrounding isolation layer, resulting in unstable lithography process. Moreover, there is no other pattern around a single test via, and the test via is easily deformed during the subsequent process of planarizing the metal layer and other processes, making it impossible to conduct tests. In addition, the probability of error in the resistance value of a single test via is high, and it cannot accurately reflect the actual resistance value of the via in the device.

[0140] In the embodiments of the present application, a via structure in the shape of "3×3 plus 2×2" is adopted. As Figure 10 shown, the first metal layer 1010 includes multiple bottom metal lines 1011, and the top metal layer 1020 includes multiple top metal lines 1021. At the four overlapping positions where two bottom metal lines intersect with two top metal lines respectively, four test vias 1030 are provided, and these four test vias connect the bottom metal line and the top metal line. In addition, there is an insulating layer (not shown in the figure) between the first metal layer 1010 and the second metal layer 1020.

[0141] The two bottom metal lines 1011 and the two top metal lines 1021 respectively connected to the four test vias 1030 are connected through test pads 1012 and 1022 respectively, so that the four test vias can be tested synchronously by using the test pads.

[0142] Auxiliary vias 1040 and dummy vias 1050 are also provided outside the four test vias 1030. Among them, the auxiliary vias 1040 can connect two metal lines of the first metal layer 1010 and the second metal layer 1020. The auxiliary vias 1040 can be used for auxiliary testing or for supporting the entire semiconductor structure. In addition, in order to stabilize the entire semiconductor structure, dummy vias 1050 can also be provided. The dummy vias 1050 are connected to the bottom metal layer 1020, penetrate the insulating layer between the first metal layer 1010 and the second metal layer 1020, but are not connected to the top metal lines.

[0143] The dummy vias 1050 and other vias can be used to form a stable and symmetric structure, reducing the possibility of deformation of the test vias. Therefore, the dummy vias 1050 do not need to be conductive, and the dummy vias 1050 can be filled with insulating materials, such as Figure 11 shown.

[0144] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitude of the sequence numbers of the above processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The sequence numbers of the embodiments of the present application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0145] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0146] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0147] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, each functional unit in the embodiments of the present application can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in a unit; the above integrated units can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0149] The above is only the implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A semiconductor substrate; A first metal layer located on the surface of the semiconductor substrate; A second metal layer located above the surface of the first metal layer; An insulating layer located between the first metal layer and the second metal layer for isolating the first metal layer and the second metal layer; At least four through-holes located in the insulating layer, and the at least four through-holes have a conductive material for connecting the first metal layer and the second metal layer; Wherein, the first metal layer includes: a plurality of bottom metal lines parallelly distributed along a first direction; The second metal layer includes: a plurality of top metal lines parallelly distributed along a second direction; wherein, the second direction is perpendicular to the first direction; Wherein, the at least four through-holes include four test through-holes; there is a spaced top metal line between two top metal lines connected to the test through-holes; and there is a spaced bottom metal line between two bottom metal lines connected to the test through-holes; The at least four through-holes further include at least a pair of auxiliary through-holes, wherein, the at least a pair of auxiliary through-holes are connected to the spaced top metal line or the spaced bottom metal line, and the distance between a pair of the auxiliary through-holes is greater than the distance between any two of the test through-holes.

2. The semiconductor structure according to claim 1, wherein The at least four through-holes are located at the overlapping positions of at least two of the bottom metal lines in the first metal layer and at least two of the top metal lines in the second metal layer.

3. The semiconductor structure according to claim 2, wherein, The four test through-holes are respectively located at the four overlapping positions of two top metal lines and two bottom metal lines.

4. The semiconductor structure according to claim 3, characterized in that, The two top metal lines connected to the test through-holes are connected through a test pad; the two bottom metal lines connected to the test through-holes are connected through a test pad.

5. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: At least two dummy through-holes, the dummy through-holes penetrate through the insulating layer and are connected to either the first metal layer or the second metal layer; the distribution positions of the at least two dummy through-holes and the at least four through-holes form a centrosymmetric or axisymmetric figure.

6. The semiconductor structure according to claim 5, wherein, The dummy through-holes are filled with an insulating material.

7. The semiconductor structure according to claim 1, wherein The at least four through-holes are used for resistance testing by the Kelvin four-wire detection method.

8. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Forming a first metal layer on the surface of the semiconductor substrate; [[ID=;19]]Covering an insulating layer on the first metal layer; Forming at least four through-holes penetrating through the insulating layer and connecting the first metal layer; Filling a conductive material in the at least four through-holes; Forming a second metal layer on the insulating layer and the at least four through-holes; The conductive material in the at least four through-holes is used for connecting the first metal layer and the second metal layer; Wherein, forming the first metal layer on the surface of the semiconductor substrate includes: Forming a plurality of bottom metal lines parallelly distributed along a first direction on the semiconductor surface; Forming the second metal layer on the insulating layer and the at least four through-holes includes: Forming a plurality of top metal lines parallelly distributed along a second direction on the insulating layer and the at least four through-holes; wherein, the second direction is perpendicular to the first direction; Forming the at least four through-holes penetrating through the insulating layer and connecting the first metal layer further includes: At four target positions of the two bottom metal lines, four test vias are formed through the insulating layer and connected to the bottom metal lines; At least one pair of auxiliary vias are formed through the insulating layer and respectively connected to different bottom metal lines in one of the top metal lines between the two top metal lines, wherein the distance between the pair of auxiliary vias is greater than the distance between any two of the test vias.

9. The method according to claim 8, characterized in that The forming of at least four vias through the insulating layer and connected to the first metal layer includes: Each of the bottom metal lines includes two target positions distributed in the second direction, and the adjacent two target positions of the two bottom metal lines are distributed in the first direction; Forming a plurality of top metal lines parallel to each other in the second direction on the insulating layer and the at least four vias includes: Forming a top metal line above two target positions distributed in the first direction, and the target positions are the overlapping positions of the two top metal lines and the two bottom metal lines.

10. The method according to claim 8, wherein The method further includes: Forming at least two dummy vias, the dummy vias penetrate through the insulating layer and are connected to either the first metal layer or the second metal layer; the figure formed by the distribution positions of the at least two dummy vias and the at least four vias is centrosymmetric or axisymmetric.

11. The method according to claim 10, wherein The method further includes: Filling insulating materials in the at least two dummy vias.

12. The method according to claim 11, wherein When the dummy vias are connected to the first metal layer, the method further includes: Forming a covering layer, the covering layer is filled between the top metal lines and covers the dummy vias.

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