Amplification circuit based on charge bootstrapped amplifier

Abstract

An amplification circuit and a charge bootstrapped amplification circuit, the amplification circuit having a first output and a second output, and comprising a first charge bootstrapped amplifier, a second charge bootstrapped amplifier, a first switch, and a second switch. The first charge bootstrapped amplifier comprises a first input, a second input, a first capacitor, and a second capacitor to amplify a first input signal during a first operation period. The second charge bootstrapped amplifier comprises a third input, a fourth input, the first capacitor, and the second capacitor to amplify a second input signal during a second operation period. The first capacitor and the second capacitor are charged during the first operation period, and the first capacitor and the second capacitor are discharged during the second operation period.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to charge-steering amplifiers, and more particularly to an amplification circuit implemented with a charge-steering amplifier. BACKGROUND

[0002] Figure 1 is a circuit diagram of a conventional charge-steering amplifier. The charge-steering amplifier 100, also known as a dynamic amplifier, is mainly composed of a transistor 110 and a transistor 120, and further includes a switch 130, a switch 140, a switch 150, a switch 160, a capacitor 170, a capacitor 180, and a capacitor 190. The connection manner of each element is shown in the figure. The charge-steering amplifier 100 alternately operates in a reset phase (the switch 130, the switch 140, and the switch 160 are turned on, and the switch 150 is not turned on, so that the capacitor 170 and the capacitor 180 are charged, and the capacitor 190 is discharged) and an amplification phase (the switch 130, the switch 140, and the switch 160 are not turned on, and the switch 150 is turned on, so that the capacitor 170 and the capacitor 180 are discharged, and the capacitor 190 is charged). The charge-steering amplifier 100 amplifies a differential input signal Vi (input from a node N1 and a node N2) in the amplification phase, and generates an output signal Vo (output from a node N3 and a node N4). The operation details of the charge-steering amplifier 100 are well known to those skilled in the art, and will not be described here.

[0003] However, the capacitor 170 and the capacitor 180 generate only one output signal Vo for each charging and discharging (i.e., the energy use efficiency is poor), and the charge-steering amplifier 100 generates the output signal Vo only after amplifying the differential input signal Vi once (i.e., the gain is poor, resulting in that the voltage of the node N3 and the voltage of the node N4 are not easy to distinguish), so there is a need for an amplification circuit to solve at least one of the above problems. SUMMARY

[0004] In view of the deficiencies of the prior art, an object of the present application is to provide an amplification circuit to improve the deficiencies of the prior art.

[0005] An embodiment of the present application provides an amplification circuit having a first output terminal and a second output terminal, and comprising a first charge- steering amplifier, a second charge-steering amplifier, a first switch, and a second switch. The first charge-steering amplifier comprises a first input terminal, a second input terminal, a first capacitor, and a second capacitor for amplifying a first input signal in a first operation period. The second charge-steering amplifier comprises a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor for amplifying a second input signal in a second operation period. The first switch is coupled between the first output terminal and a first target voltage or a second target voltage. The second switch is coupled between the second output terminal and the first target voltage or the second target voltage. The first capacitor is coupled between the first output terminal and a reference voltage, and the second capacitor is coupled between the second output terminal and the reference voltage. The first capacitor and the second capacitor are charged in the first operation period, and the first capacitor and the second capacitor are discharged in the second operation period.

[0006] Another embodiment of the present application provides a charge bootstrapping amplifier circuit having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal, and comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first control terminal is electrically connected to the first input terminal, and the second terminal is electrically connected to the first output terminal. The second transistor has a third terminal, a fourth terminal, and a second control terminal, wherein the second control terminal is electrically connected to the second input terminal, the fourth terminal is electrically connected to the second output terminal, and the third terminal is electrically connected to the first terminal. The third transistor has a fifth terminal, a sixth terminal, and a third control terminal, wherein the third control terminal is electrically connected to the third input terminal, and the sixth terminal is electrically connected to the first output terminal. The fourth transistor has a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the fourth control terminal is electrically connected to the fourth input terminal, the eighth terminal is electrically connected to the second output terminal, and the seventh terminal is electrically connected to the fifth terminal. The first capacitor is coupled between the first terminal and a reference voltage. The second capacitor is coupled between the fifth terminal and the reference voltage. The third capacitor is coupled between the first output terminal and the reference voltage. The fourth capacitor is coupled between the second output terminal and the reference voltage. The first switch is coupled between the first capacitor and the first terminal. The second switch is coupled to the first capacitor, and the first capacitor is discharged when the second switch is turned on. The third switch is coupled between the second capacitor and the fifth terminal. The fourth switch is coupled to the second capacitor, and the second capacitor is charged when the fourth switch is turned on. The fifth switch is used to couple the first output terminal to a first target voltage or a second target voltage. The sixth switch is used to couple the second output terminal to the first target voltage or the second target voltage.

[0007] Compared to conventional techniques, the amplifier circuit of the present application has greater gain, or is more power efficient.

[0008] The features, implementations, and technical effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A circuit diagram of a conventional charge bootstrapping amplifier;

[0010] Figure 2 A circuit diagram of an embodiment of the amplifier circuit of the present application;

[0011] Figure 3 A timing diagram of an operational embodiment of the amplifier circuit of the present application;

[0012] Figure 4 Timing chart for another operation example of the amplification circuit of the present application; and

[0013] Figure 5 Timing chart for another operation example of the amplification circuit of the present application.

[0014] Symbol explanation

[0015] 100, 201, 202: Charge steering amplifier

[0016] 110, 120, 210, 220, 230, 240: Transistor

[0017] 130, 140, 150, 160, SW1, SW2, SW3, SW4, SW5, SW6: Switch

[0018] 170, 180, 190, C1, C2, C3, C4: Capacitor

[0019] Vi: Differential input signal

[0020] N1, N2, N3, N4, N5, N6: Node

[0021] Vo: Output signal

[0022] 200: Amplification circuit (charge steering amplifier)

[0023] Vip, Vin: Signal

[0024] VDD: Power supply voltage

[0025] Nr: Intermediate position

[0026] Vr1: First target voltage

[0027] Vr2: Second target voltage

[0028] CK1, CK2, CK3, CK4: Clock

[0029] VN5, VN6: Voltage

[0030] t1, t2, t3, t4, t5: Time point DETAILED DESCRIPTION

[0031] The technical terms in the following description are referred to the conventional terms in the technical field, and the explanation of the terms is based on the description or definition in the present specification.

[0032] The disclosure of the present application includes an amplification circuit. Since the components included in the amplification circuit of the present application can be known components individually, the details of the known components will be omitted in the following description without affecting the sufficient disclosure and the implementability of the device application.

[0033] Figure 2 is a circuit diagram of an embodiment of the amplification circuit of the present application. The charge steering amplification circuit 200 (or simply the amplification circuit 200) includes a charge steering amplifier 201 and a charge steering amplifier 202. The charge steering amplifier 201 receives a differential input signal Vi (including a signal Vip and a signal Vin) from an input terminal (i.e., a node N1) and an input terminal (i.e., a node N2), and outputs an output signal Vo from an output terminal (i.e., a node N5) and an output terminal (i.e., a node N6). The charge steering amplifier 202 receives a differential input signal Vi (including a signal Vip and a signal Vin) from an input terminal (i.e., a node N3) and an input terminal (i.e., a node N4), and outputs an output signal Vo from an output terminal (i.e., a node N5) and an output terminal (i.e., a node N6).

[0034] The charge steering amplifier 201 includes a transistor 210 (e.g., an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS transistor)), a transistor 220 (e.g., an NMOS transistor), a switch SW1, a switch SW2, a capacitor C1, a capacitor C3, and a capacitor C4. A first terminal (e.g., a drain) of the transistor 210 is coupled or electrically connected to the node N5; a second terminal (e.g., a source) of the transistor 210 is coupled or electrically connected to the switch SW1; and a control terminal (e.g., a gate) of the transistor 210 is coupled or electrically connected to the node N1. A first terminal (e.g., a drain) of the transistor 220 is coupled or electrically connected to the node N6; a second terminal (e.g., a source) of the transistor 220 is coupled or electrically connected to the switch SW1 and the second terminal of the transistor 210; and a control terminal (e.g., a gate) of the transistor 220 is coupled or electrically connected to the node N2. The switch SW1 is coupled between the capacitor C1 and the second terminal of the transistor 210, and the switch SW1 is also coupled between the capacitor C1 and the second terminal of the transistor 220. A first terminal of the capacitor C1 is coupled or electrically connected to the switch SW1, and a second terminal of the capacitor C1 is coupled or electrically connected to a first reference voltage (e.g., ground). One terminal of the switch SW2 is coupled or electrically connected to the first terminal of the capacitor C1, and the other terminal of the switch SW2 is coupled or electrically connected to the first reference voltage. The capacitor C3 is coupled or electrically connected between the node N5 and the first reference voltage. The capacitor C4 is coupled or electrically connected between the node N6 and the first reference voltage.

[0035] The charge bootstrapping amplifier 202 includes a transistor 230 (e.g., a P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor)), a transistor 240 (e.g., a PMOS transistor), a switch SW3, a switch SW4, a capacitor C2, a capacitor C3, and a capacitor C4 (wherein the capacitor C3 and the capacitor C4 are shared with the charge bootstrapping amplifier 201). A first terminal (e.g., a drain) of the transistor 230 is coupled or electrically connected to the node N5; a second terminal (e.g., a source) of the transistor 230 is coupled or electrically connected to the switch SW3; a control terminal (e.g., a gate) of the transistor 230 is coupled or electrically connected to the node N3. A first terminal (e.g., a drain) of the transistor 240 is coupled or electrically connected to the node N6; a second terminal (e.g., a source) of the transistor 240 is coupled or electrically connected to the switch SW3 and the second terminal of the transistor 230; a control terminal (e.g., a gate) of the transistor 240 is coupled or electrically connected to the node N4. The switch SW3 is coupled between the capacitor C2 and the second terminal of the transistor 230, and the switch SW3 is also coupled between the capacitor C2 and the second terminal of the transistor 240. A first terminal of the capacitor C2 is coupled or electrically connected to the switch SW3, and a second terminal of the capacitor C2 is coupled or electrically connected to a first reference voltage. One terminal of the switch SW4 is coupled or electrically connected to the first terminal of the capacitor C2, and another terminal of the switch SW4 is coupled or electrically connected to a second reference voltage (e.g., a power supply voltage VDD). The second reference voltage is greater than the first reference voltage.

[0036] The amplification circuit 200 further includes a switch SW5 and a switch SW6. The switch SW5 and the switch SW6 can be turned on (i.e., switched to the first target voltage Vr1 or the second target voltage Vr2) or turned off (i.e., switched to the neutral position Nr). When the switch SW5 and the switch SW6 are turned on, the switch SW5 and the switch SW6 respectively couple or electrically connect the node N5 and the node N6 to the first target voltage Vr1 or the second target voltage Vr2.

[0037] In some embodiments, the first target voltage Vr1 is the second reference voltage (e.g., the power supply voltage VDD) or half of the second reference voltage (e.g., 1 / 2 of the power supply voltage VDD), and the second target voltage Vr2 is the first reference voltage (e.g., ground) or half of the second reference voltage (e.g., 1 / 2 of the power supply voltage VDD). In other words, when the node N5 and the node N6 are coupled or electrically connected to the first target voltage Vr1, the cross voltage of the capacitor C3 and the capacitor C4 is substantially the second reference voltage or half of the second reference voltage; when the node N5 and the node N6 are coupled or electrically connected to the second target voltage Vr2, the cross voltage of the capacitor C3 and the capacitor C4 is substantially zero or half of the second reference voltage.

[0038] In some embodiments, switches SW1, SW2, SW3, SW4, SW5, and SW6 can be implemented using transistors.

[0039] Figure 3 This is a timing diagram of one operational embodiment of the amplifier circuit of the present invention, which can be referred to in conjunction with it. Figure 2 In the following discussion, switch SW3 is switched (i.e., on or off) according to clock CK1: when clock CK1 is at the first level (e.g., high level), switch SW3 is off; when clock CK1 is at the second level (not equal to the first level, e.g., low level), switch SW3 is on. Switch SW1 is switched according to clock CK2: when clock CK2 is at the first level, switch SW1 is on; when clock CK2 is at the second level, switch SW1 is off. Voltage VN5 represents the voltage at node N5, and voltage VN6 represents the voltage at node N6.

[0040] When clock CK3 is at the first level (e.g., between time point t1 and time point t3), amplifier circuit 200 operates in the amplification stage; when clock CK3 is at the second level (e.g., between time point t3 and time point t4), amplifier circuit 200 operates in the reset stage.

[0041] exist Figure 3 In the embodiment, when switches SW5 and SW6 are turned on, nodes N5 and N6 are coupled or electrically connected to the second target voltage Vr2, and switches SW2, SW4, SW5 and SW6 are switched according to clock CK3: when clock CK3 is at the first level, switches SW2, SW4, SW5 and SW6 are not turned on; when clock CK3 is at the second level, switches SW2, SW4, SW5 and SW6 are turned on.

[0042] like Figure 3As shown, at time point tl, clock CK3 transitions from the second level to the first level (representing the end of the reset phase and the beginning of the amplification phase), and voltages VN5 and VN6 are the second target voltage Vr2. Clock CK2 transitions from the second level to the first level at time point t2. The amplification phase includes a first operation period (when clock CK1 is at the second level) and a second operation period (when clock CK2 is at the first level). The first operation period is substantially equal to or slightly less than the time from time point tl to time point t2, in other words, the time point at which clock CK1 transitions from the first level to the second level can be substantially equal to or slightly later than time point tl, and the time point at which clock CK1 transitions from the second level to the first level can be substantially equal to or slightly earlier than time point t2. The second operation period is substantially equal to or slightly less than the time from time point t2 to time point t3, in other words, the time point at which clock CK2 transitions from the second level to the first level is substantially equal to time point t2, and the time point at which clock CK2 transitions from the first level to the second level can be substantially equal to or slightly later than time point t3. At time point t3, clock CK3 transitions from the first level to the second level (representing the end of the amplification phase and the beginning of the reset phase).

[0043] Please refer to Figure 2 and Figure 3During the first operation period, switch SW3 is on and switch SW1 is off, so transistors 230 and 240 are active and transistors 210 and 220 are inactive, causing capacitors C3 and C4 to charge. During the first operation period, transistors 230 and 240 amplify the differential input signal Vi, so the difference between voltage VN5 (e.g., dotted line) and voltage VN6 (e.g., solid line) gradually becomes larger. During the second operation period, switch SW1 is on and switch SW3 is off, so transistors 210 and 220 are active and transistors 230 and 240 are inactive, causing capacitors C3 and C4 to discharge. During the second operation period, transistors 210 and 220 continue to amplify the differential input signal Vi (which is the same as the differential input signal Vi in the first operation period) based on voltage VN5 and voltage VN6 at time point t2, so it can be seen that the difference between voltage VN5 and voltage VN6 continues to become larger. In other words, the difference between voltage VN5 and voltage VN6 at time point t3 is larger than the difference between voltage VN5 and voltage VN6 at time point t2. Thus, after the second amplification, the difference between voltage VN5 and voltage VN6 becomes larger, which is beneficial to the operation of the subsequent circuit (e.g., a comparator). As a comparison, because the existing charge-boosted amplifier 100 only amplifies the differential input signal once, the output signal Vo implementation generated by the charge-boosted amplifier 100 for the same differential input signal Vi at most corresponds to the output signal Vo at time point t2. That is, the gain of the amplification circuit 200 of the present disclosure is larger than the gain of the charge-boosted amplifier 100.

[0044] Please note that because the differential input signal Vi remains unchanged between time point t1 and time point t3, i.e., maintains the sampling result (generated by a sampling and holding circuit (not shown in the figure)) in the previous reset stage, transistors 210, 220, 230 and 240 substantially perform amplification operations according to the same differential input signal Vi in the same amplification stage (e.g., between time point t1 and time point t3). The differential input signal Vi between time point t4 and time point t5 is the result of the sampling operation between time point t3 and time point t4.

[0045] Figure 4 Timing diagram for another operation embodiment of the amplification circuit of the present disclosure. Figure 4 With Figure 3Similar to the previous approach, the difference lies in that in each amplification phase, the second operating period precedes the first operating period, and in each reset phase, switches SW5 and SW6 couple or electrically connect nodes N5 and N6 to the first target voltage Vr1, not the second target voltage Vr2. Therefore, voltages VN5 and VN6 ​​first decrease during the amplification phase (i.e., capacitors C3 and C4 discharge, e.g., between time points t1 and t2) and then increase (i.e., capacitors C3 and C4 charge, e.g., between time points t2 and t3). Figure 3 Similar to the implementation, in each amplification stage, the differential input signal Vi is amplified twice, making the difference between voltage VN5 and voltage VN6 larger, which is beneficial to the operation of subsequent circuits (such as comparators).

[0046] Figure 5 This is a timing diagram of another operational embodiment of the amplifier circuit of the present invention. Figure 5 In this embodiment, switches SW2 and SW4 switch according to clock CK3: when clock CK3 is at the first level, switches SW2 and SW4 are not turned on; when clock CK3 is at the second level, switches SW2 and SW4 are turned on. Switches SW5 and SW6 switch according to clock CK4. When clock CK4 is at the second level (e.g., between time points t1 and t2, or between time points t3 and t4), amplifier circuit 200 operates in the amplification stage; when clock CK4 is at the first level (e.g., between time points t2 and t3, or between time points t4 and t5), amplifier circuit 200 operates in the reset stage. Similarly, Figure 5 The embodiments also include a first operation period (when clock CK1 is at the first level) and a second operation period (when clock CK2 is at the second level). For example... Figure 5 As shown, in this embodiment, there is a reset phase between the first operation period (corresponding to the first amplification operation) and the second operation period (corresponding to the second amplification operation); in other words, before the start of the first operation period and before the start of the second operation period, the voltages (i.e., voltages VN5 and VN6) at the output terminals of the amplifier circuit 200 (i.e., nodes N5 and N6) will be reset, that is, the terminal voltages of capacitors C3 and C4 will be reset.

[0047] like Figure 5 As shown, clock CK4 transitions from the first level to the second level at time points t1 and t3, and transitions from the second level to the first level at time points t2 and t4.

[0048] The first operation period is substantially equal to or slightly less than the time from time point t1 to time point t2, in other words, the time point when clock CK1 switches from the second level to the first level can be substantially equal to or slightly later than time point t1, and the time point when clock CK1 switches from the first level to the second level can be substantially equal to or slightly earlier than time point t2. The second operation period is substantially equal to or slightly less than the time from time point t3 to time t4, in other words, the time point when clock CK2 switches from the first level to the second level is substantially equal to or slightly later than time point t3, and the time point when clock CK2 switches from the second level to the first level can be substantially equal to or slightly earlier than time point t4.

[0049] Please refer to Figure 2 and Figure 5 During the first operation period (e.g. the first operation period between time point t1 and time point t2), switch SW1 is on and switch SW3 is off (i.e. transistors 210 and 220 are active and transistors 230 and 240 are inactive, capacitors C3 and C4 are discharged), transistors 210 and 220 amplify the differential input signal Vi, thus the difference between voltage VN5 and voltage VN6 becomes larger. During the reset phase after the first operation period (e.g. between time point t2 and time point t3), switches SW5 and SW6 couple or electrically connect nodes N5 and N6 to the second target voltage Vr2. During the following second operation period (e.g. the second operation period between time point t3 and time point t4), switch SW1 is off and switch SW3 is on (i.e. transistors 210 and 220 are inactive and transistors 230 and 240 are active, capacitors C3 and C4 are charged), transistors 230 and 240 amplify the differential input signal Vi, thus the difference between voltage VN5 and voltage VN6 becomes larger. During the reset phase after the second operation period (e.g. between time point t4 and time point t5), switches SW5 and SW6 couple or electrically connect nodes N5 and N6 to the first target voltage Vr1.

[0050] It is noted that because the sample-and-hold circuit samples during the reset phase, in the embodiment of Figure 5 , the amplification circuit 200 amplifies different differential input signals Vi during the first operation period and the second operation period (i.e. amplifies the results of different samplings, rather than the results of the same sampling).

[0051] As Figure 5As shown, from time point t1 to time point t5, the capacitor C3 and the capacitor C4 are only charged once (approximately between time point t3 and time point t5), but the amplification circuit 200 generates two amplification results (in the long run, the amplification circuit 200 generates the first odd amplification result in the first operation period and the second even amplification result in the second operation period). Therefore, compared with the existing charge steering amplifier 100, the amplification circuit 200 is more power saving.

[0052] The above-mentioned transistors can also be implemented by bipolar junction transistors (BJTs). The emitter, the collector and the base of the BJT can correspond to the source, the drain and the gate of the MOSFET, respectively, which is well known to those skilled in the art and will not be described here.

[0053] Please note that in the above-mentioned figures, the shapes, sizes and proportions of the elements are only for illustration and are for those skilled in the art to understand the present application, and are not intended to limit the present application.

[0054] Although the embodiments of the present application are described above, the embodiments are not intended to limit the present application, and those skilled in the art can change the technical features of the present application according to the explicit or implicit content of the present application, and any such changes can be within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be subject to the definition of the claims in the specification.

Claims

1. An amplification circuit having a first output terminal and a second output terminal, the amplification circuit comprising: a first charge-boosting amplifier including a first input terminal, a second input terminal, a first capacitor, and a second capacitor to amplify a first input signal during a first operation period; a second charge-boosting amplifier including a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor to amplify a second input signal during a second operation period; a first switch coupled between the first output terminal and a first target voltage or a second target voltage; and a second switch coupled between the second output terminal and the first target voltage or the second target voltage; wherein the first capacitor is coupled between the first output terminal and a reference voltage, the second capacitor is coupled between the second output terminal and the reference voltage, the first capacitor and the second capacitor are charged during the first operation period, and the first capacitor and the second capacitor are discharged during the second operation period. The first charge-boosting amplifier includes a first P-type metal-oxide-semiconductor field-effect transistor and a second P-type metal-oxide-semiconductor field-effect transistor, the second charge-boosting amplifier includes a first N-type metal-oxide-semiconductor field-effect transistor and a second N-type metal-oxide-semiconductor field-effect transistor, a first gate of the first P-type metal-oxide-semiconductor field-effect transistor is the first input terminal, a second gate of the second P-type metal-oxide-semiconductor field-effect transistor is the second input terminal, a third gate of the first N-type metal-oxide-semiconductor field-effect transistor is the third input terminal, and a fourth gate of the second N-type metal-oxide-semiconductor field-effect transistor is the fourth input terminal.

2. The amplification circuit of claim 1, wherein, The first input signal is equal to the second input signal, and the first operation period is earlier than the second operation period.

3. The amplification circuit of claim 2, wherein, The first input signal is equal to the second input signal, and the second operation period is earlier than the first operation period.

4. The amplification circuit of claim 2, wherein, The first input signal is not equal to the second input signal, and the first capacitor and the second capacitor are reset between the first operation period and the second operation period.

5. The amplification circuit of claim 2, wherein, 6. A charge-boosting amplification circuit having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal, the charge-boosting amplification circuit comprising: a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the first control terminal is electrically connected to the first input terminal, and the second terminal is electrically connected to the first output terminal; A first transistor has a first terminal, a second terminal, and a first control terminal, wherein a second transistor having a third terminal, a fourth terminal, and a second control terminal, wherein the second control terminal is electrically connected to the second input terminal, the fourth terminal is electrically connected to the second output terminal, and the third terminal is electrically connected to the first terminal; a third transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the third control terminal is electrically connected to the third input terminal, and the sixth terminal is electrically connected to the first output terminal; a fourth transistor having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the fourth control terminal is electrically connected to the fourth input terminal, the eighth terminal is electrically connected to the second output terminal, and the seventh terminal is electrically connected to the fifth terminal; ​ a first capacitor coupled between the first terminal and a reference voltage; a second capacitor coupled between the fifth terminal and the reference voltage; a third capacitor coupled between the first output terminal and the reference voltage; a fourth capacitor coupled between the second output terminal and the reference voltage; a first switch coupled between the first capacitor and the first terminal; a second switch coupled to the first capacitor, wherein the first capacitor is discharged when the second switch is turned on; a third switch coupled between the second capacitor and the fifth terminal; a fourth switch coupled to the second capacitor, wherein the second capacitor is charged when the fourth switch is turned on; a fifth switch for coupling the first output terminal to a first target voltage or a second target voltage; and a sixth switch for coupling the second output terminal to the first target voltage or the second target voltage.

7. The charge bootstrapped amplification circuit of claim 6, wherein, The first transistor and the second transistor are N-type metal-oxide-semiconductor field-effect transistors, the third transistor and the fourth transistor are P-type metal-oxide-semiconductor field-effect transistors, the first terminal, the third terminal, the fifth terminal and the seventh terminal are sources, the second terminal, the fourth terminal, the sixth terminal and the eighth terminal are drains, and the first control terminal, the second control terminal, the third control terminal and the fourth control terminal are gates.

8. The charge bootstrapped amplification circuit of claim 7, wherein, The charge-steering amplification circuit performs an amplification operation; during the amplification operation, the third switch is turned on first, and then the first switch is turned on; and the first switch and the third switch are not turned on at the same time.

9. The charge bootstrapped amplification circuit of claim 7, wherein, The charge-steering amplification circuit performs an amplification operation; during the amplification operation, the first switch is turned on first, and then the third switch is turned on; and the first switch and the third switch are not turned on at the same time.

10. The charge bootstrapped amplification circuit of claim 7, wherein, The first target voltage is not equal to the second target voltage; the charge-steering amplification circuit performs a first amplification operation and a second amplification operation; the fifth switch and the sixth switch couple the first output terminal and the second output terminal to the first target voltage before the first amplification operation; and the fifth switch and the sixth switch couple the first output terminal and the second output terminal to the second target voltage between the first amplification operation and the second amplification operation. The first transistor and the second transistor are N-type metal-oxide-semiconductor field-effect transistors, the third transistor and the fourth transistor are P-type metal-oxide-semiconductor field-effect transistors, the first terminal, the third terminal, the fifth terminal and the seventh terminal are sources, the second terminal, the fourth terminal, the sixth terminal and the eighth terminal are drains, and the first control terminal, the second control terminal, the third control terminal and the fourth control terminal are gates. The charge-steering amplification circuit performs an amplification operation; during the amplification operation, the third switch is turned on first, and then the first switch is turned on; and the first switch and the third switch are not turned on at the same time. The charge-steering amplification circuit performs an amplification operation; during the amplification operation, the first switch is turned on first, and then the third switch is turned on; and the first switch and the third switch are not turned on at the same time. The first target voltage is not equal to the second target voltage; the charge-steering amplification circuit performs a first amplification operation and a second amplification operation; the fifth switch and the sixth switch couple the first output terminal and the second output terminal to the first target voltage before the first amplification operation; and the fifth switch and the sixth switch couple the first output terminal and the second output terminal to the second target voltage between the first amplification operation and the second amplification operation.

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