Synchronous High-Speed Signaling Interconnection

Abstract

Synchronous high-speed signaling interconnection is disclosed. Specifically, a system is disclosed that includes a first device and a second device coupled to a link. The first device is configured to send one or more request frames for synchronization of a data layer, each request frame including a certain number of bits and an error code. The second device is configured to receive a first set of bits corresponding to the number of bits in each request frame. The second device is configured to perform an error decoding operation on the first set of bits using a first portion of the first set of bits and, in response to a successful error decoding operation, determine that the first set of bits corresponds to a frame boundary of one or more request frames. The second device is configured to send an acknowledgment for synchronization of the data layer based on determining that the first set of bits corresponds to a frame boundary.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating high-speed communication. For example, at least one embodiment relates to techniques for synchronizing a local transmitter and a remote receiver pair in a ground reference signaling (GRS) interconnect at the data link layer. Background Art

[0002] A communication system transmits signals from a transmitter to a receiver via a communication channel or medium (e.g., cable, printed circuit board, link, wireless, etc.). Communication from the transmitter to the receiver causes the receiver to need to synchronize with the transmitter, otherwise data may be corrupted. For example, when performing chip-to-chip (C2C) communication, a local transmitter may need to synchronize with a remote receiver. Some communication systems may attempt to synchronize between the transmitter and the receiver by scanning a bit stream for special symbols or field communication or using a hysteresis filter. For example, a system may attempt to synchronize the transmitter and the receiver by sending packets including bit / byte / character stuffing from the transmitter and having the receiver scan the bit stream for keywords or extra bits / bytes / characters to demarcate the boundaries of the packets. Such conventional methods may be unreliable or cause the receiver to incorrectly determine the synchronization between the transmitter and the receiver. Brief Description of the Drawings

[0003] Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:

[0004] Figure 1 is an example communication system of a method for synchronizing a receiver and a transmitter in accordance with at least some embodiments;

[0005] Figure 2 illustrates an example of a frame transmitted in a communication system in accordance with at least some embodiments;

[0006] Figure 3 is a schematic diagram of a method for synchronizing a receiver and a transmitter in accordance with at least some embodiments;

[0007] Figure 4 is a flowchart for synchronizing a high-speed signaling interconnect in accordance with at least some embodiments;

[0008] Figure 5 illustrates an example computer system including a wireless transceiver in accordance with at least some embodiments, the wireless transceiver including a chip-to-chip interconnect. Detailed Description

[0009] As described above, it may be unreliable to scan the bitstream to find a special filter or use a hysteresis filter to synchronize the local transmitter and the remote receiver. Without proper synchronization, the receiver may not be able to perform error decoding operations on the received data. For example, a communication system may include a first device (e.g., a first chip) and a second device (e.g., a second chip), and communicate data via a ground reference signaling (GRS) link - for example, the communication system may be a chip-to-chip (C2C) interconnect. The data may be transmitted from the transmitter of the first device to the receiver of the second device in frames of a fixed length via the link. For example, each frame may include the same number of bits and transmit portions of the data. In some examples, the physical layer (PL) of the GRS C2C interconnect may train (e.g., synchronize) before the link is released to the data link layer (DL). In such examples, the transition from the PL to the DL may occur at any time. Additionally, during the transition from the PL to the DL based on the GRS link architecture, the link may be constantly driven to a first logic state (e.g., logic "0") or a second logic state (e.g., logic "1"). Thus, without proper synchronization, the receiver may process the data transmitted during the transition from the PL to the DL, or process the data at any point in the data frame based on incorrectly determining the start or end of the data frame - for example, processing a portion of the first data frame and the second data frame. This may cause the receiver to be unable to perform data detection on the received data and result in a high bit error rate (BER) for the system.

[0010] Advantageously, aspects of the present disclosure relate to a method for determining, prior to sending data from a transmitter to a receiver, the frame boundaries (e.g., the start or end of a given frame) delimited by the transmitter at the remote receiver. According to an embodiment, the transmitter may send a request frame to the receiver to initiate a synchronization process. The receiver may perform an error decoding operation on a set of received bits corresponding to the frame size of the request frame using an error code encoded in each frame sent by the transmitter - for example, the receiver may perform a cyclic redundancy check (CRC) on each received frame. If the request frame passes the CRC check, the receiver may determine the frame boundary. In such an example, the receiver may send an acknowledgment of the determined frame boundary, and the transmitter may start sending data based on the acknowledgment.

[0011] If a request frame fails the CRC check, the receiver may refrain (e.g., skip) from performing CRC on a second set of bits received after the first set of bits (e.g., a certain number of bits having a size less than the frame size or a certain number of bits received during one clock cycle), and perform CRC on a third set of bits received after the second set of bits, where the third set of bits corresponds to the frame size. That is, the receiver may skip performing CRC on a predetermined size of bits (e.g., on a flit or a certain number of bits received during one clock cycle) after determining that the first set of bits corresponding to the frame size fails the CRC, and resume the error decoding operation on the subsequent third set of bits received corresponding to the frame size. The receiver may continue this process (e.g., skip that number of bits corresponding to the size of a certain number of bits received within one clock cycle and perform the error decoding operation on the subsequent bits corresponding to the frame size) until a set of bits received corresponding to the frame size passes the CRC. Thus, when the transmitter continuously sends the request frame until the receiver determines the frame boundary, the receiver can ensure frame locking. Additionally, in most examples, the receiver will determine the frame boundary within an amount of "N" corresponding to the size of the bit subset. Embodiments of the present application allow for a more reliable method of synchronization between the transmitter and the receiver and reduce the bit error rate of the system.

[0012] Figure 1 FIG. illustrates an example communication system 100 in accordance with at least one example embodiment. System 100 includes hosts 102-a, 102-b, a first device 104-a, and a second device 104-b. System 100 also includes a link 106 coupling the first device 104-a and the second device 104-b. Each device 104 may include a transceiver 125, which includes a transmitter 130, a receiver 135, a digital data source 140, and processing circuitry 145. Each transmitter 130 may include a transaction layer (TL) 108, a data layer (DL) 110, a physical layer (PL) 112, and each receiver 135 may include a TL 114, a DL 116, and a PL 118.

[0013] In at least one example, host 102 or device 104 can correspond to one or more of a personal computer (PC), laptop, tablet, smartphone, server, server farm, etc. In some examples, host 102 can correspond to any suitable type of device that communicates with other devices and is also connected to common link 106. In some examples, host 102 can send commands or data to device 104. In such examples, device 104 can transfer data to each other based on the commands or data received from host 102. As another specific but non-limiting example, host 102 and device 104 can correspond to servers that provide information resources, services, and / or applications to user devices, client devices, or other hosts in system 100.

[0014] In at least one example embodiment, first device 104-a and second device 104-b can be examples of chips - for example, system 100 can be an example of a multi-chip module or a chip-to-chip (C2C) interconnect. In such examples, device 104 can be a single chip or a chip stack. In some examples, device 104 can include a graphics processing unit (GPU), a switch (e.g., a high-speed network switch), a network adapter, a central processing unit (CPU), etc., for executing commands or functions received from host 102. Each device 104 can include a transceiver 125 for sending and receiving signals, such as data signals. The data signal can be a digital signal modulated with data, an optical signal, or other suitable signals for carrying data. Each transceiver 125 can include a receiver 135 and a transmitter 130. Transmitter 130 includes suitable software and / or hardware for receiving digital data from digital data source 140 and outputting a data signal according to the digital data for transmission to receiver 135 of device 104-b via link 106. Receiver 135 of device 104-b can include suitable hardware and / or software for receiving signals (e.g., data signals from link 106).

[0015] In one embodiment, device 104 can communicate bidirectionally - for example, from host 102-a to host 102-b or from host 102-b to host 102-a. In some examples, each receiver 135 or transmitter 130 of device 104 can operate independently and / or simultaneously. For example, receiver 135-a of first device 104-a can receive data from transmitter 130-b of second device 104-b simultaneously while transmitter 130-a of first device 104-a sends data to receiver 135-b of second device 104-b.

[0016] Each transmitter 130 and receiver 135 in device 104 may include a transaction layer (TL). In some examples, the TL 108 of transmitter 130 may be configured to request a transaction - for example, request the transmission of data. For example, the TL 108 of transmitter 130 may convey functions or assemble packets for other components of device 104. In some examples, the TL 108 of transmitter 130 may generate a transaction layer packet (TLP) that can be sent to DL 110 for further processing. In some examples, each receiver 135 in device 104 may also include a transaction layer 114. In some examples, the TL 114 of receiver 135 may be configured to complete a transaction - for example, complete the transmission of data. For example, the TL 114 of receiver 135 may receive functions from other components of each receiver of device 104 or disassemble the packets received from other components of each receiver of device 104. In some embodiments, the TL 114 of receiver 135 may verify the incoming TLP packet to ensure that the received packet is valid - for example, without errors.

[0017] Each transmitter 130 and receiver 135 in device 104 may also include a data layer. In some examples, DL110 and DL 116 may be configured to ensure that the data sent over link 106 is correct and without errors. For example, the DL 110 of transmitter 130 may encode the corresponding frame or packet being sent with an error code (e.g., a CRC value). The DL 116 of receiver 135 may generate an error code based on the received frame and decode the CRC embedded in the frame for comparison to determine if the generated error code matches the sent CRC. In some examples, DL 116 performs an error decoding operation to see if the received data is correct and without errors. In some examples, the DL 110 of transmitter 130 may be configured to add a sequence number as a header to each frame or packet being sent, and the DL 116 of receiver 135 may also be configured to check the sequence number. In some examples, the DL 110 of transmitter 130 and the DL 116 of receiver 135 may include or be coupled to a controller or control flow unit to perform an error decoding operation on the received packet or frame - for example, processing circuit 145.

[0018] Additionally, each transmitter 130 and receiver 135 in device 104 may include a physical layer (PL). In some examples, PL 112 and PL 118 may be configured to send and receive data over link 106. For example, PL 112 and PL 118 may include input / output (I / O) buffers, parallel-to-serial and serial-to-parallel converters, impedance matching circuits, logic circuits, etc., for sending and receiving data packets or frames over link 106.

[0019] Each transceiver 125 may include a digital data source 140 and processing circuitry 145 that controls transceiver 125. The digital data generator 140 may include suitable hardware and / or software for outputting data in a digital format (e.g., in binary code and / or thermometer code). The digital data output by the digital data source 140 may be retrieved from a memory (not shown) or generated based on an input (e.g., user input).

[0020] The processing circuitry 145 may include software, hardware, or a combination thereof. For example, the processing circuitry 145 may include a memory and a processor (e.g., a microprocessor), the memory including executable instructions and the processor executing the instructions on the memory. The memory may correspond to any suitable type of memory device or a collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, etc. In some embodiments, the memory and the processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, the processing circuitry 145 may include hardware, such as an application specific integrated circuit (ASIC). Other non-limiting examples of the processing circuitry 132 include integrated circuit (IC) chips, central processing unit (CPU), general processing unit (GPU), microprocessor, field programmable gate array (FPGA), a collection of logic gates or transistors, resistors, capacitors, inductors, diodes, etc. Some or all of the processing circuitry 145 may be provided on a printed circuit board (PCB) or a collection of PCBs. It should be understood that any suitable type of electrical component or a collection of electrical components may be suitable for inclusion in the processing circuitry 145. The processing circuitry 145 may send and / or receive signals to and / or from other elements of the transceiver 125 to control the overall operation of the transceiver 125.

[0021] The transceiver 125 or a selected element of the transceiver 125 may take the form of a pluggable card or a controller of the device 104. For example, the transceiver 125 or a selected element of the transceiver 125 may be implemented on a network interface card (NIC).

[0022] The link 106 may be an example of a communication network that may be used to connect the devices 104, such as an Internet Protocol (IP) network, Ethernet, InfiniBand (IB) network, Fibre Channel network, the Internet, a cellular communication network, a wireless communication network, combinations thereof (e.g., Ethernet Fibre Channel), variations thereof, and / or the like. In one specific but non-limiting example, the link 106 is a network that enables data transfer between the devices 104 using data signals (e.g., digital, optical, wireless signals).

[0023] In one embodiment, link 106 may be configured to transfer requests, data, functions, commands, etc. between a first device 104-a and a second device 104-b. In one example, link 106 may be a cable, printed circuit board, link, wireless, etc. In at least one embodiment, link 106 may be an example of a ground reference signaling (GRS) interconnect. In such an example, link 106 may include an RC-dominated channel and an LC transmission line. Additionally, the GRS interconnect may be an on-chip link, a link across a substrate (such as an organic package), or a link signaling on a printed circuit board (PCB). In some examples, GRS may use a ground network as the signal reference voltage - for example, the ground may be return signaling. Although not explicitly shown, it should be understood that host 102 and device 104 may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks such as sending and receiving data.

[0024] In some examples, based on the GRS architecture, link 106 may be configured to be driven to a logic state "1" or a logic state "0" by any transmitter of device 104. In such an example, it may be difficult to determine the transition between the PL layer and the DL layer - for example, link 106 may arbitrarily transition from sending PL layer information to DL layer information. Additionally, based on link 106 that sends high-speed data, there may be a high possibility of high BER and link 106 errors when sending data. Therefore, at least one embodiment describes a method for synchronizing the DL of transmitter 130-a of the first device 104-a with the DL of receiver 135-b of the second device 104-b before sending data. As described above, link 106 supports two-way communication. In such an embodiment, the method for synchronizing the DL may also be used independently and / or simultaneously by transmitter 130-b of the second device 104-b and receiver 135-a of the first device 104-a.

[0025] In some embodiments, system 100 may synchronize the PL of the first device 104-a and the second device 104-b before synchronizing the DL of the first device 104-a and the second device 104-b. As Figure 2 shown, after synchronizing the PL but before sending data, transmitter 130-a of the first device 104-a may send a request frame. In some embodiments, the request frame may be sent after the receiver 135 is reset, after the receiver 135 is restarted, or after any other arbitrary restart determined by the user or other code used by the receiver 135. In some examples, the request frame may also be referred to as a frame including a request or simply a request for synchronization.

[0026] As Figure 2As shown, the frame 200 sent by the transmitter may include "N" flits 202. For example, a given frame 200 may include ten (10) flits 202. In some examples, each flit 202 may include the same number of bits - for example, each flit 202 is "X" bits wide. For example, each flit 202 may be 128 bits wide. In some examples, the DL 110 of the transmitter 130 may send one (1) flit per clock cycle. Thus, each frame may be sent in "N" clock cycles based on the number "N" of flits 202. Additionally, each frame 200 may include an error code CRC 208. The DL 110 is configured to generate the CRC 208 for the entire frame. In such an embodiment, the DL 116 of the receiver 135 is configured to perform an error decoding operation across the "N" flits 202 for each frame 200 - for example, the receiver 135 is configured to perform an error decoding operation after receiving the "N" flits 202 corresponding to the size or width of the frame 200. Wherein, the error decoding operation is performed at the frame granularity. Each frame 200 may also include a header 204.

[0027] In some examples, the frame 200 may be a request frame sent by the transmitter 130-a to the receiver 135-b to initiate synchronization of the DL between the first device 104-a and the second device 104-b. For example, the transmitter 130-a may send the request frame 200 from the DL 110-a to the link 106 to initiate synchronization. Each request frame 200 sent by the transmitter 130-a may include a header 204 that includes a sequence, information, identifier, etc. indicating that the frame 200 is a request frame - for example, a request to synchronize the DL110-a with the DL 116-b of the receiver 135-b in the second device 104-b. In some embodiments, the request frame 200 may also include data - for example, training data or data otherwise used during the synchronization process. Each request frame 200 also includes a CRC 208. The receiver 135-b of the second device 104-b may utilize the CRC 208 to determine whether the received "N" flits 202 match or align with a given request frame 200 - for example, if the "N" flits 202 pass or fail the CRC error decoding operation. It should be noted that each CRC of the request frame 200 is the same - for example, each request frame 200 sent by the transmitter 130-a has at least some parts in common with another request frame 200. For example, the transmitter 130-a may send a first request frame 200 with first data and a first error code and a second request frame with second data and a second error code, where the first error code and the second error code are the same. Additional details regarding the request frame 200, the error decoding operation, and the synchronization process are referencedFigure 3 and Figure 4 will be described.

[0028] In some embodiments, if the second device 104-b determines that the received "N" flits 202 are aligned with the request frame 200, the second device 104-b may send an acknowledgment from DL 110-b to DL 116-a. That is, the control flow unit (control finite state machine (FSM), controller, etc.) may determine that DL 116-b is synchronized with DL 110-a and send a message 120-b (via the processing circuit 145-b) to the transmitter 130-b of the second device 104-b. The frame 200 sent by DL 110-b may include the acknowledgment. For example, the acknowledgment may not be a unique frame 200, but rather embedded in (or identified within) the frame 200 - for example, the header 204 may include a symbol, sequence, or identifier of the acknowledgment. In response to the acknowledgment, the first device 104-a may send a synchronization completion frame 200 (e.g., a frame 200 including a symbol, sequence, or identifier of the synchronization being completed) to the second device 104-b before sending data from the sending host 102-a - for example, before sending a data frame 200.

[0029] Figure 3 FIG. 300 illustrates a method of synchronizing a local transmitter and a remote receiver. For example, FIG. 300 illustrates a method of using an error decoding operation at the receiver to determine the frame boundary used by the transmitter. The method shown in FIG. 300 may be performed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, the method shown in FIG. 300 is performed by Figure 1 DL 116-b of the receiver 135-b in the second device 104-b or DL 116-a of the receiver 135-a in the first device 104-a. In some embodiments, as referred to in Figure 2 the receiver 135 may receive data, flits 202, bits, frames 200, etc. from DL 110-a or DL 110-b of the transmitter 103-a of the first device 104-a or the transmitter 130-b of the second device 104-b, respectively. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise stated. Thus, the illustrated embodiments should only be construed as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other figures illustrating the synchronization method are possible.

[0030] As described above, to initiate synchronization of the DL (e.g., between DL 110-a and DL 116-b) between the transmitter of the first device 104-a and the receiver of the second device 104-b, the transmitter may send a request frame. For example, DL 110-a may first send request frames "M" 302-a and subsequent request frames "M+1" 302-b, "M+2" 302-c, "M+3" 302-d, and "M+4" 302-e. Based on link 106 latency, errors, and any conversions, DL 116-b may start receiving flits (e.g., a certain number of bits) asynchronously with frame "M" 302-a. That is, DL 116-b may receive "N" flits 304 corresponding to the size or width of the request frame, but it includes portions of the transmitted frames "M" 302-a and "M+1" 302-b. In such an embodiment, DL116-b may determine that an error decoding operation on the "N" flits 304 fails. That is, DL 116-b may perform an error decoding operation by generating an error code for the first "N" flits 304 received corresponding to the frame size and determining that the CRC embedded in the flit 304 does not match the generated error code. Thus, DL 116 may determine that the flit 304 does not correspond to a frame boundary based on the failure of the error decoding operation. In such an embodiment, DL 116-b may skip or otherwise refrain from performing any error decoding operation on the next received flit 306 - for example, DL 116-b may ignore flit306 and not include flit 306 as part of receiving the next "N" flits or as part of any frame decoded by DL 116-b. In some examples, flit 306 may also be referred to as a set of bits having a size less than the frame size, a set of bits having a predetermined size, or a subset of bits. Alternatively, skipping flit306 may be referred to as skipping data or a certain number of bits received during the clock cycle after receiving the "N" slices 304.

[0031] After skipping flit 306, DL 116-b can perform an error decoding operation on the subsequent "N" flits 308 received. In the example shown in FIG. 300, flit 308 is also asynchronous with the transmitted frame 302. That is, flit 308 includes portions of frames "M+1" 302-b and "M+2" 302-c. Thus, when DL 116-b performs a decoding operation on flit 308, DL 116-b can determine that the error code generated for flit 308 does not match the CRC embedded in flit 308. Accordingly, DL 116-b can determine based on the error decoding operation that flit 308 does not correspond to a frame boundary. Thus, DL 116-b can skip or otherwise refrain from performing an error decoding operation on flit 310 - for example, excluding flit 310 from the next received quantity of "N" flits, or refraining from considering flit 310 to generate an error code.

[0032] After skipping flit 310, DL 116-b can perform an error decoding operation on the subsequent "N" flits 312 received. In the example shown in FIG. 300, flit 312 is synchronous with the transmitted frame 302. That is, flit 312 is synchronous (e.g., aligned) with the transmitted frame "M+3" 302-d. Thus, when DL 116-b performs a decoding operation on flit 312, DL 116-b can determine that the CRC embedded in flit 312 corresponds to the error code generated for the "N" flits 312. Accordingly, DL 116-b can determine based on the error decoding operation that the received "N" flits 312 correspond to a frame boundary. In the example shown in FIG. 300, DL 116-b can receive an additional set of flits 314 and perform an error decoding operation on flit 314 to ensure that the frame boundary is correct. That is, when determining the frame boundary, DL 116-b can refrain from skipping any flits.

[0033] After determining the frame boundary, DL 116-b can generate an acknowledgment and send a message 116-b to the DL110-b of the transmitter of the second device 104-b. Thus, DL 110-b can send frame 200 with an acknowledgment as described in reference Figure 2 Subsequently, in some embodiments, DL 116-a can send a message indicating the acknowledgment received from the second device 104-b to DL 110-a, and the first device 104-a can send a synchronization complete frame after the data based on the synchronization between DL 110-a of the first device 104-a and DL 116-b of the second device 104-b - for example, the first device 104-a and the second device 104-b can perform a handshake and send data based on the handshake.

[0034] Note that FIG. 300 illustrates an example and other examples are possible. In some embodiments, DL 116-b may perform more or fewer error decoding operations than indicated in FIG. 300 based on when flit 304 is received. For example, flit 304 may be received synchronously with frame "M" 302-a, and DL 116-b may determine the frame boundary after one (1) error decoding operation. In other examples, flit 304 may be received that is offset by one (1) flit from frame "M" 302-a. In such examples, DL 116-b may perform "N" error decoding operations - e.g., based on the "N" flits in the frame. That is, in most examples, DL 116-b may determine the frame boundary within the 1 to "N" received frames, where "N" is the number of flits in each frame. In some embodiments, based on random link errors, DL 116-b may determine the frame boundary after receiving "N" frames - e.g., within two (2) times "N" frames. Additionally, since each frame transmitted includes an embedded CRC, the likelihood that DL 116-a accepts corrupted or error-ridden data is reduced - e.g., each frame is protected by the CRC.

[0035] As described above, system 100 is two-way. Thus, DL 116-b may synchronize with DL 110-a independently and / or simultaneously with the synchronization of DL 116-a and DL 110-b. The synchronization of DL 116-a may be accomplished by the methods referenced Figure 3 described herein.

[0036] Figure 4 FIG. illustrates a flow chart of method 400 for synchronizing a high-speed signaling interconnect - e.g., synchronizing a local transmitter and a remote receiver. For example, method 400 illustrates using error decoding operations at the receiver to determine the frame boundary used by the transmitter. Method 400 may be performed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, method 400 is performed by Figure 1 DL 116-b of the receiver in the second device 104-b or DL 116-a of the receiver in the first device 104-a. In some embodiments, the receiver may receive from, respectively, as referenced Figure 2The DL 110-a or DL 110-b of the transmitter of the described first device 104-a or second device 104-b receives data, flits 202, bits, frames 200, etc. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise stated. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other diagrams illustrating the synchronization method are possible.

[0037] At operation 405, a transmitter (e.g., DL 110-a) in a first device (e.g., Figure 1 the first device 104-a) sends one or more request frames for synchronization of the data layer to a receiver (e.g., DL 116-b) of a second device (e.g., second device 104-b). In one embodiment, the request frames are sent via a link (e.g., link 106) coupling the first device and the second device. In some examples, the link is a GRS interconnect. In one embodiment, the request frames include a certain number of bits (e.g., flits) and error codes. In one embodiment, the transmitter sends a first request frame having first data and a first error code and a second request frame having second data and a second error code, the first error code being the same as the second error code.

[0038] At operation 410, the receiver of the second device receives a first set of bits. In one embodiment, the first set of bits corresponds to a certain number of bits in each request frame. That is, the receiver receives a certain number of bits having a width or size equal to that of each request frame.

[0039] At operation 415, the receiver performs an error decoding operation on the first set of bits using a portion of the first set of bits. In one embodiment, this portion of the first set of bits is the error code included in each request frame sent by the receiver. In one embodiment, the receiver performs a CRC operation on the first set of bits since each request frame includes a CRC value that is checked during the error decoding operation. In one embodiment, the receiver generates an error code based on the received first set of bits. In such an embodiment, the receiver compares the generated error code with the CRC code embedded in the first set of bits.

[0040] At operation 420, the receiver determines whether the first set of bits corresponds to a frame boundary. In one embodiment, the receiver determines that the first set of bits does not correspond to a frame boundary based on the failure of the error decoding operation at operation 415 - for example, based on the generated error code not matching the embedded CRC code in the first set of bits. In such an embodiment, the receiver proceeds to operation 425. In one embodiment, the receiver determines that the first set of bits does correspond to a frame boundary based on the success of the error decoding operation at operation 415. In such an embodiment, the receiver proceeds to operation 445.

[0041] At operation 425, the receiver inhibits performing an error decoding operation on a second set of bits received after the first set of bits (e.g., a flit, a set of bits less than the frame size, or a certain number of bits received during one clock cycle of the receiver). In one embodiment, the receiver ignores the second set of bits and does not consider the second set of bits as part of any frame for the error decoding operation. That is, the receiver performs an error decoding operation on a certain number of bits corresponding to the frame size, but does not consider the second set of bits as part of that number of bits that will undergo the error decoding operation - for example, the receiver does not generate an error code based on the second set of bits.

[0042] At operation 430, the receiver may receive a third set of bits from the transmitter and perform an error decoding operation on the third set of bits. In one embodiment, the third set of bits is received after the second set of bits. In one embodiment, the third set of bits has a certain number of bits corresponding to the frame size / width. In some examples, to perform the error decoding operation, the receiver may generate an error code for the received third set of bits and compare the generated error code with the CRC code embedded in the third set of bits.

[0043] At 435, the receiver may determine whether the third set of bits corresponds to a frame boundary. In one embodiment, the receiver determines that the third set of bits does not correspond to a frame boundary based on the failure of the error decoding operation at operation 430 - for example, based on the generated error code for the third set of bits not matching the CRC code embedded in the third set of bits. In such an embodiment, the receiver proceeds to operation 440. In an embodiment, the receiver determines that the third set of bits does correspond to a frame boundary based on the success of the error decoding operation at operation 430 - for example, based on the generated error code for the third set of bits matching the CRC code embedded in the third set of bits. In such an embodiment, the receiver proceeds to operation 445.

[0044] At operation 440, the receiver may repeat operations 425 - 435 until a frame boundary is found. In one embodiment, the receiver may skip a certain number of bits received having a size / width equal to that of the second set of bits (e.g., skip a certain number of bits received during a clock cycle) each time an error decoding operation is unsuccessful. As referenced Figure 3 as described, by skipping bits received during a clock cycle, the receiver will eventually determine the frame boundary based on the size of the first quantity of bits - e.g., within a frame of quantity "N". In such an embodiment, the receiver may continue to alternate between performing the error decoding operation and skipping bits received in the clock cycles following a failed error decoding operation until the frame boundary is determined - e.g., until an error code generated for a certain number of bits corresponding to the frame size matches the CRC code embedded in the corresponding requested frame. Thus, the receiver may proceed to operation 445 after determining the frame boundary.

[0045] At operation 445, the second device sends an acknowledgment of synchronization (e.g., an acknowledgment of determining the frame boundary) to the first device. In one embodiment, a transmitter of the second device (e.g., DL 110 - b) sends the acknowledgment to a receiver of the first device (e.g., DL 116 - a). In one embodiment, the second device generates the acknowledgment and transfers it from a receiver of the second device to the transmitter.

[0046] At operation 450, the first device ceases sending additional request frames based on receiving the acknowledgment. In one embodiment, the first device transfers the acknowledgment from a receiver of the first device to the transmitter.

[0047] At operation 455, the handshake between the first device and the second device is completed. In one embodiment, a transmitter of the first device sends a synchronization completion frame to a receiver of the second device based on receiving the acknowledgment. In one embodiment, the first device sends data to the second device after completing the handshake. In one embodiment, synchronization following the method described herein occurs independently / simultaneously between a transmitter of the second device and a receiver of the first device.

[0048] Figure 5 Illustrated is a computer system 500 according to at least one embodiment. In at least one embodiment, the computer system 500 may be a system having interconnected devices and components, an SOC, or some combination thereof. In at least one embodiment, the computer system 500 is formed by a processor 502, which may include execution units for executing instructions. In at least one embodiment, the computer system 500 may include, but is not limited to, components such as the processor 502 for performing algorithms for processing data using execution units including logic. In at least one embodiment, the computer system 500 may include a processor, such as Processor families, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessors, which are available from Intel Corporation in Santa Clara, California, but other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) may also be used. In at least one embodiment, computer system 500 may execute a version of the WINDOWS operating system available from Microsoft Corporation in Redmond, Washington, but other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0049] In at least one embodiment, computer system 500 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, Internet protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors (DSPs), SoCs, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that can execute one or more instructions. In one embodiment, computer system 500 may be used in devices such as graphics processing units (GPUs), network adapters, central processing units, and network devices (such as switches (e.g., high-speed direct GPU-to-GPU interconnects, such as NVIDIA GH100 NVLINK or NVIDIA Quantum2 64-port InfiniBand NDR switches)).

[0050] In at least one embodiment, computer system 500 may include, but is not limited to, a processor 502, and processor 502 may include, but is not limited to, one or more execution units 507, which may be configured to execute Compute Unified Device Architecture (“CUDA”)( A program developed by NVIDIA Corporation of Santa Clara, California). In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 500 is a single-processor desktop or server system. In at least one embodiment, the computer system 500 can be a multi-processor system. In at least one embodiment, the processor 502 can include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 502 can be coupled to a processor bus 510, which can transfer data signals between the processor 502 and other components in the computer system 500.

[0051] In at least one embodiment, the processor 502 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 504. In at least one embodiment, the processor 502 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can be located external to the processor 502. In at least one embodiment, the processor 502 can also include a combination of internal and external caches. In at least one embodiment, the register file 506 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0052] In at least one embodiment, an execution unit 507, including but not limited to logic for performing integer and floating-point operations, also resides in the processor 502. The processor 502 can also include a microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, the execution unit 502 can include logic for processing a packed instruction set 509. In at least one embodiment, by including the packed instruction set 509 in the instruction set of the general-purpose processor 502 along with the associated circuitry for executing the instructions, operations used by many multimedia applications can be performed using packed data in the general-purpose processor 502. In at least one embodiment, many multimedia applications can be more efficiently accelerated and executed by using the full width of the processor's data bus for performing operations on packed data, which can eliminate the need to transfer smaller data units through the processor's data bus to perform one or more operations on one data element at a time.

[0053] In at least one embodiment, the execution unit can also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 500 can include, but is not limited to, memory 520. In at least one embodiment, memory 520 can be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory devices. Memory 520 can store instructions 519 and / or data 521 represented by data signals that can be executed by processor 502.

[0054] In at least one embodiment, the system logic chip can be coupled to processor bus 510 and memory 520. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub (“MCH”) 516, and processor 502 can communicate with MCH 516 via processor bus 510. In at least one embodiment, MCH 516 can provide a high-bandwidth memory path 518 to memory 520 for instruction and data storage as well as storage of graphics commands, data, and textures. In at least one embodiment, MCH 516 can direct data signals among processor 502, memory 520, and other components in computer system 500 and bridge data signals among processor bus 510, memory 520, and system I / O 522. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 516 can be coupled to memory 520 via high-bandwidth memory path 518, and graphics / video card 512 can be coupled to MCH 516 via an Accelerated Graphics Port (“AGP”) interconnect 514.

[0055] In at least one embodiment, computer system 500 can couple MCH 516 to an I / O controller hub (“ICH”) 530 using system I / O 522 as a proprietary hub interface bus. In at least one embodiment, ICH 530 can provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 520, the chipset, and processor 502. Examples can include, but are not limited to, audio controller 529, firmware hub (“flash BIOS”) 528, wireless transceiver 526, data memory 524, a legacy I / O controller 523 that includes a user input interface 525 and a keyboard interface, a serial expansion port 527 (such as USB), and network controller 534. Data memory 524 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage devices. In one embodiment, wireless transceiver 526 includes a limited FFE 508.

[0056] In at least one embodiment, Figure 5 a system is illustrated that includes interconnected hardware devices or "chips" (e.g., the first device 104-a and the second device 104-b described with reference to Figure 1 ). In at least one embodiment, Figure 5 an exemplary SoC may be illustrated. In at least one embodiment, Figure 5 the devices shown in may be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof, and utilize the GRS link 106 described with reference to Figure 1 . In at least one embodiment, one or more components of the system 500 are interconnected using Compute Express Link ("CXL") interconnects.

[0057] Other variations are within the spirit of the present disclosure. Thus, although the disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments have been shown in the drawings and described in detail above. However, it is to be understood that the intention is not to limit the present disclosure to the one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative structures, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0058] Unless otherwise specified, the use of the terms "a," "an," "the," and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) will be construed to cover both the singular and the plural unless clearly contradicted by the context. The terms "comprising," "having," "including," and "containing" will be construed as open-ended terms (i.e., "including but not limited to") unless otherwise specified. "Connected," when unmodified and referring to a physical connection, shall be construed to mean partially or wholly incorporated in, attached to, or joined together, even if there are some intervening elements. Unless otherwise indicated herein, the recitation of numerical ranges herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were recited individually herein. In at least one embodiment, unless otherwise specified or clearly contradicted by the context, the use of the term "set" (e.g., "set of items") or "subset" will be construed to include a non-empty set of one or more members. Additionally, unless otherwise specified or clearly contradicted by the context, a "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but rather the subset and the corresponding set may be equal.

[0059] Unless otherwise expressly stated or clearly contradicted by the context, the disjunction of phrases such as “at least one of A, B, and C” or “at least one of A, B, and C” is otherwise understood to generally mean that the context in which items, terms, etc. may be A or B or C, or any non-empty subset of the set of A and B and C. For example, in an illustrative example in a set having three members, the disjunctive phrases “at least one of A, B, and C” and “at least one of A, B, and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such disjunctive language generally is not intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C, respectively. Further, unless otherwise stated or contradicted by the context, the term “plural” denotes a plural state (e.g., “a plurality of items” means a plurality of items). In at least one embodiment, the number of a plurality of items is at least two, but may be more when so indicated expressly or by context. Additionally, unless otherwise stated or clear from the context, the term “based on” means “at least partially based on” rather than “only based on”.

[0060] Unless otherwise specified herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, a process such as those described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) executed jointly on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, e.g., in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium does not include transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transient data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of the transient signal. In at least one embodiment, the code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media on which executable instructions (or other memory storing the executable instructions) are stored, and when executed by one or more processors of a computer system (i.e., as a result of being executed) causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more individual non-transitory storage media among the plurality of non-transitory computer-readable storage media lack all of the code, while the plurality of non-transitory computer-readable storage media together store all of the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors.

[0061] Thus, in at least one embodiment, a computer system is configured to implement one or more services that, individually or jointly, perform the operations of the processes described herein, and such a computer system is configured with suitable hardware and / or software capable of performing the operations. Further, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment, is a distributed computer system comprising a plurality of differently operating devices such that the distributed computer system performs the operations described herein and such that a single device does not perform all of the operations.

[0062] Any and all uses of example or exemplary language (e.g., "such as") provided herein are merely intended to better illustrate embodiments of the present disclosure and do not pose a limitation on the scope of the present disclosure unless otherwise stated. No language in the specification should be construed as indicating that any non-claimed element is essential for the practice of the present disclosure.

[0063] All references cited herein, including publications, patent applications, and patents, are incorporated herein by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and set forth in full herein.

[0064] In the description and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms are not necessarily intended as synonyms for each other. Rather, in a particular example, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0065] Unless otherwise expressly stated, it is understood that terms such as "processing", "computing", "calculating", "determining", etc. throughout the specification refer to actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or transform data represented as physical quantities (such as electronic quantities) in the registers and / or memory of the computing system into other data similarly represented as physical quantities in the memory, registers, or other such information storage of the computing system, transmission, or display device.

[0066] In a similar manner, the term "processor" can refer to any device or portion of a device that processes electronic data from registers and / or memory and transforms that electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Additionally, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" may be used interchangeably herein, provided that a system can embody one or more methods and a method can be considered a system.

[0067] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving the data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data may be implemented by taking the data as an input or output parameter of a function call, an application programming interface, or a parameter of an interprocess communication mechanism.

[0068] Although the description herein sets forth example embodiments of the described techniques, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. Additionally, although specific assignments of responsibilities may be defined above for purposes of description, the various functions and responsibilities may be assigned and partitioned in different ways depending on the circumstances.

[0069] Moreover, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims need not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A system, comprising: A first device coupled to a link and including a transmitter, the first device being configured to: transmit one or more request frames to a synchronization data layer, each request frame including a certain number of bits and an error code; And A second device coupled to the link and including a receiver and the data layer, the second device being configured to: Receive a first set of bits corresponding to the number of bits in each of the one or more request frames; Perform an error decoding operation on the first set of bits using a first portion of the received first set of bits; In response to a successful error decoding operation, determine that the first set of bits corresponds to a frame boundary of the one or more request frames; And Transmit an acknowledgement of synchronization to the data layer at least in part based on determining that the first set of bits corresponds to the frame boundary.

2. The system according to claim 1, wherein the first device further includes a receiver, and the first device is further configured to: Receive the acknowledgement of synchronization; and Based on receiving the acknowledgement, refrain from transmitting a request for synchronization.

3. The system according to claim 2, wherein the first device is further configured to: Based on receiving the acknowledgement, transmit a synchronization completion frame to the second device indicating completion of synchronization of the data layer; Transmit data from the first device to the second device at least in part based on transmitting the synchronization completion frame.

4. The system according to claim 1, wherein, in order to perform the error decoding operation, the second device is further configured to: Generate a second error code for the first set of bits based on receiving the first set of bits; Compare the second error code with the first portion of the first set of bits, wherein determining that the first set of bits corresponds to a frame boundary of the one or more request frames is at least in part based on the comparison.

5. The system according to claim 4, wherein the portion of the first set of bits corresponds to the error code of each request frame.

6. The system according to claim 1, wherein: The second device further includes a transmitter, and the second device is configured to: Transmit a second set of one or more request frames to synchronize a second data layer, each request frame including a second number of bits and a second error code; and The first device further includes a receiver, and the first device is configured to: Receive a second set of bits corresponding to the second number of bits in each of the second set of one or more request frames; Perform a second error decoding operation on the second set of bits using a second portion of the received second set of bits; In response to a successful error decoding operation, determine that the second set of bits corresponds to a second frame boundary of the second set of one or more request frames; And Transmit a second acknowledgement of synchronization of the second data layer at least in part based on determining that the second set of bits corresponds to the second frame boundary.

7. The system according to claim 6, wherein the second set of one or more request frames is transmitted simultaneously with the one or more request frames.

8. The system according to claim 7, wherein one or more request frames are sent during a first duration, and the second set of one or more request frames are sent during a second duration, the first duration being different from the second duration.

9. A method, comprising: receiving, by a first device, a first set of bits, wherein the number of bits in the first set of bits corresponds to a frame size; at the first device, performing an error decoding operation on the first set of bits using a portion of the first set of bits; in response to a successful error decoding operation, determining that the first set of bits corresponds to a frame boundary of a frame; and transmitting an acknowledgement to a synchronization data layer at least in part based on determining that the first set of bits corresponds to the frame boundary.

10. The method according to claim 9, wherein prior to determining that the first set of bits corresponds to the frame boundary, the method further comprises: receiving a second set of bits, wherein a second number of bits in the second set of bits corresponds to the frame size, and wherein at least some bits are common to the first set of bits and the second set of bits; performing the error decoding operation on the second set of bits using a portion of the second set of bits; and in response to a failure of the error decoding operation, determining that the second set of bits does not correspond to the frame boundary.

11. The method according to claim 10, further comprising: receiving a third set of bits after receiving the second set of bits, wherein the third set of bits comprises a third number of bits that is less than the number of bits corresponding to the frame size; and refraining from performing the error decoding operation on the third set of bits based on the failure of the error decoding operation, wherein the first set of bits is received after receiving the third set of bits.

12. The method according to claim 11, wherein the third set of bits is received during one clock cycle of the first device.

13. The method according to claim 11, wherein the second set of bits is received during two or more clock cycles of the first device.

14. The method according to claim 9, wherein in order to perform the error decoding operation, the method further comprises: generating an error code associated with the first set of bits at least in part based on receiving the first set of bits; and comparing the error code with the portion of the first set of bits.

15. The method according to claim 14, wherein determining that the first set of bits corresponds to the frame boundary of the frame further comprises: determining that the error code matches the portion of the first set of bits.

16. A device, comprising: a receiver coupled to a link, the receiver for: receiving a first set of bits, wherein the number of bits in the first set of bits corresponds to a frame size; and a controller coupled to the receiver, the controller for: performing an error decoding operation on the first set of bits using a portion of the first set of bits; in response to a successful error decoding operation, determining that the first set of bits corresponds to a frame boundary of a frame; and Generate an acknowledgment of the synchronization data layer, at least in part based on determining that the first set of bits corresponds to the frame boundary.

17. The apparatus according to claim 16, further comprising: A transmitter coupled to the link, the transmitter for: Send an acknowledgment of synchronizing the data layer to a second device.

18. The apparatus according to claim 17, wherein the receiver is further for: Receive a synchronization completion frame indicating completion of synchronization of the data layer, at least in part based on sending the acknowledgment to the second device.

19. The apparatus according to claim 16, wherein: The receiver is further for: Receive a second set of bits, wherein a second number of bits in the second set of bits corresponds to the frame size, and wherein at least some bits are common to the first set of bits and the second set of bits; and The controller is further for: Perform the error decoding operation on the second set of bits using a portion of the second set of bits; And In response to a failure of the error decoding operation, determine that the second set of bits does not correspond to the frame boundary.

20. The apparatus according to claim 19, wherein: The receiver is further for: Receive a third set of bits after receiving the second set of bits, wherein the third set of bits includes a third number of bits less than the number of bits corresponding to the frame size; and The controller is further for: Based on the failure of the error decoding operation, refrain from performing the error decoding operation on the third set of bits, wherein the first set of bits is received after receiving the third set of bits.

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