Microelectronic devices and related memory devices and electronic systems

Abstract

This application relates to microelectronic devices, memory devices, and electronic systems. A microelectronic device includes a base structure, a memory array over the base structure, and a conductive liner level over the memory array. The base structure includes a logic region including a logic device. The memory array includes vertically-extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive liner level includes a first conductive liner substantially outside the horizontal area of the logic region of the base structure and a second conductive liner horizontally adjacent the first conductive liner and within the horizontal area of the logic region of the base structure.

Description

[0001] Priority requirements

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 445,045, filed on August 13, 2021, entitled “Microelectronic Devices, and Related Memory Devices and Electronic Systems”. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] Microelectronic device designers typically aim to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, they often seek architectures that are not only compact but also offer performance advantages, as well as simplified designs that are easier and cheaper to manufacture.

[0005] An example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. Many types of memory devices exist, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also known as a “three-dimensional (3D) memory array”) architecture. A conventional vertical memory array comprises strings of memory cells extending vertically through a stacked structure containing layers of conductive and insulating materials. Each string of memory cells may contain at least one selection device that is series-coupled to a series combination of memory cells in the vertical stack. Compared to structures with a conventional planar (e.g., two-dimensional (2D)) transistor arrangement, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0006] In conventional nonvolatile memory devices (e.g., conventional 3D NAND flash memory devices), a die (e.g., a semiconductor die) containing a vertical memory array and associated internal circuitry is electrically connected to the external circuitry of a relatively large assembly (e.g., an electronic package, such as an integrated circuit (IC) package) by means of bonding pads positioned along the die periphery and bonding wires extending between the bonding pads and conductive contacts (e.g., leads) coupled to the external circuitry. However, conventional bonding pad configurations may hinder improvements in the performance of nonvolatile memory devices and / or may hinder reductions in the feature size (e.g., horizontal area) of the nonvolatile memory device. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a substrate structure; a memory array disposed on the substrate structure; and a conductive pad layer disposed on the memory array. The substrate structure includes a logic region comprising logic devices. The memory array includes a vertically extending string of memory cells within a horizontal region of the logic region of the substrate structure. The conductive pad layer includes: a first conductive pad substantially outside the horizontal region of the logic region of the substrate structure; and a second conductive pad horizontally adjacent to the first conductive pad and within the horizontal region of the logic region of the substrate structure.

[0008] In an additional embodiment, a memory device includes a substrate structure, conductive wiring layers, a stacked structure, a memory array, additional conductive wiring layers, conductive contacts, a first conductive pad, and a second conductive pad. The substrate structure includes a region containing a complementary metal-oxide-semiconductor (CMOS) circuit system, and an additional region horizontally adjacent to the region and substantially without the CMOS circuit system. The conductive wiring layers are located above the substrate structure. The stacked structure is located above the conductive wiring layers and includes a conductive material and an insulating material vertically alternating with the conductive material. The memory array includes strings of memory cells extending through the stacked structure. The memory array is located within a horizontal region of the region of the substrate structure. The additional conductive wiring layers are located above the stacked structure. The conductive contacts are horizontally offset from the memory array and extend between the conductive wiring layers and the additional conductive wiring layers. The first conductive pad is located above the additional conductive wiring layers and within a horizontal region of the additional region of the substrate structure. The first conductive pad is electrically connected to some of the conductive contacts. The second conductive pad is located above the additional conductive wiring layers and horizontally inserted between the first conductive pad and at least some of the strings of memory cells in the memory array. The second conductive pad is electrically connected to some of the other conductive contacts.

[0009] In another embodiment, an electronic system includes: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device. The memory device includes a stacked structure, a substrate structure, a memory array, and bonding pads. The stacked structure includes conductive structures vertically intersecting with an insulating structure. The substrate structure is vertically located below the stacked structure and includes a logic region containing a logic circuit system. The memory array includes strings of memory cells extending vertically through the stacked structure. The memory array is positioned within a horizontal region of the logic region of the substrate structure. Bonding pads, vertically located above the stacked structure, are electrically connected to the logic circuit system. The bonding pads include a first bonding pad and a second bonding pad. The first bonding pad is positioned outside the horizontal region of the logic region of the substrate structure. The second bonding pad is positioned within the horizontal region of the logic region of the substrate structure. Attached Figure Description

[0010] Figure 1A This is a simplified partial cross-sectional view of a microelectronic device according to an embodiment of the present disclosure.

[0011] Figure 1B for Figure 1A A simplified top view of a portion of the microelectronic device shown in the image.

[0012] Figure 2 This is a simplified partial top view of a portion of a microelectronic device according to an additional embodiment of the present disclosure.

[0013] Figure 3 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0014] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In practice, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions for forming a complete microelectronic device according to the structures can be performed using conventional manufacturing techniques.

[0015] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Shapes expected to be depicted in the drawings may vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape variations, for example, due to manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, common elements between the drawings may retain the same numerical designation.

[0016] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory, such as conventional NAND memory; conventional volatile memory, such as conventional DRAM), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory of microelectronic devices, and graphics processing units (GPUs) incorporating memory.

[0017] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and the device.

[0018] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the reference structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0019] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) mean and include features with one or more disclosed identifiers that are most closely (e.g., closest) to each other. Additional features (e.g., additional areas, additional structures, additional devices) with one or more disclosed identifiers that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features disclosed by one or more identifiers located at the vertical closest (e.g., vertically closest) to each other. Furthermore, features described as “horizontally adjacent” to each other mean and include features of one or more disclosed identifiers located at the horizontal closest (e.g., horizontally closest) to each other.

[0020] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” are used for ease of description to describe the relationship between one element or feature and another element or feature illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, then an element described as “below,” “under,” “below,” or “bottom” of another element or feature will be oriented “above” or “top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0021] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” also implicitly include the plural forms.

[0022] As used in this article, “and / or” includes any and all combinations of one or more of the associated listed items.

[0023] As used in this article, the phrase “coupled to” refers to structures that are operatively connected to each other (e.g., by direct ohmic connection or by indirect connection (e.g., by means of another structure)).

[0024] As used herein, the term "generally" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to deviations (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, property, or condition that is generally satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0025] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0026] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, Fe-based alloys) The term "conductive structure" refers to and includes structures formed from and containing conductive materials, such as gold, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel. It also includes conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides) and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from conductive materials and containing conductive materials.

[0027] As used herein, “insulating material” means and includes one or more of the following electrically insulating materials: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). xPhosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following); at least one dielectric nitride material (e.g., silicon nitride (SiN) y At least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO2)). x N y At least one dielectric carbon oxide material (e.g., silicon oxycarbonate (SiO2)). x C y At least one hydrogenated dielectric carbon oxide material (e.g., hydrogenated silicon carbide (SiC)). x O y H z )); and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2) x C z N y This document contains one or more of the chemical formulas “x”, “y”, and “z” (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C y SiC x O y H z SiO x C z N yA chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because a chemical formula represents relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of an element that cannot be expressed by a ratio of well-defined natural numbers and violates the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0028] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art. Additionally, unless the context otherwise indicates, the removal of the material described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0029] Figure 1A A simplified partial cross-sectional view of a microelectronic device 100 (e.g., a semiconductor device; a memory device, such as a 3D NAND flash memory device) according to an embodiment of the present disclosure. Figure 1B for Figure 1A The diagram shows a simplified partial top view of part A of the microelectronic device 100. For clarity and ease of understanding of the diagrams and related descriptions, Figure 1B Not depicted in the middle Figure 1A All components (e.g., features, structures, devices) of the microelectronic device 100 depicted herein. For example, Figure 1B Some components of the microelectronic device 100 that are vertically positioned above other components of the microelectronic device 100 are not shown in order to provide a clearer top view of the other components.

[0030] refer to Figure 1AThe microelectronic device 100 includes a die 101 that includes a memory array region 102 and a contact region 104 (e.g., a deep contact region) horizontally adjacent to the memory array region 102 (e.g., in the X direction). In some embodiments, the contact region 104 is located at or near the outer horizontal boundary (e.g., peripheral boundary, outer periphery) of the die 101, and the memory array region 102 is horizontally located within the contact region 104. The memory array region 102 may be horizontally inserted (e.g., in the X direction) between the contact region 104 and one or more other regions (e.g., additional contact regions, such as access line contact regions) of the die 101. As described in further detail below, the die 101 of the microelectronic device 100 includes various features (e.g., materials, structures, devices) within the horizontal regions of its different horizontal regions (e.g., memory array region 102, contact region 104).

[0031] like Figure 1A As shown, the die 101 of the microelectronic device 100 may include: a substrate structure 106; at least one first conductive wiring layer 108 including (e.g., in the Z direction) a first conductive wiring structure 110 vertically located above the substrate structure 106; a stack structure 112 vertically located above the first conductive wiring layer 108; at least one second conductive wiring layer 114 including a second conductive wiring structure 116 vertically located above the stack structure 112; at least one third conductive wiring layer 118 including a third conductive wiring structure 120 vertically located above the second conductive wiring layer 114; and at least one conductive pad layer 122 including a conductive pad 124 (e.g., a bonding pad) vertically located above the third conductive wiring layer 118. The die 101 of the microelectronic device 100 may also include cell pillar structures 126 within its memory array region 102 and contact structures 128 (e.g., deep contact structures) within its contact region 104. The foregoing features of the microelectronic device 100 are further described in detail below. The microelectronic device 100 further includes additional features, which are described in further detail below.

[0032] The substrate structure 106 includes a substrate material or construction on which additional features (e.g., materials, structures, devices) of the microelectronic device 100 are formed. The substrate structure 106 may include a substrate semiconductor material on a semiconductor structure (e.g., a semiconductor wafer) or a support structure. For example, the substrate structure 106 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate comprising semiconductor material. In some embodiments, the substrate structure 106 includes a silicon wafer. The substrate structure 106 may be formed to include different regions, materials, structures, and / or devices therein and / or on it.

[0033] like Figure 1AAs shown, substrate structure 106 may include at least one logic region 130 (also referred to herein as at least one “active region” or at least one “first region”) and at least one additional region 132 (also referred to herein as at least one “non-active region” or at least one “second region”) horizontally adjacent to logic region 130. Logic region 130 may contain logic devices and may be located at least partially within the horizontal boundary (e.g., within a horizontal region) of memory array region 102 of die 101 of microelectronic device 100. In some embodiments, logic region 130 of substrate structure 106 further extends horizontally into contact region 104 of die 101 of microelectronic device 100. Additional region 132 may not contain logic devices and may be located at least partially within the horizontal boundary (e.g., within a horizontal region) of contact region 104 of contact region 104 of die 101 of microelectronic device 100. In some embodiments, additional region 132 of substrate structure 106 is substantially confined within contact region 104 of die 101 of microelectronic device 100.

[0034] Logic devices within the logic region 130 of the substrate structure 106 are configured to control various operations of the microelectronic device 100. The logic devices are formed by and contain logic circuit systems. In some embodiments, at least some of the logic devices within the logic region 130 are formed by and contain complementary metal-oxide-semiconductor (CMOS) circuit systems. As a non-limiting example, the logic devices contained within the logic region 130 of the substrate structure 106 may include charge pumps (e.g., V0). CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delayed-locked loop (DLL) circuit systems (e.g., ring oscillators), drain supply voltage (V) ddThis includes one or more (e.g., each) of regulators, string drivers, page buffers, and various chip / stack control circuitry systems. As another non-limiting example, the logic devices contained within the logic region 130 of the substrate structure 106 may include means configured to control column operations of an array (e.g., a memory array) within the memory array region 102 of the die 101 of the microelectronic device 100, such as decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry systems (e.g., column repair circuitry systems), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices (e.g., each). As another non-limiting example, the logic devices included in the logic region 130 of the substrate structure 106 may include means configured to control row operations of an array (e.g., a memory array) within the memory array region 102 of the die 101 of the microelectronic device 100, such as a decoder (e.g., a local stack decoder, a row decoder), a driver (e.g., a word line (WL) driver), a repair circuit system (e.g., a row repair circuit system), a memory test device, a MUX, an ECC device, and a self-refresh / wear-out equalization device (e.g., each of these).

[0035] The logic region 130 of the substrate structure 106 may be divided into several (e.g., multiple) logic sub-regions 134. At least some of the logic sub-regions 134 may contain logic devices of a different type than at least some of the others in the logic sub-region 134. As a non-limiting example, one or more of the logic sub-regions 134 may contain a charge pump (e.g., V0). CCP Charge pump, V NEGWLA pump subregion (e.g., a charge pump, DVC2 charge pump). At least some of the other logical subregions 134 may not have a charge pump. As another non-limiting example, one or more of the logical subregions 134 may be driver subregions containing driver devices (e.g., string driver devices). At least some of the other logical subregions 134 may not have driver devices. As an additional non-limiting example, one or more of the logical subregions 134 may be memory cache subregions containing buffer devices (e.g., page buffer devices). At least some of the other logical subregions 134 may not have buffer devices. As another non-limiting example, one or more of the logical subregions 134 may be decoder subregions containing decoder devices. At least some of the other logical subregions 134 may not have decoder devices. As yet another non-limiting example, one or more of the logical subregions 134 may be sense amplifier subregions containing sense amplifier devices. At least some of the other logical subregions 134 may not have sense amplifier devices.

[0036] Continue to refer to Figure 1A The first conductive wiring layer 108 may be vertically inserted between the substrate structure 106 and the stack structure 112. The first conductive wiring structure 110 of the first conductive wiring layer 108 may include at least one source structure 110A (e.g., a source plate) within the memory array region 102 of the die 101 of the microelectronic device 100, and a contact pad 110B within the contact region 104 of the die 101 of the microelectronic device 100. The source structure 110A and the contact pad 110B may be horizontally adjacent to each other within the first conductive wiring layer 108 (e.g., in the X direction and in the Y direction). The source structure 110A may be electrically isolated from the contact pad 110B and may be positioned at substantially the same vertical position as the contact pad 110B (e.g., in the Z direction). At least one insulating material may be inserted between the source structure 110A and the contact pad 110B of the first conductive wiring layer 108.

[0037] The first conductive wiring structure 110 of the first conductive wiring layer 108 (including source structure 110A and contact pad 110B) may be formed of and contain conductive materials. In some embodiments, the first conductive wiring structure 110 is formed of and contains one or more of the following: metals, alloys, and conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the first conductive wiring structure 110 may be formed of and contain W. In additional embodiments, the first conductive wiring structure 110 is formed of and contains conductive doped semiconducting materials, such as one or more conductive doping forms of silicon materials, such as single-crystal silicon or polycrystalline silicon; silicon-germanium materials; germanium materials; gallium arsenide materials; gallium nitride materials; and indium phosphide materials. As a non-limiting example, the first conductive wiring structure 110 may be formed of and comprise silicon (e.g., polycrystalline silicon) doped with at least one dopant (e.g., at least one n-type dopant, at least one p-type dopant, and at least one or more other dopants).

[0038] At least some of the first conductive wiring structures 110 of the first conductive wiring layer 108 may be individually coupled to logic devices within the logic region 130 of the substrate structure 106. Additionally, at least some of the first conductive wiring structures 110 (e.g., source structures 110A) may also be individually coupled to cell pillar structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the source structures 110A of the first conductive wiring layer 108 are in direct physical contact with the cell pillar structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. In an additional embodiment, contact structures are vertically interposed between at least some of the source structures 110A and the cell pillar structures 126. Furthermore, at least some of the first conductive wiring structures 110 (e.g., at least some of the contact pads 110B) may be individually coupled to at least some of the contact structures 128 within the contact region 104 of the die 101 of the microelectronic device 100. In some embodiments, the contact pads 110B of the first conductive wiring layer 108 are directly physically contact-coupled to the contact structure 128 of the contact pads. In an additional embodiment, additional contact structures are vertically interposed between at least some of the contact pads 110B and at least some of the contact structures 128 coupled to the contact pads.

[0039] Still referencing Figure 1AThe stacked structure 112 of the die 101 of the microelectronic device 100 may be formed vertically above the first conductive wiring layer 108 and may include a series of vertically alternating conductive structures 136 and insulating structures 138 arranged in layers 140 (e.g., in the Z direction). Each of the layers 140 of the stacked structure 112 may include at least one of the conductive structures 136 that are vertically adjacent to at least one of the insulating structures 138. The stacked structure 112 may be formed to include any desired number of layers 140, such as more than or equal to sixteen (16) layers 140, more than or equal to thirty-two (32) layers 140, more than or equal to sixty-four (64) layers 140, more than or equal to one hundred and twenty-eight (128) layers 140, or more than or equal to two hundred and fifty-six (256) layers 140.

[0040] The conductive structure 136 of the layer 140 of the stacked structure 112 may be formed of and contain a conductive material. By way of non-limiting examples, each of the conductive structures 136 may be individually formed of and contain a metallic material comprising one or more of the following: at least one metal, at least one alloy, and at least one conductive metallic material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structure 136 is formed of and contains W. Each of the conductive structures 136 may be individually substantially homogeneous, or one or more of the conductive structures 136 may be individually substantially heterogeneous. In some embodiments, each of the conductive structures 136 is formed substantially homogeneous. In additional embodiments, each of the conductive structures 136 is formed heterogeneous. Each conductive structure 136 may, for example, be formed of and contain a stack of at least two different conductive materials.

[0041] At least one vertically lower (e.g., in the Z direction) conductive structure 136 of the stacked structure 112 may serve as at least one first select gate (e.g., at least one source-side select gate (SGS)) within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the first conductive structure 136 of the vertically lowermost layer 140 of the stacked structure 112 serves as a first select gate (e.g., SGS) within the memory array region 102. Additionally, one or more vertically upper (e.g., in the Z direction) conductive structures 136 of the stacked structure 112 may serve as second select gates (e.g., drain-side select gates (SGD)) within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the horizontally adjacent (e.g., in the Y direction) conductive structures 136 of the vertically uppermost layer 140 of the stacked structure 112 serve as second select gates (e.g., SGD) within the memory array region 102.

[0042] Optionally, one or more lining materials (e.g., insulating lining materials, conductive lining materials) may also be formed around the conductive structure 136. The lining materials may be formed from, for example, one or more of the following and include one or more of the following: metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the lining material includes at least one conductive material used as a seed material for forming the conductive structure 136. In some embodiments, the lining material includes titanium nitride. In other embodiments, the lining material further includes aluminum oxide. As a non-limiting example, aluminum oxide may be formed directly adjacent to the insulating structure 138, titanium nitride may be formed directly adjacent to aluminum oxide, and tungsten may be formed directly adjacent to titanium nitride. For clarity and ease of understanding of the description, Figure 1A The lining material is not specified, but it should be understood that the lining material may be placed around the conductive structure 136.

[0043] The insulating structure 138 of the layer 140 of the stacked structure 112 may be formed of and contain at least one insulating material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y In some embodiments, each of the insulating structures 138 is made of, for example, SiO2. x The insulating structure 138 is formed and comprises a dielectric oxide material such as (e.g., SiO2). Each of the insulating structures 138 may be individually substantially homogeneous or substantially heterogeneous. In some embodiments, each of the insulating structures 138 is substantially homogeneous. In other embodiments, at least one of the insulating structures 138 is substantially heterogeneous. One or more of the insulating structures 138 may be formed and comprise, for example, a stack (e.g., lamination) of at least two different insulating materials.

[0044] like Figure 1AAs shown, in some embodiments, the stacked structure 112 does not extend substantially horizontally into the contact area 104 of the die 101 of the microelectronic device 100. In other words, the contact area 104 may not have the stacked structure 112 substantially in its horizontal region. In such embodiments, the contact structure 128 within the contact area 104 may extend vertically through at least one additional insulating material (e.g., at least one dielectric oxide material, such as SiO2) horizontally adjacent to the stacked structure 112. x At least one dielectric nitride material, such as SiN y And is horizontally surrounded by the at least one additional insulating material. Within the contact area 104, the additional insulating material may extend vertically, for example, from the first conductive wiring layer 108 and the second conductive wiring layer 114, and between the first conductive wiring layer 108 and the second conductive wiring layer 114. In an additional embodiment, the stack structure 112 extends horizontally into the contact area 104 of the die 101 of the microelectronic device 100. In some such embodiments, at least some of the contact structures 128 within the contact area 104 may extend vertically through the stack structure 112 and be horizontally surrounded by the stack structure 112.

[0045] Continue to refer to Figure 1A The unit pillar structure 126 may extend vertically through the layers 140 of the stacked structure 112. Each unit pillar structure 126 may be individually formed by and contain a stack of materials. By means of a non-limiting example, each of the unit pillar structures 126 may be formed to include: a charge-blocking material, such as a first dielectric oxide material (e.g., SiO2). x For example, SiO2; AlO x (e.g., Al2O3); charge trapping materials, such as dielectric nitride materials (e.g., SiN). y (e.g., Si3N4); tunneling dielectric materials, such as second oxide dielectric materials (e.g., SiO2). x The channel material is a semiconducting material (e.g., silicon, such as polycrystalline Si); and the dielectric filling material is a dielectric oxide, dielectric nitride, or air. A charge-blocking material may be formed on or above the conductive structure 136 and insulating structure 138 of the layer 140 of the stacked structure 112, which at least partially defines the horizontal boundary of the unit pillar structure 126; a charge-trapping material may be horizontally surrounded by the charge-blocking material; a tunneling dielectric material may be horizontally surrounded by the charge-trapping material; a channel material may be horizontally surrounded by the tunneling dielectric material; and a dielectric filling material may be horizontally surrounded by the channel material.

[0046] The intersection of the cell pillar structure 126 and the conductive structure 136 of the layer 140 of the stacked structure 112 may define a vertically extending string of memory cells 142 coupled in series with each other within the stacked structure 112. In some embodiments, the memory cells 142 formed at the intersection of the conductive structure 136 and the cell pillar structure 126 within different layers 140 of the stacked structure 112 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 142 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In another embodiment, the memory cells 142 include so-called "floating gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally interposed between the central structures of the cell pillar structure 126 and the conductive structure 136 of the different layers 140 of the stacked structure 112. The vertically extending strings of memory cells 142 together form a memory array within the stacked structure 112.

[0047] Still referencing Figure 1A Contact structures 128 within contact areas 104 of the die 101 of the microelectronic device 100 can be configured and positioned to electrically connect one or more features (e.g., structures, materials, devices) of the microelectronic device 100 vertically located above the stacked structure 112 to one or more additional features of the microelectronic device 100 vertically located below the stacked structure 112. For example, contact structures 128 within contact areas 104 can electrically connect at least some of the first conductive wiring structures 110 of the first conductive wiring layer 108 vertically located below the stacked structure 112 to at least some of the second conductive wiring structures 116 of the second conductive wiring layer 114 vertically located above the stacked structure 112. Contact structures 128 may be individually formed of and contain at least one conductive material. In some embodiments, contact structures 128 are formed of and contain W. In additional embodiments, contact structures 128 are formed of and contain conductive-doped polysilicon.

[0048] In an embodiment where the stacked structure 112 extends horizontally into the contact area 104 of the die 101 of the microelectronic device 100, an insulating liner structure extends substantially continuously above and substantially covers at least some of the side surfaces of the contact structures 128. The insulating liner structure may be horizontally inserted between the contact structures 128 and the conductive structure 136 (and insulating structure 138) of the layer 140 of the stacked structure 112. The insulating liner structure may be formed of and comprise at least one insulating material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y In additional embodiments, such as those in which the stacked structure 112 does not extend horizontally into the contact area 104 of the die 101 of the microelectronic device 100, the insulating liner structure does not extend substantially continuously above and substantially cover the side surface of the contact structure 128. In some such embodiments, the contact structure 128 directly and physically contacts additional insulating material horizontally adjacent to the stacked structure 112 and extends vertically through the additional insulating material.

[0049] Still referencing Figure 1AThe second conductive wiring layer 114 may be vertically inserted between the stacked structure 112 and the third conductive wiring layer 118. The second conductive wiring structure 116 of the second conductive wiring layer 114 may include a digital line structure 116A (e.g., a bit line structure, a data line structure) within the memory array region 102 of the die 101 of the microelectronic device 100, and additional contact pads 116B within the contact region 104 of the die 101 of the microelectronic device 100. The digital line structure 116A and the additional contact pads 116B may be horizontally adjacent to each other within the second conductive wiring layer 114 (e.g., in the X direction, in the Y direction). The digital line structure 116A may be electrically isolated from the additional contact pads 116B and may be positioned at substantially the same vertical position as the additional contact pads 116B (e.g., in the Z direction). At least one insulating material may be inserted between the source structure 110A and the contact pads 110B of the second conductive wiring layer 114.

[0050] The second conductive wiring structure 116 of the second conductive wiring layer 114 (including digital line structure 116A and additional contact pads 116B) may be formed of and contain conductive materials. In some embodiments, the second conductive wiring structure 116 is formed of and contains one or more of the following: metals, alloys, and materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the second conductive wiring structure 116 may be formed of and contain W.

[0051] Some of the second conductive wiring structures 116 (e.g., digital line structures 116A) may be individually coupled to cell pillar structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the digital line structures 116A of the second conductive wiring layer 114 are electrically connected to the cell pillar structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. Conductive contact structures may be vertically interposed between and electrically connect at least some of the digital line structures 116A and at least some of the cell pillar structures 126. Additionally, some of the second conductive wiring structures 116 (e.g., at least some of the additional contact pads 116B) may be individually coupled to at least some of the contact structures 128 within the contact region 104 of the die 101 of the microelectronic device 100. In some embodiments, the additional contact pad 116B of the second conductive wiring layer 114 is electrically connected to the contact structure 128 within the contact area 104 of the die 101 of the microelectronic device 100. The additional contact pad 116B may be directly physically contact-coupled to the contact structure 128 of the additional contact pad, or another conductive contact structure may be vertically inserted between the additional contact pad 116B and at least some of the contact structures 128 and electrically connect the additional contact pad 116B and at least some of the contact structures 128.

[0052] Continue to refer to Figure 1A Within the third conductive wiring layer 118, which is vertically located above the second conductive wiring layer 114, some of the third conductive wiring structures 120 may be at least partially positioned within the memory array region 102 of the die 101 of the microelectronic device 100, and some others of the third conductive wiring structures 120 may be positioned within the contact region 104 of the die 101 of the microelectronic device 100. For example... Figure 1A As shown, at least some of the third conductive wiring structures 120 can be electrically connected by means of contact structure 144 to at least some of the second conductive wiring structures 116 of the second conductive wiring layer 114 (e.g., digital line structure 116A, additional contact pad 116B).

[0053] The third conductive wiring structure 120 of the third conductive wiring layer 118 may be formed of and contain conductive materials. In some embodiments, the third conductive wiring structure 120 is formed of and contains one or more of the following: metals, alloys, and conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the third conductive wiring structure 120 may be formed of and contain Cu. As another non-limiting example, the third conductive wiring structure 120 may be formed of and contain W.

[0054] Although Figure 1A The die 101 of the microelectronic device 100 is depicted as including a single (e.g., only one) third conductive wiring layer 118 containing a third conductive wiring structure 120, but the die 101 of the microelectronic device 100 may be formed to include multiple (e.g., more than one) third wiring layers 118, each individually containing a desired arrangement (e.g., pattern) of the third conductive wiring structure 120. By a non-limiting example, the die 101 of the microelectronic device 100 may be formed to include two or more (e.g., three or more) of the third wiring layers 118, wherein the different third wiring layers 118 are vertically offset from each other and each individually contains a desired arrangement of the third conductive wiring structure 120. At least some of the third conductive wiring structures 120 within at least one of the third wiring layers 118 may be coupled to at least some of the third conductive wiring structures 120 within at least one other of the third wiring layers 118 by means of a conductive interconnect structure.

[0055] Still referencing Figure 1A Within the conductive pad layer 122, which is vertically located above the third conductive wiring layer 118, conductive pads 124 (e.g., bonding pads) may include a first conductive pad 124A (e.g., a first bonding pad) positioned outside (e.g., outside the horizontal region) the horizontal boundary of the memory array region 102 of the die 101 of the microelectronic device 100, and a second conductive pad 124B (e.g., a second bonding pad) positioned at the horizontal boundary of the memory array region 102 of the die 101 of the microelectronic device 100 and / or at least partially within said horizontal boundary (e.g., at or at least partially within said horizontal region). The configuration and location of the conductive pads 124 of the conductive pad layer 122 are further described in detail below, including the configuration and location of the first conductive pads 124A and the second conductive pads 124B relative to each other and relative to other features of the microelectronic device 100.

[0056] like Figure 1A As shown, conductive pads 124 can be coupled to at least some of the third conductive wiring structures 120 of the third conductive wiring layer 118. At least some of the conductive pads 124, including at least some of the first conductive pads 124A and at least some of the second conductive pads 124B, can be configured to receive global signals from conductive lines 146 (e.g., bonding wires) coupled to the conductive pads and relay the global signals to the third conductive wiring structure 120 coupled to the conductive pads. By means of a non-limiting example, the global signals may include power (e.g., power supply) signals (e.g., power supply voltage (V)). cc Signal, ground (V) ssOne or more of the following: signals, data signals (e.g., input / output (I / O) signals), and control signals. In some embodiments, at least some of the conductive pads 124, including at least some of the first conductive pads 124A and at least some of the second conductive pads 124B, serve as power supply pads (e.g., V...). cc Padding, V ss (Pads), which are configured and positioned to receive electrical signals (e.g., V) from at least some of the conductive wires 146. cc Signal, V ss In additional embodiments, one or more of the conductive pads 124 serve as one or more data signal pads (e.g., I / O pads) configured and positioned to receive data signals (e.g., I / O signals) from one or more of the conductive lines 146. In further embodiments, one or more of the conductive pads 124 serve as one or more control pads configured and positioned to receive control signals from one or more of the conductive lines 146. The conductive lines 146 may be coupled to additional conductive contact structures 148 (e.g., leads) operatively associated with additional circuitry (e.g., external circuitry, such as external bus circuitry). In some embodiments, the additional conductive contact structures 148 are portions of the lead frame of a package (e.g., an electronic package, such as an integrated circuit (IC) package) that includes the microelectronic device 100 and additional features (e.g., a protective housing containing non-conductive encapsulation material). Although the microelectronic device 100 is described herein as part of a package, the microelectronic device 100 may comprise the entire package.

[0057] The conductive pads 124 of the conductive pad layer 122 (including the first conductive pad 124A and the second conductive pad 124B) may each be formed of and contain a conductive material. In some embodiments, the conductive pads 124 are formed of and contain one or more of the following: metals, alloys, and materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the conductive pads 124 may be formed of and contain Al. As another non-limiting example, the conductive pads 124 may be formed of and contain W.

[0058] Still referencing Figure 1A The first conductive pad 124A, positioned outside the horizontal boundary (e.g., outside the horizontal region) of the memory array region 102 of the die 101 of the microelectronic device 100, may be located within the horizontal boundary of the additional region 132 of the substrate structure 106 of the die 101 of the microelectronic device 100. In some embodiments, the first conductive pad 124A is substantially confined within the horizontal region of the additional region 132 of the substrate structure 106, such that the first conductive pad 124A is completely located outside the horizontal region of the logic region 130 of the substrate structure 106.

[0059] refer to Figure 1B The configuration and operational functions of the first conductive pad 124A can be selected at least in part based on the logic sub-section 134 of the logic region 130 (e.g., in the X direction) relatively horizontally proximate to the first conductive pad 124A. By means of a non-limiting example, if Figure 1B The logic sub-section 134 described in the figure includes a charge pump (V0). CCP Charge pump, V NEGWL The pump section of a charge pump (DVC2 charge pump) may include at least some of the first conductive pads 124A positioned horizontally close to the pump section (e.g., in the X direction) that are configured and positioned to receive electrical signals (e.g., V) from some of the conductive lines 146. cc Signal, V ss The power supply pad (e.g., V) for the signal) cc Padding, V ss (Pad). For example, at least one of the first conductive pads 124A may include V. cc The pad, and at least one of the other of the first conductive pad 124A may include V ss Padding. Used as a V-shaped liner. cc One or more of the first conductive pads 124A may be electrically connected to a voltage regulator device 150 (e.g., a direct current (DC) linear voltage regulator, such as a low dropout (LDO) regulator). The conductive wiring structure 152 may be used, as needed, to electrically connect at least some of the first conductive pads 124A to other features (e.g., structures, devices) of the microelectronic device 100 and / or a package containing the microelectronic device 100. By means of non-limiting examples, such as... Figure 1B As depicted, some conductive wiring structures 152 can be used as V cc One or more of the first conductive pads 124A of the pads extend between the pads and the voltage regulator device 150 and couple one or more of the first conductive pads 124A to the voltage regulator device 150.

[0060] The first conductive pad 124A can individually display the desired horizontal cross-sectional shape. For example... Figure 1BAs shown, in some embodiments, each of the first conductive pads 124A exhibits a generally regular (e.g., square) horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the first conductive pads 124A exhibits an irregular horizontal cross-sectional shape, such as one or more of the following: circular cross-sectional shape, rectangular cross-sectional shape, elliptical cross-sectional shape, teardrop-shaped cross-sectional shape, semi-circular cross-sectional shape, monumental cross-sectional shape, crescent-shaped cross-sectional shape, triangular cross-sectional shape, kite-shaped cross-sectional shape, and irregular cross-sectional shape. Additionally, each of the first conductive pads 124A may exhibit substantially the same horizontal cross-sectional dimensions (e.g., substantially the same horizontal width in the X direction and substantially the same horizontal length in the Y direction), or at least one of the first conductive pads 124A may exhibit one or more horizontal cross-sectional dimensions different from at least one other of the first conductive pads 124A (e.g., different horizontal widths in the X direction and / or different horizontal lengths in the Y direction). In some embodiments, all the first conductive pads 124A exhibit substantially the same horizontal cross-sectional dimensions.

[0061] The first conductive pads 124A may be horizontally spaced apart from each other by at least one pad spacing distance B1 (e.g., in the Y direction). The pad spacing distance B1 between two (2) horizontally adjacent first conductive pads 124A may depend at least in part on the configuration and function of the two (2) first conductive pads 124A, and the configuration and position (if present) of the second conductive pad 124B and conductive wire 146 horizontally inserted between the two (2) first conductive pads 124A. In some embodiments, the pad spacing distance B1 is greater than or equal to about 15 micrometers (µm), for example, greater than or equal to about 20 µm, in the range of about 15 µm to about 50 µm, in the range of about 15 µm to about 30 µm, in the range of about 15 µm to about 25 µm, or in the range of about 15 µm to about 20 µm. Each pair of horizontally adjacent first conductive pads 124A may be horizontally separated from each other by substantially the same pad spacing distance B1, or compared to at least another pair of horizontally adjacent first conductive pads 124A, at least one pair of horizontally adjacent first conductive pads 124A may be horizontally separated from each other by different pad spacing distances B1 (e.g., larger pad spacing distance B1, smaller pad spacing distance B1).

[0062] like Figure 1BAs shown, at least some (e.g., all) of the first conductive pads 124A may be substantially horizontally aligned with each other. For example, the first conductive pads 124A may be substantially horizontally aligned with each other within a row of the first conductive pads 124A. The row of the first conductive pads 124A may extend horizontally in the Y direction, and the horizontal centers of the first conductive pads 124A within the row may be substantially horizontally aligned with each other in the X direction perpendicular to the Y direction. In an additional embodiment, at least one of the first conductive pads 124A is at least partially horizontally offset (e.g., at least partially horizontally misaligned) from at least one other of the first conductive pads 124A in the X direction. For example, the horizontal center of at least one of the first conductive pads 124A in the X direction may be horizontally offset from the horizontal center of at least one other of the first conductive pads 124A in the X direction.

[0063] Each of the first conductive pads 124A may be individually coupled to one of the conductive lines 146, or at least one of the first conductive pads 124A may not be coupled to one of the conductive lines 146. If an individual first conductive pad 124A is coupled to an individual conductive line 146, then the first conductive pad 124A may be physically attached (e.g., bonded) to the conductive line 146 by desired means. In some embodiments, at least some of the first conductive pads 124A are bonded to at least some of the conductive lines 146 through the intervention of a conductive connection structure 154. The conductive connection structure 154 may, for example, include solder structures, such as one or more of solder balls and solder bumps.

[0064] Still referencing Figure 1B A second conductive pad 124B, positioned at the horizontal boundary of the memory array region 102 of the die 101 of the microelectronic device 100 and / or at least partially within said horizontal boundary (e.g., at or at least partially within said horizontal region), may be at least partially located within the horizontal boundary of the logic region 130 of the substrate structure 106 of the die 101 of the microelectronic device 100. In some embodiments, the second conductive pad 124B is substantially confined within the horizontal region of the logic region 130 of the substrate structure 106, such that the second conductive pad 124B is completely located outside the horizontal region of the additional region 132 of the substrate structure 106. The horizontal boundary (e.g., in the X direction) of the second conductive pad 124B that is most horizontally close to the first conductive pad 124A may be located at or relatively close to the horizontal boundary (e.g., in the X direction) of the logic region 130. In some embodiments, the second conductive pad 124B is substantially confined within the horizontal region of the memory array region 102 of the die 101. Figure 1AAs shown, the second conductive pad 124B may at least partially (e.g., substantially) horizontally overlap (e.g., in the X direction) with the stacked structure 112. In some embodiments, the second conductive pad 124B at least partially horizontally overlaps (e.g., in the X direction) with some of the unit column structures 126 that extend vertically through the stacked structure 112.

[0065] Refer again Figure 1B At least some of the second conductive pads 124B may individually, at least partially (e.g., substantially), be located within one or more horizontal regions of logic sub-regions 134 positioned relative to the additional region 132 of the substrate structure 106 of the logic region 130. In some embodiments, one or more (e.g., each) of the second conductive pads 124B are substantially confined within the horizontal region of at least one logic sub-region 134 positioned near the outer horizontal boundary (e.g., in the X direction) of the logic region 130. In an additional embodiment, for at least one (e.g., each) of the second conductive pads 124B, a portion of the second conductive pad 124B is positioned within the horizontal region of the logic sub-region 134 positioned near the outer horizontal boundary (e.g., in the X direction) of the logic region 130, and an additional portion of the second conductive pad 124B is positioned outside the horizontal region of the logic sub-region 134. The additional portion of the second conductive pad 124B may still be positioned within the horizontal region of the logic region 130 containing the logic sub-region 134, or may be positioned outside the horizontal region of the logic region 130.

[0066] The configuration and operational functions of the second conductive pad 124B can be selected at least in part based on a logic sub-section 134 of the logic region 130 that is horizontally overlapping with or (e.g., relatively horizontally close to) the second conductive pad 124B in the X direction. By means of a non-limiting example, if Figure 1B The logic sub-section 134 described in the figure includes a charge pump (V0). CCP Charge pump, V NEGWL The pump portion of the charge pump (DVC2 charge pump) may include at least some of the second conductive pads 124B positioned horizontally overlapping and / or relatively horizontally close to the logic sub-part 134, and configured and positioned to receive electrical signals (e.g., V) from some of the conductive lines 146. cc Signal, V ss The power supply pad (e.g., V) for the signal) cc Padding, V ss (Pad). For example, at least one of the second conductive pads 124B may include V. cc The pad, and at least one of the other of the second conductive pads 124B may include V ss Padding. Used as a V-shaped liner. ccOne or more of the second conductive pads 124B are electrically connected to the voltage regulator device 150. Some of the conductive wiring structures 152 may be used as needed to electrically connect at least some of the second conductive pads 124B to the microelectronic device 100 and / or other features (e.g., structures, devices) of the package containing the microelectronic device 100. By means of non-limiting examples, such as... Figure 1B As depicted, some conductive wiring structures 152 can be used as V cc One or more of the second conductive pads 124B extend between the pad and the voltage regulator device 150 and can couple one or more of the second conductive pads 124B to the voltage regulator device 150.

[0067] In some embodiments, the operational functions of at least some of the second conductive pads 124B correspond to (e.g., are substantially the same as) the operational functions of at least some of the first conductive pads 124A located most horizontally close to the second conductive pads 124B. By means of a non-limiting example, if one or more of the first conductive pads 124A include power supply pads (e.g., V... cc Padding, V ss If the first conductive pads 124A are positioned most horizontally close to one or more of the second conductive pads 124B, then one or more of the second conductive pads 124B may further include power supply pads (e.g., V). cc Padding, V ss (Pad). In some embodiments, used as V cc One or more of the second conductive pads 124B of the liner are also used as V at relatively close relative levels. cc Positioned by one or more of the first conductive pads 124A; and used as V ss One or more of the second conductive pads 124B of the liner are also used as V at relatively close relative levels. ss One or more of the first conductive pads 124A of the pads are positioned. Positioning the first conductive pads 124A and the second conductive pads 124B, which have corresponding operating functions, to be relatively horizontally close to each other can facilitate redundancy in the execution of the operating functions and ensure device reliability.

[0068] The second conductive pads 124B can each individually display the desired horizontal cross-sectional shape. For example... Figure 1BAs shown, in some embodiments, each of the second conductive pads 124B exhibits a generally regular (e.g., square) horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the second conductive pads 124B exhibits an irregular horizontal cross-sectional shape, such as one or more of the following: circular cross-sectional shape, rectangular cross-sectional shape, elliptical cross-sectional shape, teardrop-shaped cross-sectional shape, semi-circular cross-sectional shape, monumental cross-sectional shape, crescent-shaped cross-sectional shape, triangular cross-sectional shape, kite-shaped cross-sectional shape, and irregular cross-sectional shape. Additionally, each of the second conductive pads 124B may exhibit substantially the same horizontal cross-sectional dimensions (e.g., substantially the same horizontal width in the X direction and substantially the same horizontal length in the Y direction), or at least one of the second conductive pads 124B may exhibit one or more horizontal cross-sectional dimensions different from at least one other of the second conductive pads 124B (e.g., different horizontal widths in the X direction and / or different horizontal lengths in the Y direction). In some embodiments, all the second conductive pads 124B exhibit substantially the same horizontal cross-sectional dimensions.

[0069] The horizontal cross-sectional shape of each of the second conductive pads 124B may be substantially the same as that of each of the first conductive pads 124A, or one or more horizontal cross-sectional shapes of the second conductive pads 124B may differ from one or more horizontal cross-sectional shapes of the first conductive pads 124A. Furthermore, the horizontal cross-sectional dimensions of each of the second conductive pads 124B may be substantially the same as those of each of the first conductive pads 124A (e.g., substantially the same horizontal width in the X direction and substantially the same horizontal length in the Y direction), or one or more of the second conductive pads 124B may exhibit one or more horizontal cross-sectional dimensions different from those of one or more of the first conductive pads 124A (e.g., different horizontal widths in the X direction and / or different horizontal lengths in the Y direction).

[0070] The second conductive pads 124B may be horizontally spaced apart from each other by at least one additional pad spacing distance C1 (e.g., in the Y direction). The additional pad spacing distance C1 between two (2) horizontally adjacent second conductive pads 124B may depend at least in part on the configuration and function of the two (2) second conductive pads 124B, and the configuration and position (if present) of the first conductive pad 124A and conductive wire 146 horizontally inserted between the two (2) second conductive pads 124B. In some embodiments, the additional pad spacing distance C1 is greater than or equal to about 15 µm, for example, greater than or equal to about 20 µm, in the range of about 15 µm to about 50 µm, in the range of about 15 µm to about 30 µm, in the range of about 15 µm to about 25 µm, or in the range of about 15 µm to about 20 µm. Each pair of horizontally adjacent second conductive pads 124B may be horizontally separated from each other by substantially the same additional pad spacing C1, or at least one pair of horizontally adjacent second conductive pads 124B may be horizontally separated from each other by a different additional pad spacing C1 (e.g., a larger additional pad spacing C1, a smaller additional pad spacing C1) compared to at least another pair of horizontally adjacent second conductive pads 124B. The additional pad spacing C1 between all horizontally adjacent second conductive pads 124B may be substantially the same as (e.g., substantially equal to) the pad spacing B1 between all horizontally adjacent first conductive pads 124A, or the additional pad spacing C1 between at least two (2) horizontally adjacent second conductive pads 124B may be different from (e.g., less than, greater than) the pad spacing B1 between at least two (2) horizontally adjacent first conductive pads 124A. The conductive wiring structure (e.g., signal wiring structure) of the microelectronic device 100 may be positioned (e.g., partially positioned) within a space between horizontally adjacent second conductive pads 124B and may extend (e.g., horizontally or vertically) through said space.

[0071] Still referencing Figure 1BThe second conductive pad 124B may (e.g., in the X direction) be horizontally spaced from the first conductive pad 124A by at least one additional pad spacing distance D1. The additional pad spacing distance D1 between at least one of the second conductive pads 124B and at least one of the first conductive pads 124A horizontally adjacent to the second conductive pad 124B (e.g., in the X direction) may be greater than or equal to the pad spacing distance B1 between at least one of the first conductive pads 124A and at least one other of the first conductive pads 124A horizontally adjacent to at least one of the first conductive pads 124A (e.g., in the Y direction). In some embodiments, the additional pad spacing distance D1 is greater than or equal to about 15 µm, for example, greater than or equal to about 20 µm, in the range of about 15 µm to about 50 µm, in the range of about 15 µm to about 30 µm, in the range of about 15 µm to about 25 µm, or in the range of about 15 µm to about 20 µm. Each second conductive pad 124B may be horizontally separated from each first conductive pad 124A that is horizontally adjacent to the second conductive pad 124B by a substantially the same additional pad spacing distance D1, or compared to the additional pad spacing distance D1 between at least one of the second conductive pads 124B and at least one of the first conductive pads 124A that is horizontally adjacent to at least one of the second conductive pads 124B, at least one of the second conductive pads 124B may be horizontally separated from at least one of the first conductive pads 124A that is horizontally adjacent to at least one of the second conductive pads 124B by a different additional pad spacing distance D1 (e.g., a larger additional pad spacing distance D1, a smaller additional pad spacing distance D1).

[0072] like Figure 1B As shown, at least some (e.g., all) of the second conductive pads 124B may be substantially horizontally aligned with each other. For example, the second conductive pads 124B may be substantially horizontally aligned with each other within a row of the second conductive pads 124B. The row of the second conductive pads 124B may extend horizontally in the Y direction, and the horizontal centers of the second conductive pads 124B within the row may be substantially horizontally aligned with each other in the X direction perpendicular to the Y direction. The row of the second conductive pads 124B may extend horizontally substantially parallel to the row of the first conductive pads 124A. In an additional embodiment, at least one of the second conductive pads 124B is at least partially horizontally offset (e.g., at least partially horizontally misaligned) from at least one other of the second conductive pads 124B in the X direction. For example, the horizontal center of at least one of the second conductive pads 124B in the X direction may be horizontally offset from the horizontal center of at least one other of the second conductive pads 124B in the X direction.

[0073] One or more of the second conductive pads 124B (e.g., each) may be at least partially horizontally offset in the Y direction from one or more of the first conductive pads 124A (e.g., each) that are most horizontally close to (e.g., horizontally near) the second conductive pad 124B. For example, the horizontal center of the horizontal offset of at least one of the second conductive pads 124B in the Y direction may originate from the horizontal center of at least one first conductive pad 124A that is most horizontally close to the second conductive pad 124B. The horizontal centers of all the second conductive pads 124B may be horizontally offset in the Y direction from the horizontal centers of all the first conductive pads 124A, or the horizontal center of at least one of the second conductive pads 124B may be substantially aligned in the Y direction with the horizontal center of at least one of the first conductive pads 124A. Figure 1B As shown, in some embodiments, at least one (e.g., each) of the second conductive pads 124B partially overlaps horizontally in the Y direction with at least one (e.g., each) of the first conductive pads 124A that are horizontally adjacent to at least one of the second conductive pads 124B. In additional embodiments, at least one (e.g., each) of the second conductive pads 124B does not horizontally overlap with at least one (e.g., each) of the first conductive pads 124A that are horizontally adjacent to at least one of the second conductive pads 124B in the Y direction. In other words, at least one of the second conductive pads 124B may be completely horizontally offset in the Y direction from at least one of the first conductive pads 124A that are horizontally adjacent to at least one of the second conductive pads 124B.

[0074] Each of the second conductive pads 124B may be individually coupled to one of the conductive lines 146, or at least one of the second conductive pads 124B may not be coupled to one of the conductive lines 146. If an individual second conductive pad 124B is coupled to an individual conductive line 146, then the second conductive pad 124B may be physically attached (e.g., bonded) to the conductive line 146 by desired means. In some embodiments, at least some of the second conductive pads 124B are bonded to at least some of the conductive lines 146 through at least some of the conductive connection structures 154 (e.g., solder structures, such as one or more solder balls and solder bumps).

[0075] Still referencing Figure 1BThe conductive lines 146 (e.g., bonding lines) coupled to the conductive pads 124 (e.g., including the first conductive pad 124A and the second conductive pad 124B) may be horizontally spaced apart from each other by at least one line spacing distance E1 (e.g., in the Y direction). The line spacing distance E1 between two (2) horizontally adjacent conductive lines 146 may depend at least in part on the configuration of the two (2) conductive lines 146, and the configuration and position of the two (2) conductive pads 124 (e.g., one (1) first conductive pad and one (1) second conductive pad 124B, two (2) first conductive pads 124A, two (2) first conductive pads 124A) attached (e.g., bonded) to the two (2) conductive lines 146 by means of the two (2) conductive connection structures 154. Each pair of horizontally adjacent conductive lines 146 may be horizontally separated from each other by substantially the same line spacing distance E1, or at least one pair of horizontally adjacent conductive lines 146 may be horizontally separated from each other by different line spacing distances E1 (e.g., larger line spacing distance E1, smaller line spacing distance E1) compared to at least another pair of horizontally adjacent conductive lines 146. In some embodiments, the line spacing distance E1 between one conductive line 146 coupled to one of the first conductive pads 124A and another conductive line 146 coupled to one of the second conductive pads 124B horizontally adjacent to one of the first conductive pads 124A is about half (1 / 2) of the relatively large distance between one conductive line 146 and yet another conductive line 146 coupled to the other of the first conductive pads 124A horizontally adjacent to one of the first conductive pads 124A.

[0076] As previously described, the microelectronic device 100 can be configured to display and Figure 1A and 1B The configurations described herein differ from the configurations in the text. This can be achieved using non-restricted instances. Figure 2 A simplified partial top view of portion A of a microelectronic device 200 according to an additional embodiment of the present disclosure is shown. Portion A of the microelectronic device 200 may correspond to a previously referenced portion. Figure 1A and 1B The microelectronic device 100 described is part A, but compared to part A of the microelectronic device 100, it may exhibit different feature configurations in its horizontal region. Throughout... Figure 2 In related descriptions, functionally similar features (e.g., materials, structures, devices) are referred to by similar reference numerals incremented by 100. To avoid repetition, they are not described in detail herein. Figure 2 All the features shown in [the document]. Rather, unless otherwise described below, [the following is not included]. Figure 2 In the middle, from the previous reference Figure 1A and 1BThe reference numerals of one or more of the described features incremented by 100, and the features represented by the reference numerals are to be understood as substantially similar to the features previously described. As a non-limiting example, unless otherwise described below, in Figure 2 The features indicated by reference numeral 224A in this document will be understood to be substantially similar to those previously referenced in this document. Figure 1A and 1B The first conductive pad 124A is described. As another non-limiting example, unless otherwise described below, in... Figure 2 The features indicated by reference numeral 224B in this document will be understood to be substantially similar to those previously referenced in this paper. Figure 1A and 1B The second conductive pad 124B is described. Additionally, unless otherwise described below, previous references... Figure 1A The features of the microelectronic device 100 described herein may also be included in a substantially similar manner (e.g., to show a substantially similar configuration and location) by reference in this document. Figure 2 The microelectronic device 200 is described.

[0077] like Figure 2 The configuration of the microelectronic device 200 described herein may be similar to that in previous references. Figure 1A and 1B The configuration of the described microelectronic device 100 differs from that of the first conductive pad 124A ( Figure 1A and 1B ), second conductive pad 124B ( Figure 1A and 1B ) and conductive wire 146 ( Figure 1A and 1B The configuration and / or location of at least some of the first conductive pads 224A (e.g., first bonding pads), at least some of the second conductive pads 224B (e.g., second bonding pads), and at least some of the conductive lines 246 (e.g., bonding lines) may vary. The first conductive pads 224A, second conductive pads 224B, and conductive lines 246 of the microelectronic device 200 are further described in detail below, including non-limiting examples of their potential configurations and locations.

[0078] like Figure 2As shown, compared to one or more other second conductive pads 224B, one or more of the second conductive pads 224B may be positioned at different locations in the X direction. For example, one or more of the second conductive pads 224B may be horizontally positioned relatively further away from the additional region 232 of the substrate structure 206 (and therefore relatively closer to the logic region 230) in the X direction. For example, compared to one or more other second conductive pads 224B, one or more of the second conductive pads 224B (e.g., two or more) may be located at one or more different locations in the X direction within one or more logic sub-regions 234 of the logic region 230 (e.g., pump sub-region, driver sub-region, memory cache sub-region, decoder sub-region, sense amplifier sub-region). In some embodiments, one or more (e.g., two or more) of the second conductive pads 224B are horizontally offset in the X direction from one or more other second conductive pads 224B, such that one or more of the second conductive pads 224B are positioned relatively closer in the X direction to the horizontal center of the individual logic sub-region 234 of the logic region 230 compared to one or more other second conductive pads 224B.

[0079] At least two of the second conductive pads 224B may have their horizontal centers substantially horizontally aligned with each other in the X direction, and each may be horizontally offset from the horizontal center of at least one other of the second conductive pads 224B in the X direction. In some embodiments, at least two of the second conductive pads 224B that are substantially horizontally aligned with each other in the X direction are horizontally adjacent to each other in the Y direction. In an additional embodiment, at least two of the second conductive pads 224B that are substantially horizontally aligned with each other in the X direction are not horizontally adjacent to each other in the Y direction. For example, at least one other of the second conductive pads 224B having a horizontal center offset from the horizontal center of at least two of the second conductive pads 224B in the X direction may be horizontally inserted between at least two of the second conductive pads 224B in the Y direction. In another embodiment, the horizontal center of each of the second conductive pads 224B is horizontally offset from the horizontal center of each other of the second conductive pads 224B in the X direction.

[0080] Still referencing Figure 2At least one of the second conductive pads 224B may (e.g., in the Y direction) be horizontally spaced from at least one other of the second conductive pads 224B by a first additional pad spacing distance C2, which is different from (e.g., greater than, less than) a second additional pad spacing distance C3 between at least one of the second conductive pads 224B and at least one other of the second conductive pads 224B. For example, the horizontal center of at least one of the second conductive pads 224B in the Y direction may be positioned relatively closer to the horizontal center of at least one of the second conductive pads 224B in the Y direction than the horizontal center of at least one other of the second conductive pads 224B, such that the first additional pad spacing distance C2 is greater than the second additional pad spacing distance C3. Figure 2 As shown, in some such embodiments, at least one of the second conductive pads 224B horizontally overlaps with one of a pair of horizontally adjacent first conductive pads 224A in the Y direction by a greater extent than it horizontally overlaps with the other of the pair of horizontally adjacent first conductive pads 224A. In additional embodiments, at least one of the second conductive pads 224B horizontally overlaps with one of a pair of horizontally adjacent first conductive pads 224A that is most horizontally close to at least one of the second conductive pads 224B by no greater extent than it horizontally overlaps with the other of the pair of horizontally adjacent first conductive pads 224A. In some embodiments, the first additional pad spacing distance C2 and the second additional pad spacing distance C3 are each individually greater than or equal to about 15 µm, for example, greater than or equal to about 20 µm, in the range of about 15 µm to about 50 µm, in the range of about 15 µm to about 30 µm, in the range of about 15 µm to about 25 µm, or in the range of about 15 µm to about 20 µm.

[0081] Continue to refer to Figure 2One or more of the first conductive pads 224A may be positioned in the X direction at a location different from that of one or more other first conductive pads 224A. For example, one or more of the first conductive pads 224A may be horizontally positioned in the X direction relatively closer to the logic region 230 of the substrate structure 206. In some embodiments, the first conductive pads 224A are each positioned within a horizontal region of an additional region 232 of the substrate structure 206, but one or more of the first conductive pads 224A are positioned relatively closer to the horizontal boundary of the logic region 230 of the substrate structure 206 than one or more other first conductive pads 224A. In an additional embodiment, one or more of the first conductive pads 224A are partially located within the horizontal region of the additional region 232 of the substrate structure 206, and also partially located within the horizontal region of the logic region 230 of the substrate structure 206; and one or more others of the first conductive pads 224A are not partially located within the horizontal region of the logic region 230 of the substrate structure 206 (e.g., are confined within the horizontal region of the additional region 232 of the substrate structure 206). If individual first conductive pads 224A extend horizontally into the horizontal region of the logic region 230 of the substrate structure 206, then the first conductive pads 224A may be partially located within the horizontal region of the logic sub-regions 234 (e.g., pump sub-regions, driver sub-regions, memory cache sub-regions, decoder sub-regions, sense amplifier sub-regions) within the logic region 230, or may not be partially located within the horizontal region of the logic sub-regions 234 within the logic region 230. In some embodiments, one or more of the first conductive pads 224A are horizontally offset in the X direction from one or more other first conductive pads 224A, such that one or more of the first conductive pads 224A are positioned relatively closer in the X direction to the horizontal center of the individual logic sub-region 234 of the logic region 230 compared to one or more other first conductive pads 224A. For example... Figure 2 As shown in some such embodiments, one or more of the second conductive pads 224B that are horizontally adjacent to one or more of the first conductive pads 224A are positioned relatively closer in the X direction to the horizontal center of the individual logic sub-region 234 of the logic region 230 compared to one or more of the other second conductive pads 224B.

[0082] Some of the horizontal centers of the first conductive pads 224A may be substantially horizontally aligned with each other in the X direction, and may be horizontally offset from the horizontal centers of one or more of the other first conductive pads 224A in the X direction. In some embodiments, at least two of the first conductive pads 224A that are substantially horizontally aligned with each other in the X direction are horizontally adjacent to each other in the Y direction. In an additional embodiment, at least two of the first conductive pads 224A that are substantially horizontally aligned with each other in the X direction are not horizontally adjacent to each other in the Y direction. For example, at least one other of the first conductive pads 224A having a horizontal center offset from the horizontal centers of at least two of the first conductive pads 224A in the X direction may be horizontally inserted between at least two of the first conductive pads 224A in the Y direction. In another embodiment, the horizontal center of each of the first conductive pads 224A is horizontally offset from the horizontal center of each of the other first conductive pads 224A in the X direction. In yet another embodiment, the horizontal center of each of the first conductive pads 224A is horizontally aligned with the horizontal center of each of the other first conductive pads 224A in the X direction.

[0083] Still referencing Figure 2 At least one of the first conductive pads 224A may be horizontally spaced from at least one of the second conductive pads 224B in the X direction by a first additional pad spacing distance D2, which is different from (e.g., greater than, less than) a second additional pad spacing distance D3 between at least one of the first conductive pads 224A and at least one of the second conductive pads 224B. For example, the horizontal center of at least one of the first conductive pads 224A in the X direction may be positioned relatively closer to the horizontal center of at least one of the second conductive pads 224B in the X direction than the horizontal center of at least one of the first conductive pads 224A in the X direction, such that the first additional pad spacing distance D2 is greater than the second additional pad spacing distance D3. Figure 2 As shown, in some embodiments, at least one of the first conductive pads 224A is horizontally spaced from at least one other of the second conductive pads 224B in the X direction by a second additional pad spacing distance D3. In some embodiments, the first additional pad spacing distance D2 and the second additional pad spacing distance D3 are each individually greater than or equal to about 15 µm, for example, greater than or equal to about 20 µm, in the range of about 15 µm to about 50 µm, in the range of about 15 µm to about 30 µm, in the range of about 15 µm to about 25 µm, or in the range of about 15 µm to about 20 µm.

[0084] like Figure 2As depicted, in some embodiments, at least one (but not every) of the second conductive pads 224B is not coupled to any of the conductive lines 246. At least one of the second conductive pads 224B may not have a conductive connection structure 254. A first line spacing distance E2 between a pair of horizontally adjacent conductive lines 246 operatively associated with one of the first conductive pads 124A and one of the second conductive pads 224B may be different from (e.g., less than, greater than) a second line spacing distance E3 between another pair of horizontally adjacent conductive lines 246 operatively associated with a pair of first conductive pads 124A. In additional embodiments, at least one (but not every) of the first conductive pads 224A is not coupled to any of the conductive lines 246. At least one of the first conductive pads 224A may not have a conductive connection structure 254.

[0085] Therefore, according to embodiments of this disclosure, a microelectronic device includes: a substrate structure; a memory array located on the substrate structure; and a conductive pad layer located on the memory array. The substrate structure includes a logic region comprising logic devices. The memory array includes a vertically extending string of memory cells within a horizontal region of the logic region of the substrate structure. The conductive pad layer includes: a first conductive pad substantially outside the horizontal region of the logic region of the substrate structure; and a second conductive pad horizontally adjacent to the first conductive pad and within the horizontal region of the logic region of the substrate structure.

[0086] Furthermore, according to embodiments of this disclosure, a memory device includes a substrate structure, conductive wiring layers, a stacked structure, a memory array, additional conductive wiring layers, conductive contacts, a first conductive pad, and a second conductive pad. The substrate structure includes a region containing a complementary metal-oxide-semiconductor (CMOS) circuit system, and an additional region horizontally adjacent to the region and substantially without the CMOS circuit system. The conductive wiring layers are located above the substrate structure. The stacked structure is located above the conductive wiring layers and includes a conductive material and an insulating material vertically alternating with the conductive material. The memory array includes strings of memory cells extending through the stacked structure. The memory array is located within a horizontal region of the region of the substrate structure. The additional conductive wiring layers are located above the stacked structure. The conductive contacts are horizontally offset from the memory array and extend between the conductive wiring layers and the additional conductive wiring layers. The first conductive pad is located above the additional conductive wiring layers and within a horizontal region of the additional region of the substrate structure. The first conductive pad is electrically connected to some of the conductive contacts. The second conductive pad is located above the additional conductive wiring layers and horizontally inserted between the first conductive pad and at least some of the strings of memory cells in the memory array. The second conductive pad is electrically connected to some of the other conductive contacts.

[0087] The microelectronic device (e.g., microelectronic device 100, 200) according to embodiments of this disclosure can be used in embodiments of the electronic system of this disclosure. For example, Figure 3 This is a block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., an iPad® or SURFACE® tablet computer), an e-book, a navigation device, etc. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, a microelectronic device (e.g., microelectronic device 100, 200) previously described herein. The electronic system 300 may further include at least one electronic signal processor device 304 (generally referred to as a “microprocessor”). The electronic signal processor device 304 may optionally include a microelectronic device (e.g., microelectronic device 100, 200) previously described herein. Although the memory device 302 and the electronic signal processor device 304 are depicted as... Figure 3The electronic system 300 may contain two (2) separate devices, but in an additional embodiment, a single (e.g., only one) memory / processor device having the functionality of a memory device 302 and an electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include the microelectronic devices (e.g., microelectronic devices 100, 200) previously described herein. The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information to a user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 306 and the output device 308 may include a single touchscreen device that can be used to input information into the electronic system 300 and output visual information to a user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0088] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device. The memory device includes a stacked structure, a substrate structure, a memory array, and bonding pads. The stacked structure includes conductive structures vertically intersecting with an insulating structure. The substrate structure is vertically located below the stacked structure and includes a logic region containing a logic circuit system. The memory array includes a string of memory cells extending vertically through the stacked structure. The memory array is positioned within a horizontal region of the logic region of the substrate structure. The bonding pads, vertically located above the stacked structure, are electrically connected to the logic circuit system. The bonding pads include a first bonding pad and a second bonding pad. The first bonding pad is positioned outside the horizontal region of the logic region of the substrate structure. The second bonding pad is positioned within the horizontal region of the logic region of the substrate structure.

[0089] Compared to conventional structures, devices, and methods, the structures and devices of this disclosure advantageously facilitate one or more of the following: improved performance of microelectronic devices, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and increased packaging density. Compared to conventional structures and devices, the structures and devices of this disclosure also improve scalability, efficiency, and simplicity.

[0090] Additional non-limiting example embodiments of this disclosure are described below.

[0091] Example 1: A microelectronic device comprising: a substrate structure including a logic region containing logic devices; a memory array located on the substrate structure and including a vertically extending string of memory cells within a horizontal region of the logic region of the substrate structure; and a conductive pad layer located on the memory array and including: a first conductive pad substantially outside the horizontal region of the logic region of the substrate structure; and a second conductive pad horizontally adjacent to the first conductive pad and within the horizontal region of the logic region of the substrate structure.

[0092] Example 2: The microelectronic device according to Example 1, wherein: each of the second conductive pads is at least partially located in a horizontal region of a memory array region including the memory array; and each of the first conductive pads is substantially outside the horizontal region of the memory array region.

[0093] Example 3: The microelectronic device according to Example 2 further includes a conductive contact structure located on the substrate structure and in a horizontal region of a contact area horizontally adjacent to the memory array region, the conductive contact structure being electrically connected to at least some of the first conductive pads and at least some of the second conductive pads.

[0094] Example 4: The microelectronic device according to Example 3, wherein at least some of the second conductive pads are partially located in the horizontal region of the memory array region and partially located in the horizontal region of the contact region.

[0095] Example 5: A microelectronic device according to one of Examples 3 and 4, wherein at least some of the conductive contact structures are electrically connected to a charge pump within the logic region of the substrate structure.

[0096] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein: the first conductive pad includes rows of the first conductive pad; and the second conductive pad includes rows of the second conductive pad extending horizontally parallel to the rows of the first conductive pad.

[0097] Example 7: The microelectronic device according to any one of Examples 1 to 5 further includes conductive lines attached to the first conductive pad and the second conductive pad.

[0098] Example 8: In the microelectronic device according to Example 7, at least some of the first conductive pads and at least some of the second conductive pads are configured and positioned to receive electrical signals from at least some of the conductive lines.

[0099] Example 9: The microelectronic device according to Example 8, wherein one or more of the first conductive pads and one or more of the second conductive pads are electrically connected to a voltage regulator device.

[0100] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein at least some of the first conductive pads are offset from at least some of the second conductive pads by at least one distance in a first horizontal direction within a range of about 15 µm to about 50 µm.

[0101] Example 11: The microelectronic device according to Example 10, wherein at least one of the first conductive pads is offset from at least one other of the first conductive pads by at least one additional distance greater than or equal to about 15 µm in a second horizontal direction orthogonal to the first horizontal direction.

[0102] Example 12: The microelectronic device according to Example 11, wherein at least one of the second conductive pads is offset from at least one other of the second conductive pads by at least one additional distance greater than or equal to about 15 µm in the second horizontal direction.

[0103] Example 13: A microelectronic device according to any one of Examples 1 to 12, wherein at least one of the second conductive pads is offset from two of the first conductive pads closest to the second conductive pad in a first horizontal direction, and is at least partially inserted between the two of the first conductive pads in a second horizontal direction perpendicular to the first horizontal direction.

[0104] Example 14: A memory device comprising: a substrate structure including a region containing a complementary metal-oxide-semiconductor (CMOS) circuit system, and an additional region horizontally adjacent to the region and substantially without the CMOS circuit system; a conductive wiring layer located on the substrate structure; a stacked structure located on the conductive wiring layer and comprising a conductive material and an insulating material vertically alternating with the conductive material; a memory array including strings of memory cells extending through the stacked structure, the memory array being located in a horizontal region of the region of the substrate structure; an additional conductive wiring layer located on the stacked structure; conductive contacts horizontally offset from the memory array and extending between the conductive wiring layer and the additional conductive wiring layer; a first conductive pad located on the additional conductive wiring layer and in a horizontal region of the additional region of the substrate structure, the first conductive pad being electrically connected to some of the conductive contacts; and a second conductive pad located on the additional conductive wiring layer and horizontally inserted between the first conductive pad and at least some of the strings of memory cells in the memory array, the second conductive pad being electrically connected to some of the other conductive contacts.

[0105] Example 15: The memory device according to Example 14, wherein the second conductive pad is positioned together with the horizontal region of the region of the substrate structure.

[0106] Example 16: The memory device according to Example 15, wherein: some of the conductive contacts electrically connected to the first conductive pad are located in the horizontal region of the additional region of the substrate structure; and some of the other conductive contacts electrically connected to the second conductive pad are located in the horizontal region of the region of the substrate structure.

[0107] Example 17: A memory device according to any one of Examples 14 to 16, wherein: the second conductive pad is horizontally inserted between the first conductive pad and the memory array in a first horizontal direction; and the horizontal centers of at least some of the second conductive pads are substantially aligned with each other in a second horizontal direction orthogonal to the first horizontal direction.

[0108] Example 18: A memory device according to any one of Examples 14 to 16, wherein: the second conductive pad is horizontally inserted in a first horizontal direction between the first conductive pad and at least some of the memory cell strings of the memory array; and the horizontal center of each of the second conductive pads is horizontally offset from the horizontal center of each of the first conductive pads in a second horizontal direction orthogonal to the first horizontal direction.

[0109] Example 19: A memory device according to any one of Examples 14 to 18, wherein the second conductive pad is arranged in a row inserted in a first horizontal direction between the first conductive pad and at least some of the memory cell strings of the memory array, the row extending in a second horizontal direction perpendicular to the first horizontal direction.

[0110] Example 20: A memory device according to any one of Examples 14 to 19, wherein at least one of the second conductive pads horizontally overlaps with at least one of the memory cell strings of the memory array.

[0111] Example 21: A memory device according to any of Examples 14 to 20, further comprising conductive lines bonded to at least some of the first conductive pads and at least some of the second conductive pads, the conductive lines being coupled to leads of a lead frame.

[0112] Example 22: A memory device according to any one of Examples 14 to 21, wherein: at least one of the second conductive pads includes a power supply voltage (V). cc ) pad; and at least one of the other of the second conductive pads includes ground (V ss )liner.

[0113] Example 23: An electronic system comprising: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device and comprising: a stacked structure including conductive structures vertically intersecting with an insulating structure; a substrate structure vertically located below the stacked structure and including a logic region containing a logic circuit system; a memory array including a string of memory cells extending vertically through the stacked structure, the memory array being positioned within a horizontal region of the logic region of the substrate structure; and a bonding pad vertically located above the stacked structure and electrically connected to the logic circuit system, the bonding pad including a first bonding pad positioned outside the horizontal region of the logic region of the substrate structure and a second bonding pad positioned within the horizontal region of the logic region of the substrate structure.

[0114] Example 24: The electronic system according to Example 23, wherein the logic circuit system of the substrate structure includes a complementary metal-oxide-semiconductor (CMOS) circuit system.

[0115] Example 25: An electronic system according to one of Examples 23 and 24, wherein the memory device includes a 3D NAND flash memory device.

[0116] While this disclosure allows for various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, this disclosure is not limited to the specific forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of this disclosure.

Claims

1. A microelectronic device comprising: A substrate structure, which includes a logic region containing logic devices; A memory array, which is located on the substrate structure and includes a vertically extending string of memory cells within a horizontal region of the logic area of ​​the substrate structure; A conductive contact structure is located on the substrate structure and horizontally offset from the memory array; as well as A conductive pad layer, located above the memory array, includes: A first conductive pad is located outside the horizontal region of the logic area of ​​the substrate structure, and the first conductive pad is electrically connected to a portion of the conductive contact structure in the conductive contact structure. as well as A second conductive pad is horizontally adjacent to the first conductive pad and is located within the horizontal region of the logic area of ​​the substrate structure. The second conductive pad is electrically connected to other conductive contact structures in the conductive contact structure, wherein the portion of the conductive contact structure is different from the other conductive contact structures in the conductive contact structure.

2. The microelectronic device according to claim 1, wherein: Each of the second conductive pads is at least partially located within a horizontal region of the memory array region that includes the memory array; and Each of the first conductive pads is located outside the horizontal region of the memory array area.

3. The microelectronic device of claim 2, wherein the conductive contact structure is located in a horizontal region of the contact region that is horizontally adjacent to the memory array region.

4. The microelectronic device of claim 3, wherein at least some of the second conductive pads are partially located within the horizontal region of the memory array region and partially within the horizontal region of the contact region.

5. The microelectronic device of claim 3, wherein at least some of the conductive contact structures are electrically connected to a charge pump within the logic region of the substrate structure.

6. The microelectronic device according to any one of claims 1 to 5, wherein: The first conductive pad includes rows of the first conductive pad; and The second conductive pad includes rows of the second conductive pad that extend horizontally parallel to the rows of the first conductive pad.

7. The microelectronic device according to any one of claims 1 to 5, further comprising conductive lines attached to the first conductive pad and the second conductive pad.

8. The microelectronic device of claim 7, wherein at least some of the first conductive pads and at least some of the second conductive pads are configured and positioned to receive electrical signals from at least some of the conductive lines.

9. The microelectronic device of claim 8, wherein one or more of the first conductive pads and one or more of the second conductive pads are electrically connected to a voltage regulator device.

10. The microelectronic device according to any one of claims 1 to 5, wherein at least some of the first conductive pads are offset from at least some of the second conductive pads by at least one distance in a first horizontal direction within a range of 15 µm to 50 µm.

11. The microelectronic device of claim 10, wherein at least one of the first conductive pads is offset from at least one other of the first conductive pads by at least one additional distance greater than or equal to 15 µm in a second horizontal direction orthogonal to the first horizontal direction.

12. The microelectronic device of claim 11, wherein at least one of the second conductive pads is offset from at least one other of the second conductive pads by at least one additional distance greater than or equal to 15 µm in the second horizontal direction.

13. The microelectronic device according to any one of claims 1 to 5, wherein at least one of the second conductive pads is offset from two of the first conductive pads closest to the second conductive pad in a first horizontal direction, and is at least partially inserted between the two of the first conductive pads in a second horizontal direction perpendicular to the first horizontal direction.

14. A memory device comprising: A substrate structure comprising a region containing a complementary metal-oxide-semiconductor (CMOS) circuit system, and an additional region horizontally adjacent to the region but not having the CMOS circuit system; A conductive wiring layer is located above the substrate structure; A stacked structure, which is located above the conductive wiring layer and includes a conductive material and an insulating material that alternates vertically with the conductive material; A memory array comprising a string of memory cells extending through the stacked structure, the memory array being located within a horizontal region of the area of ​​the substrate structure; An additional conductive wiring layer is located above the stacked structure; A conductive contact that is horizontally offset from the memory array and extends between the conductive wiring layer and the additional conductive wiring layer; A first conductive pad is located above the additional conductive wiring layer and in the horizontal region of the additional area of ​​the substrate structure, and the first conductive pad is electrically connected to a portion of the conductive contact structure in the conductive contact. as well as A second conductive pad is located above the additional conductive wiring layer and horizontally inserted between the first conductive pad and at least some of the memory cell strings of the memory array. The second conductive pad is electrically connected to other conductive contact structures in the conductive contacts, wherein a portion of the conductive contact structures is different from the other conductive contact structures in the conductive contact structures.

15. The memory device of claim 14, wherein the second conductive pad is positioned together with the horizontal region of the region of the substrate structure.

16. The memory device according to claim 15, wherein: Some of the conductive contacts electrically connected to the first conductive pad are located within the horizontal region of the additional area of ​​the substrate structure; and Some of the other conductive contacts that are electrically connected to the second conductive pad are located within the horizontal region of the area of ​​the substrate structure.

17. The memory device according to any one of claims 14 to 16, wherein: The second conductive pad is horizontally inserted between the first conductive pad and the memory array in the first horizontal direction; and At least some of the horizontal centers of the second conductive pads are aligned with each other in a second horizontal direction orthogonal to the first horizontal direction.

18. The memory device according to any one of claims 14 to 16, wherein: The second conductive pad is horizontally inserted in a first horizontal direction between the first conductive pad and at least some of the memory cell strings of the memory array; and The horizontal center of each of the second conductive pads is horizontally offset from the horizontal center of each of the first conductive pads in a second horizontal direction orthogonal to the first horizontal direction.

19. The memory device according to any one of claims 14 to 16, wherein the second conductive pad is arranged in a row inserted in a first horizontal direction between the first conductive pad and at least some of the memory cell strings of the memory array, the row extending in a second horizontal direction perpendicular to the first horizontal direction.

20. The memory device according to any one of claims 14 to 16, wherein at least one of the second conductive pads horizontally overlaps with at least one of the memory cell strings of the memory array.

21. The memory device according to any one of claims 14 to 16, further comprising conductive lines coupled to at least some of the first conductive pads and at least some of the second conductive pads, the conductive lines being coupled to leads of a lead frame.

22. The memory device according to any one of claims 14 to 16, wherein: At least one of the second conductive pads includes a power supply voltage (V) cc ) padding; and At least one of the other components of the second conductive pad includes ground (V) ss )liner.

23. An electronic system comprising: Input device; Output device; A processor device operatively connected to the input device and the output device; as well as A memory device operatively connected to the processor device and comprising: A stacked structure comprising conductive structures that are vertically intersected with an insulating structure; A base structure, which is vertically located below the stacked structure and includes a logic area containing a logic circuit system; A memory array comprising a string of memory cells extending vertically through the stacked structure, the memory array being positioned within a horizontal region of the logic area of ​​the substrate structure; A conductive contact structure, horizontally offset from the memory array; and A bonding pad, which is vertically positioned above the stacked structure and electrically connected to the logic circuit system, the bonding pad comprising: A first bonding pad is positioned outside the horizontal region of the logic area of ​​the substrate structure, and the first bonding pad is electrically connected to a portion of the conductive contact structure in the conductive contact structure; and A second bonding pad is positioned within the horizontal region of the logic area of ​​the substrate structure, and the second bonding pad is electrically connected to other conductive contact structures in the conductive contact structure, wherein the portion of the conductive contact structure is different from the other conductive contact structures in the conductive contact structure.

24. The electronic system of claim 23, wherein the logic circuit system of the substrate structure comprises a complementary metal-oxide-semiconductor (CMOS) circuit system.

25. The electronic system according to any one of claims 23 and 24, wherein the memory device comprises a 3D NAND flash memory device.

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