Display panel, display device

Abstract

A display panel and a display device, wherein the display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), and a second electrode is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low-temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor, and the display panel further comprises: a substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer. The second conductive layer is located on one side of the substrate, the second conductive layer includes a third gate line (1Re1), the orthographic projection of the third gate line (1Re1) on the substrate extends along a first direction (X), and a partial structure of the third gate line (1Re1) is used to form a first gate of a first transistor (T1); the second active layer is located on a side of the second conductive layer away from the substrate, and a partial structure of the second active layer is used to form a channel region of the first transistor (T1); the third conductive layer is located on a side of the second active layer away from the substrate, the third conductive layer includes a fifth gate line (2Re1), the orthographic projection of the fifth gate line (2Re1) on the substrate extends along the first direction (X), and a partial structure of the fifth gate line (2Re1) is used to form a second gate of the first transistor (T1); the fourth conductive layer is located on one side of the substrate, the fourth conductive layer includes a first initial signal line (Vinit1), the orthographic projection of the first initial signal line (Vinit1) on the substrate extends along the first direction (X), and the first initial signal line (Vinit1) is used to provide a first initial signal line (Vinit1).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, in order to reduce the leakage current of the driving transistor in the light emitting stage, the pixel driving circuit can be formed by using low temperature polycrystalline oxide (LTPO) technology.

[0003] The display panel formed by the LTPO technology includes N-type oxide transistors and P-type low-temperature polysilicon transistors. The oxide transistors have a large size, so the LTPO technology is not conducive to the production of display panels with larger resolutions.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a first transistor, the first electrode of the first transistor is connected to the gate of the driving transistor, and the second electrode is connected to a first initial signal line, the driving transistor is a P-type low-temperature polysilicon transistor, the first transistor is an N-type oxide transistor, and the display panel also includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer. The second conductive layer is located on one side of the substrate, the second conductive layer includes a third gate line, the orthographic projection of the third gate line on the substrate extends along the first direction, and a partial structure of the third gate line is used to form a first gate of the first transistor; the second active layer is located on a side of the second conductive layer away from the substrate, and a partial structure of the second active layer is used to form a channel region of the first transistor; the third conductive layer is located on a side of the second active layer away from the substrate, the third conductive layer includes a fifth gate line, the orthographic projection of the fifth gate line on the substrate extends along the first direction, and a partial structure of the fifth gate line is used to form a second gate of the first transistor; the fourth conductive layer is located on one side of the substrate, the fourth conductive layer includes the first initial signal line, and the orthographic projection of the first initial signal line on the substrate extends along the first direction.

[0007] In an exemplary embodiment of the present disclosure, the square resistance of the fourth conductive layer is smaller than the square resistance of the second conductive layer, and the square resistance of the fourth conductive layer is smaller than the square resistance of the third conductive layer.

[0008] In an exemplary embodiment of the present disclosure, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate.

[0009] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, and the pixel driving circuit is used to provide a driving current to the light-emitting unit. The pixel driving circuit may also include a seventh transistor, a first electrode of the seventh transistor is connected to the light-emitting unit, and a second electrode is connected to a second initial signal line, and a partial structure of the fourth conductive layer is also used to form the second initial signal line.

[0010] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit adjacent to each other in a row direction; the second initial signal line in the first pixel driving circuit is shared as the first initial signal line in the second pixel driving circuit.

[0011] In an exemplary embodiment of the present disclosure, the display panel also includes: a first conductive layer and a first active layer, the first conductive layer is located between the base substrate and the second conductive layer, the first conductive layer includes a second reset signal line, and a partial structure of the second reset signal line is used to form a gate of the seventh transistor; the first active layer is located between the base substrate and the first conductive layer, and a partial structure of the first active layer is used to form a channel region of the seventh transistor.

[0012] In an exemplary embodiment of the present disclosure, the first initial signal line is connected to the second active layer through a via to connect to the second electrode of the first transistor; the second initial signal line is connected to the first active layer through a via to connect to the second electrode of the seventh transistor.

[0013] In an exemplary embodiment of the present disclosure, the display panel also includes a first conductive layer, which is located between the base substrate and the second conductive layer, and the first conductive layer includes a first conductive portion, which is used to form a gate of the driving transistor; the second active layer includes a first sub-active portion, which is used to form a channel region of the first transistor; wherein the orthographic projection of the third gate line on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate, and the orthographic projection of the fifth gate line on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate; the orthographic projection of the first initial signal line on the base substrate is located on a side where the orthographic projection of the third gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate; the orthographic projection of the first initial signal line on the base substrate is located on a side where the orthographic projection of the fifth gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate.

[0014] In an exemplary embodiment of the present disclosure, the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the third gate line on the substrate; the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the fifth gate line on the substrate.

[0015] In an exemplary embodiment of the present disclosure, the first conductive layer also includes a first conductive portion, which is used to form a gate of the driving transistor; the orthographic projection of the second initial signal line on the substrate is located on a side of the orthographic projection of the second reset signal line on the substrate away from the orthographic projection of the first conductive portion on the substrate; the orthographic projection of the second initial signal line on the substrate is located on a side of the orthographic projection of the second reset signal line on the substrate away from the orthographic projection of the first conductive portion on the substrate.

[0016] In an exemplary embodiment of the present disclosure, an orthographic projection of the second initial signal line on the base substrate at least partially overlaps with an orthographic projection of the second reset signal line on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor and a fourth transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode is connected to a first electrode of the driving transistor, the fourth transistor is a P-type low-temperature polysilicon transistor, and the second transistor is an N-type oxide transistor, and the display panel further includes: a first conductive layer and a second conductive portion, the first conductive layer is located between the base substrate and the second conductive layer, the first conductive layer includes: a first gate line and a first conductive portion, an orthographic projection of the first gate line on the base substrate extends along the first direction, a partial structure of the first gate line is used to form a gate electrode of the fourth transistor, and the first conductive portion is used to form a gate electrode of the driving transistor; an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first gate line on the base substrate. The second conductive layer also includes a second gate line, the orthographic projection of the second gate line on the base substrate extends along the first direction, a partial structure of the second gate line is used to form the first gate of the second transistor, and the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the first gate line on the base substrate; the fourth conductive layer also includes: a first connecting part, the first connecting part is connected to the first conductive part and the second conductive part through vias respectively.

[0018] In an exemplary embodiment of the present disclosure, the second conductive portion includes a first sub-conductive portion, the first sub-conductive portion is formed on the same layer as the second conductive layer, the orthographic projection of the first sub-conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line on the base substrate, and the first connecting portion is connected to the first sub-conductive portion through a via.

[0019] In an exemplary embodiment of the present disclosure, the second active layer includes a first active portion, and a partial structure of the first active portion is used to form a channel region of the first transistor and the second transistor; the display panel also includes a fifth conductive layer, and the fifth conductive layer is located on the side of the fourth conductive layer away from the base substrate, and the fifth conductive layer includes: a power line, the orthographic projection of the power line on the base substrate extends along the second direction, and the orthographic projection of the power line on the base substrate covers the orthographic projection of the first active portion on the base substrate; and the overlapping area of ​​the orthographic projection of the power line on the base substrate and the orthographic projection of the first connecting portion on the base substrate is less than 70% of the orthographic projection area of ​​the first connecting portion on the base substrate.

[0020] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a capacitor, which is connected between the gate of the driving transistor and the power line, and the first conductive portion is also used to form an electrode of the capacitor, and the second conductive layer also includes: a third conductive portion, which is used to form another electrode of the capacitor, and the orthographic projection of the third conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and a first opening is provided on the third conductive portion, wherein the first connecting portion is connected to the first conductive portion through a first via hole, and the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the first opening on the base substrate. The power line includes: a first extension portion, a second extension portion, and a third extension portion, wherein the orthographic projection of the first extension portion on the substrate extends along the second direction, and the orthographic projection of the first extension portion on the substrate at least partially overlaps with the orthographic projection of the first opening on the substrate; the orthographic projection of at least part of the structure of the second extension portion on the substrate extends along the second direction, and the orthographic projection of the second extension portion on the substrate covers the first active portion; the third extension portion is connected between the first extension portion and the second extension portion, and the orthographic projection of the third extension portion on the substrate extends along the first direction, and the orthographic projection of the third extension portion on the substrate at least partially overlaps with the orthographic projection of the first opening on the substrate.

[0021] In an exemplary embodiment of the present disclosure, the second extension portion includes a first sub-extension portion, and the orthographic projection of the first sub-extension portion on the substrate extends along the first direction; the power line also includes: a fourth extension portion, the fourth extension portion is connected between the first sub-extension portion and the first extension portion, and the orthographic projection of the fourth extension portion on the substrate extends along the second direction; the orthographic projection of the first sub-extension portion on the substrate does not at least partially overlap with the orthographic projection of the third gate line on the substrate.

[0022] In an exemplary embodiment of the present disclosure, an orthographic projection of the first sub-extension portion on the base substrate and an orthographic projection of the first initial signal line on the base substrate at least partially overlap.

[0023] In an exemplary embodiment of the present disclosure, the second conductive portion includes a second active portion, the second active portion is formed on the same layer as the second active layer, the orthographic projection of the second active portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line on the base substrate, and the second active portion is electrically connected to the first connecting portion.

[0024] In an exemplary embodiment of the present disclosure, the orthographic projection of the third gate line on the substrate is located on a side of the orthographic projection of the first gate line on the substrate away from the orthographic projection of the second gate line on the substrate; the overlapping area of ​​the orthographic projection of the second active portion on the substrate and the orthographic projection of the second gate line on the substrate is less than 50% of the orthographic projection area of ​​the second active portion on the substrate; the second active layer includes a first active portion, the first active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion; wherein the first sub-active portion is used to form a channel region of the first transistor, the second sub-active portion is used to form a channel region of the second transistor, the first connecting portion is connected to the third sub-active portion through a via, and the orthographic projection of the third sub-active portion on the substrate at least partially overlaps with the orthographic projection of the first gate line on the substrate.

[0025] In an exemplary embodiment of the present disclosure, the second active portion is connected to the third sub-active portion.

[0026] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a capacitor, which is connected between the gate of the driving transistor and the power line, and the second conductive layer further includes: a third conductive part, the third conductive part is used to form an electrode of the capacitor, and the electrode is connected to the power line. The second active part includes: a fourth sub-active part, a fifth sub-active part, and a sixth sub-active part, the fourth sub-active part is connected to the third sub-active part, the orthographic projection of the fourth sub-active part on the substrate extends along the first direction, and the orthographic projection of the fourth sub-active part on the substrate at least partially overlaps with the orthographic projection of the first gate line on the substrate; the fifth sub-active part is connected to the fourth sub-active part, the orthographic projection of the fifth sub-active part on the substrate extends along the second direction, and the orthographic projection of the fifth sub-active part on the substrate intersects with the orthographic projection of the second gate line on the substrate; the sixth sub-active part is connected to the fifth sub-active part, and the orthographic projection of the sixth sub-active part on the substrate at least partially overlaps with the orthographic projection of the third conductive part on the substrate.

[0027] In an exemplary embodiment of the present disclosure, a size of an orthographic projection of the fifth sub-active portion on the base substrate in the first direction is smaller than a size of an orthographic projection of the sixth sub-active portion on the base substrate in the first direction.

[0028] In an exemplary embodiment of the present disclosure, the overlapping area of ​​the orthographic projection of the fourth sub-active portion on the substrate and the orthographic projection of the first gate line on the substrate is S1; the overlapping area of ​​the orthographic projection of the fifth sub-active portion on the substrate and the orthographic projection of the second gate line on the substrate is S2; wherein S1 is greater than S2.

[0029] In an exemplary embodiment of the present disclosure, the first connecting portion includes: a fourth conductive portion, a fifth conductive portion, and a sixth conductive portion, the fourth conductive portion is connected to the third sub-active portion through a via, and the orthographic projection of the fourth conductive portion on the substrate substrate at least partially overlaps with the orthographic projection of the first gate line on the substrate substrate; the fifth conductive portion is connected to the fourth conductive portion, and the orthographic projection of the fifth conductive portion on the substrate substrate overlaps with the orthographic projection of the second gate line on the substrate substrate; the sixth conductive portion is connected to the fifth conductive portion, and the orthographic projection of the sixth conductive portion on the substrate substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate substrate; wherein the size of the orthographic projection of the fifth conductive portion on the substrate substrate in the first direction is smaller than the size of the orthographic projection of the sixth conductive portion on the substrate substrate in the first direction.

[0030] In an exemplary embodiment of the present disclosure, the first connecting portion includes: a fourth conductive portion, a fifth conductive portion, and a sixth conductive portion, the fourth conductive portion is connected to the third sub-active portion through a via, and the orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the fourth sub-active portion on the substrate; the fifth conductive portion is connected to the fourth conductive portion, and the orthographic projection of the fifth conductive portion on the substrate covers the orthographic projection of the fifth sub-active portion on the substrate; the sixth conductive portion is connected to the fifth conductive portion, and the sixth conductive portion on the substrate covers the orthographic projection of the sixth sub-active portion on the substrate; wherein the size of the orthographic projection of the fifth conductive portion on the substrate in the first direction is smaller than the size of the orthographic projection of the sixth conductive portion on the substrate in the first direction.

[0031] In an exemplary embodiment of the present disclosure, the display panel also includes: a fifth conductive layer, the fifth conductive layer is located on the side of the fourth conductive layer away from the base substrate, the fifth conductive layer includes: a power line, the orthographic projection of the power line on the base substrate extends along a second direction, and the orthographic projection of the power line on the base substrate covers the orthographic projection of the second active portion on the base substrate.

[0032] In an exemplary embodiment of the present disclosure, the power line includes a sixth extension portion and a seventh extension portion, the size of the orthographic projection of the sixth extension portion on the base substrate in the first direction is larger than the size of the orthographic projection of the seventh extension portion on the base substrate in the first direction; the orthographic projection of the sixth extension portion on the base substrate covers the orthographic projection of the second active portion on the base substrate.

[0033] In an exemplary embodiment of the present disclosure, a second opening is formed on the sixth extension portion, and an orthographic projection of the second opening on the base substrate at least partially overlaps with an orthographic projection of the second gate line on the base substrate.

[0034] In an exemplary embodiment of the present disclosure, the display panel also includes: an anode layer, the anode layer is located on the side of the fifth conductive layer away from the base substrate, the anode layer includes a plurality of anode parts, and the orthographic projection of the anode part on the base substrate covers the orthographic projection of the first active part on the base substrate.

[0035] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0038] Figure 1 A schematic diagram of a circuit structure of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0039] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0040] Figure 3 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0041] Figure 4 for Figure 3 The structural layout of the first active layer in FIG.

[0042] Figure 5 for Figure 3 A structural layout of the first conductive layer;

[0043] Figure 6 for Figure 3 The structural layout of the second conductive layer;

[0044] Figure 7 for Figure 3 The structural layout of the second active layer;

[0045] Figure 8 for Figure 3 The structural layout of the third conductive layer;

[0046] Fig. 9 for Figure 3 The structural layout of the fourth conductive layer;

[0047] Fig.10 for Figure 3 The structural layout of the fifth conductive layer;

[0048] Fig.11 for Figure 3 A structural layout of a first active layer and a first conductive layer;

[0049] Fig.12 for Figure 3 A structural layout of a first active layer, a first conductive layer, and a second conductive layer;

[0050] Fig.13 for Figure 3 A structural layout of a first active layer, a first conductive layer, a second conductive layer, and a second active layer;

[0051] Fig.14 for Figure 3 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer;

[0052] Fig.15 for Figure 3 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0053] Fig.16 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0054] Fig.17 for Fig.16 A structural layout of the first conductive layer;

[0055] Fig.18 for Fig.16 The structural layout of the second conductive layer;

[0056] Fig.19 for Fig.16 The structural layout of the fourth conductive layer;

[0057] Fig. 20 The structural layout of an exemplary embodiment of the display panel disclosed in the present invention;

[0058] Fig.21 for Fig. 20 The structural layout of the first active layer in FIG.

[0059] Fig. 22 for Fig. 20 A structural layout of the first conductive layer;

[0060] Fig.23 for Fig. 20 The structural layout of the second conductive layer;

[0061] Fig.24 for Fig. 20 The structural layout of the second active layer;

[0062] Fig.25 for Fig. 20 The structural layout of the third conductive layer;

[0063] Fig.26 for Fig. 20 The structural layout of the fourth conductive layer;

[0064] Fig. 27 for Fig. 20 The structural layout of the fifth conductive layer;

[0065] Fig.28 for Fig. 20 A structural layout of a first active layer and a first conductive layer;

[0066] Fig.29 for Fig. 20 A structural layout of a first active layer, a first conductive layer, and a second conductive layer;

[0067] Fig.30 for Fig. 20 A structural layout of a first active layer, a first conductive layer, a second conductive layer, and a second active layer;

[0068] Fig.31 for Fig. 20 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer;

[0069] Fig.32 for Fig. 20 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0070] Fig.33 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0071] Fig.34 for Fig.33 The structural layout of the fourth conductive layer;

[0072] Fig.35 for Fig.33 The structural layout of the fifth conductive layer;

[0073] Fig.36 for Fig.33 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0074] Fig.37 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0075] Fig.38 for Fig.37 The structural layout of the second active layer;

[0076] Fig.39 for Fig.37 The structural layout of the fourth conductive layer;

[0077] Fig.40 for Fig.37 The structural layout of the fifth conductive layer;

[0078] Fig.41 for Fig.37 A structural layout of a first active layer, a first conductive layer, a second conductive layer, and a second active layer;

[0079] Fig.42 for Fig.37 A structural layout of a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer;

[0080] Fig.43 A structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0081] Fig.44 for Fig.43 Partial cross-sectional view along dotted line A. DETAILED DESCRIPTION

[0082] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0083] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0084] like Figure 1 FIG. 2 is a schematic diagram of the circuit structure of the pixel driving circuit in the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED, used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, which have a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage. At the same time, the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon transistors, which have a high carrier mobility, so as to facilitate the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.

[0085] like Figure 2 As shown, Figure 1A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage T3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the first gate drive signal terminal G1 outputs a high level signal, the second gate drive signal terminal G2 outputs a low level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da output a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal, and Vth is the threshold voltage of the drive transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t4: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that Figure 1 The pixel driving circuit shown may also have other driving modes. For example, both the first transistor T1 and the seventh transistor T7 may be reset in the first reset phase, so the driving method may not set the second reset phase.

[0086] This exemplary embodiment first provides a display panel, which may include Figure 1 The pixel driving circuit shown in the figure, the display panel may also include a base substrate, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence, and an insulating layer may be provided between the above layers. Figure 3-15 As shown, Figure 3 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Figure 4 for Figure 3 The structural layout of the first active layer in Figure 5 for Figure 3 The structural layout of the first conductive layer in Figure 6 for Figure 3 The structural layout of the second conductive layer in Figure 7 for Figure 3 The structural layout of the second active layer, Figure 8 for Figure 3 The structural layout of the third conductive layer in Fig. 9 for Figure 3 The structural layout of the fourth conductive layer in Fig.10 for Figure 3 The structure of the fifth conductive layer in the figure is as follows: Fig.11 for Figure 3 The structural layout of the first active layer and the first conductive layer, Fig.12 for Figure 3 The structural layout of the first active layer, the first conductive layer, and the second conductive layer, Fig.13 for Figure 3 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Fig.14 for Figure 3 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Fig.15 for Figure 3 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.

[0087] like Figure 3 , 6 As shown in , 7, 8, 9, 12, 13, 14, and 15, the second conductive layer may include a third gate line 1Re1, the orthographic projection of the third gate line 1Re1 on the substrate extends along the first direction X, and a partial structure of the third gate line 1Re1 is used to form a first gate of the first transistor T1. The partial structure of the second active layer is used to form a channel region of the first transistor T1. The third conductive layer may include a fifth gate line 2Re1, the orthographic projection of the fifth gate line 2Re1 on the substrate may extend along the first direction X, and a partial structure of the fifth gate line 2Re1 may be used to form a second gate of the first transistor T1. The fourth conductive layer may include a first initial signal line Vinit1, the orthographic projection of the first initial signal line Vinit1 on the substrate may extend along the first direction X, and the first initial signal line Vinit1 may be used to provide Figure 1 The first initial signal terminal in.

[0088] In this exemplary embodiment, the first initial signal line Vinit1 is disposed in the fourth conductive layer outside the second conductive layer and the third conductive layer. On the one hand, the spacing between the orthographic projection of the first initial signal line Vinit1 on the substrate substrate and the orthographic projection of the third gate line 1Re1 on the substrate substrate in the second direction Y can be designed to be smaller, and even the orthographic projection of the first initial signal line Vinit1 on the substrate substrate can intersect with the orthographic projection of the third gate line 1Re1 on the substrate substrate. Similarly, the spacing between the orthographic projection of the first initial signal line Vinit1 on the substrate substrate and the orthographic projection of the fifth gate line 2Re1 on the substrate substrate in the second direction Y can be designed to be smaller, and even the orthographic projection of the first initial signal line Vinit1 on the substrate substrate can intersect with the orthographic projection of the fifth gate line 2Re1 on the substrate substrate, so that the pixel driving circuit can have a smaller size in the second direction Y, wherein the second direction Y intersects with the first direction X, for example, the first direction X is perpendicular to the second direction Y. On the other hand, since the first initial signal line Vinit1 and the third gate line 1Re1 are located in different conductive layers, there is a smaller parasitic capacitance between the third gate line 1Re1 and the first initial signal line Vinit1. Since the first initial signal line Vinit1 and the fifth gate line 2Re1 are located in different conductive layers, there is a smaller parasitic capacitance between the fifth gate line 2Re1 and the first initial signal line Vinit1. That is, the display panel provided by this exemplary embodiment can reduce the parasitic capacitance of the fifth gate line 2Re1 and the third gate line 1Re1, thereby improving the response speed of the first transistor.

[0089] In this exemplary embodiment, the square resistance of the fourth conductive layer may be smaller than the square resistance of the second conductive layer, and the square resistance of the fourth conductive layer may be smaller than the square resistance of the third conductive layer. This setting can improve the uniformity of the voltage of the first initial signal terminal at different positions of the display panel by reducing the resistance of the first initial signal line Vinit1 itself.

[0090] like Figure 3 , 6 As shown in , 7, 8, 9, 12, 13, 14, and 15, the first conductive layer may further include a second reset signal line Re2, and a portion of the second reset signal line Re2 may be used to form a gate of the seventh transistor T7. The fourth conductive layer may further include a second initial signal line Vinit2, and the second initial signal line Vinit2 may be used to provide Figure 1The distance between the orthographic projection of the second initial signal line Vinit2 on the substrate substrate and the orthographic projection of the second reset signal line Re2 on the substrate substrate in the second direction Y can be designed to be smaller, and even the orthographic projection of the second initial signal line Vinit2 on the substrate substrate can intersect with the orthographic projection of the second reset signal line Re2 on the substrate substrate. This setting can further reduce the size of the pixel driving circuit in the second direction Y.

[0091] like Figure 3 As shown, the second initial signal line Vinit2 in the pixel driving circuit can be shared as the first initial signal line Vinit1 in the next row of pixel driving circuits; the first initial signal line Vinit1 in the pixel driving circuit can be shared as the second initial signal line Vinit2 in the previous row of pixel driving circuits. This arrangement can further reduce the size of the pixel driving circuit in the second direction.

[0092] It should be understood that in other exemplary embodiments, the first initial signal line Vinit1 and the second initial signal line Vinit2 may also be arranged in other conductive layers, for example, the first initial signal line Vinit1 and the second initial signal line Vinit2 may also be arranged in the first conductive layer, the fifth conductive layer, etc. In addition, the first initial signal line Vinit1 and the second initial signal line Vinit2 may be located in the same conductive layer or in different conductive layers. In addition, in other exemplary embodiments, the pixel driving circuit in the display panel may have other structures, and the pixel driving circuit may have other driving methods.

[0093] The following exemplary embodiment describes the overall layout structure of the display panel:

[0094] like Figure 3 , 4 As shown in Figure 11, the first active layer may include active portion 064, active portion 065, active portion 066, and active portion 067, wherein active portion 064 is used to form the channel region of the fourth transistor, active portion 065 is used to form the channel region of the fifth transistor, active portion 066 is used to form the channel region of the sixth transistor, active portion 067 is used to form the channel region of the seventh transistor, and active portion 063 is used to form the channel region of the driving transistor T3. The first active layer may be formed of polycrystalline silicon semiconductor.

[0095] like Figure 3 , 5 As shown in FIG. 11 , the first conductive layer may further include a first gate line G2, an enable signal line EM, and a first conductive portion 011, wherein the first gate line G2 is used to provide Figure 1 The second gate drive signal terminal in the enable signal line EM is used to provide Figure 1The first conductive portion 011 is used to form the gate of the driving transistor T3 and an electrode of the capacitor C. The first active layer can be formed by conductorization using the first conductive layer as a mask, that is, the portion blocked by the first conductive layer forms the channel region of the transistor, and the portion not blocked by the first conductive layer forms a conductor structure.

[0096] like Figure 3 , 6 As shown in FIG. 12 , the second conductive layer may further include: a second gate line 1G1 and a third conductive portion 021, wherein the second gate line 1G1 is used to provide Figure 1 The third conductive portion 021 can form another electrode of the capacitor C.

[0097] like Figure 3 , 7 As shown in Figure 13, the second active layer may include a first sub-active portion 071, a second sub-active portion 072, and a third sub-active portion 073 connected between the first sub-active portion 071 and the second sub-active portion 072, the first sub-active portion 071 is used to form a channel region of the first transistor, and the second sub-active portion 072 is used to form a channel region of the second transistor. The second active layer may be formed of an oxide semiconductor, such as indium gallium zinc oxide.

[0098] like Figure 3 , 8 As shown in 14, the third conductive layer may further include: a fourth gate line 2G1, the fourth gate line 2G1 is used to provide Figure 1The first gate drive signal terminal in. The fifth gate line 2Re1 and the third gate line 1R1 can be connected by a via, and the via can be located in the edge routing area surrounding the display area; the fourth gate line 2G1 and the second gate line 1G1 can be connected by a via, and the via can be located in the edge routing area surrounding the display area. The orthographic projection of the fourth gate line 2G1 on the substrate can cover the orthographic projection of the second sub-active portion 072 on the substrate, and a partial structure of the fourth gate line 2G1 can be used to form the second gate of the second transistor, the orthographic projection of the second gate line 1G1 on the substrate can cover the orthographic projection of the second sub-active portion 072 on the substrate, and a partial structure of the second gate line 1G1 can be used to form the first gate of the second transistor. The orthographic projection of the third gate line 1Re1 on the substrate can cover the orthographic projection of the first sub-active portion 071 on the substrate, and a partial structure of the third gate line 1Re1 can be used to form the first gate of the first transistor. The orthographic projection of the fifth gate line 2Re1 on the substrate can cover the orthographic projection of the first sub-active portion 071 on the substrate, and a partial structure of the fifth gate line 2Re1 can be used to form the second gate of the first transistor. The second active layer can be formed as a conductor using the third conductive layer as a mask, that is, the portion blocked by the third conductive layer forms the channel region of the transistor, and the portion not blocked by the third conductive layer forms a conductor structure.

[0099] like Figure 3 , 9 As shown in FIG. 15 , the fourth conductive layer may further include: a first power line VDD1, a connecting portion 041, a connecting portion 042, a connecting portion 043, and a connecting portion 044. The first power line VDD1 is used to provide Figure 1 The first power supply terminal in the first initial signal line Vinit1 is used to provide Figure 1 The first initial signal terminal and the second initial signal line Vinit2 are used to provide Figure 1The second initial signal terminal in. The connecting portion 041 can be connected to the first active layer on one side of the active portion 064 through a via (black square) to connect the first electrode of the fourth transistor. The connecting portion 042 can be connected to the first conductive portion 011 and the third sub-active portion 073 through vias to connect the gate of the driving transistor and the first electrode of the first transistor, and the gate of the driving transistor and the first electrode of the second transistor. The connecting portion 043 can be connected to the first active layer on one side of the active portion 066 and the second active layer on one side of the second sub-active portion 072 through vias to connect the first electrode of the sixth transistor and the second electrode of the second transistor. The connecting portion 044 can be connected to the first active layer on one side of the active portion 066 through a via to connect the second electrode of the sixth transistor. The first power line VDD1 can be connected to the first active layer on one side of the active portion 065 through a via to connect the first electrode of the fifth transistor and the first power supply terminal. The first power line VDD1 can also be connected to the third conductive portion 021 through a via to connect the capacitor C and the first power supply terminal. The first initial signal line Vinit1 may be connected to the second active layer on one side of the first sub-active portion 071 through a via hole to connect the second electrode of the first transistor and the first initial signal terminal. The second initial signal line may be connected to the first active layer on one side of the active portion 067 through a via hole to connect the second initial signal terminal and the second electrode of the seventh transistor. The positive projection of the first initial signal line Vinit1 on the substrate substrate may be located on a side where the positive projection of the third gate line 1Re1 on the substrate substrate is away from the positive projection of the first conductive portion 011 on the substrate substrate, and the positive projection of the first initial signal line Vinit1 on the substrate substrate may be located on a side where the positive projection of the fifth gate line 2Re1 on the substrate substrate is away from the positive projection of the first conductive portion 011 on the substrate substrate. The positive projection of the second initial signal line Vinit2 on the substrate substrate may be located on a side where the positive projection of the second reset signal line Re2 on the substrate substrate is away from the positive projection of the first conductive portion 011 on the substrate substrate.

[0100] like Figure 3 , 10 As shown, the fifth conductive layer may include: a second power line VDD2, a data line Da, and a connecting portion 051, wherein the second power line VDD2 is used to provide Figure 1 The first power supply terminal in the data line Da is used to provide Figure 1 The orthographic projection of the second power line VDD2 on the substrate and the orthographic projection of the data line Da on the substrate can both extend along the second direction Y. The second power line VDD2 can be connected to the first power line VDD1 through a via. The data line Da can be connected to the connecting portion 041 through a via to connect the first electrode of the fourth transistor and the data signal terminal. The connecting portion 051 can be connected to the connecting portion 044 through a via, and the connecting portion 051 can be used to connect Figure 1 The anode of the light-emitting unit. Figure 3As described above, the orthographic projection of the first power line VDD1 on the base substrate may be located between the orthographic projection of the data line Da on the base substrate and the orthographic projection of the first conductive portion 011 on the base substrate, and the first power line VDD1 may shield the interference of the data line Da on the first conductive portion 011 .

[0101] like Figure 3 , 12 As shown in FIG. 15 , the orthographic projection of the second gate line 1G1 on the base substrate is located between the first gate line G2 and the first conductive portion 011. Figure 2 As shown, at the end of the compensation stage T2, the signal at the first gate drive signal end changes from a high level to a low level, and the signal at the second gate drive signal end changes from a low level to a high level, that is, at the end of the compensation stage T2, the signal of the second gate line 1G1 changes from a high level to a low level, and the signal of the first gate line G2 changes from a low level to a high level. The second gate line 1G1 is closer to the first conductive part 011 than the first gate line G2, so that at the end of the compensation stage T2, the pull-down effect of the second gate line 1G1 on the gate of the driving transistor T3 (the first conductive part 011) is stronger than the pull-up effect of the first gate line G2 on the gate of the driving transistor T3 (the first conductive part 011). The gate of the driving transistor T3 (the first conductive part 011) will be pulled down at the end of the compensation stage T2, thereby affecting the brightness of the light-emitting unit in the light-emitting stage.

[0102] Based on this, the present exemplary embodiment also provides another display panel, in which the first initial signal line and the second initial signal line are connected to the display panel. Figure 3 The first initial signal line and the second initial signal line in the display panel have the same arrangement. In addition, the display panel may include Figure 1 The pixel driving circuit shown in FIG. Figure 16-19 As shown, Fig.16 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Fig.17 for Fig.16 The structural layout of the first conductive layer in Fig.18 for Fig.16 The structural layout of the second conductive layer in Fig.19 for Fig.16The structure layout of the fourth conductive layer in the display panel. The display panel may also include: a base substrate, a first conductive layer, a second conductive layer, a second conductive portion, and a fourth conductive layer; wherein the second conductive portion may include a first sub-conductive portion 21, and the first sub-conductive portion 21 may be formed in the same layer as the second conductive layer, that is, the first sub-conductive portion 21 and the second conductive layer are formed by the same patterning process, and the first sub-conductive portion 21 is located in the second conductive layer. The first conductive layer may be located on one side of the base substrate, and the first conductive layer may include: a first gate line G2 and a first conductive portion 11, and the orthographic projection of the first gate line G2 on the base substrate may extend along the first direction X, and a partial structure of the first gate line G2 may be used to form the gate of the fourth transistor T4, and the first conductive portion 11 may be used to form the gate of the driving transistor T3; the second conductive layer may be located on one side of the base substrate, and the second conductive layer may include a second gate line 1G1, and the orthographic projection of the second gate line 1G1 on the base substrate may extend along the first direction X, and a partial structure of the second gate line 1G1 may be used to form the first gate of the second transistor T2, and the orthographic projection of the second gate line 1G1 on the base substrate may be located at The orthographic projection of the first conductive part 11 on the base substrate is between the orthographic projection of the first gate line G2 on the base substrate; the orthographic projection of the second conductive part on the base substrate may at least partially overlap with the orthographic projection of the first gate line G2 on the base substrate, for example, the orthographic projection of the first sub-conductive part 21 on the base substrate may at least partially overlap with the orthographic projection of the first gate line G2 on the base substrate; the fourth conductive layer may be located on one side of the base substrate, and the fourth conductive layer may include: a first connecting part 41, the first connecting part 41 may be connected to the first conductive part 11 and the second conductive part through a via H, for example, the first connecting part 41 may be connected to the first conductive part 11 and the first sub-conductive part 21 through a via H, respectively. The first conductive part 11 may also be used to form an electrode of a capacitor C.

[0103] In this exemplary embodiment, the first gate line G2 can provide Figure 1 The second gate drive signal terminal G2 in the second gate line 1G1 can provide Figure 1The first gate drive signal terminal G1 in the second conductive layer. In this exemplary embodiment, a first sub-conductive portion 21 is additionally provided in the second conductive layer. The orthographic projection of the first sub-conductive portion 21 on the substrate substrate at least partially overlaps with the orthographic projection of the first gate line G2 on the substrate substrate. The first sub-conductive portion 21 can form a parallel plate capacitor structure with the first gate line G2. The first gate line G2 has a certain coupling effect on the first sub-conductive portion 21. At the same time, since the first sub-conductive portion 21 is connected to the gate of the driving transistor (the first conductive portion 11) through the first connecting portion 41, the arrangement can increase the coupling effect of the first gate line G2 on the gate of the driving transistor (the first conductive portion 11), that is, the pull-up effect of the first gate line G2 on the gate of the driving transistor (the first conductive portion 11) is increased at the end of the compensation stage T2. On the one hand, the first gate line G2 and the first sub-conductive portion 21 work together to offset the pull-down effect of the second gate line 1G1 on the gate of the driving transistor (the first conductive portion 11), thereby making the voltage of the gate of the driving transistor unchanged at the end of the compensation stage; on the other hand, the first gate line G2 and the first sub-conductive portion 21 work together to increase the voltage of the gate of the driving transistor at the end of the compensation stage, thereby reducing the voltage of the data signal required to be provided by the data signal terminal when the display panel displays a black screen, that is, reducing the power of the source drive circuit.

[0104] In this exemplary embodiment, Figure 16-19 As shown, the second conductive layer can be located on the side of the first conductive layer away from the base substrate, and the fourth conductive layer can be located on the side of the second conductive layer away from the base substrate. In this exemplary embodiment, there is a small distance between the first sub-conductive portion 21 and the first gate line G2, so that the first gate line G2 can have a strong coupling effect on the first sub-conductive portion 21. It should be understood that there can be other relative positional relationships between the first conductive layer, the second conductive layer, and the fourth conductive layer, and the first sub-conductive portion 21 can also be located in other conductive layers, for example, the first sub-conductive portion 21 can be located in a light-shielding metal layer, a source-drain layer, etc. Correspondingly, in other exemplary embodiments, the distance between the first sub-conductive portion 21 and the first gate line G2 can also be reduced by reducing the thickness of the insulating layer between the first sub-conductive portion 21 and the first gate line G2. The second conductive portion may further include other conductive structures located in other conductive layers, which are connected to the first connecting portion, and the orthographic projection of the conductive portion on the substrate substrate at least partially overlaps with the orthographic projection of the first gate line on the substrate substrate, so that the conductive portion can also achieve a pull-up effect on the gate of the driving transistor at the end of the compensation stage T2. In addition, in other exemplary embodiments, the pixel driving circuit may have other structures, and the pixel driving circuit may have other driving methods.

[0105] It should be noted that, in this exemplary embodiment, the orthographic projection of structure A on the substrate extends along the X direction. It can be understood that the orthographic projection of structure A on the substrate extends along the X direction as a whole, that is, the orthographic projection of structure A on the substrate can be bent and extended along the X direction, or can be extended in a straight line along the X direction.

[0106] The display panel provided by this exemplary embodiment may further include a first active layer, a third conductive layer, and a fifth conductive layer, wherein the substrate, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be stacked in sequence. An insulating layer may be provided between the adjacent layers. The following exemplary embodiment describes the overall structure of the display panel, as shown in FIG. Figure 20-32 As shown, Fig. 20 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Fig.21 for Fig. 20 The structural layout of the first active layer in Fig. 22 for Fig. 20 The structural layout of the first conductive layer in Fig.23 for Fig. 20 The structural layout of the second conductive layer in Fig.24 for Fig. 20 The structural layout of the second active layer, Fig.25 for Fig. 20 The structural layout of the third conductive layer in Fig.26 for Fig. 20 The structural layout of the fourth conductive layer in Fig. 27 for Fig. 20 The structure of the fifth conductive layer in the figure is as follows: Fig.28 for Fig. 20 The structural layout of the first active layer and the first conductive layer, Fig.29 for Fig. 20 The structural layout of the first active layer, the first conductive layer, and the second conductive layer, Fig.30 for Fig. 20 The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Fig.31 for Fig. 20 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Fig.32 for Fig. 20 The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.

[0107] like Fig. 20 , 21As shown in Figures 28, the first active layer may include active portion 64, active portion 65, active portion 66, active portion 67, and active portion 63, wherein active portion 64 is used to form the channel region of the fourth transistor, active portion 65 is used to form the channel region of the fifth transistor, active portion 66 is used to form the channel region of the sixth transistor, active portion 67 is used to form the channel region of the seventh transistor, and active portion 63 is used to form the channel region of the driving transistor T3. The first active layer may be formed of polycrystalline silicon semiconductor.

[0108] like Fig. 20 , 22 As shown in FIG. 28 , the first conductive layer may further include: an enable signal line EM and a second reset signal line Re2, wherein the enable signal line EM is used to provide Figure 1 The second reset signal line Re2 is used to provide Figure 1 The orthographic projections of the enable signal line EM and the second reset signal line Re2 on the substrate can extend along the first direction X. The first active layer can be formed as a conductor using the first conductive layer as a mask, that is, the portion blocked by the first conductive layer forms a channel region of the transistor, and the portion not blocked by the first conductive layer forms a conductor structure.

[0109] like Fig. 20 , 23 As shown in FIG. 29 , the second conductive layer may further include: a third gate line 1Re1 and a third conductive portion 23, wherein the third gate line 1Re1 is used to provide Figure 1 The third conductive portion 23 may form another electrode of the capacitor C. The orthographic projection of the third gate line 1Re1 on the substrate may extend along the first direction X. The third conductive portion 23 may be provided with a first opening 231 .

[0110] like Fig. 20 , 24 30, the second active layer may include a first active portion 7, and the first active portion 7 may include a first sub-active portion 71, a second sub-active portion 72, and a third sub-active portion 73 connected between the first sub-active portion 71 and the second sub-active portion 72. The first sub-active portion 71 may be used to form a channel region of the first transistor T1, and the second sub-active portion 72 may be used to form a channel region of the second transistor T2. The second active layer may be formed of an oxide semiconductor, such as indium gallium zinc oxide.

[0111] like Fig. 20 , 25 As shown in FIG. 31 , the third conductive layer may include: a fifth gate line 2Re1 and a fourth gate line 2G1. The fifth gate line 2Re1 is used to provide Figure 1 The first reset signal terminal in the fourth gate line 2G1 is used to provide Figure 1The first gate drive signal terminal in. The orthographic projections of the fifth gate line 2Re1 and the fourth gate line 2G1 on the substrate can extend along the first direction X. Any segment of the orthographic projection of the fifth gate line 2Re1 on the substrate in its extension direction can at least partially overlap with the orthographic projection of the third gate line 1R1 on the substrate; any segment of the orthographic projection of the fourth gate line 2G1 on the substrate in its extension direction can at least partially overlap with the orthographic projection of the second gate line 1G1 on the substrate. The fifth gate line 2Re1 and the third gate line 1R1 can be connected by a via hole, wherein the via hole can be located in the non-display area of ​​the display panel; the fourth gate line 2G1 and the second gate line 1G1 can be connected by a via hole, wherein the via hole can be located in the non-display area of ​​the display panel. The second active layer can be formed by conductorization using the third conductive layer as a mask, that is, the portion blocked by the third conductive layer forms a channel region of the transistor, and the portion not blocked by the third conductive layer forms a conductor structure.

[0112] like Fig. 20 , 26 As shown in FIG. 32 , the fourth conductive layer may further include: a first initial signal line Vinit1, a second initial signal line Vinit2, a connecting portion 42, a connecting portion 43, a connecting portion 44, and a connecting portion 45. The first initial signal line Vinit1 may be used to provide Figure 1 The first initial signal terminal and the second initial signal line Vinit2 are used to provide Figure 1The first connecting portion 41 can be connected to the first conductive portion 11 through the first via H5, connected to the first sub-conductive portion 21 through the via H4, and connected to the third sub-active portion 73 through the via H3, so as to connect the gate of the driving transistor T3 and the first electrode of the first transistor T1, and the gate of the driving transistor T3 and the first electrode of the second transistor T2. Among them, the positive projection of the first via H5 on the substrate can be located within the positive projection of the first opening 231 on the substrate, that is, the positive projection edge of the first via H5 on the substrate and the positive projection edge of the first opening 231 on the substrate are spaced apart, so that the conductive structure in the first via H5 is insulated from the third conductive portion 23. The connecting portion 42 can be connected to the first active layer on one side of the active portion 64 through the via H2 to connect the first electrode of the fourth transistor T4. The connecting portion 43 can be connected to the first active layer on one side of the active portion 66 through the via H7, and connected to the second active layer on one side of the second sub-active portion 72 through the via H6 to connect the first electrode of the sixth transistor and the second electrode of the second transistor. The connecting portion 44 may be connected to the first active layer on one side of the active portion 66 through the via H10 to connect the second electrode of the sixth transistor. The connecting portion 45 may be connected to the first active layer on one side of the active portion 65 through the via H9, and connected to the third conductive portion 23 through the via H8 to connect the capacitor C and the first electrode of the fifth transistor. The first initial signal line Vinit1 may be connected to the second active layer on one side of the first sub-active portion 71 through the via H1 to connect the second electrode of the first transistor T1 and the first initial signal terminal. The second initial signal line Vinit2 may be connected to the first active layer on one side of the active portion 67 through the via H13 to connect the second initial signal terminal and the second electrode of the seventh transistor T7.

[0113] like Fig. 20 , 27 As shown, the fifth conductive layer may include: a power line VDD, a data line Da, and a connecting portion 51, wherein the power line VDD is used to provide Figure 1 The first power supply terminal in the data line Da is used to provide Figure 1 The power line VDD can be connected to the connecting portion 45 through the via H12. The data line Da can be connected to the connecting portion 42 through the via H14 to connect the first electrode of the fourth transistor and the data signal terminal. The connecting portion 51 can be connected to the connecting portion 44 through the via H11. The connecting portion 51 can be used to connect Figure 1 The anode of the light-emitting unit.

[0114] In this exemplary embodiment, Fig. 20As shown, the orthographic projection of the power line VDD on the substrate can extend along the second direction Y, and the orthographic projection of the power line VDD on the substrate can cover the orthographic projection of the first active portion 7 on the substrate. The characteristics of the oxide semiconductor are easily changed under the action of light. In this exemplary embodiment, the power line VDD is used to shield the first active portion 7, thereby improving the stability of the first transistor T1 and the second transistor T2.

[0115] In this exemplary embodiment, the second active layer may be located between the second conductive layer and the third conductive layer. It should be understood that in other exemplary embodiments, the display panel may not include the third conductive layer, and the second active layer may be located between the first conductive layer and the second conductive layer. Accordingly, the first conductive layer may also be provided with a gate line connected in parallel with the second gate line 1G1 and a gate line connected in parallel with the third gate line 1Re1.

[0116] In this exemplary embodiment, the first initial signal line Vinit1 and the second initial signal line Vinit2 can output initial signals of the same voltage or different voltages. When the first initial signal line Vinit1 and the second initial signal line Vinit2 output initial signals of the same voltage, the second initial signal line Vinit2 can be shared as the first initial signal line Vinit1 in the next row of pixel driving circuits.

[0117] In this exemplary embodiment, Fig. 20 , 27As shown, the power line VDD may include: a first extension portion VDD1, a second extension portion VDD2, and a third extension portion VDD3, wherein the orthographic projection of the first extension portion VDD1 on the substrate may extend along the second direction Y, and the orthographic projection of the first extension portion VDD1 on the substrate may at least partially overlap with the orthographic projection of the first opening 231 on the substrate; the orthographic projection of at least part of the structure of the second extension portion VDD2 on the substrate may extend along the second direction Y, and the orthographic projection of the second extension portion VDD2 on the substrate may cover the first active portion 7; the third extension portion VDD3 may be connected between the first extension portion VDD1 and the second extension portion VDD2, the orthographic projection of the third extension portion VDD3 on the substrate may extend along the first direction X, and the orthographic projection of the third extension portion VDD3 on the substrate may at least partially overlap with the orthographic projection of the first opening 231 on the substrate. Among them, the orthographic projection of the first extension portion VDD1 on the base substrate at least partially overlaps with the orthographic projection of the first opening 231 on the base substrate, so that the first extension portion VDD1 can form a parallel plate capacitor structure with the first conductive portion 11, and this setting can not only increase the capacitance value of the capacitor C, but also the first extension portion VDD1 can stabilize the voltage of the first conductive portion 11. Similarly, the orthographic projection of the third extension portion VDD3 on the base substrate at least partially overlaps with the orthographic projection of the first opening 231 on the base substrate, so that the third extension portion VDD3 can form a parallel plate capacitor structure with the first conductive portion 11, and this setting can not only increase the capacitance value of the capacitor C, but also the third extension portion VDD3 can stabilize the voltage of the first conductive portion 11.

[0118] like Figure 3 As shown, the second transistor T2 as an oxide transistor has a smaller leakage current, and the second transistor T2 has two gates located in the second conductive layer and the third conductive layer respectively. Compared with the single-gate structure of the fourth transistor T4, the second transistor T2 has a higher switching current ratio, a lower subthreshold swing and a stronger device stability. However, the second transistor T2 is a dual-gate structure, which has a larger channel capacitance, so when the gate voltage of the second transistor T2 changes, the gate voltage of the second transistor T2 has a longer rising edge and falling edge, that is, when the second transistor T2 is driven, it takes a longer time to fully turn on or off the second transistor T2.

[0119] like Fig. 20 As shown, this exemplary embodiment is compared with Figure 3In the display panel shown in the figure, the exemplary embodiment does not set the first power line VDD1 in the fourth conductive layer, but only sets the power line VDD in the fifth conductive layer. This setting can reduce the parasitic capacitance between the second gate line 1G1 and the power line, and the parasitic capacitance between the fourth gate line 2G1 and the power line, thereby increasing the charging speed of the gate of the second transistor T2. Figure 3 In a single pixel driving circuit in, the sum of the parasitic capacitance between the first sub-gate driving signal line and the power line, and the sum of the parasitic capacitance between the second sub-gate driving signal line and the power line can reach 12fF. In the single pixel driving circuit of this exemplary embodiment, the sum of the parasitic capacitance between the second gate line 1G1 and the power line, and the sum of the parasitic capacitance between the fourth gate line 2G1 and the power line can be reduced to 7.5fF. It should be noted that this setting can also reduce the parasitic capacitance between the gate of the first transistor T1 and the power line, thereby increasing the charging speed of the gate of the first transistor T1. In addition, this setting can also be used to solve the technical problem of slow charging speed of the gate of the first transistor and the gate of the second transistor caused by other reasons.

[0120] In other exemplary embodiments, the fourth conductive layer and the fifth conductive layer may have other structures. Figure 33-36 As shown, Fig.33 This is a structural diagram of another exemplary embodiment of the display panel disclosed herein. Fig.34 for Fig.33 The structural layout of the fourth conductive layer in Fig.35 for Fig.33 The structure of the fifth conductive layer in the figure is as follows: Fig.36 for Fig.33 The structure of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in the display panel can be Fig. 20 The structure of the display panel is the same.

[0121] like Fig.33 , 34 , 36, and Fig. 20 Different from the display panel in FIG. 1 , in this exemplary embodiment, the fourth conductive layer may further include a connecting portion 46, wherein the connecting portion 45 is connected to the first active layer on one side of the active portion 65 through the via hole H9 to connect the first electrode of the fifth transistor. The connecting portion 46 is connected to the third conductive portion 23 through the via hole H8. Fig.33 , 35 As shown, the power line VDD is connected to the connection part 46 through the via H15 to connect to the third conductive part 23, and the power line VDD is connected to the connection part 45 through the via H12 to connect the first electrode of the fifth transistor and the first power supply terminal.

[0122] like Fig.35 As shown, Fig. 20 What is different from the display panel is that the power line VDD may also include a fourth extension portion VDD4. The second extension portion VDD2 may include a first sub-extension portion VDD21, and the orthographic projection of the first sub-extension portion VDD21 on the substrate may extend along the first direction X. The orthographic projection of the fourth extension portion VDD4 on the substrate may extend along the second direction Y, and the fourth extension portion VDD4 may be connected between the first sub-extension portion VDD21 and the first extension portion VDD1. The third extension portion VDD3, the fourth extension portion VDD4, and the second extension portion VDD2 may form a ring structure. This arrangement may reduce the resistance of the power line VDD itself, thereby improving the uniformity of the display of the display panel. As Fig.33 As shown, the orthographic projection of the first sub-extension VDD21 on the substrate substrate may at least partially overlap with the orthographic projection of the first initial signal line Vinit1 on the substrate substrate, and this arrangement may increase the light transmittance of the display panel. The orthographic projection of the first sub-extension VDD21 on the substrate substrate may at least partially not overlap with the orthographic projection of the third gate line 1Re1 on the substrate substrate, for example, the orthographic projection of the first sub-extension VDD21 on the substrate substrate may not overlap with the orthographic projection of the third gate line 1Re1 on the substrate substrate.

[0123] like Fig. 20 , 33 As shown, the overlapping area of ​​the orthographic projection of the power line VDD on the substrate and the orthographic projection of the first connection portion 41 on the substrate may be less than 70% of the orthographic projection area of ​​the first connection portion 41 on the substrate. For example, the overlapping area of ​​the orthographic projection of the power line VDD on the substrate and the orthographic projection of the first connection portion 41 on the substrate may be equal to 5%, 10%, 20%, 30%, 40%, 50%, 60%, etc. of the orthographic projection area of ​​the first connection portion 41 on the substrate.

[0124] In other exemplary embodiments, the second active layer, the fourth conductive layer, and the fifth conductive layer may have other structures. Figure 37-42 As shown, Fig.37 This is a structural diagram of another exemplary embodiment of the display panel disclosed herein. Fig.38 for Fig.37 The structural layout of the second active layer, Fig.39 for Fig.37 The structural layout of the fourth conductive layer in Fig.40 for Fig.37 The structure of the fifth conductive layer in the figure is as follows: Fig.41 for Fig.37The structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Fig.42 for Fig.37 The structure of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in the display panel can be Fig. 20 The structure of the display panel is the same.

[0125] like Fig.37 , 38 , 41, and Fig. 20 The difference from the display panel shown is that in this exemplary embodiment, the second conductive portion may further include a second active portion 74, and the second active portion 74 may be formed in the same layer as the second active layer, that is, the second active portion 74 is located in the second active layer. The orthographic projection of the second active portion 74 on the base substrate may at least partially overlap with the orthographic projection of the first gate line G2 on the base substrate, and the second active portion 74 is electrically connected to the first connecting portion 41.

[0126] In this exemplary embodiment, a second active portion 74 is added to the second active layer, and the second active portion 74 can form a parallel plate capacitor structure with the first gate line G2. The first gate line G2 has a certain coupling effect on the second active portion 74. At the same time, since the second active portion 74 is connected to the gate of the driving transistor (the first conductive portion 11) through the first connecting portion 41, the arrangement can increase the coupling effect of the first gate line G2 on the gate of the driving transistor (the first conductive portion 11), that is, increase the pull-up effect of the first gate line G2 on the gate of the driving transistor (the first conductive portion 11) at the end of the compensation stage T2. On the one hand, the first gate line G2 and the second active portion 74 can work together to offset the pull-down effect of the second gate line 1G1 on the gate of the driving transistor (the first conductive portion 11), so that the voltage of the gate of the driving transistor remains unchanged at the end of the compensation stage; on the other hand, the first gate line G2 and the second active portion 74 can also work together to increase the voltage of the gate of the driving transistor at the end of the compensation stage, so that the data signal voltage required to be provided by the data signal terminal when the display panel displays a black screen can be reduced, that is, the power of the source drive circuit is reduced.

[0127] In this exemplary embodiment, Fig.41As shown, the orthographic projection of the third gate line 1Re1 on the substrate substrate can be located on a side of the orthographic projection of the first gate line G2 on the substrate substrate away from the orthographic projection of the second gate line 1G1 on the substrate substrate, so that the orthographic projection of the third sub-active portion 73 on the substrate substrate can at least partially overlap with the orthographic projection of the first gate line G2 on the substrate substrate. Since the third sub-active portion 73 is connected to the first connecting portion 41, this arrangement can further enhance the pull-up effect of the first gate line on the gate of the driving transistor at the end of the compensation stage through the third sub-active portion 73.

[0128] In this exemplary embodiment, Fig.38As shown, the second active portion 74 may be connected to the third sub-active portion 73. The overlapping area of ​​the orthographic projection of the second active portion 73 on the substrate substrate and the orthographic projection of the second gate line 1G1 on the substrate substrate may be less than 50% of the orthographic projection area of ​​the second active portion 74 on the substrate substrate. For example, the overlapping area of ​​the orthographic projection of the second active portion 73 on the substrate substrate and the orthographic projection of the second gate line 1G1 on the substrate substrate may be equal to 1%, 2%, 3%, 4%, 5%, 7%, 10%, 20%, 30%, 40%, etc. of the orthographic projection area of ​​the second active portion 74 on the substrate substrate. The second active portion may include: a fourth sub-active portion 744, a fifth sub-active portion 745, and a sixth sub-active portion 746. The fourth sub-active portion 744 may be connected to the third sub-active portion 73. The orthographic projection of the fourth sub-active portion 744 on the substrate may extend along the first direction X, and the orthographic projection of the fourth sub-active portion 744 on the substrate may at least partially overlap with the orthographic projection of the first gate line G1 on the substrate. The fifth sub-active portion 745 may be connected to the fourth sub-active portion. The fifth sub-active portion 745 may be disposed on the substrate substrate. The orthographic projection on the panel can extend along the second direction Y, and the orthographic projection of the fifth sub-active portion 745 on the substrate substrate can intersect with the orthographic projection of the second gate line 1G1 on the substrate substrate, and the orthographic projection of the fifth sub-active portion 745 on the substrate substrate can intersect with the orthographic projection of the fourth gate line 2G1 on the substrate substrate; the sixth sub-active portion 746 can be connected to the fifth sub-active portion 745, and the orthographic projection of the sixth sub-active portion 746 on the substrate substrate can at least partially overlap with the orthographic projection of the third conductive portion 23 on the substrate substrate. Among them, the orthographic projection of the fourth sub-active portion 744 on the substrate substrate at least partially overlaps with the orthographic projection of the first gate line G1 on the substrate substrate, so that the shading effect of the fourth sub-active portion 744 on the display panel can be reduced, and the light transmittance of the display panel can be improved. In addition, the orthographic projection of the sixth sub-active portion 746 on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate, so that the sixth sub-active portion 746 can form a parallel plate capacitor structure with the third conductive portion 23, and this setting can increase the capacitance value of capacitor C.

[0129] In this exemplary embodiment, Fig.38As shown, the size of the orthographic projection of the fifth sub-active portion 745 on the base substrate in the first direction X may be smaller than the size of the orthographic projection of the sixth sub-active portion 746 on the base substrate in the first direction X. This arrangement can minimize the parasitic capacitance between the second gate line 1G1 and the fifth sub-active portion 745, and the parasitic capacitance between the fourth gate line 2G1 and the fifth sub-active portion 745, thereby increasing the charging speed of the second gate line 1G1.

[0130] In this exemplary embodiment, since the second transistor has a dual-gate structure, the second gate line 1G1 and the fourth gate line 2G1 form a large capacitance with other structures, and the charging speed of the gate of the second transistor is slower than that of the gate of the fourth transistor. Fig.38 As shown, the overlapping area of ​​the orthographic projection of the fourth sub-active portion 744 on the substrate and the orthographic projection of the first gate line G2 on the substrate can be S1; the overlapping area of ​​the orthographic projection of the fifth sub-active portion 745 on the substrate and the orthographic projection of the second gate line 1G1 on the substrate is S2; the overlapping area of ​​the orthographic projection of the fifth sub-active portion 745 on the substrate and the orthographic projection of the fourth gate line 2G1 on the substrate is S3, wherein S1 can be greater than S2, and S1 can be greater than S3. This exemplary embodiment can compensate for the charging speed of the gate of the second transistor through the difference in the projection overlapping area, so that the second transistor and the fourth transistor have similar or identical response speeds during the compensation stage.

[0131] In this exemplary embodiment, Fig.37 , 39 , 42, and Fig. 20The display panel shown in the figure is different in that the first connecting portion 41 may include: a fourth conductive portion 414, a fifth conductive portion 415, and a sixth conductive portion 416. The fourth conductive portion 414 may be connected to the third sub-active portion 73 through a via H3, and the orthographic projection of the fourth conductive portion 414 on the substrate may cover the orthographic projection of the fourth sub-active portion 744 on the substrate, and the orthographic projection of the fourth conductive portion 414 on the substrate may also at least partially overlap with the orthographic projection of the first gate line G2 on the substrate; the fifth conductive portion 415 may be connected to the fourth conductive portion 414, and the orthographic projection of the fifth conductive portion 415 on the substrate may cover the orthographic projection of the fifth sub-active portion 745 on the substrate. The orthographic projection of the fifth conductive portion 415 on the substrate substrate can also overlap with the orthographic projection of the second gate line 1G1 on the substrate substrate; the sixth conductive portion 416 can be connected to the fifth conductive portion 415, the sixth conductive portion 416 on the substrate substrate can cover the orthographic projection of the sixth sub-active portion 746 on the substrate substrate, and the sixth conductive portion 416 on the substrate substrate can also overlap with the orthographic projection of the third conductive portion on the substrate substrate at least in part; wherein the size of the orthographic projection of the fifth conductive portion 415 on the substrate substrate in the first direction X can be smaller than the size of the orthographic projection of the sixth conductive portion 416 on the substrate substrate in the first direction X. On the one hand, the first connecting portion 41 can produce a light shielding effect on the second active portion 74; on the other hand, the first connecting portion 41 can also form a parallel plate capacitor structure with the third conductive portion 23 to further increase the capacitance value of the capacitor C.

[0132] like Fig.38 , 42 As shown, the first connection part 41 can be connected to the first sub-conductive part 21 through the via H4, so that an opening 7441 is formed on the fourth sub-active part 744; the first connection part 41 can be connected to the first conductive part 11 through the via H5, so that an opening 7461 is formed on the sixth sub-active part 746.

[0133] In this exemplary embodiment, Fig.37 , 40 As shown, Fig. 20What is different from the display panel shown in the figure is that the power line VDD may include a sixth extension portion VDD6 and a seventh extension portion VDD7, and the size of the orthographic projection of the sixth extension portion VDD6 on the base substrate in the first direction X may be larger than the size of the orthographic projection of the seventh extension portion VDD7 on the base substrate in the first direction X; the orthographic projection of the sixth extension portion VDD6 on the base substrate may cover the orthographic projection of the second active portion 74 on the base substrate. The sixth extension portion VDD6 may form a parallel plate capacitor structure with the second active portion 74, thereby further increasing the capacitance value of the capacitor C. In addition, the sixth extension portion VDD6 may also form a parallel plate capacitor structure with the first connecting portion 41 to increase the capacitance value of the capacitor C. As shown in FIG. Fig.40 As shown, the sixth extension portion VDD6 may be provided with a second opening 52, and the orthographic projection of the second opening 52 on the base substrate may at least partially overlap with the orthographic projection of the second gate line 1G1 on the base substrate, and the orthographic projection of the second opening 52 on the base substrate may at least partially overlap with the orthographic projection of the fourth gate line 2G1 on the base substrate. Fig.40 As shown, the second opening 52 can be a closed figure, that is, the orthographic projection of the second opening 52 on the substrate is located within the orthographic projection of the sixth extension VDD6 on the substrate. It should be understood that in other exemplary embodiments, the second opening 52 can also be a non-closed figure, for example, the second opening 52 can be a gap located at the edge of the sixth extension VDD6. In this exemplary embodiment, the second opening 52 is provided on the sixth extension VDD6, so that the parasitic capacitance between the sixth extension VDD6 and the second gate line 1G1 can be reduced, and the parasitic capacitance between the sixth extension VDD6 and the fourth gate line 2G1 can be reduced, so that the charging speed of the second transistor gate can be further increased. In the single pixel driving circuit of this exemplary embodiment, the sum of the parasitic capacitance between the second gate line 1G1 and the power line, and the parasitic capacitance between the fourth gate line 2G1 and the power line can be reduced to 7.7fF.

[0134] like Fig.43 FIG. 1 is a structural diagram of another exemplary embodiment of the display panel disclosed in the present invention. Fig. 20 On the basis of the display panel shown in the figure, the display panel may further include an anode layer, the anode layer may include a plurality of anode portions, and the plurality of anode portions may be used to form anodes of the light-emitting units respectively. The orthographic projection of the anode portion on the base substrate covers the orthographic projection of the first active portion 7 on the base substrate. The anode portion may further shield the first active portion 7. Fig.43 As shown, the display panel may be of RGGB structure, that is, the anode layer may include a plurality of red anode portions R, a plurality of blue anode portions B, and a plurality of green anode portions G, wherein: Fig.43 Only partial structures of the anode portion R, the anode portion B, and the anode portion G are shown. Fig.43 As shown, the positive projection of the anode portion R on the substrate covers the positive projection of the first active portion 7 in the pixel driving circuit on the substrate. The positive projection of the anode portion B on the substrate can cover the positive projection of the first active portion in the pixel driving circuit on the left side of the pixel driving circuit on the substrate. The positive projection of the anode portion G on the substrate can cover the positive projection of the first active portion in the pixel driving circuit on the bottom side of the pixel driving circuit on the substrate. Fig.43 As shown, the orthographic projection of the anode portion G on the substrate can also at least partially overlap with the orthographic projection of the first connecting portion 41 on the substrate. Since the voltage of the anode portion G is stable during the light-emitting stage, the anode portion G can stabilize the voltage of the first connecting portion 41 through coupling.

[0135] like Fig.44 As shown, Fig.43 Partial cross-sectional view along dotted line A in FIG. The display panel may also include a buffer layer 82, a second insulating layer 83, a third insulating layer 84, a fourth insulating layer 85, a fifth insulating layer 86, a dielectric layer 87, a passivation layer 88, a first flat layer 89, and a second flat layer 810. Among them, the base substrate 81, the buffer layer 82, the first active layer, the second insulating layer 83, the first conductive layer, the third insulating layer 84, the second conductive layer, the fourth insulating layer 85, the second active layer, the fifth insulating layer 86, the third conductive layer, the dielectric layer 87, the fourth conductive layer, the passivation layer 88, the first flat layer 89, the fifth conductive layer, the second flat layer 810, and the anode layer are stacked in sequence. Among them, the buffer layer 82 may include at least one of a silicon oxide layer and a silicon nitride layer. The second insulating layer 83 may be a silicon oxide layer. The third insulating layer 84 may be a silicon nitride layer. The fourth insulating layer 85 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 86 may be a silicon oxide layer. The dielectric layer 87 may include a silicon oxide layer and a silicon nitride layer. The materials of the first planar layer and the second planar layer may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like. The anode layer may be formed of indium tin oxide (ITO) material. The materials of the fourth conductive layer and the fifth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or a titanium / aluminum / titanium stack. The materials of the first conductive layer, the second conductive layer and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or the like.

[0136] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0137] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0138] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a first transistor, a first electrode of the first transistor is connected to a gate of the driving transistor, and a second electrode is connected to a first initial signal line, the driving transistor is a P-type low-temperature polysilicon transistor, and the first transistor is an N-type oxide transistor, and the display panel further includes: substrate substrate; a second conductive layer, located on one side of the base substrate, the second conductive layer comprising a third gate line, an orthographic projection of the third gate line on the base substrate extending along a first direction, and a partial structure of the third gate line being used to form a first gate of the first transistor; A second active layer, located on a side of the second conductive layer away from the substrate, wherein a portion of the second active layer is used to form a channel region of the first transistor; a third conductive layer, located on a side of the second active layer away from the substrate, the third conductive layer comprising a fifth gate line, an orthographic projection of the fifth gate line on the substrate extending along the first direction, and a partial structure of the fifth gate line being used to form a second gate of the first transistor; a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising the first initial signal line, and an orthographic projection of the first initial signal line on the base substrate extending along the first direction; A first conductive layer, located between the base substrate and the second conductive layer, wherein the first conductive layer comprises a first conductive portion, and the first conductive portion is used to form a gate of the driving transistor; A first active layer, wherein the first active layer is located between the base substrate and the first conductive layer, and a portion of the first active layer is used to form a channel region of the driving transistor; The pixel driving circuit also includes a capacitor, which is connected between the gate of the driving transistor and a power line. The first conductive portion is also used to form an electrode of the capacitor. The second conductive layer also includes: a third conductive portion, which is used to form another electrode of the capacitor.

2. The display panel according to claim 1, wherein: The square resistance of the fourth conductive layer is smaller than the square resistance of the second conductive layer, and the square resistance of the fourth conductive layer is smaller than the square resistance of the third conductive layer.

3. The display panel according to claim 1, wherein: The fourth conductive layer is located on a side of the third conductive layer away from the substrate.

4. The display panel according to claim 1, wherein: The display panel also includes a light-emitting unit, and the pixel driving circuit is used to provide a driving current to the light-emitting unit. The pixel driving circuit may also include a seventh transistor, a first electrode of the seventh transistor is connected to the light-emitting unit, and a second electrode is connected to a second initial signal line. Part of the structure of the fourth conductive layer is also used to form the second initial signal line.

5. The display panel according to claim 4, wherein: The display panel includes a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit adjacent to each other in a second direction; The second initial signal line in the first pixel driving circuit is commonly used as the first initial signal line in the second pixel driving circuit.

6. The display panel according to claim 4, wherein: The display panel further includes: The first conductive layer includes a second reset signal line, and a portion of the structure of the second reset signal line is used to form a gate of the seventh transistor; A portion of the structure of the first active layer is used to form a channel region of the seventh transistor.

7. The display panel according to claim 6, wherein: The first initial signal line is connected to the second active layer through a via hole to connect to the second electrode of the first transistor; The second initial signal line is connected to the first active layer through a via hole to connect to the second electrode of the seventh transistor.

8. The display panel according to claim 1, wherein: The second active layer comprises: a first sub-active portion, the first sub-active portion being used to form a channel region of the first transistor; The orthographic projection of the third gate line on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate, and the orthographic projection of the fifth gate line on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate; The orthographic projection of the first initial signal line on the base substrate is located on a side where the orthographic projection of the third gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate; The orthographic projection of the first initial signal line on the base substrate is located on a side of the orthographic projection of the fifth gate line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

9. The display panel according to claim 1, wherein: The orthographic projection of the first initial signal line on the base substrate at least partially overlaps with the orthographic projection of the third gate line on the base substrate; The orthographic projection of the first initial signal line on the base substrate at least partially overlaps with the orthographic projection of the fifth gate line on the base substrate.

10. The display panel according to claim 7, wherein: The orthographic projection of the second initial signal line on the base substrate is located on a side of the orthographic projection of the second reset signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate; The orthographic projection of the second initial signal line on the base substrate is located on a side of the orthographic projection of the second reset signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

11. The display panel according to claim 7, wherein: The orthographic projection of the second initial signal line on the base substrate at least partially overlaps with the orthographic projection of the second reset signal line on the base substrate.

12. The display panel according to claim 1, wherein: The pixel driving circuit further includes a second transistor and a fourth transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode is connected to a first electrode of the driving transistor, the fourth transistor is a P-type low temperature polysilicon transistor, and the second transistor is an N-type oxide transistor, and the display panel further includes: The first conductive layer further includes: a first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction, a partial structure of the first gate line is used to form the gate of the fourth transistor, and the first conductive portion is used to form the gate of the driving transistor; a second conductive portion, wherein an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first gate line on the base substrate; The second conductive layer further includes a second gate line, an orthographic projection of the second gate line on the base substrate extends along the first direction, a partial structure of the second gate line is used to form a first gate of the second transistor, and an orthographic projection of the second gate line on the base substrate is located between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the first gate line on the base substrate; The fourth conductive layer further includes: a first connecting portion, wherein the first connecting portion is connected to the first conductive portion and the second conductive portion through via holes.

13. The display panel according to claim 12, wherein: The second conductive portion includes a first sub-conductive portion, the first sub-conductive portion is formed on the same layer as the second conductive layer, the orthographic projection of the first sub-conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line on the base substrate, and the first connecting portion is connected to the first sub-conductive portion through a via.

14. The display panel according to claim 13, wherein: The second active layer includes a first active portion, a portion of the first active portion being used to form a channel region of the first transistor and the second transistor; The display panel further includes a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, and the fifth conductive layer includes: A power line, wherein the orthographic projection of the power line on the substrate extends along a second direction, and the orthographic projection of the power line on the substrate covers the orthographic projection of the first active part on the substrate; and an overlapping area between the orthographic projection of the power line on the substrate and the orthographic projection of the first connecting part on the substrate is less than 70% of the orthographic projection area of ​​the first connecting part on the substrate.

15. The display panel according to claim 14, wherein: The orthographic projection of the third conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and a first opening is provided on the third conductive portion, wherein the first connecting portion is connected to the first conductive portion through a first via hole, and the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the first opening on the base substrate; The power cord comprises: A first extension portion, an orthographic projection on the base substrate extending along the second direction, and an orthographic projection of the first extension portion on the base substrate at least partially overlaps with an orthographic projection of the first opening on the base substrate; A second extending portion, wherein an orthographic projection of at least a portion of the structure of the second extending portion on the base substrate extends along the second direction, and the orthographic projection of the second extending portion on the base substrate covers the orthographic projection of the first active portion on the base substrate; A third extension portion is connected between the first extension portion and the second extension portion, wherein the orthographic projection of the third extension portion on the base substrate extends along the first direction, and the orthographic projection of the third extension portion on the base substrate at least partially overlaps with the orthographic projection of the first opening on the base substrate.

16. The display panel according to claim 15, wherein: The second extending portion includes a first sub-extending portion, an orthographic projection of the first sub-extending portion on the base substrate extends along the first direction, and an orthographic projection of the first sub-extending portion on the base substrate at least partially overlaps with an orthographic projection of the first initial signal line on the base substrate; An orthographic projection of the first sub-extension portion on the base substrate and an orthographic projection of the third gate line on the base substrate at least partially do not overlap.

17. The display panel according to claim 12, wherein: The second conductive portion includes a second active portion, which is formed on the same layer as the second active layer, an orthographic projection of the second active portion on the base substrate at least partially overlaps with an orthographic projection of the first gate line on the base substrate, and the second active portion is electrically connected to the first connecting portion.

18. The display panel according to claim 17, wherein: The orthographic projection of the third gate line on the substrate is located on a side where the orthographic projection of the first gate line on the substrate is away from the orthographic projection of the second gate line on the substrate; An overlapping area of ​​an orthographic projection of the second active portion on the base substrate and an orthographic projection of the second gate line on the base substrate is less than 50% of an orthographic projection area of ​​the second active portion on the base substrate; The second active layer includes a first active portion, the first active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected between the first sub-active portion and the second sub-active portion, and the second active portion is connected to the third sub-active portion; Among them, the first sub-active portion is used to form a channel region of the first transistor, the second sub-active portion is used to form a channel region of the second transistor, the first connecting portion is connected to the third sub-active portion through a via, and the orthographic projection of the third sub-active portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line on the base substrate.

19. The display panel according to claim 18, wherein: The third conductive portion is connected to the power line; The second active portion includes: a fourth sub-active portion connected to the third sub-active portion, the orthographic projection of the fourth sub-active portion on the base substrate extending along the first direction, and the orthographic projection of the fourth sub-active portion on the base substrate at least partially overlapping with the orthographic projection of the first gate line on the base substrate; a fifth sub-active portion connected to the fourth sub-active portion, wherein an orthographic projection of the fifth sub-active portion on the base substrate extends along a second direction, and an orthographic projection of the fifth sub-active portion on the base substrate intersects an orthographic projection of the second gate line on the base substrate; The sixth sub-active portion is connected to the fifth sub-active portion, and an orthographic projection of the sixth sub-active portion on the base substrate at least partially overlaps with an orthographic projection of the third conductive portion on the base substrate.

20. The display panel according to claim 19, wherein: A size of an orthographic projection of the fifth sub-active portion on the base substrate in the first direction is smaller than a size of an orthographic projection of the sixth sub-active portion on the base substrate in the first direction.

21. The display panel according to claim 19, wherein: The overlap area of ​​the orthographic projection of the fourth sub-active portion on the base substrate and the orthographic projection of the first gate line on the base substrate is S1; The overlapping area of ​​the orthographic projection of the fifth sub-active portion on the base substrate and the orthographic projection of the second gate line on the base substrate is S2; Among them, S1 is greater than S2.

22. The display panel according to claim 20, wherein: The first connecting portion comprises: a fourth conductive portion, connected to the third sub-active portion through a via hole, and an orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first gate line on the base substrate; a fifth conductive portion, connected to the fourth conductive portion, wherein an orthographic projection of the fifth conductive portion on the base substrate overlaps an orthographic projection of the second gate line on the base substrate; a sixth conductive portion, connected to the fifth conductive portion, wherein an orthographic projection of the sixth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the third conductive portion on the base substrate; The size of the orthographic projection of the fifth conductive portion on the base substrate in the first direction is smaller than the size of the orthographic projection of the sixth conductive portion on the base substrate in the first direction.

23. The display panel according to claim 19, wherein: The display panel further includes: a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, and the fifth conductive layer includes: A power line, wherein an orthographic projection of the power line on the base substrate extends along a second direction, and the orthographic projection of the power line on the base substrate covers an orthographic projection of the second active portion on the base substrate.

24. The display panel according to claim 23, wherein: The power line comprises a sixth extension portion and a seventh extension portion, wherein a size of an orthographic projection of the sixth extension portion on the base substrate in the first direction is greater than a size of an orthographic projection of the seventh extension portion on the base substrate in the first direction; The orthographic projection of the sixth extension portion on the base substrate covers the orthographic projection of the second active portion on the base substrate; A second opening is formed on the sixth extending portion, and an orthographic projection of the second opening on the base substrate at least partially overlaps with an orthographic projection of the second gate line on the base substrate.

25. The display panel according to claim 14 or 23, wherein: The display panel further includes: The anode layer is located on a side of the fifth conductive layer away from the base substrate, and the anode layer includes a plurality of anode parts, and the orthographic projections of the anode parts on the base substrate cover the orthographic projections of the first active parts on the base substrate.

26. A display device, wherein: A display panel comprising any one of claims 1-25.

Images