Data reading and writing method and device, computer device and readable storage medium

Abstract

Embodiments of the present application disclose a data read-write method and device, computer equipment and a readable storage medium, which are used for reading and writing data in DRAM through SRAM. The method comprises the following steps: when writing data to the DRAM, writing first target data into a first cache area of the SRAM and generating write data control information; writing the first target data into the DRAM according to the write data control information; when reading data from the DRAM, generating read data control information; reading second target data from the DRAM according to the read data control information and writing the second target data into a second cache area of the SRAM; and reading the second target data from the second cache area. The present application uses SRAM as an intermediate medium, so that the CPU can read and write a large amount of data in the DRAM, and effectively increases the read-write efficiency of the CPU for reading and writing data in the DRAM.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a data reading and writing method, apparatus, computer device, and readable storage medium. Background Technology

[0002] With the rapid development of cloud computing, artificial intelligence, and the Internet of Things, terminal products and services are demanding more and more storage capacity from solid-state drives (SSDs) and faster data read and write speeds. However, without dynamic random access memory (DRAM), SSDs struggle to maintain full disk read and write speeds without slowing down.

[0003] Under the existing read / write scheme, when the CPU reads data from DRAM, it often occupies the CPU's working resources for a long time, resulting in low CPU efficiency, which in turn affects the efficiency of data read / write.

[0004] Therefore, there is an urgent need for a data read and write solution with higher read and write efficiency. Summary of the Invention

[0005] To address the aforementioned technical problems, embodiments of this application provide a data reading and writing method, apparatus, computer device, and readable storage medium, the specific solutions of which are as follows:

[0006] In a first aspect, embodiments of this application provide a data read / write method for reading and writing data in DRAM via SRAM, the method comprising:

[0007] When writing data to the DRAM, the first target data is written to the first cache area of ​​the SRAM, and write data control information is generated. The write data control information includes the preset storage address of the first target data in the DRAM.

[0008] The first target data is written into the DRAM according to the write data control information;

[0009] When reading data from the DRAM, read data control information is generated, and the read data control information includes the preset storage address of the second target data in the DRAM;

[0010] The second target data is read from the DRAM according to the read data control information, and the second target data is written into the second cache area of ​​the SRAM;

[0011] Read the second target data from the second cache area.

[0012] According to a specific embodiment of this application, when writing data to the DRAM, if the preset storage addresses of the first target data in the DRAM are consecutive, the method further includes:

[0013] The first target data is continuously written into the first cache area until the first cache area is full.

[0014] When the first cache area is full, determine whether the first target data has been completely written into the first cache area;

[0015] If the first target data has been completely written into the first cache area, proceed to the step of writing the first target data into the DRAM according to the write data control information;

[0016] If the first target data is not completely written to the first cache area, when the data in the first cache area is cleared, the remaining first target data will be continuously written to the first cache area.

[0017] According to a specific embodiment of the present application, the method further includes:

[0018] Read the hardware-read SRAM data pointer from the preset pointer storage area of ​​SRAM, and read the firmware-written SRAM data pointer from the preset register;

[0019] Determine whether the firmware has written SRAM data pointer is equal to the hardware has read SRAM data pointer;

[0020] If the firmware has written an SRAM data pointer equal to the hardware has read an SRAM data pointer, it is determined that the first cache area has been cleared.

[0021] According to a specific embodiment of this application, when writing data to the DRAM, if the preset storage address of the first target data in the DRAM is not contiguous, the method further includes:

[0022] The first target data and its corresponding DRAM address are divided into multiple frames of write data instructions, which are written into the third cache area of ​​the SRAM respectively, and write data configuration information is generated.

[0023] According to the write data configuration information, the first target data in the third cache area is sequentially written into its corresponding DRAM address.

[0024] According to a specific implementation of this application, the step of sequentially writing the first target data in the third cache region into its corresponding DRAM address according to the write data configuration information includes:

[0025] After writing the first target data included in a frame of write data instructions to its corresponding DRAM address according to the write data configuration information, the next frame of write data instructions is read from the third cache area until the amount of the first target data written to the DRAM is equal to the preset write data amount of the write data configuration information.

[0026] According to a specific embodiment of this application, when reading data from the DRAM, if the storage addresses of the second target data in the DRAM are consecutive, the method further includes:

[0027] The second target data is continuously read from the DRAM according to the read data control information until the amount of the second target data is equal to the preset amount of data to be read in the read data control information.

[0028] The second target data is written into the second cache area of ​​the SRAM until the second cache area is full.

[0029] When the second cache area is full, determine whether the second target data has been completely written into the second cache area;

[0030] If the second target data has been completely written to the second cache area, proceed to the step of reading the second target data from the second cache area;

[0031] If the second target data is not completely written to the second cache area, when the data in the second cache area is cleared, the remaining second target data will be continuously written to the second cache area.

[0032] According to a specific embodiment of this application, when reading data from the DRAM, if the storage address of the second target data in the DRAM is not contiguous, the method further includes:

[0033] Generate read data configuration information;

[0034] Write the read data configuration information into the third cache area of ​​the SRAM;

[0035] The read data configuration information is sequentially retrieved from the third cache area, and the second target data is written into the second cache area of ​​the SRAM according to the read data configuration information;

[0036] Read the second target data from the second cache area.

[0037] Secondly, embodiments of this application provide a data read / write device for reading and writing data in DRAM via SRAM, the data read / write device comprising:

[0038] The write data module is used to write a first target data into the first cache area of ​​the SRAM when writing data to the DRAM, and generate write data control information, the write data control information including a preset storage address of the first target data in the DRAM; and write the first target data into the DRAM according to the write data control information.

[0039] A read data module is used to generate read data control information, the read data control information including a preset storage address of the second target data in the DRAM; read the second target data from the DRAM according to the read data control information, and write the second target data into the second cache area of ​​the SRAM; and read the second target data from the second cache area.

[0040] Thirdly, embodiments of this application provide a computer device, the computer device including a processor and a memory, the memory storing a computer program, the computer program executing the data read / write method described in the first aspect and any embodiment of the first aspect when running on the processor.

[0041] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when run on a processor, executes the data read / write method described in the first aspect and any embodiment of the first aspect.

[0042] This application provides a data read / write method, apparatus, computer device, and readable storage medium for reading and writing data in DRAM via SRAM. The method includes: when writing data to the DRAM, writing first target data into a first cache area of ​​the SRAM and generating write data control information, the write data control information including a preset storage address of the first target data in the DRAM; writing the first target data into the DRAM according to the write data control information; when reading data from the DRAM, generating read data control information, the read data control information including a preset storage address of second target data in the DRAM; reading the second target data from the DRAM according to the read data control information and writing the second target data into a second cache area of ​​the SRAM; and reading the second target data from the second cache area. This invention uses SRAM as an intermediate medium to read and write data in DRAM, effectively increasing the CPU's read / write efficiency in DRAM. Attached Figure Description

[0043] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0044] Figure 1 This illustration shows a flowchart of a data read / write method provided in an embodiment of this application.

[0045] Figure 2 This illustration shows one of the application scenarios of a data read / write method provided in an embodiment of this application;

[0046] Figure 3 This illustration shows a second application scenario diagram of a data read / write method provided in an embodiment of this application;

[0047] Figure 4 This illustration shows a third application scenario diagram of a data read / write method provided in an embodiment of this application;

[0048] Figure 5 This illustration shows the fourth application scenario diagram of a data read / write method provided in this application embodiment;

[0049] Figure 6 This illustration shows the fifth application scenario diagram of a data read / write method provided in this application embodiment;

[0050] Figure 7 This illustration shows a mode switching diagram of a DRAM control component in a data read / write method according to an embodiment of this application;

[0051] Figure 8 This illustration shows a schematic diagram of a data read / write device module provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0053] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0054] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0055] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0057] To meet the requirement of not slowing down the full read and write speed of a solid state disk (SSD), an SSD controller that supports DRAM interface is needed, which adds DRAM chips to the SSD platters.

[0058] Because DRAM stores the Flash Translation Layer (FTL) file of the solid-state drive (SSD). The FTL file is a mapping table file from the logical layer to the physical layer of the SSD. Before reading and writing data in the SSD, the CPU reads the FTL file from DRAM and obtains the physical mapping table of the flash memory (NAND Flash) from the FTL file. Through the address mapping relationship in the physical mapping table, the CPU reads and writes data into the NAND Flash.

[0059] When reading and writing data on an SSD, the central processing unit (CPU) in the SSD controller frequently reads and writes the FTL file in DRAM. The CPU's efficiency in reading and writing data to DRAM directly affects the efficiency in reading and writing data to the SSD.

[0060] refer to Figure 1 This is a flowchart illustrating a data read / write method provided in an embodiment of this application. The data read / write method provided in this embodiment is used to read and write data in DRAM via SRAM, such as... Figure 1 As shown, the method includes:

[0061] Step S101: When writing data to the DRAM, the first target data is written to the first cache area of ​​the SRAM, and write data control information is generated. The write data control information includes the preset storage address of the first target data in the DRAM.

[0062] Step S102: Write the first target data into the DRAM according to the write data control information;

[0063] Step S103: When reading data from the DRAM, read data control information is generated, and the read data control information includes the preset storage address of the second target data in the DRAM;

[0064] Step S104: Read the second target data from the DRAM according to the read data control information, and write the second target data into the second cache area of ​​the SRAM;

[0065] Step S105: Read the second target data from the second cache area.

[0066] Specifically, the data read / write method proposed in this embodiment can be applied to scenarios where the central processing unit reads and writes data to the DRAM in the solid-state drive, or to scenarios where other devices including the SRAM interface read and write data to the DRAM in the solid-state drive. This embodiment does not make any specific limitations on this.

[0067] This embodiment uses Static Random-Access Memory (SRAM) as a transmission bridge. The CPU writes data and CMD instruction information into the SRAM. The DRAM control component can write data into the DRAM according to the corresponding write data instruction, and the DRAM control component can also write data into the SRAM according to the corresponding read data instruction, so that the CPU can read the data in the DRAM.

[0068] In one embodiment, the application scenario of the data read / write method in this embodiment can be as follows: Figure 2 As shown, in practical application scenarios, the SRAM also includes a write data SRAM Buffer component, a write data control component, a register component, a PtrSRAM component, an instruction SRAM Buffer component, an instruction control component, a read data SRAM Buffer component, and a read data control component.

[0069] The DRAM includes a DRAM control component and dynamic random access memory (DRAM).

[0070] Specifically, steps S101-S102 are steps for the CPU to write data to the DRAM. When writing data to the DRAM, the first target data is first written to the first cache area in the DRAM.

[0071] like Figure 2 As shown, the write data SRAM Buffer component can be the first cache area. When the CPU needs to write data to the DRAM, it can use the write data SRAM Buffer as an intermediate medium to write the first target data to be written into the write data SRAM Buffer.

[0072] The write data SRAM Buffer component and the write data control component are communicatively connected. The write data control component acts as a bridge between the write data SRAM Buffer component and the DRAM control component. When the DRAM control component needs to write data to the DRAM, the DRAM requests data from the write data control component.

[0073] The write data control component can also serve as the first cache area, caching a certain amount of the first target data. When the cache of the write data control component is not full, but the cache of the SRAM Buffer component still contains the first target data, the write data control component will fill its cache. Conversely, when the cache of the write data control component contains the first target data, it will respond to requests from the DRAM control component and provide the first target data to the DRAM control component.

[0074] After the CPU stores the first target data into the first cache area, it generates write data control information corresponding to the first target data. The write data control information includes the preset storage location of the first target data in DRAM, the size of the first target data, and a pointer to the data already written to SRAM by the firmware.

[0075] After parsing the write data control information sent by the CPU, the register component distributes the parsed write data control information to the write data control component and the DRAM control component to transfer and write the first target data into the DRAM.

[0076] The instruction SRAM Buffer component is used to cache read and write instructions issued by the CPU. The CMD format of the write instruction is as follows:

[0077] CMD_ID CMD_OP DRAM_Address Write_Data

[0078] It should be noted that the instructions stored in the instruction SRAM Buffer component can be in CMD format or CFG format, wherein the instructions in CMD format are in command mode and the instructions in CFG format are in configuration mode.

[0079] Command mode instructions can process either first or second target data at contiguous addresses, or they can process first or second target data at non-contiguous addresses. Configuration mode instructions can only process first or second target data at contiguous addresses.

[0080] Specifically, in command mode, users can switch between read and write instructions at any time. In configuration mode, however, read instructions can only be processed after the CPU-configured write instructions have been completed, and vice versa.

[0081] The instruction control component is used to cache some instructions to ensure that the data reading and writing steps of the DRAM control component remain continuous during operation, and that the execution of instructions is not interrupted due to configuration instructions or other reasons.

[0082] The register component is used to parse configuration information, interrupt information, and status query information issued by the CPU, such as write data control information, read data control information, write data configuration information, and read data configuration information.

[0083] The Ptr SRAM component is used to store the SRAM pointers of each hardware that performs SRAM caching and control functions, while the register component stores all the firmware issued by the CPU. By judging the number of SRAM pointers in the firmware and the number of SRAM pointers executed by the hardware, it is possible to accurately determine whether the data in each cache has been completely processed.

[0084] The CPU communicates with the Ptr SRAM component, enabling it to read relevant parameters from each cache faster and further improve the efficiency of reading and writing DRAM data.

[0085] Specifically, steps S103-S105 are steps for the CPU to read data from the DRAM. When reading data from the DRAM, configuration information needs to be sent to the register component first to notify the DRAM control component to read the second target data from the DRAM and move the second target data to the second cache area.

[0086] The read data control component is used to store the second target data into the read data SRAM Buffer component according to the write request sent by the DRAM control component. The read data SRAM Buffer component can be the second cache area, and in some cases, the read data control component can also serve as the second cache area.

[0087] When the SRAM Buffer component has no cache space, the read data control component sends a corresponding stop signal to the DRAM control component to stop the DRAM control component from reading data from the DRAM until the CPU reads the second target data from the read data SRAM Buffer component. At this time, the read data SRAM Buffer component releases the cache space, and the read data component controls the DRAM control component to continue reading the second target data until all the second target data has been read.

[0088] Specifically, the data read / write method proposed in this embodiment includes various data read / write scenarios. For example, the addresses of the data to be written in DRAM are continuous, the addresses of the data to be written in DRAM are non-contiguous, the addresses of the data to be read in DRAM are continuous, and the addresses of the data to be read in DRAM are non-contiguous.

[0089] In this embodiment, the SRAM resources called upon by the CPU differ depending on the data read / write scenario. In practice, the CPU only calls upon SRAM resources relevant to the data read / write scenario to reduce SRAM resource consumption. After completing the current data read / write operation, the CPU reclaims the called SRAM resources to improve SRAM resource utilization efficiency.

[0090] like Figures 3 to 6 As shown, the implementation box represents the resources that the CPU calls in the current application scenario, and the dashed box represents the resources that the CPU does not call in the current application scenario.

[0091] refer to Figure 3 According to a specific embodiment of this application, when writing data to the DRAM, if the preset storage addresses of the first target data in the DRAM are consecutive, the method further includes:

[0092] The first target data is continuously written into the first cache area until the first cache area is full.

[0093] When the first cache area is full, determine whether the first target data has been completely written into the first cache area;

[0094] If the first target data has been completely written into the first cache area, proceed to the step of writing the first target data into the DRAM according to the write data control information;

[0095] If the first target data is not completely written to the first cache area, when the data in the first cache area is cleared, the remaining first target data will be continuously written to the first cache area.

[0096] In a specific embodiment, such as Figure 3 As shown, when the CPU writes the first target data with a continuous address to the DRAM, the CPU calls the write data SRAM Buffer component as the data buffer for the CPU to write the data. After configuring the corresponding write data control information, the write data control information is sent to the register component so that the parameters of the write data control component and the DRAM control component are synchronized through the register component.

[0097] In practical applications, for the first target data whose data volume is less than a certain threshold, the write data control information sent by the CPU to the register component can be in CMD format or CFG format. For the first target data whose data volume is greater than a certain threshold, the write data control information sent by the CPU to the register component is in CFG format. The threshold can be adaptively set according to the actual application scenario, and is not specifically limited here.

[0098] In practical applications, the write data SRAM Buffer component has a storage limit. When the amount of the first target data exceeds the storage limit of the write data SRAM Buffer component, the transfer of the first target data to the write data SRAM Buffer component can be stopped when the SRAM Buffer component's cache is full.

[0099] After the write data control component and the DRAM control component empty the first target data in the write data SRAM Buffer component, they continue to write the remaining first target data. If the write data SRAM Buffer component is filled a second time and all the first target data has not been processed, the above steps are repeated until all the first target data with consecutive storage addresses is written into the DRAM.

[0100] According to a specific embodiment of the present application, the method further includes:

[0101] Read the hardware-read SRAM data pointer from the preset pointer storage area of ​​SRAM, and read the firmware-written SRAM data pointer from the preset register;

[0102] Determine whether the firmware has written SRAM data pointer is equal to the hardware has read SRAM data pointer;

[0103] If the firmware has written an SRAM data pointer equal to the hardware has read an SRAM data pointer, it is determined that the first cache area has been cleared.

[0104] In a specific embodiment, the preset pointer storage area is: Figure 3 The Ptr SRAM component in the memory has a default register as the register component.

[0105] This embodiment can determine whether cached data has been processed by identifying SRAM data pointers in the hardware and firmware. It can also determine whether a write operation is complete by identifying the amount of data already transferred and the preset data amount in the write data control information.

[0106] refer to Figure 4 According to a specific embodiment of this application, when writing data to the DRAM, if the preset storage address of the first target data in the DRAM is not contiguous, the method further includes:

[0107] The first target data and its corresponding DRAM address are divided into multiple frames of write data instructions, which are written into the third cache area of ​​the SRAM respectively, and write data configuration information is generated.

[0108] According to the write data configuration information, the first target data in the third cache area is sequentially written into its corresponding DRAM address.

[0109] In a specific embodiment, since the storage addresses of each first target data in DRAM are not contiguous, it is necessary to first divide the corresponding first target data and its corresponding storage address into multiple frames of write data instructions to obtain multiple write data configuration information.

[0110] like Figure 4 As shown, at this time, the data configuration information sent by the CPU to the register component is instruction information in CMD format.

[0111] The instruction SRAM Buffer component can be the third cache area. In some processing cases, the instruction control component can also be the third cache area.

[0112] The CPU stores multiple frames of write data instructions in the instruction SRAM Buffer component, and the instruction control component reads the write data instructions in the SRAM Buffer component according to the data configuration information.

[0113] According to a specific implementation of this application, the step of sequentially writing the first target data in the third cache region into its corresponding DRAM address according to the write data configuration information includes:

[0114] After writing the first target data included in a frame of write data instructions to its corresponding DRAM address according to the write data configuration information, the next frame of write data instructions is read from the third cache area until the amount of the first target data written to the DRAM is equal to the preset write data amount of the write data configuration information.

[0115] In a specific embodiment, after reading a frame of write data instructions, the DRAM control component checks the cache of the instruction control component. If the cache of the instruction control component still contains remaining write data instructions, the DRAM will immediately read the next frame of write data instructions until all write data instructions have been processed.

[0116] Specifically, when the instruction control component obtains write data instructions from the instruction SRAM Buffer component, it can determine whether the pointer of the instruction SRAM Buffer component already read by the hardware is less than the instruction already written to the instruction SRAM Buffer component by the firmware. If it is less, it means that the instruction control component still needs to obtain write data instructions from the instruction SRAM Buffer component. If it is equal, it means that the write data instructions in the instruction SRAM Buffer component have been completely read.

[0117] refer to Figure 5 According to a specific embodiment of this application, when reading data from the DRAM, if the storage addresses of the second target data in the DRAM are consecutive, the method further includes:

[0118] The second target data is continuously read from the DRAM according to the read data control information until the amount of the second target data is equal to the preset amount of data to be read in the read data control information.

[0119] The second target data is written into the second cache area of ​​the SRAM until the second cache area is full.

[0120] When the second cache area is full, determine whether the second target data has been completely written into the second cache area;

[0121] If the second target data has been completely written to the second cache area, proceed to the step of reading the second target data from the second cache area;

[0122] If the second target data is not completely written to the second cache area, when the data in the second cache area is cleared, the remaining second target data will be continuously written to the second cache area.

[0123] In a specific embodiment, such as Figure 5 As shown, the read data SRAM Buffer component can serve as the second cache area, and in some cases, the read data control component can also serve as the second cache area.

[0124] Specifically, the register component receives the read data control information sent by the CPU and provides the corresponding parameter information to the DRAM control component so that the DRAM control component can obtain the second target data at consecutive addresses.

[0125] In practical applications, if the read data SRAM Buffer component includes data that the CPU has not read, the register component will automatically send an interrupt instruction to the CPU to remind the CPU that it can send the second target data to the read data SRAM Buffer component.

[0126] Specifically, when the cache in the read data control component is full, a stop command is sent to the DRAM control component to suspend the DRAM control component from continuing to transfer the second target data to the read data control component until the cache of the read data control component becomes available.

[0127] The CPU can determine how much secondary target data is still to be read by querying the write data SRAM Buffer pointer in the Ptr SRAM component.

[0128] According to a specific embodiment of this application, when reading data from the DRAM, if the storage address of the second target data in the DRAM is not contiguous, the method further includes:

[0129] Generate read data configuration information;

[0130] Write the read data configuration information into the third cache area of ​​the SRAM;

[0131] The read data configuration information is sequentially retrieved from the third cache area, and the second target data is written into the second cache area of ​​the SRAM according to the read data configuration information;

[0132] Read the second target data from the second cache area.

[0133] In a specific embodiment, such as Figure 6As shown, the instruction SRAM Buffer component can be the third cache region, and in some cases, the instruction control component can also be the third cache region.

[0134] The CPU writes the read data configuration information corresponding to the second target data at non-contiguous storage addresses into the instruction SRAM Buffer component and the register component, respectively, so that the DRAM control component can obtain the second target data located at different storage addresses from the DRAM.

[0135] After the DRAM control component reads the read data configuration information from the instruction control component once, if the instruction control component's cache still contains the remaining read data configuration information and the pointer of the hardware write instruction SRAM Buffer component is less than the pointer of the firmware write instruction SRAM Buffer component, it continues to read data from the instruction control component until the pointer of the hardware write instruction SRAM Buffer component is equal to the pointer of the firmware write instruction SRAM Buffer component, at which point the operation ends.

[0136] The CPU retrieves the second target data from the instruction SRAM Buffer until the amount of the second target data retrieved is equal to the preset amount of data in the read data configuration information.

[0137] In practical applications, when processing the writing step of the first target data at a non-contiguous storage address, the reading step of the second target data at a non-contiguous storage address can also be processed simultaneously. The execution process can be referred to the specific implementation process in the above method embodiments, which will not be elaborated here.

[0138] like Figure 7 As shown, the DRAM control component in this embodiment has seven control states: Idle state (IDLE), Command mode read data state (CMD_R), Command mode write data state (CMD_W), Configuration mode read data state (CFG_R), Configuration mode write data state (CFG_W), Write data complete state (W_F), and Read data complete state (R_F).

[0139] In practical applications, the IDLE state is the state that the CPU enters when it initializes and configures the DRAM controller to enable DRAM memory.

[0140] The command mode read data state CMD_R and command mode write data state CMD_W are the read and write data instruction modes that the CPU controls the DRAM control component to enter after receiving the CMD control signal.

[0141] Specifically, upon receiving the `cmd_read` command, the DRAM control component switches from the idle state (IDLE) to the command mode (CMD_R) for reading data. Upon receiving the `cmd_write` command, the DRAM control component switches from the idle state (IDLE) to the command mode (CMD_W) for writing data. The `cmd_read` command is controlled by `CMD_OP` in the SRAM Buffer component, and the `cmd_write` command is controlled by `CMD_OP` in the SRAM Buffer component.

[0142] The DRAM control unit can also switch between the command mode read data state CMD_R and the command mode write data state CMD_W according to the cmd_write and cmd_read instructions.

[0143] If the DRAM control component finishes its operation in the command mode read data state (CMD_R) and receives the cmdr_done instruction, it switches to the read data complete state (R_F). If the DRAM control component finishes its operation in the command mode write data state (CMD_W) and receives the cmdw_done instruction, it switches to the write data complete state (W_F).

[0144] Upon receiving the cfg_read instruction, the DRAM control component switches to the configuration mode read data state CFG_R. Upon receiving the cfg_write instruction, the DRAM control component switches to the configuration mode write data state CFG_W.

[0145] In configuration mode, the DRAM control component must complete the read / write operations of the data size set in the configuration information before entering the corresponding completion state. Furthermore, configuration modes cannot be switched between each other.

[0146] The data read / write method provided in this embodiment can support CPU read / write operations on DRAM data in multiple scenarios, including scenarios involving large amounts of DRAM data with contiguous memory addresses, scenarios involving large amounts of DRAM data with non-contiguous memory addresses, and scenarios combining reading and writing of DRAM data with non-contiguous memory addresses. By converting CPU read / write operations on DRAM data into CPU read / write operations on SRAM data, the operation is simpler and faster, and efficiency is significantly improved.

[0147] refer to Figure 8 This is a schematic diagram of a data read / write device 800 provided in an embodiment of this application. The data read / write device 800 provided in this embodiment is used to read and write data in DRAM via SRAM, such as... Figure 8 As shown, the device 800 includes:

[0148] The write data module 801 is used to write first target data into the first cache area of ​​the SRAM when writing data to the DRAM, and generate write data control information, the write data control information including the preset storage address of the first target data in the DRAM; and write the first target data into the DRAM according to the write data control information.

[0149] The read data module 802 is used to generate read data control information, the read data control information including a preset storage address of the second target data in the DRAM; read the second target data from the DRAM according to the read data control information, and write the second target data into the second cache area of ​​the SRAM; and read the second target data from the second cache area.

[0150] In addition, this application embodiment also provides a computer device, which includes a processor and a memory. The memory stores a computer program, and the computer program executes the data read and write method in the foregoing method embodiment when it is run on the processor.

[0151] This application also provides a computer-readable storage medium storing a computer program, which executes the data read / write method described in the foregoing method embodiments when run on a processor.

[0152] The specific implementation process of the data reading and writing device, computer equipment and computer-readable storage medium mentioned in the above embodiments can be found in the specific implementation process of the above method embodiments, and will not be repeated here.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0154] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0155] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A data read / write method, characterized by, A method for reading and writing data in DRAM through SRAM, the method comprising: when writing data to the DRAM, writing first target data into a first cache area of the SRAM and generating write data control information, the write data control information comprising preset storage addresses of the first target data in the DRAM; writing the first target data into the DRAM according to the write data control information; when reading data from the DRAM, generating read data control information, the read data control information comprising preset storage addresses of second target data in the DRAM; reading the second target data from the DRAM according to the read data control information and writing the second target data into a second cache area of the SRAM; reading the second target data from the second cache area; when writing data to the DRAM, if preset storage addresses of the first target data in the DRAM are discontinuous, the method further comprises: dividing the first target data and corresponding DRAM addresses of the first target data into multiple frames of write data instructions and writing the multiple frames of write data instructions into a third cache area of the SRAM respectively, and generating write data configuration information; and writing the first target data in the third cache area into corresponding DRAM addresses according to the write data configuration information; the first cache area, the second cache area and the third cache area are functionally independent cache areas.

2. The data read / write method of claim 1, wherein, when writing data to the DRAM, if preset storage addresses of the first target data in the DRAM are continuous, the method further comprises: continuously writing the first target data into the first cache area until the first cache area is full; when the first cache area is full, determining whether the first target data has been completely written into the first cache area; if the first target data has been completely written into the first cache area, jumping to the step of writing the first target data into the DRAM according to the write data control information; if the first target data has not been completely written into the first cache area, continuously writing the remaining first target data into the first cache area when data in the first cache area is emptied.

3. The data read / write method of claim 2, wherein, the method further comprises: reading a hardware-read SRAM data pointer from a preset pointer storage area of the SRAM and reading a firmware-written SRAM data pointer from a preset register; determining whether the firmware-written SRAM data pointer is equal to the hardware-read SRAM data pointer; if the firmware-written SRAM data pointer is equal to the hardware-read SRAM data pointer, determining that the first cache area is emptied.

4. The data read / write method of claim 1, wherein, the step of writing the first target data in the third cache area into corresponding DRAM addresses according to the write data configuration information comprises: After the first target data included in a frame of write data instruction is written into the corresponding DRAM address according to the write data configuration information, the next frame of write data instruction is read from the third cache area until the data amount of the first target data written into the DRAM equals the preset write data amount of the write data configuration information.

5. The data read / write method of claim 1, wherein, When the data is read from the DRAM, if the storage addresses of the second target data in the DRAM are continuous, the method further comprises: According to the read data control information, the second target data is continuously read from the DRAM until the data amount of the second target data equals the preset read data amount in the read data control information; The second target data is written into the second cache area of the SRAM until the second cache area is full; When the second cache area is full, it is judged whether the second target data has been completely written into the second cache area; If the second target data has been completely written into the second cache area, the step of reading the second target data from the second cache area is skipped; If the second target data has not been completely written into the second cache area, when the data in the second cache area is emptied, the remaining second target data is continuously written into the second cache area.

6. The data read / write method of claim 1, wherein, When the data is read from the DRAM, if the storage addresses of the second target data in the DRAM are non-continuous, the method further comprises: Generating read data configuration information; Writing the read data configuration information into the third cache area of the SRAM; Calling the read data configuration information from the third cache area in sequence, and writing the second target data into the second cache area of the SRAM according to the read data configuration information; Reading the second target data from the second cache area.

7. A data read / write device, characterized by The data reading and writing device for reading and writing data in the DRAM through the SRAM comprises: A write data module for writing the first target data into the first cache area of the SRAM when data is written into the DRAM, and generating write data control information, the write data control information including the preset storage addresses of the first target data in the DRAM; and writing the first target data into the DRAM according to the write data control information; A read data module for generating read data control information, the read data control information including the preset storage addresses of the second target data in the DRAM; reading the second target data from the DRAM according to the read data control information, and writing the second target data into the second cache area of the SRAM; and reading the second target data from the second cache area. The write data module is further configured to, when writing data to the DRAM, if the preset storage addresses of the first target data in the DRAM are discontinuous, divide the first target data and the corresponding DRAM addresses thereof into multiple frames of write data instructions, write the first target data into a third cache area of the SRAM respectively, and generate write data configuration information; and write the first target data in the third cache area into the corresponding DRAM addresses thereof in sequence according to the write data configuration information. The first cache area, the second cache area, and the third cache area are functionally independent cache areas.

8. A computer device, comprising: The computer device comprises a processor and a memory, and the memory stores a computer program, which, when executed on the processor, performs the data read-write method of any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, which, when executed on the processor, performs the data read-write method of any one of claims 1 to 6.

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