Semiconductor memory device

Abstract

The semiconductor storage device of the present application includes: a substrate; a plurality of gate electrodes; a semiconductor layer facing the gate electrodes; a charge accumulation layer provided between the gate electrodes and the semiconductor layer; a conductive layer connected to one end portion of the semiconductor layer; and a control circuit electrically connected to the gate electrodes and the conductive layer. The plurality of gate electrodes includes: a first gate electrode; a second gate electrode farther from the conductive layer than the first gate electrode; and a dummy gate electrode provided between the first gate electrode and the second gate electrode. The control circuit is configured to be capable of performing an erase operation. The erase operation includes: a first erase voltage supply operation for the conductive layer; a first programming operation for the dummy gate electrode, performed after the first erase voltage supply operation; and a second erase voltage supply operation performed after the first programming operation, in which a second erase voltage equal to or greater than the first erase voltage is supplied to the conductive layer.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application is based on and claims priority pursuant to the prior Japanese Patent Application No. 2021-133715, filed on August 18, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present embodiment relates to a semiconductor storage device. BACKGROUND

[0004] A semiconductor storage device is known that includes a substrate, a plurality of gate electrodes arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and facing the plurality of gate electrodes. SUMMARY

[0005] An embodiment of the present application provides a semiconductor storage device capable of achieving appropriate erasing operation.

[0006] The semiconductor storage device of an embodiment includes a substrate, a plurality of gate electrodes arranged in a first direction intersecting a surface of the substrate, a semiconductor layer extending in the first direction and facing the plurality of gate electrodes, a charge accumulation layer provided between the plurality of gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer in the first direction, and a control circuit electrically connected to the plurality of gate electrodes and the conductive layer. The plurality of gate electrodes includes a plurality of first gate electrodes, a plurality of second gate electrodes farther from the conductive layer than the plurality of first gate electrodes, and a dummy gate electrode provided between the plurality of first gate electrodes and the plurality of second gate electrodes. The control circuit is configured to be capable of performing erasing operation. The erasing operation includes at least one first erasing voltage supply operation of supplying a first erasing voltage to the conductive layer, a first programming operation of supplying a programming voltage to the dummy gate electrode after the at least one first erasing voltage supply operation, and at least one second erasing voltage supply operation of supplying a second erasing voltage, which is the same as or greater than the first erasing voltage, to the conductive layer after the first programming operation.

[0007] According to the configuration, it is possible to provide a semiconductor storage device capable of achieving appropriate erasing operation. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 of the first embodiment.

[0009] Figure 2 is a schematic side view showing an example of the configuration of the memory system 10.

[0010] Figure 3is a schematic plan view showing a configuration example of the memory system 10.

[0011] Figure 4 is a schematic block diagram showing a configuration of the memory die MD.

[0012] Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0013] Figure 6 is a schematic perspective view showing a part of the configuration of the memory die MD.

[0014] Figure 7 is a schematic sectional view showing a part of the configuration of the memory die MD.

[0015] Figure 8 is a schematic sectional view showing a part of the configuration of the memory die MD.

[0016] Figure 9 is a schematic sectional view showing a part of the configuration of the memory die MD.

[0017] Figure 10 is a schematic histogram for explaining threshold voltages of the memory cells MC in which 1-bit data is recorded.

[0018] Figure 11 (a) to (c) are schematic histograms for explaining threshold voltages of the memory cells MC in which 3-bit data is recorded.

[0019] Figure 12 is a flowchart for explaining a method of operation of the memory die MD.

[0020] Figure 13 is a timing chart for explaining a method of operation of the memory die MD.

[0021] Figure 14 is a schematic sectional view for explaining a method of operation of the memory die MD.

[0022] Figure 15 is a schematic sectional view for explaining a method of operation of the memory die MD.

[0023] Figure 16 is a schematic sectional view for explaining a method of operation of the memory die MD.

[0024] Figure 17 is a schematic sectional view for explaining a method of operation of the memory die MD.

[0025] Figure 18(a) to (c) are schematic column graphs for illustrating threshold voltages of the normal memory cell MC and the dummy memory cell DMC.

[0026] Figure 19 (a) to (c) are schematic column graphs for illustrating threshold voltages of the normal memory cell MC and the dummy memory cell DMC.

[0027] Figure 20 is a timing chart for illustrating an erase operation of the semiconductor storage device of Comparative Example 1.

[0028] Figure 21 is a timing chart for illustrating an erase operation of the semiconductor storage device of Comparative Example 2.

[0029] Figure 22 is a schematic column graph for illustrating threshold voltages of the dummy memory cell DMC of Comparative Example 2.

[0030] Figure 23 is a schematic sectional view showing a part of the configuration of the semiconductor storage device of the variation example.

[0031] Figure 24 is a flowchart for illustrating an erase operation of the semiconductor storage device of the second embodiment.

[0032] Figure 25 is a timing chart for illustrating an erase operation of the semiconductor storage device of the second embodiment.

[0033] Figure 26 is a flowchart for illustrating an erase operation of the semiconductor storage device of the third embodiment.

[0034] Figure 27 is a timing chart for illustrating an erase operation of the semiconductor storage device of the third embodiment. DETAILED DESCRIPTION

[0035] Next, the semiconductor storage device of the embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples, and are not intended to limit the present application.

[0036] In addition, in the present specification, when referring to a "semiconductor storage device", it sometimes refers to a memory die (memory chip), and sometimes refers to a memory system including a controller die such as a memory card, an SSD (Solid State Drive), and the like. Furthermore, it sometimes refers to a configuration including a host such as a smartphone, a tablet terminal, a personal computer, and the like.

[0037] In addition, in this specification, when a first component is referred to as being "electrically connected to" a second component, it can be directly connected to the second component, or remote from the second component via a wiring, a semiconductor element, or a transistor, and the like. For example, in the case where three transistors are connected in series, even if a second transistor is in an off state, a first transistor is "electrically connected" to a third transistor.

[0038] In addition, in this specification, when a first component is referred to as being "connected to" between a second component and a third component, it means that the first component, the second component, and the third component are connected in series, and the second component is connected to the third component via the first component.

[0039] In addition, in this specification, when a circuit or the like is referred to as "turning on" two wirings or the like, for example, it means that the circuit or the like includes a transistor or the like, the transistor or the like is provided on a current path between the two wirings, and the transistor or the like is in an on state.

[0040] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0041] In addition, in this specification, a direction along a specific surface is sometimes referred to as a first direction, a direction intersecting the first direction along the specific surface is sometimes referred to as a second direction, and a direction intersecting the specific surface is sometimes referred to as a third direction. The first direction, the second direction, and the third direction can or can not correspond to any of the X direction, the Y direction, and the Z direction.

[0042] In addition, in this specification, "upper", "lower", and the like are based on the substrate. For example, a direction away from the substrate along the Z direction is referred to as upper, and a direction approaching the substrate along the Z direction is referred to as lower. In addition, with respect to a certain component, when a lower surface or a lower end is referred to, it means a surface or an end portion on the substrate side of the component, and when an upper surface or an upper end is referred to, it means a surface or an end portion on the side opposite to the substrate of the component. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface, and the like.

[0043] In addition, in this specification, with respect to a component, a member, and the like, when a "width", a "length", or a "thickness", and the like of a certain direction are referred to, it sometimes means a width, a length, or a thickness, and the like of a cross section, and the like observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), and the like.

[0044] [1st Embodiment] [Memory System 10]Figure 1 is a schematic block diagram showing the configuration of the memory system 10 of the first embodiment.

[0045] The memory system 10 performs readout, writing, erasure, and the like of user data in accordance with a signal transmitted from the host 20. The memory system 10 is, for example, a memory card, an SSD, or another system capable of storing user data. The memory system 10 is provided with a plurality of memory dies MD that store user data, and a controller die CD that is connected to the plurality of memory dies MD and the host 20. The controller die CD is provided with, for example, a processor, a RAM (Random Access Memory), and the like, and performs processing such as conversion of a logical address and a physical address, bit error detection / correction, garbage collection (compaction), wear leveling, and the like.

[0046] Figure 2 is a schematic side view showing a configuration example of the memory system 10 of the present embodiment. Figure 3 is a schematic plan view showing a configuration example of the memory system 10 of the present embodiment. For convenience of explanation, Figure 2 and Figure 3 part of the configuration is omitted in

[0047] As shown in Figure 2 , the memory system 10 of the present embodiment is provided with a mounting substrate MSB, a plurality of memory dies MD laminated on the mounting substrate MSB, and a controller die CD laminated on the memory dies MD. A solder pad electrode P is provided in an end region in the Y direction in the upper surface of the mounting substrate MSB, and the other region is adhered to the lower surface of the memory dies MD via an adhesive or the like. A solder pad electrode P is provided in an end region in the Y direction in the upper surface of the memory dies MD, and the other region is adhered to the lower surface of the other memory dies MD or the controller die CD via an adhesive or the like. A solder pad electrode P is provided in an end region in the Y direction in the upper surface of the controller die CD.

[0048] As shown in Figure 3 , the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are each provided with a plurality of solder pad electrodes P arranged in the X direction. The plurality of solder pad electrodes P provided in the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0049] Furthermore, Figure 2 and Figure 3 the configuration shown in Figure 2 and Figure 3In the example shown, a controller die CD is stacked on multiple memory dies MD, and these are connected by bonding wires B. In this configuration, the multiple memory dies MD and the controller die CD are included in one package. However, the controller die CD can also be included in a package different from the memory die MD. Additionally, the multiple memory dies MD and the controller die CD can be connected to each other via through electrodes or the like instead of the bonding wires B.

[0050] [Circuit Configuration of Memory Die MD] Figure 4 It is a schematic block diagram showing the configuration of the memory die MD of the first embodiment. Figure 5 It is a schematic circuit diagram showing a part of the configuration of the memory die MD. For ease of explanation, Figure 4 and Figure 5 a part of the configuration is omitted.

[0051] In addition, Figure 4 multiple control terminals and the like are illustrated. These multiple control terminals sometimes represent control terminals corresponding to high-active signals (positive logic signals), sometimes represent control terminals corresponding to low-active signals (negative logic signals), and sometimes represent control terminals corresponding to both high-active signals and low-active signals. Figure 4 In, the symbol of the control terminal corresponding to the low-active signal includes an overline (overline). In this specification, the symbol of the control terminal corresponding to the low-active signal includes a slash (" / "). In addition, Figure 4 taking the description of as an example, the specific aspects can be appropriately adjusted. For example, some or all of the high-active signals can be made into low-active signals, or some or all of the low-active signals can be made into high-active signals. Additionally, the terminal RY / ( / BY) described below is a terminal that outputs a ready signal as a high-active signal and a busy signal as a low-active signal. The slash (" / ") between RY and ( / BY) represents a separator between the ready signal and the busy signal.

[0052] As Figure 4 shown, the memory die MD includes: memory cell arrays MCA0, MCA1 for storing user data, and a peripheral circuit PC connected to the memory cell arrays MCA0, MCA1. In addition, in the following description, the memory cell arrays MCA0, MCA1 are sometimes referred to as the memory cell array MCA.

[0053] [Circuit Configuration of Memory Cell Array MCA] As Figure 5As shown, the memory cell array MCA has multiple memory blocks BLK. Each memory block BLK has multiple string components SU. Each string component SU has multiple memory strings MS. One end of each memory string MS is connected to the peripheral circuit PC via a bit line BL. The other end of each memory string MS is connected to the peripheral circuit PC via a common source line SL.

[0054] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes referred to simply as selection transistors (STD, STS).

[0055] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. A memory cell (MC) typically stores one or more bits of user data. Furthermore, the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0056] The select transistor (STD, STS) is a field-effect transistor, comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the select transistor (STD, STS) is connected to the drain-side select gate line SGD and the source-side select gate line SGS, respectively. The drain-side select gate line SGD is provided for a string assembly SU and is commonly connected to all memory strings MS in one string assembly SU. The source-side select gate line SGS is commonly connected to all memory strings MS in the memory block BLK. Hereinafter, the drain-side select gate line SGD and the source-side select gate line SGS are sometimes simply referred to as the select gate line (SGD, SGS).

[0057] [Circuit configuration of the peripheral circuit PC] For example, Figure 4 As shown, the peripheral circuit PC includes row decoders RD0 and RD1, and sense amplifiers SA0 and SA1, respectively connected to the memory cell arrays MCA0 and MCA1. Additionally, the peripheral circuit PC includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes input / output control circuitry (I / O), logic circuitry CTR, address register ADR, instruction register CMR, and status register STR. In the following description, row decoders RD0 and RD1 are sometimes referred to as row decoders RD, and sense amplifiers SA0 and SA1 are sometimes referred to as sense amplifiers SA.

[0058] [The structure of the line decoder RD] For example, Figure 5 As shown, the line decoder RD( Figure 4 ) has the ability to add (add( address data) Figure 4 Address decoder 22 for decoding. Additionally, line decoder RD( Figure 4 It has a block selection circuit 23 and a voltage selection circuit 24 that transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0059] Address decoder 22 is connected to multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, refers sequentially to address register ADR according to control signals from sequencer SQC. Figure 4 The row address RA of ).

[0060] The block selection circuit 23 has multiple block selection circuits 34 corresponding to the storage block BLK.

[0061] The block select circuit 34 has multiple block select transistors 35 corresponding to the word line WL and the select gate lines (SGD, SGS).

[0062] The block select transistor 35 is, for example, a field-effect transistor. The drain electrode of the block select transistor 35 is electrically connected to the corresponding word line WL or select gate line (SGD, SGS). The source electrode of the block select transistor 35 is electrically connected to the voltage supply line 31 via wiring CG and voltage selection circuit 24. The gate electrode of the block select transistor 35 is commonly connected to the corresponding block select line BLKSEL.

[0063] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS). Each of these voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0064] [Composition of Sensing Amplifier SA] Sensing amplifiers SA0, SA1 ( Figure 4 Each of the two modules has a sense amplifier module (SAM0, SAM1) and a high-speed cache memory (CM0, CM1, data register). The high-speed cache memory (CM0, CM1) has latch circuits (XDL0, XDL1).

[0065] In addition, in the following description, the sense amplifier modules SAM0 and SAM1 are sometimes referred to as sense amplifier modules SAM, the cache memory CM0 and CM1 are referred to as cache memory CM, and the latch circuits XDL0 and XDL1 are referred to as latch circuits XDL.

[0066] Multiple latch circuits XDL are connected to the latch circuit within the sense amplifier module SAM. The latch circuits XDL store, for example, user data written to or read from the memory unit MC.

[0067] The cache memory CM, for example, is connected to the column decoder. The column decoder will access the address register ADR (...). Figure 4 The column address CA stored in the memory is decoded, and the latch circuit XDL corresponding to the column address CA is selected.

[0068] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transferred to the latch circuit within the sense amplifier module SAM during a write operation. Additionally, the user data Dat contained in the latch circuit within the sense amplifier module SAM is sequentially transferred to the latch circuit XDL during a read operation. Finally, the user data Dat contained in the latch circuit XDL is sequentially transferred to the input / output control circuit I / O during a data output operation.

[0069] [The structure of the voltage generation circuit VG] For example, Figure 5 As shown, the voltage generation circuit VG( Figure 4 The voltage generation circuit VG is connected to multiple voltage supply lines 31. It includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are respectively connected to the power supply voltage V. CC and grounding voltage V SS ( Figure 4 The voltage supply lines of the reference. These voltage supply lines are connected, for example, to the reference. Figure 2 , Figure 3 The pad electrode P described herein. The voltage generation circuit VG, for example, generates various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations for the memory cell array MCA, according to control signals from the sequencer SQC, and simultaneously outputs them to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 can be appropriately adjusted according to the control signals from the sequencer SQC.

[0070] [Structure of Sequencer SQC] Sequencer SQC ( Figure 4) outputs internal control numbers to the row decoders RD0, RD1, the sense amplifier modules SAM0, SAM1, and the voltage generation circuit VG, in accordance with the instruction data Cmd stored in the instruction register CMR. In addition, the sequencer SQC appropriately outputs state data Stt indicating the state of the memory die MD to the state register STR.

[0071] In addition, the sequencer SQC generates a ready / busy signal, and outputs it to the terminal RY / ( / BY). During the period when the terminal RY / ( / BY) is in the "L" state (busy period), access to the memory die MD is basically prohibited. In addition, during the period when the terminal RY / ( / BY) is in the "H" state (ready period), access to the memory die MD is permitted. Furthermore, the terminal RY / ( / BY) is realized, for example, by referring to the pad electrode P described above. Figure 2 、 Figure 3

[0072] [Configuration of the address register ADR] As shown in FIG. 6, the address register ADR is connected to the input / output control circuit I / O, and stores the address data Add input from the input / output control circuit I / O. The address register ADR has, for example, a plurality of 8-bit register columns. The register columns hold, for example, the address data Add corresponding to the internal action being executed, at the time of execution of an internal action such as a readout action, a write action, or an erase action. Figure 4

[0073] Furthermore, the address data Add includes, for example, a column address CA( Figure 4 ) and a row address RA( Figure 4 ). The row address RA includes, for example, a block address specifying a storage block BLK( Figure 5 ), a page address specifying a string component SU and a word line WL, a memory plane address specifying a memory cell array MCA (memory plane), and a chip address specifying the memory die MD.

[0074] [Configuration of the instruction register CMR] The instruction register CMR is connected to the input / output control circuit I / O, and stores the instruction data Cmd input from the input / output control circuit I / O. The instruction register CMR has, for example, at least one set of 8-bit register columns. After the instruction register CMR stores the instruction data Cmd, it sends a control signal to the sequencer SQC.

[0075] ​​[Configuration of the state register STR] The state register STR is connected to the input / output control circuit I / O, and stores state data Stt output to the input / output control circuit I / O. The state register STR has, for example, a plurality of 8-bit register columns. The register columns hold, for example, state data Stt related to an internal operation in progress at the time of execution of a read operation, a write operation, or an erase operation, and the like. In addition, the register columns hold, for example, ready / busy information of the memory cell arrays MCAO, MCA1.

[0076] [Configuration of the input / output control circuit I / O] The input / output control circuit I / O Figure 4 has data signal input / output terminals DQO to DQ7, data strobe signal input / output terminals DQS, / DQS, a shift register, and a buffer circuit.

[0077] The data signal input / output terminals DQO to DQ7, and the data strobe signal input / output terminals DQS, / DQS are each realized, for example, by referring to Figure 2 , Figure 3 a pad electrode P as described below. Data input via the data signal input / output terminals DQO to DQ7 is input from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR, in accordance with an internal control signal from the logic circuit CTR. In addition, data output via the data signal input / output terminals DQO to DQ7 is input from the cache memory CM or the state register STR to the buffer circuit, in accordance with an internal control signal from the logic circuit CTR.

[0078] A signal (for example, a data strobe signal and a complementary signal thereof) input via the data strobe signal input / output terminals DQS, / DQS is used when data is input via the data signal input / output terminals DQO to DQ7. Data input via the data signal input / output terminals DQO to DQ7 is latched into the shift register within the input / output control circuit I / O at a point in time at which the voltage at the data strobe signal input / output terminal DQS is at a rising edge (input signal switching) and the voltage at the data strobe signal input / output terminal / DQS is at a falling edge (input signal switching), and at a point in time at which the voltage at the data strobe signal input / output terminal DQS is at a falling edge (input signal switching) and the voltage at the data strobe signal input / output terminal / DQS is at a rising edge (input signal switching).

[0079] [Configuration of the logic circuit CTR] The logic circuit CTR Figure 4) a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, and a logic circuit connected to the plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O in accordance therewith.

[0080] Further, the external control terminals / CE, CLE, ALE, / WE, / RE, RE are each realized, for example, by a pad electrode P as described with reference to Figure 2 , Figure 3 .

[0081] [Configuration of the memory die MD] Figure 6 is a schematic perspective view showing a part of the configuration of the memory die MD. Figure 7 is a schematic plan view showing a part of the configuration of the memory die MD. Figure 8 is a schematic cross-sectional view showing the configuration shown in Figure 7 , taken along the line B-B' and viewed in the direction of the arrows. Figure 9 is a schematic cross-sectional view showing the region D shown in Figure 8 , shown on an enlarged scale. For the sake of convenience in explanation, a part of the configuration in Figure 6-9 is omitted.

[0082] As shown, for example, in Figure 6 , the semiconductor storage device of the present embodiment is provided with: a transistor layer L TR provided on a semiconductor substrate 100; and a memory cell array layer L MCA provided above the transistor layer L TR .

[0083] [Configuration of the transistor layer L TR As shown, for example, in Figure 6 , on the upper surface of the semiconductor substrate 100, through an unillustrated insulating layer, a wiring layer GC is provided. The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. In addition, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are connected to a contact CS, respectively.

[0084] The plurality of electrodes gc each face the surface of the semiconductor substrate 100, and function as gate electrodes of a plurality of transistors Tr constituting a peripheral circuit PC, and electrodes of a plurality of capacitors, and the like.

[0085] Multiple contacts CS extend along the Z-direction and are connected at their lower ends to the upper surface of the semiconductor substrate 100 or the electrode gc. At the connection point between the contacts CS and the semiconductor substrate 100, an impurity region containing N-type or P-type impurities is provided. The contacts CS may also comprise a multilayer film, for example, a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0086] Wiring layers D0, D1, and D2 each contain multiple wirings that are electrically connected to at least one component in the memory cell array (MCA) and the peripheral circuitry (PC). These wirings may, for example, comprise multilayer films having barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0087] [Storage cell array layer L] MCA [Construction] as Figure 6 As shown, the storage cell array layer L MCA It has a storage block BLK. The storage block BLK has a storage cell array layer L. MCA1 and set in the storage cell array layer L MCA1 The upper storage cell array layer L MCA2 .like Figure 8 As shown, the storage cell array layer L MCA1 and storage cell array layer L MCA2 It includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0088] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. For example... Figure 9 As shown, the conductive layer 110 may also comprise a laminated film having a barrier conductive film 116 such as titanium nitride (TiN) and a metal film 115 such as tungsten (W). Furthermore, an insulating metal oxide film 134 such as aluminum oxide (AlO) may be provided at a position covering the outer periphery of the barrier conductive film 116. Additionally, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). At the X-direction ends of the plurality of conductive layers 110, contacts CC (…) are respectively provided. Figure 6 An insulating layer 101, such as silicon oxide (SiO2), is disposed between multiple conductive layers 110 arranged in the Z direction. Figure 8 ).

[0089] Below the multiple conductive layers 110, such as Figure 8 As shown, semiconductor layers 111, 113, and 112 are disposed with an insulating layer 101 in between. A portion of a gate insulating film 130 is disposed between semiconductor layers 111 and 112 and semiconductor layer 120. Semiconductor layer 113 is connected to the lower end of semiconductor layer 120.

[0090] The upper surface of the semiconductor layer 113 is connected to the semiconductor layer 111, and the lower surface is connected to the semiconductor layer 112. A conductive layer 114 can also be provided on the lower surface of the semiconductor layer 112. The semiconductor layer 111, the semiconductor layer 113, the semiconductor layer 112, and the conductive layer 114 function as a source line SL Figure 5 ). The semiconductor layer 111, the semiconductor layer 113, and the semiconductor layer 112 contain, for example, polysilicon containing an impurity such as phosphorus (P) or boron (B). The conductive layer 114 can also contain, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or another conductive layer.

[0091] Among the plurality of conductive layers 110 provided in the memory cell array layer L MCA1 ( Figure 8 ), the conductive layer 110 located at the lowermost layer functions as a source side selection gate line SGS Figure 5 ) and a gate electrode of a plurality of source side selection transistors STS Figure 5 ) connected to the source side selection gate line SGS. This conductive layer 110 is electrically independent in each memory block BLK.

[0092] In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L MCA1 ( Figure 8 ), a part of the plurality of conductive layers 110 located above the conductive layer 110 functioning as the source side selection gate line SGS or the like functions as a word line WL and a gate electrode of a plurality of memory cells MC connected to the word line. Between these conductive layers 110 and the semiconductor layer 120, the memory cell MC described with reference to Figure 5 These plurality of conductive layers 110 are electrically independent in each memory block BLK, respectively.

[0093] Hereinafter, among the plurality of conductive layers 110 provided in the memory cell array layer L MCA1 ( Figure 8 ), a part functioning as the word line WL or the like (a part functioning as the gate electrode of the "normal word line WL" and the "normal memory cell MC" described below) will be referred to as a first gate electrode 110_1. In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L MCA1 ( Figure 8 ), a part of the conductive layer 110 functioning as the word line WL or the like (a part functioning as the gate electrode of the "dummy word line WLD" and the "dummy memory cell DMC" described below) will be referred to as a dummy conductive layer 110DM.

[0094] In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L MCA2 ( Figure 8A portion of the multiple conductive layers 110 functions as a word line WL and the gate electrodes of multiple memory cells MC connected to the word line WL. A reference layer is disposed between these conductive layers 110 and the semiconductor layer 120. Figure 5 The memory cell MC is described. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0095] Additionally, it is set in the storage cell array layer L MCA2 ( Figure 8 Of the multiple conductive layers 110, one or more conductive layers 110 located above the conductive layers 110 that function as part of a word line WL, etc., function as the gate electrodes of a drain-side select gate line SGD and a plurality of drain-side select transistors STD connected to the drain-side select gate line SGD. These multiple conductive layers 110 have a smaller width in the Y direction compared to the other conductive layers 110. Furthermore, an inter-string component insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. These multiple conductive layers 110 are electrically independent in each string component SU.

[0096] The following will be set in the storage cell array layer L MCA2 ( Figure 8 Of the multiple conductive layers 110, one conductive layer 110 that functions as a word line WL, etc. (hereinafter referred to as the second gate electrode 110_2, which functions as the gate electrode of a "normal word line WL" and a "normal memory cell MC"). Additionally, a conductive layer 110 provided in the memory cell array layer L... MCA2 ( Figure 8 Among the multiple conductive layers 110, a portion of the conductive layer 110 that functions as a word line WL (the portion that functions as the gate electrode of the "virtual word line WLD" and "virtual memory cell DMC" as described below) is called the virtual conductive layer 110DM.

[0097] Semiconductor layer 120, for example Figure 7 As shown, the semiconductor layer 120 is arranged in a specific pattern in the X and Y directions. The semiconductor layer 120 serves as a memory string (MS). Figure 5 The multiple memory cells (MCs) and channel regions of the selection transistors (STDs, STSs) contained within the semiconductor layer 120 function as semiconductor layers, such as polysilicon (Si). Figure 6 As shown, it has a roughly cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is provided in the central part.

[0098] like Figure 8 As shown, the semiconductor layer 120 includes a memory cell array layer L. MCA1 Includes semiconductor region 120 L, and a memory cell array layer L MCA2 The semiconductor region 120 included in the semiconductor layer 120 U The semiconductor layer 120 has a semiconductor region 120 J connected to the upper end of the semiconductor region 120 L and the lower end of the semiconductor region 120 U , an impurity region 122 connected to the lower end of the semiconductor region 120 L , and an impurity region 121 connected to the upper end of the semiconductor region 120 U .

[0099] The semiconductor region 120 L is a substantially cylindrical region extending in the Z direction. The outer peripheral surface of the semiconductor region 120 L is surrounded by and faces a plurality of conductive layers 110 included in the memory cell array layer L MCA1 .

[0100] The semiconductor region 120 U is a substantially cylindrical region extending in the Z direction. The outer peripheral surface of the semiconductor region 120 U is surrounded by and faces a plurality of conductive layers 110 included in the memory cell array layer L MCA2 .

[0101] The semiconductor region 120 J is disposed at a position higher than the plurality of conductive layers 110 included in the memory cell array layer L MCA1 and at a position lower than the plurality of conductive layers 110 included in the memory cell array layer L MCA2 .

[0102] The impurity region 122 is connected to the semiconductor layer 113. The impurity region 122 includes, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B). The portion of the semiconductor layer 120 located directly above the impurity region 122 functions as a channel region of a source side select transistor STS.

[0103] The impurity region 121 includes, for example, an N-type impurity such as phosphorus (P). The impurity region 121 is connected to the bit line BL via the contact Ch and the contact Vy( Figure 6 ).

[0104] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 9As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction.

[0105] In addition, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0106] In addition, Figure 7 In the example, the storage block BLK has 5 string components SUa~SUe, from one side in the Y direction ( Figure 7 The middle (positive side in the Y direction) is set to the other side in the Y direction ( Figure 7 (The middle part is the negative side in the Y direction). These multiple string components SUa~SUe correspond to the reference respectively. Figure 5 The string assembly SU is described. Between two adjacent string assemblies SU in the Y direction, an inter-string assembly insulating layer SHE, such as silicon oxide (SiO2), is provided. An inter-block structure ST is provided between two adjacent memory blocks BLK in the Y direction.

[0107] like Figure 6 As shown, the inter-block structure ST extends in both the Z and X directions. Additionally, as... Figure 8 As shown, the inter-block structure ST is a structure in which multiple insulating layers 101, multiple conductive layers 110, semiconductor layers 111 and 113 are separated in the Y direction and extend to the semiconductor layer 112. The inter-block structure ST is, for example, an insulating layer such as silicon oxide (SiO2). In addition, the inter-block structure ST may include a conductive layer such as tungsten extending in the X and Z directions at its center in the Y direction, and the lower end of the conductive layer may also be connected to the semiconductor layer 112.

[0108] [Virtual Conductive Layer 110DM] One or more virtual conductive layers 110DM may also be provided between the first gate electrode 110_1 and the source-side select gate line SGS. In addition, one or more virtual conductive layers 110DM may also be provided between the second gate electrode 110_2 and the drain-side select gate line SGD.

[0109] Additionally, it is set in the storage cell array layer L MCA1 Of the multiple conductive layers 110, the one closest to the semiconductor region 120 J One or more conductive layers 110 can also be configured as virtual conductive layers 110DM.

[0110] In addition, one or more of the plurality of conductive layers 110 disposed in the memory cell array layer L MCA2 closest to the semiconductor region 120 J may also be provided as a dummy conductive layer 110DM.

[0111] That is, the dummy conductive layer 110DMmay also be provided between the first gate electrode 110_1 and the second gate electrode 110_2.

[0112] The dummy conductive layer 110DMfunctions as a dummy word line WLD Figure 14 and a gate electrode of a plurality of dummy memory cells DMC Figure 14 connected to the dummy word line WLD. The dummy word line WLD is provided as a part of the plurality of word lines WL. Hereinafter, the plurality of word lines WL other than the dummy word line WLD and the word lines WL described below are sometimes referred to as "normal word lines WL". The dummy word line WLD basically has the same configuration as the normal word lines WL. However, in the read operation, the write operation, and the erase operation, the voltage supplied to the dummy word line WLD is sometimes different from the voltage supplied to the normal word lines WL. ND

[0113] The dummy memory cell DMC is provided between the dummy word line WLD and the semiconductor layer 120. The dummy memory cell DMC is provided as a part of the plurality of memory cells MC. Hereinafter, the plurality of memory cells MC other than the dummy memory cell DMC and the memory cells MC described below are sometimes referred to as "normal memory cells MC". The dummy memory cell DMC basically has the same configuration as the normal memory cells MC. However, the dummy memory cell DMC does not perform recording of user data. As described below, the threshold voltage of the dummy memory cell DMC is sometimes adjusted to a necessary and specific size at the time of the read operation, the write operation, and the erase operation. ND

[0114] [Radial width of the semiconductor regions 120 L , 120 U , 120 J Next, the radial width of the semiconductor regions 120 L , 120 U , 120 J will be described. Hereinafter, in the present specification, the width of the semiconductor layer in the X direction or the Y direction that intersects with the extension direction of the semiconductor regions 120 L , 120 U , that is, the Z direction, is referred to as the radial width. Furthermore, for the convenience of explanation, the width in the Y direction is illustrated as the radial width in FIGS. 12A to 12C, and the like. Figure 8 ​​​

[0115] semiconductor region 120 L lower end portion (e.g., a portion located lower than the plurality of conductive layers 110 included in the memory cell array layer L MCA1 radial width W 120LL of the semiconductor region 120 L upper end portion (e.g., a portion located upper than the plurality of conductive layers 110 included in the memory cell array layer L MCA1 radial width W 120LU is small. That is, the more lower, the smaller the radial width of the semiconductor region 120 L

[0116] semiconductor region 120 U lower end portion (e.g., a portion located lower than the plurality of conductive layers 110 included in the memory cell array layer L MCA2 radial width W 120UL of the semiconductor region 120 U upper end portion (e.g., a portion located upper than the plurality of conductive layers 110 included in the memory cell array layer L MCA2 radial width W 120UU is small. That is, the more lower, the smaller the radial width of the semiconductor region 120 U J

[0117] semiconductor region 120 J radial width W 120J of the semiconductor region 120 L radial width W 120LU of the semiconductor region 120 U radial width W 120UL of the semiconductor region 120 VFYEr

[0118] [Threshold voltage of memory cell MC recording 1-bit data] Next, the threshold voltage of the memory cell MC recording 1-bit data is described with reference to Figure 10

[0119] Figure 10 is a schematic bar graph for illustrating the threshold voltage of the memory cell MC recording 1-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0120] Figure 10 In the example of FIG. 14, the threshold voltage of the memory cell MC is controlled to 2 states. For example, the threshold voltage of the memory cell MC controlled to the lower state is smaller than the erase verify voltage V VFYEr . In addition, the threshold voltage of the memory cell MC controlled to the upper state is larger than the verify voltage V​​​VFYS Large, and smaller than the readout path voltage V READ .

[0121] In addition, Figure 10 In the example of Fig. 8, the threshold distribution corresponding to the lower state is set to be smaller than the readout voltage V CGR .

[0122] For example, the lower state corresponds to a lower threshold voltage. The storage cell MC of the lower state is, for example, a storage cell MC in the erased state. The storage cell MC of the lower state is, for example, assigned the data "1".

[0123] In addition, the upper state corresponds to a higher threshold voltage. The storage cell MC of the upper state is, for example, a storage cell MC in the written state. The storage cell MC of the upper state is, for example, assigned the data "0".

[0124] [Threshold voltage of storage cell MC recording multiple bits] Next, the threshold voltage of the storage cell MC recording multiple bits of data will be described. Figure 11 , the threshold voltage of the storage cell MC recording 3 bits of data will be described as an example. Figure 11

[0125] Figure 11 (a) is a schematic bar graph for explaining the threshold voltage of the storage cell MC recording 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of storage cells MC. Figure 11 (b) is a table showing an example of the relationship between the threshold voltage of the storage cell MC recording 3 bits of data and the recorded data. Figure 11 (c) is a table showing another example of the relationship between the threshold voltage of the storage cell MC recording 3 bits of data and the recorded data.

[0126] Figure 11 In the example of (a), the threshold voltage of the storage cell MC is controlled to 8 states. The threshold voltage of the storage cell MC controlled to the Er state is smaller than the erase verify voltage V VFYEr . In addition, for example, the threshold voltage of the storage cell MC controlled to the A state is larger than the verify voltage V VFYA , and smaller than the verify voltage V VFYB . In addition, for example, the threshold voltage of the storage cell MC controlled to the B state is larger than the verify voltage V VFYB , and smaller than the verify voltage V VFYC . Also below, the threshold voltage of the storage cell MC controlled to the C state to the F state is larger than the verify voltage V VFYC to the verify voltage V VFYF , and smaller than the verify voltage V VFYD to the verify voltage V​VFYG small. In addition, for example, the threshold voltage of the memory cell MC controlled to the G state is larger than the verify voltage V VFYG and is smaller than the readout path voltage V READ .

[0127] In addition, Figure 11 In the example of (a), the threshold distribution corresponding to the Er state is set to be smaller than the threshold distribution corresponding to the A state, and the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state. In the example of (b), the threshold distribution corresponding to the Er state is set to be smaller than the threshold distribution corresponding to the A state, and the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state, and the threshold distribution corresponding to the B state is set to be smaller than the threshold distribution corresponding to the C state. CGAR In addition, the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state, and the threshold distribution corresponding to the B state is set to be smaller than the threshold distribution corresponding to the C state. CGBR In the example of (b), the threshold distribution corresponding to the Er state is set to be smaller than the threshold distribution corresponding to the A state, and the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state, and the threshold distribution corresponding to the B state is set to be smaller than the threshold distribution corresponding to the C state. CGBR In addition, the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state, and the threshold distribution corresponding to the B state is set to be smaller than the threshold distribution corresponding to the C state. CGGR .

[0128] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC of the Er state is, for example, a memory cell MC in the erased state. The memory cell MC of the Er state is, for example, assigned the data "111".

[0129] In addition, the A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. The memory cell MC of the A state is, for example, assigned the data "101".

[0130] In addition, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the A state. The memory cell MC of the B state is, for example, assigned the data "001".

[0131] In the example of (b), the threshold distribution corresponding to the Er state is set to be smaller than the threshold distribution corresponding to the A state, and the threshold distribution corresponding to the A state is set to be smaller than the threshold distribution corresponding to the B state, and the threshold distribution corresponding to the B state is set to be smaller than the threshold distribution corresponding to the C state.

[0132] In addition, in the case of assignment as exemplified in Figure 11 (b), the data of the lower bits can be discriminated by one readout voltage V CGDR , the data of the middle bits can be discriminated by three readout voltages V CGAR , V CGCR , and V CGFR , and the data of the upper bits can be discriminated by three readout voltages V CGBR , V CGER , and V CGGR . This assignment of data is sometimes referred to as 1-3-3 coding.

[0133] Further, the number of bits of data, the number of states, the allocation of data to each state, and the like recorded in the memory cell MC can be changed as appropriate.

[0134] For example, in the case of allocation as illustrated in Figure 11 (c), the data of the lower bits can be discriminated by 1 read voltage V CGDR , the data of the middle bits can be discriminated by 2 read voltages V CGBR , V CGFR , and the data of the upper bits can be discriminated by 4 read voltages V CGAR , V CGCR , V CGER , V CGGR . This allocation of data is sometimes referred to as 1-2-4 coding.

[0135] [Erasing Operation] Next, the erasing operation of the semiconductor storage device of the present embodiment will be described. Figure 12 is a flowchart for explaining the erasing operation. Figure 13 is a timing chart for explaining the erasing operation. Figure 14 is a schematic cross-sectional view for explaining the erasing operation (1) and the erasing operation (2) included in the erasing operation. Figure 15 is a schematic cross-sectional view for explaining the erase verifying operation included in the erasing operation. Figure 16 is a schematic cross-sectional view for explaining the WLD programming operation included in the erasing operation. Figure 17 is a schematic cross-sectional view for explaining the erasing operation (3) included in the erasing operation.

[0136] Further, in the following description, as illustrated in Figure 14-17 , the word line WL provided between the virtual word line WLD and the ordinary word line WL is referred to as the word line WL ND , and the memory cell MC connected to the word line WL ND is referred to as the memory cell MC ND . The word line WL ND basically has the same configuration as the ordinary word line WL. However, regarding the read operation, the write operation, and the erasing operation, the voltage supplied to the word line WL ND is sometimes different from the voltage supplied to the ordinary word line WL. The word line WL ND is realized by, for example, the upper conductive layer 110 of each virtual conductive layer 110DM and the lower conductive layer 110 of the virtual conductive layer 110DM. The memory cell MC ND has the same configuration as the ordinary memory cell MC. In addition, the recording of user data is performed on the memory cell MC ND in the same manner as the ordinary memory cell MC.

[0137] Further, in the following description, an example of performing an erasing operation on a memory block BLK as an operation object will be described.

[0138] [Step of erasing operation] First, using Figure 12 Each step of the erasing operation of the present embodiment will be described.

[0139] In step S101, the number of cycles n E is set to 1.

[0140] In step S102, it is determined whether the number of cycles n E is a specific number "3". In the case where the number of cycles n E is not the specific number "3", step S103 is entered. In the case where the number of cycles n E is the specific number "3", after step S109 is entered, step S103 is entered.

[0141] In step S103, an erasing operation (n E ) corresponding to the number of cycles n E is performed. The erasing operation (n E ) will be described later.

[0142] In step S104, it is determined whether the number of cycles n E is a specific number "1". In the case where the number of cycles n E is the specific number "1", step S105 is entered. In the case where the number of cycles n E is not the specific number "1", step S106 is entered.

[0143] In step S105, the number of cycles n E is incremented by 1, and step S102 is entered.

[0144] In step S106, an erasing verification operation is performed. The erasing verification operation will be described later. After the erasing verification operation, a not-illustrated counting circuit or the like in the peripheral circuit PC Figure 1 ) counts the number of normal memory cells MC and memory cells MC ND whose threshold voltages reach a target value, or the number of normal memory cells MC and memory cells MC ND whose threshold voltages do not reach the target value.

[0145] In step S107, the result of the erasing verification operation is determined. For example, with reference to the counting circuit or the like, it is determined whether the number of normal memory cells MC and memory cells MC NDPASS), and the process proceeds to step S110. On the other hand, in the case where the threshold voltage of the normal memory cell MC and the memory cell MC ND PASS), and the process proceeds to step S110. On the other hand, in the case where the threshold voltage of the normal memory cell MC and the memory cell MC

[0146] In step S108, it is determined whether the number of cycles n E reaches a certain number N E . In the case where the number of cycles n E does not reach the certain number N E , the process proceeds to step S105. In the case where the number of cycles n E reaches the certain number N

[0147] In step S109, a WLD programming operation is performed. The WLD programming operation will be described later.

[0148] In step S110, state data Stt intended to express that the erase operation has ended normally is stored in a state register STR Figure 4 , and the erase operation is ended.

[0149] In step S111, state data Stt intended to express that the erase operation has not ended normally is stored in a state register STR Figure 4 , and the erase operation is ended.

[0150] [Erasing Operation Cycle] Next, each cycle of the erase operation will be described. Further, at a time point t101 Figure 13 before the start of the erase operation cycle, the terminal RY / ( / BY) becomes "L" state from "H" state, and access to the memory die MD is prohibited. In addition, at the start of the erase operation cycle, in step S101 Figure 12 , the number of cycles n E is set to 1.

[0151] [Erasing Operation: Cycle "1"] The case where the number of cycles n E is "1" will be described. The cycle "1" of the erase operation is performed from the time point t102 to the time point t104 in Figure 13 .

[0152] In the case where the number of cycles n E is "1", in step S102 Figure 12 , the process proceeds to step S103.

[0153] In step S103 Figure 12 , the erase operation (1) in the cycle "1" is performed. The erase operation (1) is, for example, performed from Figure 13The execution proceeds from time t102 to time t103.

[0154] In the erasure action (1), for example, as Figure 14 As shown, the gate line SGD is supplied with voltage V to the drain side. SG' The source-side gate line SGS is supplied with voltage V. SG” Voltage V SG' The size of the drain-side selected transistor STD when it is in the off state. For example, in semiconductor layer 113 ( Figure 8 In the presence of P-type impurities such as boron (B), the voltage V SG” When the source-side selection transistor STS operates as a PMOS (P-Channel Metal Oxide Semiconductor) transistor, the size at which the source-side selection transistor STS is turned on is known. For example, in semiconductor layer 113 ( Figure 8 When N-type impurities such as phosphorus (P) are present, the voltage V SG” It has the magnitude of GIDL (Gate Induced Drain Leakage) generated in the source-side select transistor STS.

[0155] Additionally, in the erasure action (1), such as Figure 13 and Figure 14 As shown, the first erase voltage V is supplied to the source line SL. ERA1 For the usual word line WL and word line WL ND Supply the first voltage V SS1 The first voltage V SS1 Can be connected to ground voltage V SS The voltage can be the same, or it can be greater than or less than the ground voltage V. SS Therefore, for the ordinary memory cell MC connected to the ordinary word line WL, and the memory cell connected to the word line WL... ND storage unit MC ND Supply voltage difference V ERA1 -V SS1 This allows holes to be injected into the charge storage membrane 132, and the typical memory cell MC and memory cell MC ND The threshold voltage is reduced.

[0156] Additionally, in the erasure action (1), such as Figure 13 and Figure 14 As shown, the voltage V supplied to the virtual word line WLD is... WLD1 Voltage V WLD1 Greater than the first voltage V SS1 Less than the first erasure voltage V ERA1 Therefore, a voltage difference V is supplied to the virtual memory cell DMC connected to the virtual word line WLD.ERA1 -V WLD1 The voltage difference V applied to the virtual memory cell DMC ERA1 -V WLD1 The voltage difference V applied to a typical memory cell MC ERA1 -V SS1 Small. Therefore, the threshold voltage of these virtual memory cells (DMCs) did not decrease much.

[0157] In the number of loops n E When the value is "1", step S104 ( Figure 12 In step S105, the erase verification action in step S106 is not executed in loop "1".

[0158] Step S105 ( Figure 12 In step S102, add 1 to the loop count "1" to make the loop count "2".

[0159] [Erase action: loop "2"] Next, loop number n E Let's explain the case of "2". The eraser cycle "2" is in... Figure 13 In the process, execution proceeds from time point t104 to time point t107.

[0160] In the number of loops n E When the value is "2", in step S102 ( Figure 12 In step S103, proceed to step S103.

[0161] Step S103 ( Figure 12 In the loop "2", the erase action (2) is executed. The erase action (2) is, for example, from... Figure 13 The execution proceeds from time t104 to time t105.

[0162] In the erasure action (2), such as Figure 13 and Figure 14 As shown, the voltage supplied is basically the same as that in erase operation (1). However, in erase operation (2), the source line SL is supplied with the same voltage as the first erase voltage V. ERA1 Same as or greater than the first erase voltage V ERA1 The second erase voltage V ERA2 Therefore, the typical memory cell MC and the memory cell MC ND The threshold voltage is further reduced.

[0163] In addition, in the erase operation (2), the same voltage V is supplied to the virtual word line WLD as in the erase operation (1). WLD1 Therefore, a voltage difference V is supplied to the virtual memory cell DMC connected to the virtual word line WLD. ERA2 -V WLD1The voltage difference V applied to the virtual memory cell DMC ERA2 -V WLD1 The voltage difference V applied to a typical memory cell MC ERA2 -V SS1 Small. Therefore, the threshold voltage of these virtual memory cells (DMCs) did not decrease much.

[0164] In the number of loops n E When the value is "2", in step S104 ( Figure 12 In step S106, proceed to step S106.

[0165] In step S106 ( Figure 12 In the loop "2", the erase verification action is performed. For example, the erase verification action in loop "2" starts from... Figure 13 The execution proceeds from time t106 to time t107.

[0166] In the erase verification action, for example, Figure 13 and Figure 15 As shown, a ground voltage V is supplied to the source line SL. SRC The power supply voltage V is supplied to the alignment line BL. DD The read path voltage V is supplied to the virtual word line WLD. READ Read the path voltage V READ The voltage used to turn on the virtual memory cell DMC is used when the virtual memory cell DMC operates as an NMOS transistor. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS). SG The voltage VSG is the voltage at which the select transistors (STD, STS) are turned on when they operate as NMOS transistors.

[0167] Additionally, during the erase verification process, the usual word line WL and word line WL are also included. ND Supply erase verification voltage V VFYEr Therefore, as Figure 15 As shown, the threshold voltage is the erase verification voltage V. VFYEr The following normal memory cells MC and MCND are turned on, and the threshold voltage is greater than the erase verification voltage V. VFYEr Typical storage unit MC and storage unit MC ND It becomes disconnected. Via bit line BL, using the sense amplifier module SAM ( Figure 4 This is used to detect the on / off state of these memory cells (MCs) and obtain data representing the state of that memory cell (MC). The readout path voltage V... READ Greater than the erase verification voltage V VFYEr .

[0168] In step S107 ( Figure 12 In step S108, the result of the verification action is determined. The following explains the cases where verification fails. Additionally, in step S108, a specific number of times N... E The value is greater than "3". In this case, proceed to step S105.

[0169] In step S105, the number of iterations n E Then add 1 to make the number of cycles "3", and proceed to step S102.

[0170] Furthermore, regarding the time point t107 at the end of loop "2", multiple normal memory cells MC, multiple memory cells MC ND The threshold voltage distribution of multiple virtual memory cells (DMCs) will be described below.

[0171] [Erase action: loop "3"] Next, loop number n E Let's explain the case of "3". The erase action cycle "3" is in... Figure 13 In the process, execution proceeds from time point t107 to time point t113.

[0172] In the number of loops n E In the case of "3", in step S102 ( Figure 12 In step S109, proceed to step S109.

[0173] Step S109 ( Figure 12 Within ), execute WLD programming actions. WLD programming actions, for example, from... Figure 13 The execution proceeds from time t108 to time t109.

[0174] In WLD programming actions, such as Figure 13 and Figure 16 As shown, a ground voltage V is supplied to the bit line BL and the source line SL. SRC The gate line SGD on the drain side is supplied with voltage V. SGD The source side selects to supply ground voltage V to the gate line SGS. SS Voltage V SGD When the drain-side selection transistor STD is operated as an NMOS transistor, the drain-side selection transistor STD is in the ON state. Therefore, the drain-side selection transistor STD is in the ON state, and the source-side selection transistor STS is in the OFF state.

[0175] Additionally, in WLD programming operations, the usual word line WL and word line WL are... ND Write path voltage V PASS The programming voltage V is supplied to the virtual word line WLD. DPGM Write path voltage V PASSWhen the memory cell MC operates as an NMOS transistor, the degree to which the memory cell MC is in the ON state is determined by the programming voltage V. DPGM This causes the threshold voltage of the virtual memory cell (DMC) to rise. Programming voltage V DPGM Greater than the write path voltage V PASS .

[0176] Step S103 ( Figure 12 In the loop "3", the erase action (3) is executed. The erase action (3) is, for example, from... Figure 13 The execution will proceed from time t110 to time t111.

[0177] In the erasure action (3), such as Figure 13 and Figure 17 As shown, the voltage supplied is basically the same as that in erase operation (1). However, in erase operation (3), the source line SL is supplied with the same voltage as the second erase voltage V. ERA2 The same as or greater than the second erase voltage V ERA2 The third erase voltage V ERA3 Therefore, the typical memory cell MC and the memory cell MC ND The threshold voltage is further reduced.

[0178] In addition, unlike erase actions (1) and (2), in erase action (3), a voltage V is supplied to the virtual word line WLD. WLD2 Voltage V WLD2 Less than voltage V WLD1 Therefore, a voltage difference V is supplied to the virtual memory cell DMC. ERA3 -V WLD2 Voltage difference V ERA3 -V WLD2 The voltage difference V greater than that in erase action (1) and erase action (2) ERA2 -V WLD1 .

[0179] In the number of loops n E In the case of "3", in step S104 ( Figure 12 In step S106, proceed to step S106.

[0180] Step S106 ( Figure 12 In loop "3", the same erase verification action as in loop "2" is performed. The erase verification action in loop "3" is, for example, from... Figure 13 The execution proceeds from time t112 to time t113.

[0181] Step S107 ( Figure 12) is the same as the cycle "2", the result of the erase verification action is determined. In the case where the verification is not passed, the step S108 is entered, and in the case where the cycle number "3" does not reach the specified number N E , the cycle "4" after the step S105 is started. In the case where the verification is passed, the step S110 is entered, and the erase action is ended.

[0182] Further, with respect to the time point t113 at the end of the cycle "3", the threshold voltage distributions of the plurality of normal memory cells MC, the plurality of memory cells MC ND , and the plurality of dummy memory cells DMC will be described below.

[0183] [Threshold voltage distribution in erase action] Next, the threshold voltage distributions of the normal memory cells MC, the memory cells MC ND , and the dummy memory cells DMC in the erase action of the present embodiment will be described. Figure 18 and Figure 19 are schematic histograms for illustrating the threshold voltage distributions in the erase action.

[0184] [Threshold voltage distribution at the end of cycle "2"] Figure 18 (a) is a histogram of the threshold voltages of the normal memory cells MC at the end of the cycle "2" (time point t107). The number of cells of these normal memory cells MC whose threshold voltages are lower than the erase verification voltage V VFYEr is indicated as the number of erased cells N PASS_a1 , and the number of cells exceeding the erase verification voltage V VFYEr is indicated as the number of unerased cells N FAIL_a1 .

[0185] Figure 18 (b) is a histogram of the threshold voltages of the memory cells MC ND at the end of the cycle "2" (time point t107). The number of cells of these memory cells MC ND whose threshold voltages are lower than the erase verification voltage V VFYEr is indicated as the number of erased cells N PASS_b1 , and the number of cells exceeding the erase verification voltage V VFYEr is indicated as the number of unerased cells N FAIL_b1 .

[0186] Figure 18 (c) is a histogram of the threshold voltages of the dummy memory cells DMC at the end of the cycle "2" (time point t107). The average of the threshold voltage distributions of these dummy memory cells DMC is indicated as the voltage V WLD_TH1 , and the width of the distribution is indicated as the width Δ WLD_TH1 .

[0187] like Figure 18 (a) and Figure 18 (b) shows the storage cell MC in the storage block BLK. ND The number of unerased units N FAIL_b1 The ratio is higher than the number of unerased cells N in a typical memory cell MC within a memory block BLK. FAIL_a1 The ratio.

[0188] Here, as described above, in the erase operation (1) and erase operation (2), a voltage difference V is supplied between the channel region of the normal memory cell MC and the conductive layer 110, which functions as the normal word line WL. ERA1 -V SS1 or voltage difference V ERA2 -V SS1 Therefore, by injecting holes into the charge storage film 132, the threshold voltage of the typical memory cell MC is reduced. Here, the first voltage V is supplied not only to the typical word line WL connected to the typical memory cell MC. SS1 It also supplies the first voltage V to the word line WL adjacent to the normal word line WL. SS1 In this case, a voltage can be appropriately supplied to the gate insulating film 130. Therefore, holes can be appropriately injected into the charge storage film 132.

[0189] Here, connected to the storage unit MC ND The letter line WL ND It is adjacent to the virtual word line WLD. Additionally, the voltage V supplied to the gate insulating layer of the virtual memory cell DMC... WLD1 Greater than the supply to storage unit MC, MC ND The first voltage V of the gate insulating layer SS1 Therefore, the supply to the storage unit MC ND The effective voltage of the charge storage film 132 may sometimes be lower than the effective voltage supplied to the charge storage film 132 in a typical memory cell MC. In such cases, it may be impossible to properly inject holes into the charge storage film 132, and the memory cell MC... ND The threshold voltage becomes difficult to reduce.

[0190] In addition, such as Figure 18 As shown in (c), at the end of cycle "2", the voltage V WLD_TH1 Sufficiently greater than the erase verification voltage V VFYEr Width Δ WLD_TH1 Relatively narrow. This is because the voltage difference V applied to the virtual memory cell DMC is... ERA2 -V WLD1 Sufficiently less than the voltage difference V applied to the memory cell MC ERA2 -V SS1Therefore, there is no need to significantly reduce the threshold voltage of the virtual memory cell (DMC).

[0191] [Threshold voltage distribution at the end of cycle "3"] Figure 19 (a) is a bar chart of the threshold voltage of memory cell MC at the end of cycle "3" (time point t113). Among these memory cell MCs, those with threshold voltages lower than the erase verification voltage V VFYEr The number of units is represented as the number of units N to be erased. PASS_a2 This will exceed the erase verification voltage V. VFYEr The number of cells is represented by the number of unerased cells N. FAIL_a2 .

[0192] Figure 19 (b) is the memory cell MC at the end of cycle "3" (time point t113). ND A histogram of threshold voltages. These memory cells MC... ND In the middle, the threshold voltage is lower than the erase verification voltage V. VFYEr The number of units is represented as the number of units N to be erased. PASS_b2 This will exceed the erase verification voltage V. VFYEr The number of cells is represented by the number of unerased cells N. FAIL_b2 .

[0193] Figure 19 (c) is a bar chart of the threshold voltages of the virtual memory cell DMCs at the end of cycle "3" (time point t113). The average value of the threshold voltage distribution of these virtual memory cell DMCs is expressed as voltage V. WLD_TH2 The distribution width is expressed as width Δ WLD_TH2 .

[0194] like Figure 19 (a) and Figure 19 (b) shows the storage cell MC in the storage block BLK. ND The number of unerased units N FAIL_b2 The ratio is related to the number of unerased cells N in the typical memory cell MC within the memory block BLK. FAIL_a2 The ratio is the same. That is, in the storage unit MC ND In this process, the threshold voltage is reduced to the same extent as in a typical memory cell MC. This is because, in cycle "3", a relatively large voltage difference V is supplied to the virtual memory cell DMC. ERA3 -V WLD2 It is also easy to access the memory cells MC adjacent to the virtual memory cell DMC. ND A relatively large voltage is applied to the gate insulating layer of the memory cell MC. ND The threshold voltage is easy to decrease.

[0195] In addition, such as Figure 20As shown in (c), at the end of cycle "3", the voltage V WLD_TH2 Sufficiently greater than the erase verification voltage V VFYEr Width Δ WLD_TH2 Relatively narrow. Here, in the erase operation (3), a relatively large voltage difference V is applied to the gate insulating film 130 of the virtual memory cell DMC. ERA3 -V WLD2 Compared to erase operation (1) and erase operation (2), the threshold voltage of the virtual memory cell (DMC) sometimes decreases. Therefore, in this embodiment, a WLD programming operation is performed in step S109, thereby adjusting the threshold voltage of the virtual memory cell (DMC).

[0196] [Comparative Example 1] Figure 13 This is a timing diagram used to illustrate the erase operation of the semiconductor memory device in Comparative Example 1.

[0197] In the erase operation of the semiconductor memory device in Comparative Example 1, instead of cycle "3" in the first embodiment ( Figure 20 ) and execute the loop "3x" ( Figure 13 Unlike loop "3", loop "3x" does not execute WLD programming actions at the very beginning of the loop.

[0198] Furthermore, in the erase operation of the semiconductor memory device in Comparative Example 1, an erase operation (3x) is performed instead of an erase operation (3). In the erase operation (3x) from time point tx01 to time point tx02, a voltage V is supplied to the virtual word line WLD. WLD1 rather than voltage V WLD2 ( Figure 21 ).

[0199] [Threshold distribution of memory cell MC in the erasure operation of Comparative Example 1] In Comparative Example 1, during the erasure operations (1), (2), and (3x), a relatively low voltage difference V is supplied to the virtual memory cell DMC. ERA1 -V WLD1 V ERA2 -V WLD1 V ERA3 -V WLD1 Therefore, the storage unit MC adjacent to the virtual storage unit DMC ND The threshold voltage is not easily reduced, and after a "3x" cycle, the unerased memory cell MC... ND The quantity may increase.

[0200] [Comparative Example 2] Figure 13 This is a timing diagram used to illustrate the erase operation of the semiconductor memory device in Comparative Example 2.

[0201] In the erasure operation of Comparative Example 2, instead of the cycle "1", "2", "3" of the first embodiment ( Figure 21 ), execute the loop "1y", "2y", "3y" ( Figure 22 ).

[0202] In the loop "1y" from time point ty01 to time point ty03, the erasure action (1y) is performed from time point ty01 to time point ty02.

[0203] In the loop "2y" from time point ty03 to time point ty05, the erasure action (2y) is performed from time point ty03 to time point ty04.

[0204] In the erase operation (1y) and erase operation (2y), unlike in the first embodiment, a specific voltage V is supplied to the virtual word line WLD. WLD1 Small voltage V WLD2 .

[0205] In the loop "3y" from time point ty05 to time point ty07, unlike loop "3" in the first embodiment, the WLD programming action is not performed at the beginning of loop "3y".

[0206] [Threshold distribution of memory cell MC in the erasure operation of Comparative Example 2] Next, the threshold distribution of virtual memory cell DMC at the end of loop "3y" (time point ty07) in the erasure operation of Comparative Example 2 will be explained. Figure 22 It is a schematic bar chart used to illustrate the threshold voltage of the virtual memory cell (DMC).

[0207] Figure 22 In this context, for example, the average value of the threshold voltage distribution of the virtual memory cell (DMC) during repeated data write and erase operations is expressed as voltage V. WLD_THx The distribution width is expressed as width Δ WLD_THx .like Figure 19 As shown, the width Δ WLD_THx Width Δ WLD_TH2 ( Figure 9 The deviation of the threshold voltage of the virtual memory cell DMC sometimes becomes larger during the erase operation in Comparative Example 2. The reason for this is believed to be as follows: During cycles "1y" to "3y", a relatively large voltage difference V is supplied to the virtual memory cell DMC. ERA2 -V WLD2 Therefore, the charge accumulation film 132 of the virtual memory cell DMC (refer to...) Figure 22holes. Here, in a case where the erasing operation is continuously performed, holes are continuously supplied to the dummy memory cell DMC, and the threshold voltage of the dummy memory cell DMC is continuously decreased until a certain time. However, if the erasing operation is further performed, electrons in the conductive layer 110 are supplied into the charge accumulation film 132, and the voltage of the dummy memory cell DMC can instead increase. By the decrease as described above, the variation of the threshold voltage of the dummy memory cell DMC can become larger than before the erasing operation. Thus, as shown in FIG. 8, the variation of the threshold voltage of the dummy memory cell DMC can become larger when the data write to the memory cell and the erasing operation are repeatedly performed a plurality of times. Figure 13

[0208] [Effects] In the erasing operation of the semiconductor storage device of the present embodiment, relatively high voltage V Figure 13 is supplied to the dummy word line WLD in the cycle "1" ( Figure 22 ) to the cycle "2" ( WLD1 ), and the voltage applied to the dummy memory cell DMC is relatively decreased. Thereby, it is possible to suppress the variation of the threshold voltage of the dummy memory cell DMC or the decrease of the threshold voltage of the dummy memory cell DMC before the end of the cycle "2" as in Comparative Example 2.

[0209] In addition, in the erasing operation of the semiconductor storage device of the present embodiment, the erasing verification operation is performed in the cycle "2", and when the result is not passed, voltage V WLD1 lower than voltage V WLD2 is supplied to the dummy word line WLD after the cycle "3". Thereby, it is possible to prevent the number of the memory cells MC ND which are not erased from increasing as in Comparative Example 1.

[0210] In addition, in the erasing operation of the semiconductor storage device of the present embodiment, the WLD programming operation is performed in the cycle "3". Thereby, it is possible to suppress the accumulation of excessive holes in the charge accumulation film 132 of the dummy memory cell DMC, and to suppress the occurrence of the phenomenon as described with reference to Figure 10 , thereby suppressing the variation of the threshold voltage of the dummy memory cell DMC.

[0211] In addition, according to this method, the erasing verification operation is performed in the cycle "2", and when the result is passed, the WLD programming operation is not performed in the erasing operation. Thus, it is possible to suppress the variation of the threshold voltage of the dummy memory cell DMC, and to make the time required for the erasing operation relatively short.

[0212] Further, as described with reference to Figure 11 , the normal memory cell MC and the memory cell MC ND ​It can also record 1 bit of data. Here, in the usual storage unit MC and storage unit MC ND In semiconductor memory devices that record 1 bit of data, the number of write and erase operations is relatively large, and the threshold voltage of the virtual memory cell (DMC) may fluctuate relatively easily. According to the semiconductor memory device of the first embodiment, even in this case, fluctuations in the threshold voltage of the virtual memory cell (DMC) can be suppressed relatively easily.

[0213] Additionally, as referenced Figure 11 The description above refers to the typical storage unit MC and storage unit MC in the first embodiment. ND It can also record multi-bit data. Here, the typical storage unit MC and storage unit MC... ND Semiconductor storage devices that record multi-bit data, such as Figure 22 The example illustrates a typical memory cell MC and a memory cell MC. ND The threshold voltage may be controlled within a relatively wide voltage range. In this case, it is sometimes easy to generate voltages such as the reference voltage. Figure 23 The phenomenon described herein. Even under these circumstances, the semiconductor memory device according to the first embodiment can relatively easily suppress fluctuations in the threshold voltage of the virtual memory cell (DMC).

[0214] [Example of variation] Next, refer to Figure 23 A variation of the semiconductor memory device of the first embodiment will be described. Figure 23 This is a schematic cross-sectional view showing a portion of a semiconductor memory device as an example of a variation.

[0215] like Figure 23 As shown, the memory cell array layer L of the semiconductor memory device in this variation example MCA With storage cell array layer L MCA1 , set in the storage cell array layer L MCA1 The upper storage cell array layer L MCA2 and set in the storage cell array layer L MCA2 The upper storage cell array layer L MCA3 .

[0216] Will be set in storage cell array layer L MCA1 L MCA2 L MCA3 The conductive layers 110 that function as gate electrodes for the usual word lines WL and the usual memory cells MC are respectively referred to as the first gate electrode 110_1, the second gate electrode 110_2, and the third gate electrode 110_3.

[0217] Furthermore, in this variation, a conductive layer 110, which functions as a drain-side selected gate line (SGD), is provided in the memory cell array layer L. MCA3 rather than the storage cell array layer L MCA2 .

[0218] like Figure 24 As shown, the semiconductor layer 120 in this variation example includes a memory cell array layer L. MCA1 The included semiconductor region 120 L Storage cell array layer L MCA2 The included semiconductor region 120 U and storage cell array layer L MCA3 The included semiconductor region 120 U2 Additionally, the semiconductor layer 120 has connections in the semiconductor region 120. L The upper end and semiconductor region 120 U The lower semiconductor region 120 J , connected in semiconductor region 120 U The upper end and semiconductor region 120 U2 The lower semiconductor region 120 J2 , connected in semiconductor region 120 L The lower end of the impurity region 122 and the connection to the semiconductor region 120 U2 The impurity region 121 at the upper end.

[0219] Semiconductor Area 120 U2 It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U2 The outer periphery is composed of storage cell array layers L MCA3 It is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110.

[0220] Semiconductor Area 120 J2 Set in the L layer of the memory cell array MCA2 The multiple conductive layers 110 contained therein are located at the upper position, and are positioned above the memory cell array layer L. MCA3 It contains multiple conductive layers 110 located at the lower position.

[0221] [Virtual Conductive Layer 110DM] One or more virtual conductive layers 110DM may be provided between the first gate electrode 110_1 and the source-side select gate line SGS. Alternatively, one or more virtual conductive layers 110DM may be provided between the third gate electrode 110_3 and the drain-side select gate line SGD.

[0222] Additionally, it is set in the storage cell array layer L MCA1The region closest to the semiconductor in the multiple conductive layers 110 J One or more conductive layers 110 can also be configured as virtual conductive layers 110DM.

[0223] Additionally, it is set in the storage cell array layer L MCA2 The region closest to the semiconductor in the multiple conductive layers 110 J One or more conductive layers 110 can also be configured as virtual conductive layers 110DM.

[0224] Additionally, it is set in the storage cell array layer L MCA2 The region closest to the semiconductor in the multiple conductive layers 110 J2 One or more conductive layers 110 can also be configured as virtual conductive layers 110DM.

[0225] Additionally, it is set in the storage cell array layer L MCA3 The region closest to the semiconductor in the multiple conductive layers 110 J2 One or more conductive layers 110 can also be configured as virtual conductive layers 110DM.

[0226] That is, the virtual conductive layer 110DM can also be disposed between the first gate electrode 110_1 and the second gate electrode 110_2. Alternatively, the virtual conductive layer 110DM can also be disposed between the second gate electrode 110_2 and the third gate electrode 110_3.

[0227] [Second Embodiment] Next, refer to Figure 25 and Figure 24 The semiconductor memory device of the second embodiment will be described. Figure 25 This is a flowchart used to explain the erasure operation in the second embodiment. Figure 24 This is a timing diagram used to illustrate the erasure operation of the second embodiment. Furthermore, in the following description, details regarding configurations and operations identical to those in the first embodiment are sometimes omitted.

[0228] The semiconductor memory device of this embodiment is configured in essentially the same manner as the semiconductor memory device of the first embodiment. However, the method of erasing the semiconductor memory device of the second embodiment differs from that of the first embodiment.

[0229] [Steps for erasing] First, use... Figure 24 The steps of the erasure operation in the second embodiment will be explained.

[0230] The same operation as the erasing operation of the first embodiment is performed in steps S101, S103, and S105 to S110. However, in the erasing operation of the second embodiment, step S102 is replaced with step S202.

[0231] In step S202, it is determined whether the cycle number n E is a specific number "2". In the case where the cycle number n E is not the specific number "2", step S103 is performed. In the case where the cycle number n E is the specific number "2", after step S109 is entered, step S103 is entered.

[0232] In addition, Figure 12 In the example of n Figure 24 = 1, step S104 Figure 25 is not performed. Therefore, In the example of n

[0233] = 1, the verifying operation is also performed in the cycle "1". Figure 25 [Erasing operation cycle] Next, each cycle of the erasing operation will be described with reference to

[0234] Figure 24 [Erasing operation: cycle "1"] A case where the cycle number n E is "1" will be described. The cycle "1" of the erasing operation is performed from time t201 to time t204 in

[0235] In the case where the cycle number n E is "1", in step S202 Figure 24 , step S103 is entered.

[0236] In step S103 Figure 24 , from time t201 to time t202, the same erasing operation (1) as the first embodiment is performed.

[0237] In step S106 Figure 24 , from time t203 to time t204, the same erasing verifying operation as the first embodiment is performed.

[0238] In step S107 Figure 25 , the result of the erasing verifying operation is determined. Hereinafter, a case where the determination is that the verifying has failed will be described. In addition, in step S108, the specific number N E is made greater than "1", and step S105 is entered.

[0239] In step S105, the cycle number n E is further incremented by 1, and the cycle number is made "2", and step S102 is entered.

[0240] [Erasing Action: Cycle "2"] Next, the case where the cycle number n E is "2" is explained. The cycle "2" of the erasing action is executed from the time point t204 to the time point t210 in the first embodiment. Figure 24

[0241] In the case where the cycle number n E is "2", the process proceeds to Step S109 in Step S202 Figure 24 .

[0242] In Step S109 Figure 24 , the same WLD programming action as in the first embodiment is executed from the time point t205 to the time point t206.

[0243] In Step S103 Figure 24 , the erasing action (2) is executed from the time point t207 to the time point t208. The erasing action (2) is basically executed in the same manner as the erasing action (2) in the first embodiment. However, the voltage V WLD2 is supplied to the dummy word line WLD instead of the voltage V WLD1 .

[0244] In Step S106 Figure 26 , the same erasing verifying action as in the first embodiment is executed from the time point t209 to the time point t210.

[0245] [Third Embodiment] Next, the configuration of the semiconductor storage device of the third embodiment is explained with reference to FIG. 17 and FIG. 18. Figure 27 Figure 26 is a flowchart for explaining the erasing action. Figure 27 is a timing chart for explaining the erasing action. In the following explanation, the same configuration and action as in the first embodiment are sometimes omitted. Figure 26

[0246] The semiconductor storage device of the present embodiment is basically configured in the same manner as the semiconductor storage device of the first embodiment. However, the method of the erasing action of the semiconductor storage device of the third embodiment is different from that of the first embodiment.

[0247] [Steps of Erasing Action] First, the steps of the erasing action of the third embodiment are explained with reference to FIG. 17. Figure 12

[0248] In Steps S101 and S103 to S110, the same action as in the erasing action of the first embodiment is executed. However, in the erasing action of the third embodiment, Step S302 is executed instead of Step S102 Figure 27 .​​​​

[0249] In step S302, the number of iterations n is determined. E Is it a specific number "4"? In the loop count n E If the number of iterations is not a specific "4", proceed to step S103. The loop count is n. E If the number is "4" for a specific number of times, proceed to step S109 and then to step S103.

[0250] [Erase Action Loop] Next, refer to Figure 13 The various cycles of the erasure operation will be explained. In cycle "1" and cycle "2" of the erasure operation in the third embodiment, the same operations as in cycle "1" and cycle "2" of the first embodiment are performed. Figure 13 The same action.

[0251] In the erase operation loop "3" of the third embodiment, the same operation as the erase operation loop "2" is performed. However, in the erase operation (3)' of the erase operation loop "3" of the third embodiment, a third erase voltage V is supplied to the source line SL. ERA3 The voltage V supplied to the virtual word line WLD WLD1 .

[0252] In the erase operation loop "4" of the third embodiment, the erase operation loop "3" of the first embodiment is executed. Figure 12 The same operation. However, in the erase operation (4)' of the erase operation cycle "4" in the third embodiment, the source line SL is supplied with the same erase voltage as the third erase voltage V. ERA3 Same as, or greater than, the third erase voltage V ERA3 The fourth erase voltage V ERA4 .

[0253] [Other] In the first embodiment, such as Figure 24 Step S102 is shown, indicating n E This is an example of executing the WLD programming action in step S109 when the value is "3". However, when entering loop "4", the same WLD programming action as in loop "3" can be executed in the subsequent loops, or the action can be omitted.

[0254] In addition, in the second embodiment, such as Figure 26 Step S202 is shown, indicating n E This is an example of executing the WLD programming action in step S109 when the value is "2". However, when entering loop "3", the same WLD programming action as in loop "3" can be executed in the subsequent loops, or the action can be omitted.

[0255] In addition, in the third embodiment, such asFigure 14 Step S302 is shown, indicating n E This is an example of executing the WLD programming action in step S109 when the value is "4". However, when entering loop "5", the same WLD programming action as in loop "4" can be executed in the loop after loop "5", or the action can be omitted.

[0256] In addition, the erasure operation (n) of embodiments 1 to 3 is performed. E When, such as Figure 17 and ​ As shown, the supply voltage V for the gate line SGD selected on the drain side is illustrated. SG' An example of a drain-side selector transistor STD being in the off state. However, in the erase operation (n E In this process, the gate line SGD can also be selected to supply voltage V to the drain side. SG” GIDL is generated in the drain-side select transistor STD. Additionally, a voltage V can be supplied to the source-side select gate line SGS at this time. SG” It can also supply voltage V SG' Furthermore, in the erasure verification operation of embodiments 1 to 3, the erasure verification voltage V VFYEr It can also be the voltage V of the first voltage. SS1 Larger voltage, not voltage V than the first voltage. SS1 Low voltage.

[0257] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A semiconductor memory device, characterized in that... Possessing: a substrate; a plurality of gate electrodes arranged in a first direction intersecting a surface of the substrate; a semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a charge accumulation layer provided between the plurality of gate electrodes and the semiconductor layer; a conductive layer connected to an end portion of the semiconductor layer in the first direction; and a control circuit electrically connected to the plurality of gate electrodes and the conductive layer; the plurality of gate electrodes include: a plurality of first gate electrodes; a plurality of second gate electrodes farther from the conductive layer than the plurality of first gate electrodes; and a third gate electrode provided between the plurality of first gate electrodes and the plurality of second gate electrodes; and the control circuit is configured to be capable of performing an erasing operation; the erasing operation includes: at least one first operation of supplying a first voltage to the conductive layer; a second operation performed after at least one of the first operation, of supplying a second voltage to the third gate electrode; and at least one third operation performed after the second operation, of supplying a third voltage equal to or greater than the first voltage to the conductive layer; wherein the third gate electrode is a dummy electrode.

2. The semiconductor storage device according to claim 1, wherein: the control circuit is in the first operation, the plurality of first gate electrodes and the plurality of second gate electrodes are supplied with a fourth voltage smaller than the first voltage, and the third gate electrode is supplied with a fifth voltage greater than the fourth voltage and smaller than the first voltage, in the second operation, the plurality of first gate electrodes and the plurality of second gate electrodes are supplied with a sixth voltage greater than the fourth voltage and smaller than the second voltage, in the third operation, the plurality of first gate electrodes and the plurality of second gate electrodes are supplied with the fourth voltage, and the third gate electrode is supplied with a seventh voltage greater than the fourth voltage and smaller than the fifth voltage. Possessing:

3. A semiconductor memory device, characterized by a substrate; a plurality of gate electrodes arranged in a first direction intersecting a surface of the substrate; a semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a charge accumulation layer provided between the plurality of gate electrodes and the semiconductor layer; a conductive layer connected to an end portion of the semiconductor layer in the first direction; and a control circuit electrically connected to the plurality of gate electrodes and the conductive layer; the plurality of gate electrodes include: a plurality of first gate electrodes; a plurality of second gate electrodes farther from the conductive layer than the plurality of first gate electrodes; and a third gate electrode provided between the plurality of first gate electrodes and the plurality of second gate electrodes; and the control circuit is configured to be capable of performing an erasing operation; the erasing operation includes: a first operation of supplying a first voltage to the plurality of first gate electrodes and the plurality of second gate electrodes, and supplying a second voltage greater than the first voltage to the third gate electrode; a second operation of supplying a third voltage greater than the first voltage to the plurality of first gate electrodes and the plurality of second gate electrodes, and supplying a fourth voltage greater than the third voltage to the third gate electrode. ​ ​ and In a third operation, the first voltage is supplied to the plurality of first gate electrodes and the plurality of second gate electrodes, and a fifth voltage larger than the first voltage and smaller than the second voltage is supplied to the third gate electrode.

4. The semiconductor memory device according to claim 3, wherein: The third gate electrode is a dummy electrode.

5. The semiconductor storage device according to any one of claims 1 to 3, characterized by: The semiconductor storage device includes a first terminal capable of outputting a ready signal or a busy signal of the semiconductor storage device and connected to the control circuit, The output of the first terminal changes from the ready signal to the busy signal before the first operation, The output of the first terminal maintains the busy signal from the first operation to the end of the third operation, The output of the first terminal changes from the busy signal to the ready signal after the end of the third operation.

6. The semiconductor storage device according to any one of claims 1 to 3, wherein: The semiconductor layer includes: a first region extending in the first direction and facing the plurality of first gate electrodes; and a second region extending in the first direction and facing the plurality of second gate electrodes; when an end portion of the first region on the substrate side in the first direction is set as a first end portion, when an end portion of the first region on the opposite side of the substrate in the first direction is set as a second end portion, when an end portion of the second region on the substrate side in the first direction is set as a third end portion, when an end portion of the second region on the opposite side of the substrate in the first direction is set as a fourth end portion, when a width of the first end portion in a second direction intersecting the first direction is set as a first width, when a width of the second end portion in the second direction is set as a second width, when a width of the third end portion in the second direction is set as a third width, when a width of the fourth end portion in the second direction is set as a fourth width, the second width is different from the first width, the fourth width is different from the third width.

7. The semiconductor storage device according to claim 6, wherein: the semiconductor layer includes a third region connected between the first region and the second region, when a width of the third region in the second direction is set as a fifth width, the fifth width is larger than the second width and the third width.

8. The semiconductor storage device according to claim 6, wherein: the third gate electrode is provided between the plurality of first gate electrodes and the second end portion.

9. The semiconductor storage device according to claim 6, wherein: the third gate electrode is provided between the plurality of second gate electrodes and the third end portion.

10. A semiconductor memory device, characterized by including: a memory string extending in a first direction and including a selection transistor, a dummy cell, and a plurality of memory cells; a selection gate electrode connected to the selection transistor; a dummy gate electrode connected to the dummy cell; a plurality of gate electrodes connected to the plurality of memory cells; a conductive layer connected to one end portion of the memory string; and ​ A control circuit connected to the selection gate electrode, the plurality of gate electrodes, the dummy gate electrode, and the conductive layer, and capable of performing an erasing operation of the plurality of memory cells; and The erasing operation includes: A first operation of supplying a first voltage to the plurality of gate electrodes and supplying a second voltage greater than the first voltage to the dummy gate electrode, A second operation performed after the first operation of supplying a third voltage greater than the first voltage to the plurality of gate electrodes and supplying a fourth voltage greater than the third voltage to the dummy gate electrode; and A third operation performed after the second operation of supplying a fifth voltage less than the second voltage to the plurality of gate electrodes and supplying a sixth voltage greater than the fifth voltage and less than the second voltage to the dummy gate electrode. In the first operation, 11. The semiconductor memory device according to claim 10, wherein: a seventh voltage greater than the second voltage is supplied to the conductive layer, In the third operation, an eighth voltage equal to or greater than the seventh voltage is supplied to the conductive layer. The control circuit does not record user data in the dummy cell.

12. The semiconductor memory device according to claim 10, wherein: A fourth operation of supplying a ninth voltage lower than the third voltage to the plurality of gate electrodes and supplying a tenth voltage lower than the fourth voltage and higher than the ninth voltage to the dummy gate electrode is performed after the first operation and before the second operation.

13. The semiconductor storage device according to any one of claims 10 to 12, wherein: ​

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