Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, the substrate having a gate structure formed thereon, source / drain doped layers formed in the substrate on both sides of the gate structure, a sidewall spacer formed on sidewalls of the gate structure, an etching stop layer formed on sidewalls of the sidewall spacer, a first interlayer dielectric layer formed on the substrate exposed by the gate structure, the first interlayer dielectric layer covering sidewalls of the etching stop layer; forming a first protective layer on top of the gate structure, the sidewall spacer and the etching stop layer; after forming the first protective layer, forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the first protective layer; after forming the second interlayer dielectric layer, forming a first opening through the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layers; forming a source / drain plug in the first opening. The etching stop layer is beneficial to ensure the covering ability of the sidewall spacer, so that the risk of the sidewall spacer being damaged due to being exposed is also reduced, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate, the gate structure including a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; source / drain doped layers located in the substrate on both sides of the gate structure; sidewalls covering the sidewalls of the gate structure; an etch stop layer located on the sidewalls of the sidewalls; a protective layer located on top of the gate structure, the sidewalls, and the etch stop layer; an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped layers, the interlayer dielectric layer also covering the top of the protective layer; a source / drain plug penetrating the interlayer dielectric layer located on top of the source / drain doped layers, the bottom of the source / drain plug being electrically connected to the top of the source / drain doped layers; and a gate plug penetrating the interlayer dielectric layer and the protective layer on top of the gate structure, the bottom of the gate plug being electrically connected to the top of the gate structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, sidewalls are formed on the sidewalls of the gate structure, etch stop layers are formed on the sidewalls of the sidewalls, a first interlayer dielectric layer is formed on the exposed portion of the substrate of the gate structure, the first interlayer dielectric layer covering the sidewalls of the etch stop layer; forming a first protective layer on top of the gate structure, sidewalls and etch stop layer; after forming the first protective layer, forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the top of the first protective layer; after forming the second interlayer dielectric layer, forming a first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source and drain doped layer; and forming a source and drain plug in the first opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. A first protective layer is formed on top of a gate structure, sidewalls, and an etch stop layer. Since the first protective layer can protect the top of the sidewalls and the etch stop layer, the probability of damage to the top of the etch stop layer caused by the etching process during the formation of a first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layer is reduced. This helps ensure the integrity of the etch stop layer and, correspondingly, helps ensure the coverage capability of the etch stop layer on the sidewalls. Under the joint protection of the etch stop layer and the protective layer, the risk of damage to the sidewalls due to exposure is also reduced, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 5 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0013] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 A substrate is provided, the substrate including a substrate 10 and fins 12 protruding from the substrate 10. A gate structure 19 is formed on the substrate. Source and drain doped layers 18 are formed in the substrate on both sides of the gate structure 19. A gate capping layer 17 is formed on the top of the gate structure 19. Sidewalls 16 are formed on the sidewalls of the gate structure 19 and the gate capping layer 17. An etch stop layer 15 is formed on the sidewalls of the sidewalls 16. The etch stop layer 15 covers the exposed surfaces of the sidewalls 16 of the gate structure 19 and the gate capping layer 17. A first interlayer dielectric layer 13 is formed on the exposed substrate of the gate structure 19. The first interlayer dielectric layer 13 covers the sidewalls of the etch stop layer 15, and the top of the first interlayer dielectric layer 13 is flush with the top of the etch stop layer 15.

[0015] refer to Figure 2 A second interlayer dielectric layer 20 is formed on top of the first interlayer dielectric layer 13, the etch stop layer 15, the sidewall 16 and the gate cap layer 17.

[0016] refer to Figure 3 An opening 26 is formed on the top of the source / drain doped layer 18, penetrating the first interlayer dielectric layer 13 and the second interlayer dielectric layer 20, and the opening 26 exposes the top and sidewalls of the etch stop layer 15.

[0017] Studies have revealed that during the formation of the opening 26 penetrating the first interlayer dielectric layer 13 and the second interlayer dielectric layer 20 on the top of the source / drain doped layer 18, the opening 26 is susceptible to overlay shift or dimensional deviation during formation. This can easily lead to the opening 26 exposing the top of the etch stop layer 15, resulting in the etching process used to form the opening 26 potentially damaging the exposed top of the etch stop layer 15 (e.g., ...). Figure 3 As shown in the dashed circle, the morphological integrity of the etch stop layer 15 is compromised. Consequently, the coverage of the sidewall 16 by the etch stop layer 15 decreases, which greatly increases the probability that the sidewall 16 will be exposed. This increases the risk of damage to the sidewall 16 due to exposure, thereby reducing the performance of the semiconductor structure.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a gate structure on the substrate, forming source / drain doped layers in the substrate on both sides of the gate structure, forming sidewalls on the sidewalls of the gate structure, forming etch stop layers on the sidewalls of the sidewalls, forming a first interlayer dielectric layer on the exposed portion of the substrate of the gate structure, the first interlayer dielectric layer covering the sidewalls of the etch stop layer; forming a first protective layer on top of the gate structure, sidewalls, and etch stop layer; after forming the first protective layer, forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the top of the first protective layer; after forming the second interlayer dielectric layer, forming a first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layer; and forming source / drain plugs in the first opening.

[0019] In the formation method provided by this invention, a first protective layer is formed on top of the gate structure, sidewalls, and etch stop layer. Since the first protective layer protects the top of the sidewalls and the etch stop layer, the probability of damage to the top of the etch stop layer caused by the etching process during the formation of the first opening penetrating the second and first interlayer dielectric layers on top of the source / drain doped layers decreases. This helps ensure the integrity of the etch stop layer and, correspondingly, helps ensure the etch stop layer's coverage of the sidewalls. Under the joint protection of the etch stop layer and the protective layer, the risk of damage to the sidewalls due to exposure is also reduced, thereby improving the performance of the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0022] The semiconductor structure includes: a substrate; a gate structure 209 located on the substrate, the gate structure 209 including a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer; source / drain doped layers 208 located in the substrate on both sides of the gate structure 209; sidewalls 206 covering the sidewalls of the gate structure 209; an etch stop layer 205 located on the sidewalls of the sidewalls 206; a protective layer 228 located on top of the gate structure 209, sidewalls 206, and etch stop layer 205; and an interlayer dielectric layer 260. A source / drain doped layer 208 is located on the substrate on the side of the gate structure 209 and covers it. The interlayer dielectric layer 260 also covers the top of the protective layer 228. A source / drain plug 230 penetrates the interlayer dielectric layer 260 located on top of the source / drain doped layer 208, and the bottom of the source / drain plug 230 is electrically connected to the top of the source / drain doped layer 208. A gate plug 226 penetrates the interlayer dielectric layer 260 and the protective layer 228 on top of the gate structure 209, and the bottom of the gate plug 230 is electrically connected to the top of the gate structure 209.

[0023] The substrate is used to provide a process platform for subsequent process manufacturing.

[0024] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 200 and fins 202 protruding from the substrate 200. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0025] In this embodiment, the material of the fin 202 is the same as that of the substrate 200, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0026] In this embodiment, the semiconductor structure further includes an isolation layer 201 located on the substrate 200 exposed by the fin 202, the isolation layer 201 covering part of the sidewall of the fin 202.

[0027] When the device is in operation, the gate structure 209 is used to control the opening or closing of the conductive channel.

[0028] In this embodiment, the gate structure 209 is located on the substrate 200, and the gate structure 209 spans the fin 202 and covers part of the top and part of the sidewall of the fin 202.

[0029] In this embodiment, the gate structure 209 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0030] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0031] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0032] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0033] In this embodiment, the semiconductor structure further includes a gate cap layer 207, located on top of the gate structure 209.

[0034] The gate cap layer 207 is used to protect the top of the gate structure 209. In the semiconductor structure formation process, during the formation of the source-drain plug 230, it reduces the probability of damage to the top of the gate structure 209 and short circuit between the source-drain plug 230 and the gate structure 209.

[0035] The gate cap layer 207 is made of a material that has etching selectivity with the sidewall 206 and the second interlayer dielectric layer 217, which helps to ensure that the gate cap layer 207 can protect the top of the gate structure 209.

[0036] The gate cap layer 207 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate cap layer 207 is made of SiN.

[0037] The source and drain doped layers 208 are used as the source and drain regions of the transistor.

[0038] When forming an NMOS transistor, the source / drain doped layer 208 includes a stress layer doped with N-type ions. The stress layer is made of Si, SiC, or SiP. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer 208 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0039] The sidewall 206 is used to protect the sidewalls of the gate structure 209. The sidewall 206 can be a single-layer structure or a multilayer structure, and the material of the sidewall 206 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 206 is a single-layer structure, and the material of the sidewall 206 is silicon oxide.

[0040] In this embodiment, during the formation of the semiconductor structure, after removing a portion of the thickness of the gate structure 209, a gate cap layer 207 is formed in the space enclosed by the sidewall 206 and the remaining gate structure 209. Therefore, the sidewall 206 also covers the sidewall of the gate cap layer 207.

[0041] The etching stop layer 205 is used to protect the sidewalls of the sidewall layer 206. In the semiconductor structure formation process, during the formation of the source / drain plugs 230, it reduces the probability of the related etching process causing damage to the sidewalls of the sidewall layer 206.

[0042] The etching stop layer 205 is made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the etching stop layer 205 is made of silicon nitride.

[0043] The interlayer dielectric layer 260 is used to isolate adjacent devices and also to provide electrical isolation between the gate plugs 226 and between the source and drain plugs 230.

[0044] In this embodiment, the interlayer dielectric layer 260 includes: a first interlayer dielectric layer 203, located on the substrate on the side of the gate structure 209 and covering the source / drain doped layer 208, wherein the first interlayer dielectric layer 209 covers part of the sidewall of the etch stop layer 205 exposed by the protective layer 228; and a second interlayer dielectric layer 217, covering the top of the first interlayer dielectric layer 203 and the protective layer 228.

[0045] The first interlayer dielectric layer 203 is used to isolate adjacent devices and also to provide electrical isolation between the source and drain plugs 230.

[0046] In this embodiment, the first interlayer dielectric layer 209 covers part of the sidewall of the etch stop layer 205 exposed by the protective layer 228, so that a sacrificial layer can be formed on top of the first interlayer dielectric layer 209 during the formation of the semiconductor structure, and a protective layer can be formed on top of the gate structure, sidewall and etch stop layer exposed by the sacrificial layer using a selective deposition process.

[0047] The first interlayer dielectric layer 203 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the first interlayer dielectric layer 203 is made of silicon oxide.

[0048] The second interlayer dielectric layer 217 provides electrical isolation between the gate plugs 226 and between the source and drain plugs 230.

[0049] The material of the second interlayer dielectric layer 217 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the second interlayer dielectric layer 217 is silicon oxide.

[0050] The protective layer 228 protects the top of the sidewall 206 and the etch stop layer 205. During the formation of the source / drain plug 230 penetrating the interlayer dielectric layer 260 on the top of the source / drain doped layer 208, the probability of the etching process damaging the top of the etch stop layer 205 is reduced, which helps ensure the integrity of the morphology of the etch stop layer 205. Correspondingly, it helps ensure the coverage of the sidewall 206 by the etch stop layer 205. Under the joint protection of the etch stop layer and the protective layer, the risk of the sidewall 206 being damaged due to exposure is also reduced, thereby improving the performance of the semiconductor structure.

[0051] In this embodiment, the gate cap layer 207 is located on top of the gate structure 209, and the protective layer 228 is correspondingly located on top of the gate cap layer 207. To ensure that the depth of adjacent gate plugs 226 penetrating the interlayer dielectric layer 260 and the protective layer 228 is consistent, during the formation of the gate plugs 226, the etching stop position of the interlayer dielectric layer 260 is defined by the protective layer 228 on top of the gate structure 209, and then the etching of the gate cap layer 207 continues.

[0052] In this embodiment, the protective layer 228 also extends to cover part of the sidewall of the etching stop layer 205.

[0053] In the semiconductor fabrication process where the protective layer 228 extends to cover part of the sidewalls of the etch stop layer 205 and forms the source / drain plugs 230 on top of the source / drain doped layer 208, the protective layer 228 can achieve a self-alignment effect, reducing the probability of damage to the top and sidewalls of the etch stop layer 205. Consequently, it improves the morphological integrity of the etch stop layer 205, thereby reducing the risk of damage to the sidewalls 206 due to exposure, and thus improving the performance of the semiconductor structure.

[0054] It should be noted that the thickness of the protective layer 228 should not be too large or too small. If the thickness of the protective layer 228 is too large, it increases the difficulty of removing the protective layer 228 from the top of the gate structure 209 during the formation process of the semiconductor structure forming the gate plug 226 on top of the gate structure 209, affecting process efficiency. It also reduces the process window for forming the gate plug 226, further increasing the difficulty of forming the gate plug 226. Furthermore, when the protective layer 228 extends to cover part of the sidewall of the etch stop layer 205, an excessively large thickness of the protective layer 228 can easily lead to… This results in a smaller process window for forming the source / drain plug 230, thus affecting the performance of the semiconductor structure. If the protective layer 228 is too thin, its protective effect on the top of the etch stop layer 205 is reduced. In the semiconductor structure formation process of forming the source / drain plug 230 on top of the source / drain doped layer 208, this increases the probability of the etching process damaging the top of the etch stop layer 205. Consequently, it also increases the risk of damage to the sidewall 206 due to exposure, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the protective layer 228 is 3 to 4 nanometers.

[0055] It should also be noted that when the protective layer 228 extends to cover part of the sidewall of the etch stop layer 205, the height of the protective layer 228 covering the etch stop layer 205 should not be too small or too large. If the height of the protective layer 228 covering the etch stop layer 205 is too large, the size of the source / drain plug 230 formed on top of the source / drain doped layer 208 will not meet the process requirements, resulting in increased contact resistance between the source / drain plug 230 and the source / drain doped layer 208, thereby affecting the performance of the semiconductor structure. If the height of the protective layer 228 covering the etch stop layer 205 is too small, the protective effect of the protective layer 228 on the sidewall of the etch stop layer 205 will easily decrease, increasing the probability of damage to the sidewall 206, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the height of the protective layer 228 covering the etch stop layer 205 is 2 nanometers to 5 nanometers. For example, the height of the protective layer 228 covering the etch stop layer 205 is 3 nanometers or 4 nanometers.

[0056] In this embodiment, the material of the protective layer 228 includes one or more of TiO2 and HfO2.

[0057] By selecting one or more of TiO2 and HfO2, the protective layer 228 can be formed using a selective deposition process in the semiconductor structure formation process, making the material of the protective layer 228 compatible with the selective deposition process. Specifically, before forming the protective layer 228, the surface of the sacrificial layer (not shown) is passivated using H2 plasma, which modifies the surface of the sacrificial layer into dangling bonds (CH). As a result, during the formation of the protective layer 228, the sacrificial layer is less likely to react with the precursors used in the deposition process, thus increasing the difficulty of depositing the protective layer 228 on top of the passivated sacrificial layer.

[0058] Furthermore, the TiO and HfO2 materials have high hardness and are not easily reacted with the carbon and fluorine gases commonly used in etching. In the process of forming the source and drain plug 230 on the top of the source and drain doped layer 208, the rate at which the protective layer 228 is removed is lower than the rate at which the interlayer dielectric layer 260 is removed, so that the protective layer 228 can play a good protective role for the top of the sidewall 206 and the etch stop layer 205.

[0059] The source / drain plug 230 is used to realize the electrical connection between the source / drain doped layer 208 and external circuits or other interconnection structures.

[0060] In this embodiment, the source / drain plug 230 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the source / drain plug 230, thereby reducing power consumption. In other embodiments, the source / drain plug can also be made of conductive materials such as molybdenum or ruthenium.

[0061] Gate plug 226 is used to realize the electrical connection between gate structure 209 and external circuitry or other interconnection structures.

[0062] In this embodiment, during the semiconductor structure formation process, the source / drain plug 230 and the gate plug 226 are formed in the same step. Therefore, the material of the gate plug 226 is the same as that of the source / drain plug 230, which is tungsten. In other embodiments, the source / drain plug can also be made of conductive materials such as molybdenum or ruthenium.

[0063] In this embodiment, the gate plug 226 also penetrates the gate cap layer 207 located on top of the gate structure 209.

[0064] The gate plug 226 penetrates the gate cap layer 207 located on top of the gate structure 209, so that the gate plug 226 is electrically connected to the top of the gate structure 209, thereby meeting the electrical requirements of the gate plug 226.

[0065] Figures 5 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0066] refer to Figure 5 A substrate is provided, on which a gate structure 109 is formed. Active and drain doped layers 108 are formed in the substrate on both sides of the gate structure 109. Sidewalls 106 are formed on the sidewalls of the gate structure 109. Etch stop layers 105 are formed on the sidewalls of the sidewalls of the sidewalls 106. A first interlayer dielectric layer 103 is formed on the exposed part of the substrate of the gate structure 109. The first interlayer dielectric layer 103 covers the sidewalls of the etch stop layer 105.

[0067] The substrate is used to provide a process platform for subsequent process manufacturing.

[0068] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 102 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0069] In this embodiment, the material of the fin 102 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0070] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 102, forming an isolation layer 101 on the substrate 100 exposed by the fin 102, the isolation layer 101 covering part of the sidewall of the fin 102.

[0071] The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.

[0072] When the device is in operation, the gate structure 109 is used to control the opening or closing of the conductive channel.

[0073] In this embodiment, the gate structure 109 is located on the substrate 100, and the gate structure 109 spans the fin 102 and covers part of the top and part of the sidewall of the fin 102.

[0074] In this embodiment, the gate structure 109 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0075] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0076] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0077] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0078] The source and drain doped layers 108 are used as the source and drain regions of the transistor.

[0079] When forming an NMOS transistor, the source / drain doped layer 108 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer 108 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0080] The sidewall 106 is used to protect the sidewalls of the gate structure 109. The sidewall 106 can be a single-layer structure or a multilayer structure, and the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 is a single-layer structure, and the material of the sidewall 106 is silicon oxide.

[0081] The etching stop layer 105 is used to protect the sidewall of the sidewall 106 and reduce the probability that the etching process will damage the sidewall of the sidewall 106 during the subsequent formation of the first opening.

[0082] The etch stop layer 105 is made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the etch stop layer 105 is made of silicon nitride.

[0083] The first interlayer dielectric layer 103 serves to isolate adjacent devices and also occupies space for the subsequently formed source / drain plugs and second protective layer.

[0084] The first interlayer dielectric layer 103 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the first interlayer dielectric layer 103 is made of silicon oxide.

[0085] In this embodiment, during the step of providing the substrate, a gate cap layer 107 is also formed on the top of the gate structure 109.

[0086] The gate cap layer 107 is used to protect the top of the gate structure 109, thereby reducing the probability of damage to the gate structure 109 and short circuit between the source / drain plug and the gate structure 109 during the subsequent formation of the source / drain plug.

[0087] The gate cap layer 107 is made of a material that is etch-selective with the sidewall 106 and the subsequently formed second interlayer dielectric layer, which helps to ensure that the gate cap layer 107 can protect the top of the gate structure 109.

[0088] The gate cap layer 107 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate cap layer 107 is made of SiN.

[0089] refer to Figure 6 A portion of the thickness of the first interlayer dielectric layer 103 is removed to form a groove 110 formed by the sidewalls of the etching stop layer 105 and the top of the remaining first interlayer dielectric layer 103.

[0090] The groove 110 provides space for the subsequent formation of the sacrificial layer and the protective layer.

[0091] In this embodiment, a portion of the thickness of the first interlayer dielectric layer 103 is etched back, thereby removing a portion of the thickness of the first interlayer dielectric layer 103.

[0092] Specifically, the etching processes used include dry etching.

[0093] The dry etching process includes anisotropic dry etching, which has the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate, which can remove part of the thickness of the first interlayer dielectric layer 103 while ensuring the morphological quality of the sidewalls of the groove 110.

[0094] It should be noted that the depth of the groove 110 should not be too large or too small. If the depth of the groove 110 is too large, the thickness of the sacrificial layer subsequently formed in the groove 110 will also be too large. Since a second protective layer is subsequently formed on the sidewall of the groove 110, the process window for removing the sacrificial layer becomes smaller, increasing the difficulty of removing the sacrificial layer and thus affecting the performance of the semiconductor structure. Moreover, it is also easy to cause unnecessary over-etching, resulting in wasted process costs. If the depth of the groove 110 is too small, after the sacrificial layer that meets the process size requirements is formed in the groove 110, the space reserved for the second protective layer is too small, making the size requirements of the second protective layer not meet the process requirements, thus affecting the self-alignment function of the second protective layer in the process of forming the first opening. Therefore, in this embodiment, the depth of the groove 110 is 10 nanometers to 20 nanometers.

[0095] refer to Figures 7 to 8 A sacrificial layer 112 is formed in the groove 110.

[0096] Specifically, a sacrificial layer 112 is formed in the groove, exposing the top of the etch stop layer 105, sidewall 106, and gate cap layer 107. This facilitates the subsequent formation of a first protective layer on top of the etch stop layer 105, sidewall 106, and gate cap layer 107. Furthermore, in the subsequent deposition process for forming the first protective layer, by selecting a material with poor deposition performance on top of the sacrificial layer 112, the probability of forming the first protective layer on top of the sacrificial layer 112 is reduced. This eliminates the need for the process step of removing the first protective layer formed on top of the sacrificial layer 112, thereby simplifying the process and reducing costs.

[0097] In this embodiment, the top of the sacrificial layer 112 is lower than the top of the etch stop layer 105, and the sacrificial layer 112 exposes part of the sidewall of the etch stop layer 105.

[0098] The sacrificial layer 112 exposes a portion of the sidewall of the etch stop layer 105, facilitating the subsequent formation of a second protective layer on the exposed sidewall of the etch stop layer 105. As a result, during the subsequent formation of the first opening on the top of the source / drain doped layer 108, the second protective layer can achieve a self-alignment effect, reducing the probability of damage to the top of the gate structure and sidewall caused by the etching process related to the formation of the first opening, thereby improving the performance of the semiconductor structure.

[0099] It should be noted that the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 should not be too small or too large. If the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 is too large, it will easily lead to an excessively high height of the second protective layer subsequently formed on the sidewall of the etch stop layer 105. Consequently, the size of the source / drain plug subsequently formed on the top of the source / drain doped layer 108 will not meet the process requirements, resulting in increased contact resistance between the source / drain plug and the source / drain doped layer 108, thus affecting the performance of the semiconductor structure. If the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 is too small, it will easily lead to an excessively low height of the second protective layer subsequently formed on the sidewall of the etch stop layer 105. Consequently, the protective effect of the second protective layer on the sidewall of the etch stop layer 105 will decrease, increasing the probability of damage to the sidewall 106. At the same time, during the subsequent formation of the first opening on the top of the source / drain doped layer 108, the etch stop function of the second protective layer will also be affected, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 is 10 nanometers to 20 nanometers.

[0100] In this embodiment, the step of forming the sacrificial layer 112 in the groove 110 includes: as follows Figure 7 As shown, a sacrificial material layer 111 is formed in the groove 110, and the sacrificial material layer 111 also covers the top of the gate structure 109, the sidewall 106, and the etch stop layer 105; as Figure 8 As shown, the sacrificial material layer 111 on top of the gate structure 109, sidewall 106 and etch stop layer 105, as well as a portion of the thickness of the sacrificial material layer 111 in the groove 110, are removed. The remaining sacrificial material layer 111 in the groove 110 serves as the sacrificial layer 112, which exposes a portion of the sidewall of the etch stop layer 105.

[0101] In other embodiments, depending on process requirements, the top of the sacrificial layer may be flush with the top of the etch stop layer, so that the first protective layer is formed only on top of the gate structure, sidewalls and etch stop layer.

[0102] In this embodiment, in the step of forming the sacrificial layer 112 in the groove 110, the material of the sacrificial layer 112 includes one or both of amorphous carbon and spin-coated carbon.

[0103] The amorphous carbon and spin-coated carbon materials have the characteristic of low material hardness, which is beneficial for the subsequent removal of the sacrificial layer 112 by ashing or wet etching processes, thus reducing the process difficulty of removing the sacrificial layer 112.

[0104] Simultaneously, before forming the first protective layer, H2 plasma is used to passivate the surface of the sacrificial layer 112, modifying its surface into dangling bonds (CH). This makes it difficult for the sacrificial layer 112 to react with the precursors used in the deposition process during the formation of the first protective layer, increasing the difficulty of depositing the first protective layer on top of the passivated sacrificial layer 112. Therefore, the amorphous carbon and spin-coated carbon materials have the characteristic of being difficult to deposit. During the subsequent formation of the first protective layer on top of the gate structure 109, sidewall 106, and etch stop layer 105, the material forming the first protective layer is less likely to deposit on top of the sacrificial layer 112, thereby reducing the number of process steps required to remove the top of the sacrificial layer 112 and lowering process costs.

[0105] In this embodiment, the process of forming the sacrificial material layer 111 in the groove 110 includes a chemical vapor deposition process.

[0106] The chemical vapor deposition has the characteristics of fast deposition rate and good filling effect. The sacrificial layer 112 formed in the groove 110 can be closely attached to the sidewall of the etch stop layer 105, so that a second protective layer is formed only on the sidewall of the etch stop layer 105 exposed by the sacrificial layer 112.

[0107] In this embodiment, a portion of the sacrificial material layer 111 is etched back, thereby removing the sacrificial material layer 111 on top of the gate structure 109, sidewall 106, and etch stop layer 105, as well as a portion of the sacrificial material layer 111 in the groove 110.

[0108] Specifically, the etching processes used include dry etching.

[0109] Since the gate structure 109, sidewall 106, and etch stop layer 105 have a high etch selectivity with the sacrificial material layer 111, the dry etching process has anisotropic dry etching characteristics. In the process of removing the sacrificial material layer 111 on the top of the gate structure 109, sidewall 106, and etch stop layer 105, as well as a portion of the thickness of the sacrificial material layer 111 in the groove 110, the use of the dry etching process can reduce damage to other films in the semiconductor structure.

[0110] Moreover, the dry etching process has the characteristics of anisotropic etching, which can achieve vertical etching. This reduces the thickness of the sacrificial material layer 111 and improves the flatness and thickness uniformity of the top surface of the sacrificial layer 112, thereby improving the uniformity of the height of the subsequent second protective layer covering the etch stop layer 105.

[0111] refer to Figure 9 A first protective layer 115 is formed on top of the gate structure 109, the sidewall 106 and the etch stop layer 105.

[0112] It should be noted that a first protective layer 115 is formed on top of the gate structure 109, sidewall 106, and etch stop layer 105. Since the first protective layer 115 can protect the top of the sidewall 106 and the etch stop layer 105, the probability of the etching process damaging the top of the etch stop layer 105 is reduced during the subsequent formation of the first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layer 108. This helps to ensure the integrity of the etch stop layer 105, and correspondingly, it helps to ensure the coverage of the sidewall 106 by the etch stop layer 105, thus reducing the risk of the sidewall 106 being damaged due to exposure, thereby improving the performance of the semiconductor structure.

[0113] In this embodiment, during the step of forming a first protective layer 115 on top of the gate structure 109, sidewall 106 and etch stop layer 105, the first protective layer 115 also covers the top of the gate cap layer 107.

[0114] Specifically, in the subsequent process of forming the second opening on the top of the gate structure 109, in order to ensure that the etching depth of adjacent second openings is consistent, the first protective layer 115 on the top of the gate cap layer 107 is first used as the etching stop position, and then the gate cap layer 107 is etched simultaneously.

[0115] In this embodiment, the step of forming the first protective layer 115 includes: forming the first protective layer 115 on top of the gate structure 109, sidewall 106 and etch stop layer 105 exposed on the sacrificial layer 112 using an area-selective-deposition (ASD) process.

[0116] In this embodiment, in the selective deposition process, the deposition difficulty of the first protective layer 115 on the surface of the sacrificial layer 112 is greater than the deposition difficulty on the surfaces of the gate structure 109, sidewall 106 and etch stop layer 105, thereby enabling the selective formation of the first protective layer 115 on the top of the gate structure 109, sidewall 106 and etch stop layer 105 exposed on the sacrificial layer 112.

[0117] Specifically, H2 plasma is used to passivate the surface of the sacrificial layer 112. After passivation, a first protective layer 115 is selectively formed on top of the gate structure 109, sidewall 106 and etch stop layer 105 exposed on the sacrificial layer 112.

[0118] Before forming the first protective layer 115, the surface of the sacrificial layer 112 is passivated using H2 plasma, which modifies the surface of the sacrificial layer 112 into dangling bonds (CH). As a result, during the formation of the first protective layer 115, the sacrificial layer 112 is less likely to react with the precursors used in the deposition process, which increases the difficulty of depositing the first protective layer 115 on top of the passivated sacrificial layer 112.

[0119] Specifically, the selective deposition process has features such as deposition flexibility, and its deposition rate varies on different materials to meet the required process requirements. During the process of forming the first protective layer 115 on the top of the gate structure 109, sidewall 106 and etch stop layer 105 exposed on the sacrificial layer 112 using the selective deposition process, the deposition rate of the first protective layer 115 on the surfaces of the gate structure 109, sidewall 106 and etch stop layer 105 is much greater than the deposition rate on the surface of the sacrificial layer 112, so that a small amount of the first protective layer 115 is deposited on the surface of the sacrificial layer 112. At the same time, in the subsequent cleaning process, the small amount of the first protective layer 115 formed on the surface of the sacrificial layer 112 will be completely removed.

[0120] Correspondingly, by using a selective deposition process, the first protective layer 115 can be formed directly at the target location without patterning (e.g., etching), which helps to reduce the probability that the process of forming the first protective layer 115 will damage the gate structure 109, sidewall 106 and etch stop layer 105.

[0121] In this embodiment, the top of the sacrificial layer 112 is lower than the top of the etch stop layer 105, and the sacrificial layer 112 exposes part of the sidewall of the etch stop layer 105. Therefore, in the step of forming a first protective layer 115 on the top of the gate structure 109, sidewall 106 and etch stop layer 105 exposed by the sacrificial layer 112 using a selective deposition process, the material forming the first protective layer 115 is also selectively deposited on the sidewall of the etch stop layer 105 exposed by the sacrificial layer 112, forming a second protective layer 116 on the sidewall of the etch stop layer 105 exposed by the sacrificial layer 112. The top of the second protective layer 116 is flush with the top of the first protective layer 115, and the second protective layer 116 and the first protective layer 115 constitute a protective layer 128.

[0122] By forming a second protective layer 116 on the sidewall of the etch stop layer 105 exposed on the sacrificial layer 112, the second protective layer 116 can achieve a self-aligning effect during the subsequent formation of the first opening on the top of the source / drain doped layer 108. This reduces the probability that the etching process forming the first opening will damage the top and sidewall of the etch stop layer 105, thereby improving the morphological integrity of the etch stop layer 105. Consequently, the risk of the sidewall 106 being damaged due to exposure is reduced, thereby improving the performance of the semiconductor structure.

[0123] It should be noted that the thickness of the first protective layer 115 should not be too large or too small. If the thickness of the first protective layer 115 is too large, the process of removing the first protective layer 115 during the subsequent formation of the second opening on the top of the gate structure 109 will increase the difficulty of removing the first protective layer 115, affecting the process efficiency. At the same time, it will also make the process window for removing the sacrificial layer 112 smaller, increasing the process difficulty of removing the sacrificial layer 112, thereby affecting the performance of the semiconductor structure. If the thickness of the first protective layer 115 is too small, it will easily reduce the protective effect of the first protective layer 115 on the top of the sidewall 106 and the etch stop layer 105. During the subsequent formation of the first opening on the top of the source / drain doped layer 108, the probability of the etching process damaging the top of the etch stop layer 105 will increase. Correspondingly, the risk of the sidewall 106 being damaged due to exposure will also increase, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first protective layer 115 is 2 nanometers to 5 nanometers.

[0124] In this embodiment, the material of the first protective layer 115 includes one or more of TiO2 and HfO2.

[0125] By selecting one or more of TiO2 and HfO2, the first protective layer 115 can be formed using a selective deposition process, making the material of the first protective layer 115 compatible with the selective deposition process. Simultaneously, the high hardness of TiO2 and HfO2 means that during the subsequent formation of the first opening on top of the source / drain doped layer 108, the removal rate of the first protective layer 115 is lower than the removal rate of the subsequently formed second interlayer dielectric layer. This allows the first protective layer 115 to effectively protect the top of the sidewall 106 and the etch stop layer 105.

[0126] It should be noted that in this embodiment, the groove is formed by etching back the first interlayer dielectric layer 103, the sacrificial layer 112 is formed by etching back the sacrificial material layer 111, and the first protective layer 115 is formed by selective deposition. That is to say, the steps of etching back the first interlayer dielectric layer 103, etching back the sacrificial material layer 111, and forming the first protective layer 115 do not require the use of an additional photomask. Therefore, the formation method described in this embodiment does not add an additional photomask, which helps to reduce the process cost.

[0127] refer to Figure 10 Remove the sacrificial layer 112.

[0128] The sacrificial layer 112 is removed to provide space for the subsequent formation of a second interlayer dielectric layer covering the top of the first interlayer dielectric layer 103 and the first protective layer 115.

[0129] Meanwhile, since the sacrificial layer 112 material itself has insufficient mechanical strength and is not suitable as a material for the dielectric layer, it is necessary to remove the sacrificial layer 112.

[0130] In this embodiment, the process for removing the sacrificial layer 112 includes a wet etching process.

[0131] The wet etching process is characterized by isotropic etching, with features such as strong etching target, high etching efficiency, and strong lateral etching capability. It can reduce damage to the first interlayer dielectric layer 103 at the bottom of the groove 110 and the etching stop layer 105 on the sidewall of the groove 110 during the process of removing the sacrificial layer 112 on the sidewall of the groove 110 in the lateral direction.

[0132] In other embodiments, an ashing process may also be used to remove the sacrificial layer.

[0133] refer to Figure 11 After the first protective layer 115 is formed, a second interlayer dielectric layer 117 is formed covering the top of the first interlayer dielectric layer 103 and the first protective layer 115.

[0134] The second interlayer dielectric layer 117 provides the process basis for the subsequent formation of gate plugs and source-drain plugs, and also provides electrical isolation for the subsequently formed gate plugs and source-drain plugs.

[0135] In this embodiment, the process for forming the second interlayer dielectric layer 117 includes chemical vapor deposition.

[0136] The material of the second interlayer dielectric layer 117 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the second interlayer dielectric layer 117 is silicon oxide.

[0137] refer to Figure 12 After the second interlayer dielectric layer 117 is formed, a first opening 120 is formed on the top of the source / drain doped layer 108, penetrating the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103.

[0138] The first opening 120 provides space for the subsequent formation of the source-drain plug.

[0139] In this embodiment, the step of forming a first opening 120 penetrating the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 on the top of the source / drain doped layer 108 includes: forming an initial first opening 125 penetrating the second interlayer dielectric layer 117 on the top of the source / drain doped layer 108; after forming the initial first opening 125, using the sidewall of the second protective layer 116 as the lateral etching stop position, forming an initial second opening 118 penetrating the first interlayer dielectric layer 103 and exposing the top of the source / drain doped layer 108 between adjacent second protective layers 116, wherein the initial second opening 125 and the initial first opening 118 constitute the first opening 120.

[0140] Specifically, the protective layer 128 and the second interlayer dielectric layer 117 have a large etching selectivity. During the formation of the first opening 120, the protective layer 128 is removed at a low rate, which increases the process window for forming the first opening 120 and reduces the process difficulty of forming the first opening 120.

[0141] It should be noted that the protective layer 128 and the first interlayer dielectric layer 103 also have a large etching selectivity, as described above, and will not be repeated here.

[0142] In this embodiment, the process of forming a first opening 120 penetrating the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 on the top of the source / drain doped layer 108 includes a dry etching process.

[0143] refer to Figure 13 A filling layer 119 is formed in the first opening 120.

[0144] By forming a filling layer 119 in the first opening 120, the damage to the top surface of the source / drain doped layer 108 exposed by the selected etching process during the subsequent formation of the second opening on the top of the gate structure 109 is reduced, thereby improving the performance of the semiconductor structure.

[0145] In this embodiment, the step of forming a filling layer 119 in the first opening 120 includes: forming a filling material layer (not shown) on the top of the second interlayer dielectric layer 117 and in the first opening 120; taking the top of the second interlayer dielectric layer 117 as the stop position, performing planarization processing on the filling material layer above the top of the second interlayer dielectric layer 117, and using the remaining filling material layer in the first opening 120 as the filling layer 119.

[0146] In this embodiment, the process of forming the filling layer 119 in the first opening 120 includes chemical vapor deposition. In other embodiments, the process of forming the filling layer in the first opening may also include one or both of atomic layer deposition and physical vapor deposition.

[0147] To facilitate the subsequent removal of the filling layer 119 formed in the first opening 120, an easily removable material needs to be selected as the material of the filling layer 119. Therefore, in this embodiment, the material of the filling layer 119 includes one or more of ODL (organic dielectric layer), spin-on carbon (SOC), and APF (Advanced Patterning Film).

[0148] refer to Figures 14 to 16 A second opening 123 is formed on the top of the gate structure 109, penetrating the second interlayer dielectric layer 117 and the first protective layer 115.

[0149] The second opening 123 provides space for the subsequent formation of the gate plug.

[0150] In this embodiment, the step of forming a second opening 123 penetrating the second interlayer dielectric layer 117 and the first protective layer 115 on the top of the gate structure 109 includes: as follows Figure 14 As shown, the second interlayer dielectric layer 117 on top of the gate structure 109 is etched until an initial third opening 121 is formed exposing the top surface of the first protective layer 115; as shown Figures 15 to 16 As shown, the first protective layer 115 and the gate cap layer 107 exposed by the initial third opening 121 are etched to form an initial fourth opening 122 that exposes the top of the gate structure 109. The initial third opening 121 and the initial fourth opening 122 constitute the second opening 123.

[0151] In this embodiment, in the step of forming a second opening 123 through the second interlayer dielectric layer 117 and the first protective layer 115 on the top of the gate structure 109, the second opening 123 penetrates the gate cap layer 107 located on the top of the gate structure 109.

[0152] The second opening 123 penetrates the gate cap layer 107 located on top of the gate structure 109, so that the gate plug subsequently formed in the second opening 123 can be electrically connected to the gate structure 109.

[0153] It should be noted that there is an etch selectivity between the sidewall 106 and the gate cap layer 107. Therefore, during the formation of the second opening 123, the sidewall 106 can play a self-aligning role, reducing the probability of damage to the top of the source and drain doped layers 108 on both sides of the gate structure 109.

[0154] In this embodiment, the process of forming a second opening 123 through the second interlayer dielectric layer 117 and the first protective layer 115 on the top of the gate structure 109 includes a dry etching process.

[0155] In this embodiment, after forming a first opening 120 penetrating the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 on the top of the source / drain doped layer 108, a second opening 123 penetrating the second interlayer dielectric layer 117 and the first protective layer 115 is formed on the top of the gate structure 109.

[0156] It should be noted that forming the first opening 120 first and then the second opening 123 eliminates the step of removing the top filling layer of the gate structure 109. Correspondingly, this reduces the probability of damage to the top of the gate structure 109, thereby improving the performance of the semiconductor structure. At the same time, by forming the first opening 120 and the second opening 123 in different steps, it is beneficial to reduce the impact caused by the small distance between the gate structure 109 and the source / drain doped layer 108, and also to reduce the impact of overlay accuracy deviation.

[0157] It should be noted that in this embodiment, after forming the second opening 123 and before forming the source / drain plug and the gate plug, the method further includes removing the filling layer 119 in the first opening 120.

[0158] In this embodiment, the process for removing the filler layer 119 includes a wet etching process.

[0159] refer to Figure 17 A source / drain plug 130 is formed in the first opening 120.

[0160] The source / drain plug 130 is used to realize the electrical connection between the source / drain doped layer 108 and external circuits or other interconnection structures.

[0161] In this embodiment, the step of forming a source / drain plug 130 in the first opening 120 includes: forming a conductive material layer (not shown) in the first opening 120, the conductive material layer also covering the top of the second interlayer dielectric layer 117; taking the top of the second interlayer dielectric layer 117 as the stop position, planarizing the conductive material layer above the top of the second interlayer dielectric layer 117, and the remaining conductive material layer in the first opening 120 serves as the source / drain plug 130.

[0162] In this embodiment, the process of planarizing the conductive material layer above the top of the second interlayer dielectric layer 117 includes a chemical mechanical polishing process.

[0163] In this embodiment, the source / drain plug 130 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the source / drain plug 130, thereby reducing power consumption. In other embodiments, the source / drain plug can also be made of conductive materials such as molybdenum or ruthenium.

[0164] In this embodiment, during the step of forming the source / drain plug 130 in the first opening 120, a gate plug 126 is also formed in the second opening 123.

[0165] The gate plug 126 is used to realize the electrical connection between the gate structure 109 and external circuitry or other interconnection structures.

[0166] Specifically, the source / drain plug 130 and the gate plug 126 are formed in the same step, reducing process steps and lowering process costs. In other embodiments, the source / drain plug may be formed first, followed by the gate plug, or vice versa.

[0167] In this embodiment, in the same step, a source / drain plug 130 is formed in the first opening 120, and a gate plug 126 is formed in the second opening 123. Therefore, the material of the gate plug 126 is the same as that of the source / drain plug 130, which is tungsten. In other embodiments, the source / drain plug can also be made of conductive materials such as molybdenum or ruthenium.

[0168] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: Base; A gate structure is located on the substrate, the gate structure including a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; Source and drain doped layers are located in the substrate on both sides of the gate structure; Sidewalls, covering the sidewalls of the gate structure; An etching stop layer is located on the sidewall of the sidewall; A one-step formed protective layer is located on top of the gate structure, sidewalls and etch stop layer, and extends to cover part of the sidewalls of the etch stop layer, and the protective layer is an integral structure; An interlayer dielectric layer is located on the substrate on the side of the gate structure and covers the source and drain doped layers. The interlayer dielectric layer also covers the top of the protective layer. A source / drain plug penetrates the interlayer dielectric layer located on top of the source / drain doped layer, and the bottom of the source / drain plug is electrically connected to the top of the source / drain doped layer. A gate plug extends through the interlayer dielectric layer and the protective layer at the top of the gate structure, and the bottom of the gate plug is electrically connected to the top of the gate structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes: a gate cap layer located on top of the gate structure; The protective layer is located on top of the gate cap layer; The gate plug also extends through the gate cap layer located on top of the gate structure.

3. The semiconductor structure of claim 1, wherein, The interlayer dielectric layer includes: a first interlayer dielectric layer located on the substrate on the side of the gate structure and covering the source and drain doped layers, wherein the first interlayer dielectric layer covers a portion of the sidewall of the etch stop layer exposed by the protective layer; The second interlayer dielectric layer covers the top of the first interlayer dielectric layer and the protective layer.

4. The semiconductor structure of claim 1, wherein, The thickness of the protective layer is 2 nanometers to 5 nanometers.

5. The semiconductor structure of claim 1, wherein, The material of the protective layer includes one or both of TiO2 and HfO2.

6. The semiconductor structure of claim 1, wherein, The sidewall material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

7. The semiconductor structure of claim 1, wherein, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

8. A method of forming a semiconductor structure, comprising: include: A substrate is provided, on which a gate structure is formed, and source and drain doped layers are formed in the substrate on both sides of the gate structure. Sidewalls are formed on the sidewalls of the gate structure, and etch stop layers are formed on the sidewalls of the sidewalls. A first interlayer dielectric layer is formed on the exposed substrate of the gate structure, and the first interlayer dielectric layer covers the sidewalls of the etch stop layer. A portion of the thickness of the first interlayer dielectric layer is removed to form a groove surrounded by the sidewalls of the etch stop layer and the top of the remaining first interlayer dielectric layer; A sacrificial layer is formed in the groove, the top of the sacrificial layer being lower than the top of the etch stop layer, and the sacrificial layer exposing a portion of the sidewall of the etch stop layer; In the same step, a first protective layer is formed on top of the gate structure, sidewalls and etch stop layer, and a second protective layer is formed on the sidewalls of the etch stop layer exposed on the sacrificial layer. The top of the second protective layer is flush with the top of the first protective layer, and the second protective layer and the first protective layer constitute a protective layer with an integral structure. After the protective layer is formed, a second interlayer dielectric layer is formed covering the first interlayer dielectric layer and the top of the first protective layer; After the second interlayer dielectric layer is formed, a first opening is formed on the top of the source / drain doped layer, penetrating the second interlayer dielectric layer and the first interlayer dielectric layer; A source / drain plug is formed in the first opening.

9. The method of forming a semiconductor structure of claim 8, wherein, Before forming the source / drain plug in the first opening, the method further includes: forming a second opening on top of the gate structure that penetrates the second interlayer dielectric layer and the first protective layer; In the step of forming a source / drain plug in the first opening, a gate plug is also formed in the second opening.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the first protective layer includes: forming the first protective layer on top of the gate structure, sidewalls and etch stop layer exposed on the sacrificial layer using a selective deposition process.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming a first protective layer on top of the gate structure, sidewalls and etch stop layer exposed by the sacrificial layer using a selective deposition process, the material of the first protective layer is also selectively deposited on the sidewalls of the etch stop layer exposed by the sacrificial layer.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming a sacrificial layer in the groove includes: forming a sacrificial material layer in the groove, the sacrificial material layer further covering the top of the gate structure, sidewalls and etch stop layer; The sacrificial material layer on top of the gate structure, sidewalls, and etch stop layer, as well as a portion of the sacrificial material layer in the groove, are removed. The remaining sacrificial material layer in the groove serves as the sacrificial layer, which exposes a portion of the sidewall of the etch stop layer.

13. The method of forming a semiconductor structure of claim 8, wherein, The step of forming a first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layer includes: forming an initial first opening penetrating the second interlayer dielectric layer on top of the source / drain doped layer; after forming the initial first opening, using the sidewall of the second protective layer as the lateral etching stop position, forming an initial second opening penetrating the first interlayer dielectric layer and exposing the top of the source / drain doped layer between adjacent second protective layers, wherein the initial second opening and the initial first opening constitute the first opening.

14. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, a gate cap layer is also formed on top of the gate structure; In the step of forming a first protective layer on top of the gate structure, sidewalls and etch stop layer, the first protective layer also covers the top of the gate cap layer; In the step of forming a second opening at the top of the gate structure that penetrates the second interlayer dielectric layer and the first protective layer, the second opening also penetrates the gate cap layer located at the top of the gate structure.

15. The method of forming a semiconductor structure of claim 9, wherein, After forming a first opening penetrating the second interlayer dielectric layer and the first interlayer dielectric layer on top of the source / drain doped layer, a second opening penetrating the second interlayer dielectric layer and the first protective layer is formed on top of the gate structure.

16. The method of forming a semiconductor structure of claim 9, wherein, After forming a first opening on top of the source / drain doped layer and before forming a second opening on top of the gate structure, the method further includes: forming a filling layer in the first opening; After forming the second opening and before forming the source / drain plug and the gate plug, the method further includes: removing the filler layer in the first opening.

17. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming a sacrificial layer in the groove, the material of the sacrificial layer includes one or both of amorphous carbon and spin-coated carbon.

18. The method of forming a semiconductor structure of claim 8, wherein, After the protective layer is formed, but before the second interlayer dielectric layer is formed, the process further includes: removing the sacrificial layer.

19. The method of forming a semiconductor structure of claim 8, wherein, The material of the first protective layer includes one or more of TiO2 and HfO2.

20. The method of forming a semiconductor structure of claim 8, wherein, The sidewall material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

Images