Enhanced p-channel gallium nitride power device, preparation method thereof, and electronic device

Abstract

The present invention provides an enhanced p-channel gallium nitride power device and a manufacturing method thereof. A p-channel enhancement-mode gallium nitride transistor can be achieved without performing gate recess etching on p-GaN, avoiding the negative impacts on the p-channel enhancement-mode device caused by the reduction of channel mobility due to the gate etching method and the high-density trap states formed on the etched surface, thereby effectively improving the performance of the enhanced p-channel gallium nitride transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to an enhancement-mode p-channel gallium nitride power device, a preparation method thereof, and an electronic device. Background Art

[0002] Gallium nitride high electron mobility transistors (AlGaN / GaN HEMTs) have high breakdown field strength and low on-resistance, and are suitable for high-frequency and high-power application scenarios, having great potential in power supplies and other directions. With the rapid development of gallium nitride technology, its manufacturing cost is also continuously decreasing. Currently, discrete gallium nitride power devices and integrated circuit modules have been gradually commercialized and are applied in consumer electronics fields such as mobile phone fast charging. When integrated with peripheral driving, control, and protection circuits, the performance of gallium nitride power devices can be further improved. Most of the existing peripheral circuits are implemented based on silicon chips and are co-packaged with discrete gallium nitride power devices, so parasitic inductance generated due to interconnection is inevitably present. To achieve a true GaN complementary logic integrated circuit, p-channel devices are required, but there are many technical problems. As an alternative, currently, enhancement-mode and depletion-mode devices with an AlGaN / GaN heterojunction as the n-channel are usually combined to form a high-speed direct-coupled logic circuit (DCFL) to achieve the same function. However, this solution has a relatively large static power. Therefore, achieving a true complementary logic circuit is an urgent need for current gallium nitride monolithic integration technology.

[0003] Currently, research on p-channel gallium nitride transistors mainly aims to improve the carrier density and hole mobility by epitaxially constructing a quantum well with a two-dimensional hole gas (2DHG). From the perspective of integration, these specific epitaxial structures cannot be combined with n-channel gallium nitride transistors to form a complementary logic circuit. On current commercial p-GaN / AlGaN / GaN epitaxial wafers, in addition to the two-dimensional electron gas (2DEG) existing in the traditional AlGaN / GaN heterojunction, a 2DHG also exists in the p-GaN / AlGaN heterojunction, and a relatively high concentration of holes can be confined at the p-GaN / AlGaN interface, which will help to achieve a true complementary logic circuit.

[0004] Another approach is to etch the p-GaN in the gate region, which can gradually shift the threshold of the p-channel device negatively to achieve an enhancement-mode device. However, p-GaN etching not only causes lattice damage and reduces the hole mobility in the channel, but also forms a high-density trap state on the etched surface, thus having a serious impact on p-channel enhancement-mode devices.

[0005] Therefore, it is necessary to improve the preparation process of p-GaN HEMTs. Summary of the Invention

[0006] The present invention proposes a technical solution and a process preparation flow for realizing a p-channel enhancement-mode gallium nitride transistor without performing trench etching on p-GaN.

[0007] According to a first aspect of the present invention, a method for preparing an enhanced p-channel gallium nitride power device is provided, including:

[0008] S1: Provide a substrate;

[0009] S2: Form an epitaxial structure, where the epitaxial structure includes a stacked first AlN layer, a buffer layer, a GaN layer, a second AlN layer, an AlGaN layer, and a p-GaN channel layer formed on the substrate in sequence along a direction away from the substrate;

[0010] S3: Deposit a hard mask layer, and perform patterned etching on the hard mask layer through photolithography and etching processes so that it only covers a first region of the p-GaN channel layer;

[0011] S4: Epitaxially grow a p-GaN secondary growth layer on the p-GaN channel layer outside the first region;

[0012] S5: Remove the hard mask layer on the first region to form a gate groove;

[0013] S6: Form a gate dielectric layer, where the gate dielectric layer is deposited on the inner wall of the gate groove and covers the p-GaN secondary growth layer;

[0014] S7: Form a source ohmic contact electrode and a drain ohmic contact electrode, where the source ohmic contact electrode and the drain ohmic contact electrode penetrate through the gate dielectric layer and contact the p-GaN secondary growth layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the gate groove;

[0015] S8: Form a gate metal layer, where the gate metal layer is formed in the gate groove and on the gate dielectric layer;

[0016] S9: Form a passivation layer, where the passivation layer covers the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode, and the gate dielectric layer;

[0017] S10: Form a metal interconnection layer, where the metal interconnection layer includes a source metal interconnection layer, a drain metal interconnection layer, and a gate metal interconnection layer, and the source metal interconnection layer, the drain metal interconnection layer, and the gate metal interconnection layer penetrate through the passivation layer and are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate metal layer respectively.

[0018] Optionally, the thickness of the p-GaN channel layer is 5 - 15 nm

[0019] Optionally, the thickness of the p-GaN secondary growth layer is 50 - 90 nm.

[0020] Optionally, the material of the gate dielectric layer is any one of Al2O3, AlN, SiO2, HfO2, SiN x and their stacked combinations.

[0021] Optionally, the thickness of the gate dielectric layer is 5 - 15 nm.

[0022] Optionally, the material of the gate metal layer is Ni / Au stacked metal.

[0023] Optionally, in the Ni / Au stacked metal, the thickness of the Ni metal is 40 nm and the thickness of the Au metal is 60 nm.

[0024] Optionally, the source ohmic contact electrode and the drain ohmic contact electrode are made of Ni / Au stacked metal.

[0025] Optionally, in the Ni / Au stacked metal, the thickness of the Ni metal is 40 nm and the thickness of the Au metal is 60 nm.

[0026] Optionally, the passivation layer is a SiN layer with a thickness of 40 - 80 nm.

[0027] Optionally, after forming the gate dielectric layer and before forming the source and drain ohmic contact electrodes, the method further includes:

[0028] Performing active region isolation to form an isolation layer in the p-GaN secondary growth layer, p-GaN channel layer, AlGaN layer, second AlN layer, and GaN layer.

[0029] According to the second aspect of the present invention, there is provided an enhancement-mode p-channel gallium nitride power device, characterized in that it is prepared by the preparation method described in the first aspect of the present invention.

[0030] According to the third aspect of the present invention, there is provided an electronic device, including the enhancement-mode p-channel gallium nitride power device described in the second aspect of the present invention.

[0031] The preparation method of the enhanced p-channel gallium nitride power device provided by the present invention epitaxially grows a p-GaN channel layer on the basis of an AlGaN / GaN epitaxial wafer, and then forms the structure of the gate groove by selectively epitaxially growing the p-GaN secondary growth layer, so as to realize a p-channel enhancement-mode gallium nitride transistor without performing gate trench etching on the p-GaN, avoiding the reduction of the channel mobility caused by the gate etching method and the negative impact on the p-channel enhancement-mode device caused by the high-density trap states formed on the etched surface, effectively improving the performance of the enhanced p-channel gallium nitride transistor, and providing a solution for a true GaN complementary logic integrated circuit. Brief Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0033] Figure 1 It is a schematic flow chart of the preparation method of the enhanced p-channel gallium nitride power device provided by an embodiment of the present invention;

[0034] Figure 2A - 2J It is a schematic cross-sectional view of the device structure at different process stages according to the preparation method of the enhanced p-channel gallium nitride power device provided by an embodiment of the present invention;

[0035] Figure 3 It is a schematic cross-sectional view of the structure of the enhanced p-channel gallium nitride power device provided by an embodiment of the present invention;

[0036] Description of the Reference Numerals:

[0037] 201 - Substrate;

[0038] 202 - First AlN layer;

[0039] 203 - Buffer layer;

[0040] 204 - GaN layer;

[0041] 205 - Second AlN layer;

[0042] 206 - AlGaN layer;

[0043] 207 - p-GaN channel layer;

[0044] 208 - p-GaN secondary growth layer;

[0045] 209 - Gate dielectric layer;

[0046] 210 - Source ohmic contact electrode;

[0047] 211 - Drain ohmic contact electrode;

[0048] 212 - Gate metal layer;

[0049] 213 - Passivation layer;

[0050] 214 - Source metal interconnect layer;

[0051] 215 - Drain metal interconnect layer;

[0052] 216 - Gate metal interconnect layer;

[0053] 217 - Active region isolation layer;

[0054] 218 - Hard mask layer;

[0055] 219 - First region;

[0056] 220 - Gate groove. Detailed implementation manner

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0058] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0059] Gallium nitride high electron mobility transistors (AlGaN / GaN HEMTs) have high breakdown field strength and low on-resistance, making them suitable for high-frequency and high-power application scenarios and having great potential in power supplies and other fields. When integrated with peripheral drive, control, and protection circuits, the performance of gallium nitride power devices can be further improved. Most existing peripheral circuits are implemented based on silicon chips and are co-packaged with discrete gallium nitride power devices, so parasitic inductance generated by interconnection is inevitably present. To achieve a true GaN complementary logic integrated circuit, p-channel devices are required, but there are many technical difficulties. As an alternative, currently, enhancement-mode and depletion-mode devices with an AlGaN / GaN heterojunction as the n-channel are usually combined to form a high-speed direct-coupled logic circuit (DCFL) to achieve the same function. However, this solution has a relatively large static power. Another approach is to gradually shift the threshold of p-channel devices negatively by etching the p-GaN in the gate region to achieve enhancement-mode devices. However, p-GaN etching not only causes lattice damage and reduces the hole mobility in the channel but also forms a high density of trap states on the etched surface, which seriously affects p-channel enhancement-mode devices.

[0060] In view of this, the inventors have proposed a technical solution and process flow for realizing a p-channel enhancement-mode gallium nitride transistor without performing trench gate etching on p-GaN, thereby solving the negative impacts on p-channel enhancement-mode devices caused by the reduction of channel mobility and the high density of trap states formed on the etched surface by the existing gate etching method, and providing a solution for a true GaN complementary logic integrated circuit.

[0061] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0062] Please refer to Figure 1 , according to an embodiment of the present invention, a method for fabricating an enhancement-mode p-channel gallium nitride power device is provided, and the method includes:

[0063] S1: Provide a substrate, as Figure 2A shown.

[0064] S2: Form an epitaxial structure, where the epitaxial structure includes a stacked first AlN layer 202, a buffer layer 203, a GaN layer 204, a second AlN layer 205, an AlGaN layer 206, and a p-GaN channel layer 207 formed on the substrate in sequence along the direction away from the substrate, as Figure 2B shown.

[0065] S3: Deposit a hard mask layer 218, and perform patterning etching on the hard mask layer 218 through photolithography and etching processes so that it only covers the first region 219 of the p-GaN channel layer 207, as Figure 2C shown.

[0066] S4: Epitaxially grow a p-GaN secondary growth layer 208, and the p-GaN secondary growth layer 208 is formed on the p-GaN channel layer 207 outside the first region 219. The schematic diagram of the device structure after this step is as Figure 2D shown.

[0067] S5: Remove the hard mask layer on the first region 219 to form a gate groove 220. The schematic diagram of the device structure after this step is as Figure 2E shown.

[0068] Among them, this first region is the gate region.

[0069] Through the process steps of S3 - S5, the enhancement-mode p-channel gallium nitride power device provided by the present invention forms a gate groove without performing gate trench etching on p-GaN, thereby realizing a p-channel enhancement-mode gallium nitride transistor, avoiding the negative impacts of the reduction of channel mobility caused by the gate etching method and the high-density trap states formed on the etched surface on the p-channel enhancement-mode device.

[0070] S6: Form a gate dielectric layer 209, and the gate dielectric layer 209 is deposited on the inner wall of the gate groove 220 and covers the p-GaN secondary growth layer 208, as Figure 2F shown.

[0071] S7: Form a source ohmic contact electrode 210 and a drain ohmic contact electrode 211. The source ohmic contact electrode 210 and the drain ohmic contact electrode 21 penetrate through the gate dielectric layer 209 and contact the p-GaN secondary growth layer 208, and the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are respectively located on both sides of the gate groove 220, as Figure 2G shown.

[0072] S8: Form a gate metal layer 212, and the gate metal layer 212 is formed in the gate groove 220 and located on the gate dielectric layer 209, as Figure 2H shown.

[0073] S9: Form a passivation layer 213, and the passivation layer 213 covers the gate metal layer 212, the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate dielectric layer 209, as Figure 2I shown.

[0074] S10: Form a metal interconnect layer, where the metal interconnect layer includes a source metal interconnect layer 214, a drain metal interconnect layer 215, and a gate metal interconnect layer 216. After the source metal interconnect layer 214, the drain metal interconnect layer 215, and the gate metal interconnect layer 216 penetrate through the passivation layer 213, they are electrically connected to the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate metal layer 216 respectively. The schematic diagram of the device structure after this step is as shown in Figure 2J shown.

[0075] In an embodiment of the present invention, the thickness of the p-GaN channel layer 207 is 5 - 15 nm. Of course, it should be realized that the present invention is not limited thereto, and other thickness values of the p-GaN channel layer 207 are also within the protection scope of the present invention.

[0076] In an embodiment of the present invention, the thickness of the p-GaN secondary growth layer 208 is 50 - 90 nm. Of course, it should be realized that the present invention is not limited thereto, and other thickness values of the p-GaN secondary growth layer 208 are also within the protection scope of the present invention.

[0077] In an embodiment of the present invention, the material of the gate dielectric layer 209 is any one of Al2O3, AlN, SiO2, HfO2, SiNx and their laminated combinations. Of course, it should be realized that the present invention is not limited thereto, and the materials of other gate dielectric layers are also within the protection scope of the present invention.

[0078] In an embodiment of the present invention, the thickness of the gate dielectric layer 209 is 5 - 15 nm. Of course, it should be realized that the present invention is not limited thereto, and other thickness values of the gate dielectric layer 209 are also within the protection scope of the present invention.

[0079] In an embodiment of the present invention, the material of the gate metal layer 212 is a Ni / Au laminated metal. In an example, the thickness of the Ni metal in the Ni / Au laminated metal is 40 nm, and the thickness of the Au metal is 60 nm. Of course, it should be realized that the material and thickness of the gate metal layer 212 should not be construed as a limitation to the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0080] In an embodiment of the present invention, the materials of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are Ni / Au laminated metals. In an example, the thickness of the Ni metal in the Ni / Au laminated metal is 40 nm, and the thickness of the Au metal is 60 nm. Of course, it should be realized that the materials and thicknesses of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 should not be construed as a limitation to the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0081] In one embodiment of the present invention, the passivation layer 213 is a SiN layer. In one example, its thickness is 40 - 80 nm. Of course, it should be realized that the material and thickness of the passivation layer 213 should not be construed as a limitation of the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0082] In one example, after step S6, the method further includes:

[0083] Performing active region isolation to form an isolation layer 217 in the p-GaN secondary growth layer 208, p-GaN channel layer 207, AlGaN layer 206, second AlN layer 205, and GaN layer 204.

[0084] Please continue to refer to Figure 3 , according to an embodiment of the present invention, there is also provided an enhancement-mode p-channel gallium nitride power device, which is prepared by the preparation method of the enhancement-mode p-channel gallium nitride device shown in Figure 1 the figure.

[0085] The enhancement-mode p-channel gallium nitride power device provided by the present invention can be realized without performing gate recess etching on p-GaN, avoiding the negative impacts of the gate etching method on the reduction of channel mobility and the high-density trap states formed on the etched surface on the p-channel enhancement-mode device, thereby effectively improving the performance of the gallium nitride device.

[0086] In addition, the present invention also provides an electronic device, including the enhancement-mode p-channel gallium nitride power device involved in the above embodiment.

[0087] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preparation method of an enhanced p-channel gallium nitride power device, characterized in that, The method includes: S1: providing a substrate; S2: forming an epitaxial structure, wherein the epitaxial structure comprises a first AlN layer, a buffer layer, a GaN layer, a second AlN layer, an AlGaN layer, and a p-GaN channel layer stacked on the substrate in sequence in a direction away from the substrate; S3: depositing a hard mask layer, and patterning and etching the hard mask layer by photolithography and etching processes so that the hard mask layer only covers the first region of the p-GaN channel layer; S4: epitaxially growing a p-GaN secondary growth layer, wherein the p-GaN secondary growth layer is formed on the p-GaN channel layer outside the first region; S5: removing the hard mask layer on the first region to form a gate groove; S6: forming a gate dielectric layer, wherein the gate dielectric layer is deposited on the inner wall of the gate groove and covers the p-GaN secondary growth layer; S7: forming a source ohmic contact electrode and a drain ohmic contact electrode, wherein the source ohmic contact electrode and the drain ohmic contact electrode penetrate the gate dielectric layer and contact the p-GaN secondary growth layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the gate groove; S8: forming a gate metal layer, wherein the gate metal layer is formed in the gate groove and is located on the gate dielectric layer; S9: forming a passivation layer, wherein the passivation layer covers the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode and the gate dielectric layer; S10: forming a metal interconnection layer, wherein the metal interconnection layer comprises a source metal interconnection layer, a drain metal interconnection layer and a gate metal interconnection layer, wherein the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer penetrate through the passivation layer and are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode and the gate metal layer respectively.

2. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 1, characterized in that The thickness of the p-GaN channel layer is 5-15 nm.

3. The preparation method of the enhanced p-channel gallium nitride power device according to claim 1, characterized in that, The thickness of the p-GaN secondary growth layer is 50-90 nm.

4. The preparation method of the enhanced p-channel gallium nitride power device according to claim 1, characterized in that, The material of the gate dielectric layer is any one of Al2O3, AlN, SiO2, HfO2, SiN x and their laminated combinations.

5. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 4, wherein, The thickness of the gate dielectric layer is 5-15 nm.

6. The preparation method of the enhanced p-channel gallium nitride power device according to claim 1, characterized in that, The gate metal layer is made of Ni / Au laminated metal.

7. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 6, characterized in that, In the Ni / Au laminated metal, the thickness of the Ni metal is 40 nm, and the thickness of the Au metal is 60 nm.

8. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 1, characterized in that, The source ohmic contact electrode and the drain ohmic contact electrode are made of Ni / Au laminated metal.

9. The preparation method of the enhanced p-channel gallium nitride power device according to claim 8, characterized in that, In the Ni / Au laminated metal, the thickness of the Ni metal is 40 nm, and the thickness of the Au metal is 60 nm.

10. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 1, wherein, The passivation layer is a SiN layer, and the thickness thereof is 40-80 nm.

11. The manufacturing method of the enhanced p-channel gallium nitride power device according to claim 1, wherein After forming the gate dielectric layer and before forming the source and drain ohmic contact electrodes, the method further includes: Active region isolation is performed, and an isolation layer is formed in the p-GaN secondary growth layer, the p-GaN channel layer, the AlGaN layer, the second AlN layer, and the GaN layer.

12. An enhanced p-channel gallium nitride power device, characterized in that, Prepared by the preparation method according to any one of claims 1 to 11.

13. An electronic device, characterized in that, It comprises the enhancement mode p-channel gallium nitride power device as claimed in claim 12.

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