QC-LDPC improved decoder eliminating waiting period

Abstract

This invention relates to an improved QC-LDPC decoder that eliminates wait cycles, belonging to the field of communication technology. It includes a posterior message storage module, a -C2V FIFO, a C2V_RAM, a V2C_signs FIFO, a permutation module, a calculation module, a FIFO buffer module, a C2V message recovery module, and an inverse permutation module. The posterior message storage module includes two real dual-port RAMs, llr_ram_0 and llr_ram_1. This invention reduces computational complexity, eliminates the need for calculating and storing flag signals, improves system flexibility, and eliminates wait cycles, thereby increasing system throughput. By using two real dual-port RAMs for ping-pong access to initial channel information and updated node posterior probability information, it saves inter-frame initial channel message buffering time, further improving system throughput and demonstrating good hardware utilization.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to an improved QC-LDPC decoder that eliminates waiting cycles. Background Technology

[0002] With the continuous development of information technology, low-density parity check codes (LDPCs) have been applied in various communication scenarios due to their advantages such as low system complexity and low error levels. The quasi-cyclic structure of quasi-cyclic QC-LDPC codes makes them suitable for high-throughput and low-latency systems. Currently, to accelerate decoding convergence, layered decoding is often employed, allowing the next layer to use the latest updated probability information after the previous layer has been updated.

[0003] In existing QC-LDPC decoding schemes, the following methods are mainly used to resolve the waiting period caused by changes in the row weight of the base matrix and read / write conflicts between layers.

[0004] The first approach addresses the waiting period caused by changes in the row weight of the base matrix. The parity check matrix of QC-LDPC consists of a circulant permutation matrix (CPM) or a circulant square matrix with row weights not equal to 1 and a zero-matrix matrix. Typically, the size of the square matrix is ​​used as a layer for layered decoding. During layered decoding, when updating the parity check node from a layer with a larger row weight to a layer with a smaller row weight, the intermediate calculated values ​​are overwritten by the calculated values ​​of the next layer before the parity check node information of that layer is completely updated, causing data update errors. Adding a waiting period can effectively avoid this situation. To eliminate the waiting period, a decoupled First-In-First-Out (FIFO) memory is usually added to temporarily store intermediate calculated values ​​of one layer. The data in the FIFO is read out during parity check node message allocation.

[0005] The second approach addresses the waiting period introduced by data access conflicts between layers. A flag signal is added to determine if the Log-Likelihood Ratio (LLR) used to calculate V2C messages is up-to-date. If it is, the message is updated accordingly. Conversely, it is In this context, V2C represents the message passed from the variable node to the verification node, and C2V represents the message passed from the verification node to the variable node. It is the updated node posterior probability message. This is not the latest message updated in the previous layer, but rather the posterior probability message of the nodes updated in the previous few layers; 'it' represents the current iteration number, and 'l' represents the l-th column block of the QC-LDPC verification matrix. The variable node of the l-th column block needs to send a V2C message to the verification node c, representing the layer. This is the C2V message that the layer represented by node c in the it-th iteration needs to pass to the block variable node in the l-th column.

[0006] like Figure 1 As shown, the introduced `outofdate` flag is used to indicate whether the LLR used in the calculated V2C message is up-to-date. If it is up-to-date, the V2C message is buffered in a FIFO manner; otherwise, a negative C2V message is buffered. The `doPatch` signal has the same flag condition as the `outofdate` signal, indicating how the node's posterior information is calculated after the update.

[0007] Figure 1 The LLR RAM shown consists of two simple dual-port RAMs: one for decoding the current codeword, called the decoding memory, and the other for reading the decoded codeword and writing the next codeword, called the buffer memory. When writing a posterior probability LLR message, it is determined whether the LLR to be written has already read the content of the next layer's computation. If it has, the LLR will also be written to the buffer memory. In this case, the write port of the buffer memory cannot be used for writing the next codeword.

[0008] The second approach, when resolving the waiting cycles introduced by data access conflicts between layers, increases the computational complexity of the system due to the calculation of flag signals and the write operation judgment of dual-port RAM. Furthermore, the multi-code decoder needs to store the flag signals for each code, lacking good flexibility. Figure 1 When writing to the buffer memory in the LLR RAM shown, the next codeword cannot be written, which increases the complexity of system control. Summary of the Invention

[0009] To address the aforementioned problems in the existing technology, this invention provides an improved QC-LDPC decoder that eliminates the waiting period. This reduces computational complexity, eliminates the need for calculating and storing flag signals, and improves system flexibility. Simultaneously, it eliminates the waiting period, thereby increasing system throughput. By using two real dual-port RAMs for ping-pong access to the initial channel information and the updated node posterior probability information, it can save the initial channel message buffering time between frames, further improving system throughput and demonstrating good hardware utilization.

[0010] The objective of this invention can be achieved through the following technical solutions:

[0011] An improved QC-LDPC decoder that eliminates wait cycles includes a post-message storage module, a -C2V FIFO, a C2V_RAM, a V2C_signs FIFO, a permutation module, a calculation module, a FIFO buffer module, a C2V message recovery module, and an inverse permutation module;

[0012] The a posteriori message storage module includes two real dual-port RAMs, llr_ram_0 and llr_ram_1, which are used for ping-pong access of the initial channel message and the updated node a posteriori message during the decoding of two frames of codewords.

[0013] The C2V_RAM is used to store the C2V messages from the previous iteration and the C2V messages updated during the current iteration.

[0014] The -C2V FIFO is used to cache negative C2V messages read from C2V_RAM;

[0015] The replacement module is used to change the node V2C message sequence from the order of variable nodes to the order of corresponding verification nodes;

[0016] The V2C_signs FIFO is used to cache the calculated symbol values ​​of V2C messages in the V2C_signs FIFO. When allocating C2V messages, the symbol values ​​are read from the V2C_signs FIFO to calculate the symbol values ​​of the C2V messages.

[0017] The calculation module is used to obtain the minimum value, the second smallest value, and the signed XOR value of each row in the first-level CPM based on the V2C message of the first level, and record the column position where the minimum value is located.

[0018] The FIFO cache module is used to cache the minimum value, the second smallest value, the sign XOR value, and the position of the minimum value obtained by the calculation module into the FIFO cache module;

[0019] The C2V message recovery module is used to output updated C2V messages based on the values ​​in the FIFO cache module and the V2C_signs FIFO.

[0020] The inverse permutation module is used to change the order of the updated C2V message sequence from the order of the verification nodes to the order of the corresponding variable nodes.

[0021] As a preferred technical solution of the present invention, llr_ram_0 and llr_ram_1 are indicated by the ping_pong signal to perform ping-pong access to the initial channel message and the updated node posterior probability message between two frames of codewords;

[0022] The width of the two real dual-port RAMs is Z×Width_APP_LLR, and the depth is N / Z, where Z is the size of the CPM that makes up the QC-LDPC check matrix, Width_APP_LLR is the width of the posterior probability message of a node, and N is the code length of the QC-LDPC.

[0023] As a preferred embodiment of the present invention, the width of the C2V_RAM is Z×Width_C2V_LLR, and it stores only C2V messages of CPM starting from the first row. The depth is the total row weight of the QC-LDPC code base matrix, and Width_C2V_LLR is the width of the C2V message of a node.

[0024] As a preferred embodiment of the present invention, the displacement module and the reverse displacement module are composed of a barrel-shaped shifter, which is used to realize the function of leftward cyclic shift.

[0025] As a preferred embodiment of the present invention, the V2C_signs FIFO has a width of Z and a depth equal to the maximum value of the row weight of the QC_LDPC base matrix.

[0026] As a preferred embodiment of the present invention, the calculation module compares the absolute values ​​of the V2C messages.

[0027] As a preferred embodiment of the present invention, the width of the FIFO cache module is:

[0028] Width_sign+Width_min0+Width_idx0+Width_min1

[0029] Its depth is no greater than Where Width_sign represents the width of the sign XOR value, Width_min0 represents the width of the minimum value, Width_idx0 represents the width of the position where the minimum value is located, Width_min1 represents the width of the second smallest value, max_row_weight is the maximum row weight of the QC-LDPC code base matrix, and min_row_weight is the minimum row weight of the QC-LDPC base matrix.

[0030] As a preferred embodiment of the present invention, the method for the C2V message recovery module to output updated C2V messages is as follows:

[0031] The allocation is based on the column position of the minimum value in the FIFO buffer module. If the column position of the minimum value is the column block that the allocated C2V message needs to be transmitted, the second smallest value is allocated; otherwise, the minimum value is allocated. The sign value of the updated C2V message is obtained by XORing the sign value in the FIFO buffer module with the sign value of the V2C message output by V2C_signs FIFO.

[0032] As a preferred embodiment of the present invention, the formula for calculating the updated node posterior probability message in the posterior message storage module is as follows:

[0033]

[0034] in, It is the updated node posterior probability message. This is the latest node posterior probability message before the posterior message storage module updates. C2V represents the message passed from the verification node to the variable node, it is the current iteration number, and l is the l-th column block of the QC-LDPC verification matrix. This is the C2V message that the layer represented by node c in the it-th iteration needs to pass to the block variable node in the l-th column.

[0035] The beneficial effects of this invention are as follows:

[0036] This invention provides an improved QC-LDPC decoder that eliminates waiting cycles. It has low computational complexity and can eliminate waiting cycles introduced by line weight changes and inter-layer address read / write conflicts. Without increasing the system architecture with additional computation, it effectively improves the hardware utilization and flexibility of the system, reduces stored data, and increases the decoder's throughput. Furthermore, by using two real dual-port RAMs for ping-pong access to initial channel information and updated node posterior probability information, it can save the initial channel message buffering time between frames, further improving system throughput. It has good hardware utilization and can be used in high-speed, high-throughput communication applications. Attached Figure Description

[0037] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0038] Figure 1 A schematic diagram of an existing decoder architecture that can eliminate wait cycles;

[0039] Figure 2 This is a schematic diagram of the improved decoder architecture of the present invention;

[0040] Figure 3 This is a schematic diagram of the replacement module in this invention. Detailed Implementation

[0041] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0042] Please see Figure 1-3An improved QC-LDPC decoder that eliminates waiting cycles includes a post-message storage module, a -C2V FIFO, a C2V_RAM, a V2C_signs FIFO, a permutation module, a calculation module, a FIFO buffer module, a C2V message recovery module, and an inverse permutation module;

[0043] The a posteriori message storage module includes two real dual-port RAMs, llr_ram_0 and llr_ram_1, which are used for ping-pong access of the initial channel message and the updated node a posteriori message when decoding two frames of codewords. That is, when llr_ram_0 (llr_ram_1) accesses the updated node a posteriori message of one frame of codewords, llr_ram_1 (llr_ram_0) is storing the initial channel message of another frame of codewords.

[0044] The C2V_RAM is used to store the C2V messages from the previous iteration and the C2V messages updated during the current iteration. The C2V messages output during the first iteration of decoding a codeword frame are set to 0.

[0045] The -C2V FIFO is used to cache negative C2V messages read from C2V_RAM;

[0046] The permutation module is used to change the node V2C message sequence from the order of variable nodes to the order of corresponding verification nodes. The V2C message sequence is composed of the log-likelihood ratio messages of the V2C nodes of the size of the cyclic square matrix. The V2C message is obtained by adding the node posterior probability message output by the posterior message storage module to the C2V message stored in the negative C2V_RAM in the previous iteration.

[0047] The V2C_signs FIFO is used to cache the calculated symbol values ​​of V2C messages in the V2C_signs FIFO. When allocating C2V messages, the symbol values ​​are read from the V2C_signs FIFO to calculate the symbol values ​​of the C2V messages.

[0048] The calculation module is used to obtain the minimum value, second minimum value, and signed XOR value of each row in the first-level CPM based on the V2C messages of the first level, and to record the column position of the minimum value, corresponding to... Figure 2 min0, min1, sign, and idx0 in the data;

[0049] The FIFO cache module is used to cache the minimum value, the second smallest value, the sign XOR value, and the position of the minimum value obtained by the calculation module into the FIFO cache module;

[0050] The C2V message recovery module is used to output updated C2V messages based on the values ​​in the FIFO cache module and the V2C_signs FIFO.

[0051] The inverse permutation module is used to change the order of the updated C2V message sequence from the order of the verification nodes to the order of the corresponding variable nodes, and the C2V messages are distributed by the C2V message recovery module.

[0052] Specifically, llr_ram_0 and llr_ram_1 are connected via... Figure 2 The ping_pong signal in the code indicates that the initial channel message and the updated node posterior probability message between two frames of codewords are ping-pong accessed; the width of the two real dual-port RAMs is Z×Width_APP_LLR, and the depth is N / Z, where Z is the size of the CPM that makes up the QC-LDPC parity check matrix, Width_APP_LLR is the width of the posterior probability message of a node, and N is the code length of QC-LDPC.

[0053] In this embodiment, the ping_pong signal is 0 at the beginning of decoding, such as... Figure 2 As shown, `llr_init`, the initial channel information, is stored in `llr_ram_0`. When the initial channel information of the first frame codeword is completely cached, the `ping_pong` signal is inverted to 1. At this time, the posterior message storage module reads the initial channel information of the first frame codeword cached in `llr_ram_0` to start decoding. During the decoding process, the updated node posterior probability message, `llr_updated`, is stored in `llr_ram_0`, and the initial channel information of the second frame codeword is stored in `llr_ram_1`. When the iterative decoding of the first frame codeword ends, the initial channel LLR message of the second frame codeword has also been stored, and the `ping_pong` signal is inverted to 0. The posterior message storage module reads the initial channel information of the second frame codeword cached in `llr_ram_1` to start decoding. During the decoding process, the updated node posterior probability message, `llr_updated`, is stored in `llr_ram_1` for iterative decoding, and the initial channel information of the third frame codeword is stored in `llr_ram_0`. When the second frame codeword iteration decoding ends, the initial channel LLR message of the third frame codeword has also been stored. The ping_pong signal is then inverted to 1, and the ping-pong storage and retrieval operation of the initial channel information and the updated node posterior probability information between frames is carried out in this way.

[0054] Specifically, the width of the C2V_RAM is Z×Width_C2V_LLR, and it stores only C2V messages of CPM starting from the first row. The depth is the total row weight of the QC-LDPC code base matrix, and Width_C2V_LLR is the width of the C2V message of a node.

[0055] In this embodiment, the C2V_RAM module uses a simple dual-port RAM to store C2V messages. The read enable is valid before the update module starts. The read C2V messages are used to calculate V2C messages. After the update module ends, the updated C2V messages are rewritten into the C2V_RAM.

[0056] The displacement module and the reverse displacement module are composed of barrel shifters, which are used to realize the function of leftward cyclic shift.

[0057] In this embodiment, as Figure 2 As shown, the input to the permutation module is the node posterior probability information (llr_rd1) output by the posterior message storage module plus the C2V message output by the negative C2V_RAM. This refers to node V2C messages. Taking a circular matrix of size 336 as an example... Figure 3 As shown, a V2C message vector has 336 LLR messages, each LLR message is 8 bits wide, and the shift registers have a total of The system consists of 336 MUX2 units per stage. Each bit of the shift value (shift_value) controls whether a shift is performed in each stage. If shift_value[i] = 0, the output of that stage remains in the same order as the input of that stage; if shift_value[i] = 1, the output is circularly shifted left by 2 bits. i If the input vector size is too large, pipelined processing can be inserted between stages to increase the module's clock frequency. The inverse permutation module differs from the permutation module in that its input is the updated C2V message output from the C2V message recovery module in the current iteration, consisting of 336 LLR messages, each 6 bits wide.

[0058] The V2C_signs FIFO has a width of Z and a depth of max_row_weight, which is the maximum row weight of the QC_LDPC base matrix.

[0059] The calculation module compares the absolute values ​​of the V2C messages.

[0060] The width of the FIFO buffer module is the sum of the widths of the signed XOR value, the minimum value and its position, and the second smallest value, i.e., Width_sign + Width_min0 + Width_idx0 + Width_min1, and its depth is no greater than [missing value].

[0061] Specifically, the method for the C2V message recovery module to output updated C2V messages is as follows:

[0062] The allocation is based on the column position of the minimum value in the FIFO buffer module. If the column position of the minimum value is the column block that the allocated C2V message needs to be transmitted, the second smallest value is allocated; otherwise, the minimum value is allocated. The sign value of the updated C2V message is obtained by XORing the sign value in the FIFO buffer module with the sign value of the V2C message output by V2C_signs FIFO.

[0063] In this embodiment, when the C2V message recovery module allocates verification node information, it reads the value in the FIFO cache module. After the verification node messages of the first layer are allocated, it starts reading the calculation information of the next layer.

[0064] Specifically, the formula for calculating the updated node posterior probability message in the posterior message storage module is as follows:

[0065]

[0066] in, It is the updated node posterior probability message. This is the latest node posterior probability message before the posterior message storage module updates. C2V represents the message passed from the verification node to the variable node, it is the current iteration number, and l is the l-th column block of the QC-LDPC verification matrix. This is the C2V message that the layer represented by node c in the it-th iteration needs to pass to the block variable node in the l-th column.

[0067] In this embodiment, It could be the latest updated posterior probability message from the previous layer node, or it could be the posterior probability message from the nodes updated in the previous few layers. That is, the latest updated node posterior probability information should be used as much as possible. If it is not needed, the old information should be read. This is to resolve the waiting period caused by data access conflicts between layers.

[0068] Working principle and usage process of this invention:

[0069] Taking the decoding of the first frame of codewords as an example, at the beginning of decoding, the ping_pong signal is 0, such as... Figure 2 As shown, `llr_init` stores the initial channel information in `llr_ram_0`. When the initial channel information of the first frame codeword is buffered, the `ping_pong` signal is inverted to 1. At this time, the a posteriori message storage module reads the initial channel information of the first frame codeword buffered in `llr_ram_0` and begins iterative decoding, as follows... Figure 2As shown in llr_rd1; during the iterative decoding process, the updated node posterior probability message, i.e., llr_updated, is stored in llr_ram_0, and the initial channel information of the second frame codeword is stored in llr_ram_1. In the first iteration, it = 1, the C2V message sequence in C2V_RAM is set to 0, and llr_rd1 is used as the node posterior probability message and the message read from the negative C2V_RAM. Adding them together gives This represents the V2C message of the l-th column block in the first iteration, and simultaneously the negative C2V_RAM read. Store in -C2V FIFO.

[0070] The V2C message permutation module changes the sequence of node V2C messages from the order of variable nodes to the order of corresponding check nodes. After permutation, the V2C messages are cached in the V2C_signs FIFO along one path and input to the calculation module along the other. The calculation module calculates the minimum, second minimum, and sign XOR values ​​of the permuted V2C messages in the first layer, records the column position of the minimum value, and outputs it to the FIFO caching module for caching. Figure 2 As shown, the minimum value is min0, the second minimum value is min1, the sign XOR value of the first-level V2C message is sign, and the column position of the minimum value is idx0.

[0071] The C2V message recovery module allocates C2V messages by comparing the data in the previously cached V2C_signs FIFO with the data in the FIFO cache module. If the column position of the minimum value is the column block of the allocated C2V message transmission, the second smallest value is allocated; otherwise, the minimum value is allocated. The sign value of the updated C2V message is obtained by XORing the sign value in the FIFO cache module with the sign value of the V2C message output by the V2C_signs FIFO. The allocated C2V messages are then processed by the inverse permutation module to change the order of the updated C2V message sequence from that of the check nodes to that of the corresponding variable nodes, resulting in... That is, the first iteration's updated C2V message is obtained, one path is input into C2V_RAM for buffering, and the other path is combined with the message stored in -C2V FIFO. Adding them together gives At this point, the node posterior probability message is read from the posterior message storage module. Figure 2 The llr_rd2 shown corresponds to and Adding them together gives Figure 2 The llr_updated shown corresponds to The message is written to llr_ram_0 in the posterior message storage module. At this point, the posterior probability of the node in the l-th column block of the layer is updated. Once all columns in all layers have been updated, one iteration ends. Since there is no waiting period, the next iteration of the first layer begins immediately. This cycle continues until the posterior probability message of the last node in the last iteration is written to the posterior message storage module, and the decoding of the codeword of the first frame ends.

[0072] When the decoding of the first frame codeword is completed, the initial channel message llr_init of the second frame codeword is also stored. The ping_pong signal is inverted to 0. The a posteriori message storage module reads the initial channel message of the second frame codeword buffered in llr_ram_1 for decoding. The updated node a posteriori probability message of the second frame codeword is stored in llr_ram_1. The initial channel message llr_init of the third frame codeword will be written to llr_ram_0. This enables the a posteriori message storage module to use the ping_pong signal to access the initial channel message and the updated node a posteriori message during the decoding of the two frames of codewords.

[0073] This invention employs a layered minimum sum decoding approach, with serial inter-block and parallel intra-block decoding. The size of the cyclic matrix is ​​used as a layer. The minimum sum algorithm can utilize the normalized minimum sum algorithm and the offset minimum sum algorithm. By adding a decoupled FIFO buffer module, the minimum value related calculation information of V2C messages in one layer is temporarily stored. When the check node message is allocated, the data in the FIFO buffer module is read out. After allocation is completed, the intermediate calculation value of the next layer pre-stored in the FIFO buffer module is read out to update the check node of the next layer. This eliminates the waiting period caused by changes in the row weight of the base matrix.

[0074] To address the waiting period caused by data access conflicts between layers, the improved approach is to utilize the latest updated node log-likelihood ratio information whenever possible. If this information is not needed, older node information is read. This eliminates the need for calculating and storing existing structural flag signals, simplifying the decoding architecture. The posterior message storage module uses two real dual-port RAMs for ping-pong read / write operations. The two real dual-port RAMs operate on codewords from different frames, increasing the decoder's throughput.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A QC-LDPC improved decoder to eliminate the waiting period, characterized by: The posterior message storage module, the C2V FIFO, the C2V_RAM, the V2C_signs FIFO, the permutation module, the calculation module, the FIFO cache module, the C2V message recovery module and the inverse permutation module are included. The posterior message storage module includes two real dual-port RAMs, llr_ram_0 and llr_ram_1, which are used for the initial channel message and the updated node posterior message to be accessed in ping-pong mode when two frames of code words are decoded. The C2V_RAM is used for storing the C2V message of the last iteration and the updated C2V message in the current iteration process. The C2V FIFO is used for buffering the negative C2V message read from the C2V_RAM. The permutation module is used for arranging the node V2C message sequence in the order of the corresponding check nodes. The V2C_signs FIFO is used for buffering the sign value of the calculated V2C message into the V2C_signs FIFO, and reading the sign value from the V2C_signs FIFO to calculate the sign value of the C2V message. The calculation module is used for obtaining the minimum value, the second minimum value and the sign XOR value of each row in a layer of CPM according to the V2C message of the layer, and recording the column position of the minimum value. The FIFO cache module is used for buffering the minimum value, the second minimum value, the sign XOR value and the position of the minimum value obtained by the calculation module into the FIFO cache module. The C2V message recovery module is used for outputting the updated C2V message according to the values in the FIFO cache module and the V2C_signs FIFO. The inverse permutation module is used for arranging the updated C2V message sequence in the order of the corresponding variable nodes.

2. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The llr_ram_0 and the llr_ram_1 are instructed by a ping-pong signal to access the initial channel message and the updated node posterior probability message in ping-pong mode between two frames of code words. The width of the two real dual-port RAMs is ZxWidth_APP_LLR, and the depth is N / Z, Z is the size of the CPM constituting the QC-LDPC check matrix, Width_APP_LLR is the width of the posterior probability message of one node, and N is the code length of the QC-LDPC.

3. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The width of the C2V_RAM is ZxWidth_C2V_LLR, and the depth is the total row weight of the QC-LDPC code base matrix, and Width_C2V_LLR is the width of the C2V message of one node.

4. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The permutation module and the inverse permutation module are composed of barrel shifters, which are used for realizing the function of left circular shift.

5. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The width of the V2C_signs FIFO is Z, and the depth is the maximum value of the row weight of the QC-LDPC code base matrix.

6. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The calculation module compares the absolute value of the V2C message.

7. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The width of the FIFO cache module is: Width_sign+Width_min0+Width_idx0+Width_min1 a depth not greater than wherein Width_sign represents a width of a sign XOR value, Width_min0 represents a width of a minimum value, Width_idx0 represents a width of a position of the minimum value, Width_min1 represents a width of a second minimum value, max_row_weight is a maximum row weight of a QC-LDPC code base matrix, and min_row_weight is a minimum row weight of the QC-LDPC code base matrix.

8. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The method for outputting the updated C2V message by the C2V message recovery module is: According to the column position of the minimum value in the FIFO cache module, if the column position of the minimum value is the column block to which the allocated C2V message needs to be transmitted, the second minimum value is allocated, otherwise the minimum value is allocated, and the sign value of the updated C2V message is obtained by XORing the sign in the FIFO cache module and the V2C message sign value output by the V2C_signs FIFO.

9. The QC-LDPC improved decoder without waiting period according to claim 1, characterized in that: The calculation formula of the updated node posterior probability message of the posterior message storage module is: wherein, is the updated node posterior probability message, is the latest node posterior probability message before the update of the posterior message storage module, C2V denotes the message passed from the check node to the variable node, it is the current iteration number, and l is the lth column block of the QC-LDPC check matrix, is the C2V message to be passed from the layer represented by the check node c to the variable node of the lth column block in the itth iteration.

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