Solid-state imaging device

Abstract

The purpose of this invention is to suppress dead time during mode switching. A solid-state imaging device according to the invention includes: a plurality of pixels (300), each pixel outputting a brightness change of incident light; and a detection circuit (305) that outputs an event signal based on the brightness change output from each pixel. Each pixel includes: a photoelectric conversion element (311) for generating charge according to the amount of incident light; a logarithmic conversion circuit (312, 313) connected to the photoelectric conversion element and converting the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent; and a first transistor (318) whose drain is connected to a sensing node of the logarithmic conversion circuit.

Description

Technical Field

[0001] This disclosure relates to solid-state imaging devices and imaging apparatuses. Background Technology

[0002] Conventional technologies related to imaging devices have employed synchronous solid-state imaging devices that capture image data (frames) synchronously with a synchronization signal (such as a vertical synchronization signal). Such typical synchronous solid-state imaging devices can only acquire image data per synchronization signal cycle (e.g., 1 / 60th of a second), making it difficult to handle faster processing when required in fields such as transportation and robotics. To address this problem, a solid-state imaging device has been proposed that detects events where the amount of change in pixel brightness exceeds a threshold for each pixel address as address events (e.g., refer to Patent Document 1). Solid-state imaging devices that detect address events for each pixel in this way are also called event-based vision sensors (EVS) or dynamic vision sensors (DVS).

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: JP 5244587 B2 Summary of the Invention

[0006] Technical issues

[0007] However, in traditional EVS, there are situations where operation becomes unstable due to noise generation and potential fluctuations when switching operating modes.

[0008] In view of this, the present disclosure proposes a solid-state imaging device and an imaging apparatus capable of suppressing the occurrence of unstable operation.

[0009] Solution to the problem

[0010] To address the aforementioned problems, a solid-state imaging apparatus according to one aspect of this disclosure includes: a plurality of pixels, each pixel outputting a brightness change of incident light; and a detection circuit that outputs an event signal based on the brightness change output from each pixel, wherein each pixel includes: a photoelectric conversion element that generates a charge according to the amount of incident light; a logarithmic conversion circuit connected to the photoelectric conversion element and converting the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent; and a first transistor whose drain is connected to a sensing node of the logarithmic conversion circuit. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus according to a first embodiment.

[0012] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state imaging device according to a first embodiment.

[0013] Figure 3 This is an example of a plan view of an optical receiver chip according to the first embodiment.

[0014] Figure 4 This is an example of a plan view of the detection chip according to the first embodiment.

[0015] Figure 5 This is an example of a plan view of the address event detection unit according to the first embodiment;

[0016] Figure 6 This is a circuit diagram showing an example configuration of the logarithmic response unit according to the first embodiment.

[0017] Figure 7 This is a circuit diagram showing another configuration example of the logarithmic response unit according to the first embodiment.

[0018] Figure 8 This is a circuit diagram showing a schematic configuration example of the readout circuit according to the first embodiment.

[0019] Figure 9 This is a circuit diagram showing a schematic configuration example of the response circuit according to the first embodiment.

[0020] Figure 10 This is a block diagram illustrating an example configuration of a detection block according to the first embodiment.

[0021] Figure 11 This is a circuit diagram illustrating an example configuration of a differential according to a first embodiment.

[0022] Figure 12 This is a circuit diagram showing an example configuration of the comparison unit according to the first embodiment.

[0023] Figure 13 This is a circuit diagram illustrating an example configuration of the differential, selector, and comparator according to the first embodiment.

[0024] Figure 14 This is a timing diagram illustrating an example of the control of the row drive circuit in EVS mode according to the first embodiment.

[0025] Figure 15 This is a timing diagram illustrating an example of the control of the row drive circuit in CIS mode according to the first embodiment.

[0026] Figure 16 This is a block diagram illustrating an example configuration of the detection pixel and detection circuit according to the first embodiment.

[0027] Figure 17 This is a flowchart illustrating an example of the operation of a solid-state imaging apparatus according to a first embodiment.

[0028] Figure 18 This is a block diagram illustrating an example configuration of the detection pixel and detection circuit according to a variation of the first embodiment.

[0029] Figure 19 This is a timing diagram illustrating an example of the control of the row drive circuit according to a variation of the first embodiment.

[0030] Figure 20 This is a waveform diagram showing the dead time period during mode transition.

[0031] Figure 21 This is a circuit diagram illustrating an example configuration of the response circuit according to the first embodiment.

[0032] Figure 22 This is a circuit diagram showing an example configuration of the response circuit of a first variant according to the first embodiment.

[0033] Figure 23 This is a circuit diagram showing an example configuration of the response circuit of a second variation of the first embodiment.

[0034] Figure 24 This is a circuit diagram showing an example of the configuration of the response circuit according to a third variation of the first embodiment.

[0035] Figure 25 This is a circuit diagram showing an example of the configuration of the response circuit according to a fourth variation of the first embodiment.

[0036] Figure 26 This is a circuit diagram showing an example of the configuration of the response circuit according to a fifth variation of the first embodiment.

[0037] Figure 27 This is a circuit diagram showing an example of the configuration of the response circuit according to the sixth variation of the first embodiment.

[0038] Figure 28 This is a circuit diagram showing an example of the configuration of the response circuit according to the seventh variation of the first embodiment.

[0039] Figure 29 This is a circuit diagram showing an example of the configuration of the response circuit according to the eighth variation of the first embodiment.

[0040] Figure 30 This is a timing diagram illustrating an example of operation when switching from CIS mode to EVS mode according to the first embodiment.

[0041] Figure 31 This is a flowchart illustrating an operational example of the imaging apparatus according to the first embodiment.

[0042] Figure 32 This is a circuit diagram illustrating an example of the circuit configuration of a shared block according to a first shared example of a first embodiment.

[0043] Figure 33 This is a circuit diagram illustrating an example of the circuit configuration of a shared block according to a second shared example of the first embodiment.

[0044] Figure 34 This is a circuit diagram illustrating an example of the circuit configuration of a shared block according to a third shared example of the first embodiment.

[0045] Figure 35 This is a circuit diagram illustrating an example of the circuit configuration of a shared block according to a fourth shared example of the first embodiment.

[0046] Figure 36 This is a plan view showing a layout example of a shared block according to a first layout example of a first embodiment.

[0047] Figure 37 This is a plan view showing a layout example of a shared block according to a second layout example of the first embodiment.

[0048] Figure 38 This is a timing diagram illustrating an operational example of a first control example according to the second embodiment when transitioning from CIS mode to EVS mode.

[0049] Figure 39 This is a timing diagram illustrating an operational example of a second control example according to the second embodiment when transitioning from CIS mode to EVS mode.

[0050] Figure 40 This is a timing diagram illustrating an operational example of switching from CIS mode to EVS mode according to a third control example of the second embodiment.

[0051] Figure 41 This is a timing diagram illustrating an operational example of the fourth control example according to the second embodiment when transitioning from CIS mode to EVS mode.

[0052] Figure 42 This is a timing diagram illustrating an operational example of the fifth control example according to the second embodiment when switching from CIS mode to EVS mode.

[0053] Figure 43 This is a timing diagram illustrating an operational example of the sixth control example according to the second embodiment when transitioning from CIS mode to EVS mode.

[0054] Figure 44 This is a timing diagram illustrating an operational example of the seventh control example according to the second embodiment when switching from CIS mode to EVS mode.

[0055] Figure 45 This is a circuit diagram illustrating an example configuration of the response circuit according to the third embodiment.

[0056] Figure 46 This is a circuit diagram showing a modified example of the response circuit according to the third embodiment.

[0057] Figure 47 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the third embodiment.

[0058] Figure 48 This is a flowchart illustrating an operational example of the imaging apparatus according to the third embodiment.

[0059] Figure 49 This is a circuit diagram illustrating an example configuration of the response circuit according to the fourth embodiment.

[0060] Figure 50 This is a circuit diagram showing a modified example of the response circuit according to the fourth embodiment.

[0061] Figure 51 This is a timing diagram illustrating an example of operation when switching from CIS mode to EVS mode according to the fourth embodiment.

[0062] Figure 52 This is a flowchart illustrating an operational example of the imaging apparatus according to the fourth embodiment.

[0063] Figure 53 This is an example of a plan view of the detection chip according to the fifth embodiment.

[0064] Figure 54 This is a circuit diagram illustrating an example configuration of a shared block according to the fifth embodiment.

[0065] Figure 55 A circuit diagram illustrating an example of the circuit configuration of a shared block according to a first shared example of a fifth embodiment.

[0066] Figure 56 A circuit diagram illustrating an example of the circuit configuration of a shared block according to a second shared example of a fifth embodiment.

[0067] Figure 57 A circuit diagram illustrating an example of the circuit configuration of a shared block according to a third shared example of a fifth embodiment.

[0068] Figure 58This is a circuit diagram illustrating an example configuration of the response circuit according to the sixth embodiment.

[0069] Figure 59 This is a plan view showing a schematic configuration example of the detection chip in the solid-state imaging apparatus according to the seventh embodiment.

[0070] Figure 60 This is a plan view showing an example layout of a shared block according to a first layout variation of the eighth embodiment.

[0071] Figure 61 This is a plan view showing a layout example of a shared block according to a second layout variation of the eighth embodiment.

[0072] Figure 62 This is a plan view showing an example of the layout of a shared block according to a third layout variation of the eighth embodiment.

[0073] Figure 63 This is a plan view showing an example of the layout of the shared block in the fourth layout variation according to the eighth embodiment.

[0074] Figure 64 This is a plan view showing an example of the layout of a shared block according to the fifth layout variation of the eighth embodiment.

[0075] Figure 65 This is a plan view showing a layout example of a shared block according to the sixth layout variation of the eighth embodiment.

[0076] Figure 66 This is a plan view showing an example of the layout of the shared block in the seventh layout variation according to the eighth embodiment.

[0077] Figure 67 This is a cross-sectional view showing the wiring structure of a first example according to the ninth embodiment.

[0078] Figure 68 This is a cross-sectional view showing the wiring structure of a second example according to the ninth embodiment.

[0079] Figure 69 This is a cross-sectional view showing the wiring structure of a third example according to the ninth embodiment.

[0080] Figure 70 This is a cross-sectional view showing the wiring structure of the fourth example according to the ninth embodiment.

[0081] Figure 71 This is a plan view showing an example of the wiring layout of the first wiring layer according to the ninth embodiment.

[0082] Figure 72This is a plan view showing an example of the wiring layout of the second wiring layer according to the ninth embodiment.

[0083] Figure 73 This is a plan view showing an example of the wiring layout of the third wiring layer according to the ninth embodiment.

[0084] Figure 74 This is a plan view showing an example of the wiring layout of the fourth wiring layer according to the ninth embodiment.

[0085] Figure 75 It shows along Figures 71 to 74 A cross-sectional view of an example structure cut by line A-A' in the diagram.

[0086] Figure 76 This is a plan view showing an example of the wiring layout of the first wiring layer according to a variation of the ninth embodiment.

[0087] Figure 77 This is a diagram illustrating an example of the circuit configuration of the shared block shown in the tenth embodiment.

[0088] Figure 78 This is a diagram illustrating an example of the connection between the transmission transistor / switching transistor and each drive line as shown in the tenth embodiment.

[0089] Figure 79 This is a cross-sectional view showing an example of a wiring structure according to the tenth embodiment.

[0090] Figure 80 This is a plan view showing an example of the wiring layout of the first wiring layer according to the first embodiment.

[0091] Figure 81 This is a plan view showing an example of the wiring layout of the second wiring layer according to the first embodiment.

[0092] Figure 82 This is a plan view showing an example of the wiring layout of the third wiring layer according to the first embodiment.

[0093] Figure 83 This is a plan view showing an example of the wiring layout of the fourth wiring layer according to the first embodiment.

[0094] Figure 84 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0095] Figure 85 This is an example diagram illustrating the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0096] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. In each of the following embodiments, the same components are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0097] This disclosure will be described in the following order.

[0098] 1. First Implementation Method

[0099] 1.1 Example of Imaging Device Configuration

[0100] 1.2 Configuration Example of Solid State Imaging Device

[0101] 1.3 Configuration Example of Logarithmic Response Unit

[0102] 1.3.1 Variation of the logarithmic response unit

[0103] Example of 1.4 pixel circuit configuration

[0104] 1.5 Basic Configuration Example of Response Circuit

[0105] 1.6 Configuration Example of Detection Block

[0106] 1.6.1 Configuration examples of differentials, selectors, and comparators

[0107] 1.7 Example of line drive circuit control

[0108] 1.7.1 EVS Mode

[0109] 1.7.2 CIS Mode

[0110] 1.8 Example of Pixel and Circuit Detection Configuration

[0111] 1.8.1 Operational Example of Solid State Imaging Device in EVS Mode

[0112] 1.9 Modifications to the detection pixel and detection circuit

[0113] 1.9.1 Control Example of Horizontal Drive Circuit According to the Modified Example

[0114] Dead zone during 1.10 mode transition

[0115] 1.11 Example of Response Circuit Configuration

[0116] 1.12 Modified Examples of Response Circuits

[0117] 1.12.1 First Variation Example

[0118] 1.12.2 Second Variation Example

[0119] 1.12.3 Third Variation Example

[0120] 1.12.4 Fourth Variation Example

[0121] 1.12.5 Fifth Variation

[0122] 1.12.6 Sixth Variation

[0123] 1.12.7 Seventh Variation

[0124] 1.12.8 Eighth Variation

[0125] 1.13 The shift from CIS model to EVS model

[0126] 1.14 Operating Procedures

[0127] 1.15 Circuit Sharing

[0128] 1.15.1 First Shared Example

[0129] 1.15.2 Second Shared Example

[0130] 1.15.3 Third Shared Example

[0131] 1.15.4 Fourth Shared Example

[0132] 1.16 Merging mode and full-pixel mode using circuit sharing 1.17 Layout of shared blocks

[0133] 1.17.1 First Layout Example

[0134] 1.17.2 Example of the Second Layout

[0135] 1.18 Functions and Effects

[0136] 2. Second Implementation Method

[0137] 2.1 First Control Example

[0138] 2.2 Second Control Example

[0139] 2.3 Example of Third Control

[0140] 2.4 Fourth Control Example

[0141] 2.5 Fifth Control Example

[0142] 2.6 Sixth Control Example

[0143] 2.7 Seventh Control Example

[0144] 2.8 Functions and Effects

[0145] 3. Third Implementation Method

[0146] 3.1 Example of Response Circuit Configuration

[0147] 3.1.1 Variations of the response circuit

[0148] 3.2 The shift from CIS model to EVS model

[0149] 3.3 Operating Procedures

[0150] 3.4 Functions and Effects

[0151] 4. Fourth Implementation Method

[0152] 4.1 Example of Response Circuit Configuration

[0153] 4.1.1 Variations of the response circuit

[0154] 4.2 The shift from CIS model to EVS model

[0155] 4.3 Operating Procedures

[0156] 4.4 Functions and Effects

[0157] 5. Fifth Implementation Method

[0158] 5.1 Example of chip layout

[0159] 5.2 Basic Configuration Example of Shared Blocks

[0160] 5.3 Circuit Sharing Merging Mode

[0161] 5.3.1 First Shared Example

[0162] 5.3.2 Second Shared Example

[0163] 5.3.3 Third Shared Example

[0164] 5.4 Functions and Effects

[0165] 6. Sixth Implementation Method

[0166] 6.1 Example of Response Circuit Configuration

[0167] 6.2 Functions and Effects

[0168] 7. Seventh Implementation Method

[0169] 8. Eighth Implementation Method

[0170] 8.1 Example of a variation of the first layout

[0171] 8.2 Second Layout Variation Example

[0172] 8.3 Third Layout Variation Example

[0173] 8.4 Fourth Layout Variation Example

[0174] 8.5 Fifth Layout Variation Example

[0175] 8.6 Sixth Layout Variation Example

[0176] 8.7 Seventh Layout Variation Example

[0177] 9. Ninth Implementation Method

[0178] 9.1 Wiring Structure Example

[0179] 9.2 Effect

[0180] 9.3 Specific examples of wiring layout

[0181] 10. Tenth Implementation Method

[0182] 10.1 Example of cross-sectional structure and wiring layout

[0183] 11. Examples of application to moving bodies

[0184] 1. First Implementation Method

[0185] First, the first embodiment will be described in detail with reference to the accompanying drawings. In the EVS, by switching the number of photoelectric conversion elements used when detecting an address event, various operating modes can be implemented to change the sensitivity and resolution regarding the address event. Furthermore, by incorporating a readout circuit for generating grayscale data from the photoelectric conversion elements, an operating mode for generating grayscale or color image data can be implemented in addition to the address event detection operating mode.

[0186] However, when switching operating modes in a conventional EVS, the potential of the sensing node in the circuit used to detect address events sometimes deviates from the expected range. This deviation of the sensing node's potential from the normal range causes the address event detection to fail. Therefore, conventional EVSs have a dead time period, during which an address event cannot be detected until the sensing node's potential stabilizes within the normal range.

[0187] In view of this, this embodiment proposes a solid-state imaging device and an imaging device capable of suppressing the dead time period during mode switching.

[0188] 1.1 Example of Imaging Device Configuration

[0189] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus 100 according to a first embodiment of the present disclosure. The imaging apparatus 100 includes an optical unit 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. Examples of the imaging apparatus 100 are assumed to include devices such as cameras mounted on industrial robots and vehicle-mounted cameras.

[0190] The optical unit 110 converges the incident light and guides it to the solid-state imaging device 200. The solid-state imaging device 200 photoelectrically converts the incident light to generate image data. The solid-state imaging device 200 performs predetermined signal processing (such as image recognition processing) on ​​the generated image data and outputs the processed data to the recording unit 120 via the signal line 209.

[0191] For example, the recording unit 120 includes a device such as flash memory, and records data output from the solid-state imaging device 200 and data output from the control unit 130.

[0192] For example, the control unit 130 includes an information processing device such as an application processor, and controls the solid-state imaging device 200 to output image data.

[0193] 1.2 Configuration Example of Solid State Imaging Device

[0194] (Example of a stacked structure)

[0195] Figure 2 This is a diagram illustrating an example of the stacked structure of a solid-state imaging device 200 according to this embodiment. The solid-state imaging device 200 includes a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. These chips are electrically connected to each other via connection portions such as through-holes. In addition to through-holes, Cu-Cu bonding or bumps can be used for connection. For example, the light-receiving chip 201 may be an example of the first chip in the claim, and the detection chip 202 may be an example of the second chip in the claim.

[0196] (Layout example of an optical receiver chip)

[0197] Figure 3 This is an example of a plan view of a light receiving chip according to this embodiment. The light receiving chip 201 includes a light receiving section 220 and through-hole arrangement sections 211, 212 and 213.

[0198] Through-hole arrangement sections 211, 212, and 213 are sections where through-holes connected to the detection chip 202 are arranged. The light receiving section 220 is where a plurality of shared blocks 221 are arranged in a two-dimensional grid pattern.

[0199] In each shared block 221, one or more response circuits 301 are arranged. For example, four response circuits 301 are arranged in a 2-row × 2-column pattern for each shared block 221. These four response circuits 301 share the circuitry on the detection chip 202. Details of the shared circuitry will be described below. Note that the number of response circuits 301 in the shared block 221 is not limited to four. Furthermore, some or all of the circuitry configuration, excluding the photoelectric conversion element 311, in each response circuit 301 may be arranged on the detection chip 202 side.

[0200] As described below, the response circuit 301 includes: a logarithmic response unit 310, which converts the photocurrent flowing from the photoelectric conversion element 311 into a voltage signal VPR based on the logarithmic value; and a pixel circuit 370, which generates a pixel signal (corresponding to grayscale data) with a voltage value based on the amount of charge accumulated in the photoelectric conversion element 311.

[0201] Pixel addresses, including row and column addresses, are assigned to each response circuit 301. It should be noted that pixels in this disclosure may have a configuration based on the photoelectric conversion element 311 described below, and in this embodiment, for example, may have a configuration referred to as detection pixels and / or grayscale pixels, as described below.

[0202] (Layout example of a detection chip)

[0203] Figure 4 This is an example of a plan view of the detection chip according to this embodiment. The detection chip 202 includes via arrangement portions 231, 232, and 233, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252, an address event detection unit 260, and a column analog-to-digital converter (column ADC) 270. The via arrangement portions 231, 232, and 233 are portions that arrange vias connected to the optical receiving chip 201.

[0204] Address event detection unit 260 detects the presence or absence of address events in each response circuit 301 (more specifically, each logarithmic response unit 310) and generates a detection signal indicating the detection result.

[0205] The row drive circuit 251 selects the row address and causes the address event detection unit 260 to output a detection signal corresponding to the row address.

[0206] The column drive circuit 252 selects the column address and causes the address event detection unit 260 to output a detection signal corresponding to the column address.

[0207] The signal processing circuit 240 performs predetermined signal processing on the detection signal output from the address event detection unit 260. The signal processing circuit 240 arranges the detection signal as pixel signals into a two-dimensional lattice pattern and generates image data with 2 bits of information for each pixel. The signal processing circuit 240 then performs signal processing such as image recognition processing on the image data.

[0208] Furthermore, the column ADC 270 includes, for example, an AD converter corresponding one-to-one with each vertical signal line VSL provided for each response circuit 301 (more specifically, each pixel circuit 370), and performs analog-to-digital (AD) conversion on the analog pixel signal input from each pixel circuit 370 via the vertical signal lines VSL. The column ADC 270 then provides the digital signal, which has undergone AD conversion, to the signal processing circuit 240. The signal processing circuit 240 performs predetermined image processing on the image data including the digital signal. It should be noted that the column ADC 270 may include, for example, correlated double sampling (CDS) circuitry and may reduce kTC noise included in the digital pixel signal.

[0209] (Layout example of a detection chip)

[0210] Figure 5 This is an example of a plan view of the address event detection unit 260 according to this embodiment. The address event detection unit 260 is a portion in which a plurality of detection blocks 320 are arranged. Detection blocks 320 are arranged on the optical receiver chip 201 for each shared block 221. When the number of shared blocks 221 is N (N is an integer), N detection blocks 320 are arranged. Each detection block 320 is connected to a corresponding shared block 221.

[0211] 1.3 Configuration Example of Logarithmic Response Unit

[0212] Figure 6 This is a circuit diagram illustrating a basic configuration example of the logarithmic response unit according to this embodiment. (As shown...) Figure 6 As shown, the logarithmic response unit 310 included in the response circuit 301 includes a photoelectric conversion element 311, n-channel metal-oxide-semiconductor (nMOS) transistors 312 and 313, and a p-channel MOS (pMOS) transistor 314. The two nMOS transistors 312 and 313, for example, constitute a logarithmic conversion circuit that converts the photocurrent flowing from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value of the photocurrent. The wiring connected to the gate of the nMOS transistor 313 and the wiring through which the photocurrent from the photoelectric conversion element 311 flows serve as a sensing node SN when an address event is detected. The nMOS transistor 313 may, for example, correspond to the second transistor in the claim, and the nMOS transistor 312 may, for example, correspond to the third transistor in the claim.

[0213] Furthermore, pMOS transistor 314 operates as a load MOS transistor for a logarithmic conversion circuit that includes two nMOS transistors 312 and 313. Note that photoelectric conversion element 311 and nMOS transistors 312 and 313 can, for example, be arranged on photoreceiver chip 201, and pMOS transistor 314 can be arranged on detection chip 202.

[0214] The nMOS transistor 312 has a source connected to the cathode of the photoelectric conversion element 311 and a drain connected to the power supply terminal. The pMOS transistor 314 and the nMOS transistor 313 are connected in series between the power supply terminal and the ground terminal. Furthermore, the connection point of the pMOS transistor 314 and the nMOS transistor 313 is connected to the gate of the nMOS transistor 312 and the input terminal of the detection block 320, and serves as the output node for outputting the voltage signal VPR to the detection block 320. Additionally, a predetermined bias voltage Vbias1 is applied to the gate of the pMOS transistor 314.

[0215] The drains of nMOS transistors 312 and 313 are connected to the power supply side, and such a circuit is called a source follower. The two source followers connected in a ring convert the photocurrent from photoelectric conversion element 311 into a voltage signal VPR corresponding to its logarithm. Furthermore, pMOS transistor 314 provides a constant current to nMOS transistor 313.

[0216] Note that the grounding of the optical receiver chip 201 and the grounding of the detection chip 202 can be isolated from each other to combat interference.

[0217] 1.3.1 Variation of the logarithmic response unit

[0218] although Figure 6 This is an example of the configuration of the source follower type logarithmic response section 310, but the configuration of this section is not limited to this example. Figure 7 This is a circuit diagram illustrating a basic configuration example of the logarithmic response unit according to a modified example of this embodiment. For example... Figure 7 As shown, for example, the logarithmic response unit 310A has a configuration known as a gain boost circuit configuration, and... Figure 6 Compared to the source follower type circuit configuration shown, Figure 7 The logarithmic response unit 310A includes an additional nMOS transistor 315 connected in series between nMOS transistor 312 and the power supply line, and an additional nMOS transistor 316 connected in series between nMOS transistor 313 and pMOS transistor 314. The four nMOS transistors 312, 313, 315 and 316 constitute, for example, a logarithmic conversion circuit that converts the photocurrent flowing from photoelectric conversion element 311 into a voltage signal VPR according to the logarithmic value of the photocurrent.

[0219] In this way, even when using a gain boost type logarithmic response unit 310A, the photocurrent from the photoelectric conversion element 311 can be converted into a logarithmic voltage signal VPR corresponding to the amount of charge.

[0220] Example of 1.4 pixel circuit configuration

[0221] Figure 8This is a circuit diagram illustrating a schematic configuration example of the pixel circuit according to this embodiment. (e.g.) Figure 8 As shown, the pixel circuit 370 in the response circuit 301 includes a transfer transistor 372, a reset transistor 373, an amplification transistor 375, and a selection transistor 376. A node connected to the drain of the transfer transistor 372, the source of the reset transistor 373, and the gate of the amplification transistor 375 serves as a floating diffusion region (FD) 374 with a current-to-voltage conversion function (i.e., the function of converting accumulated charge into a voltage corresponding to the amount of charge). The transfer transistor 372 may, for example, correspond to the fifth transistor of claim 5.

[0222] The pixel circuit 370 shares the photoelectric conversion element 311 with the logarithmic response unit 310 / 310A in the same response circuit 301, and operates to generate grayscale pixels of pixel signals based on the amount of light received by the photoelectric conversion element 311.

[0223] For example, the drain of reset transistor 373 and the drain of amplification transistor 375 are connected to the power supply voltage VDD. However, the drain of reset transistor 373 may be connected to a reset voltage, for example, different from the power supply voltage VDD. The source of amplification transistor 375 is connected to the drain of selection transistor 376, and the source of selection transistor 376 is connected to the vertical signal line VSL for inputting analog pixel signals to the column ADC 270 described below.

[0224] When a pixel signal is read, a high-level transmission signal TRG is applied from the row drive circuit 251 to the gate of the transmission transistor 372. This turns on the transmission transistor 372, causing the charge accumulated in the cathode of the photoelectric conversion element 311 to be transferred through the transmission transistor 372 to the floating diffusion region 374. As a result, a pixel signal with a voltage value corresponding to the amount of charge accumulated in the floating diffusion region 374 appears at the source of the amplifying transistor 375. Subsequently, by setting the selection signal SEL applied from the row drive circuit 251 to the gate of the selection transistor 376 to a high level, the pixel signal appearing at the source of the amplifying transistor 375 appears in the vertical signal line VSL.

[0225] Furthermore, when the charge accumulated in the floating diffusion region 374 is released to reset the floating diffusion region 374, a high-level reset signal RST is applied from the row drive circuit 251 to the gate of the reset transistor 373. This allows the charge accumulated in the floating diffusion region 374 to be released to the power supply side through the reset transistor 373 (FD reset). At this time, the charge accumulated in the cathode of the photoelectric conversion element 311 can also be released to the power supply side by turning on the transmission transistor 372 during the same cycle (PD reset).

[0226] In each shared block 221, the number of photoelectric conversion elements 311 simultaneously connected to the pixel circuit 370 when reading grayscale image data, i.e., the number of transmission transistors 372 turned on during the same period, is not limited to one, but can be multiple. For example, when reading high-resolution grayscale image data in each shared block 221, the transmission transistors 372 can be sequentially connected to the pixel circuit 370 in a time-division manner, and when reading is performed with an extended dynamic range under low brightness conditions (during merging), two or more transmission transistors 372 can be turned on during the same period.

[0227] 1.5 Basic Configuration Example of Response Circuit

[0228] Next, a basic configuration example of the response circuit 301, including the logarithmic response unit 310 / 310A and the pixel circuit 370, will be described. Figure 9 This is a circuit diagram illustrating a basic configuration example of the response circuit according to this embodiment. Although the following description is an exemplary case using the logarithmic response unit 310A, the configuration is not limited thereto, and various circuits, such as the logarithmic response unit 310, can be used to convert the photocurrent from the photoelectric conversion element 311 into a logarithmic voltage signal VPR according to the amount of charge.

[0229] like Figure 9 As shown, the response circuit 301 according to this embodiment has wherein Figure 7 The logarithmic response unit 310A shown is Figure 8 The pixel circuit 370 shown shares the configuration of the photoelectric conversion element 311. However, the response circuit 301 also includes a switching transistor 317 for switching between EVS mode and CIS mode. The switching transistor 317 may be, for example, an nMOS transistor. The switching transistor 317 may, for example, correspond to the fourth transistor in the claim.

[0230] In EVS mode, for example, the row drive circuit 251 constantly applies a high-level switching signal to the gate of the switching transistor 317. On the other hand, for example, the row drive circuit 251 constantly applies a low-level transmission signal TRG to the gate of the transmission transistor 372. This results in the formation of a current path for the photocurrent flowing from the photoelectric conversion element 311 to the sensing node SN side through the switching transistor 317.

[0231] On the other hand, in CIS mode, for example, a low-level switching signal is constantly applied from the row drive circuit 251 to the gate of the switching transistor 317. On the other hand, for example, a high-level transmission signal TRG, indicating a predetermined control operation, is applied from the row drive circuit 251 to the gate of the transmission transistor 372. Using this operation, the charge accumulated in the photoelectric conversion element 311 is transferred to the floating diffusion region 374 of the pixel circuit 370 at a predetermined timing.

[0232] 1.6 Configuration Example of Detection Block

[0233] Figure 10 This is a block diagram illustrating an example configuration of the detection block 320 according to this embodiment. The detection block 320 includes a plurality of buffers 330, a plurality of differentials 340, a selection unit 400, a comparison unit 500, and a transmission circuit 360. The buffers 330 and differentials 340 are provided for each logarithmic response unit 310 in the shared block 221. For example, when there are four logarithmic response units 310 in the shared block 221, four buffers 330 and four differentials 340 are arranged.

[0234] The buffer 330 outputs the voltage signal from the corresponding logarithmic response unit 310 to the differential unit 340. The buffer 330 can improve the driving force used to drive subsequent stages. In addition, the buffer 330 can ensure isolation from noise associated with switching operations in subsequent stages.

[0235] Differential converter 340 obtains the change in voltage signal, that is, the change in brightness of light incident on photoelectric conversion element 311, as a differential signal. Differential converter 340 receives voltage signal from corresponding logarithmic response unit 310 through buffer 330 and obtains the change in voltage signal through differential processing. Subsequently, differential converter 340 supplies differential signal to selection unit 400. The m-th differential signal Sin (m is an integer from 1 to M) in detection block 320 is defined as Simm. For example, differential converter 340 may correspond to the first circuit in claim 1.

[0236] The selection unit 400 selects one of the M differential signals based on the selection signal from the line drive circuit 251. The selection unit 400 includes selectors 410 and 420.

[0237] M differential signals Sin are input to selector 410. Selector 410 selects one of these differential signals Sin according to a selection signal and supplies the selected differential signal Sin as Sout+ to comparator 500. M differential signals Sin are also input to selector 420. Selector 420 selects one of these differential signals Sin according to a selection signal and supplies the selected differential signal Sin as Sout- to comparator 500.

[0238] The comparison unit 500 compares the differential signal (i.e., the amount of change) selected by the selection unit 400 with a predetermined threshold. The comparison unit 500 provides a signal representing the comparison result as a detection signal to the transmission circuit 360. For example, the comparison unit 500 may correspond to the second circuit in the claim.

[0239] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 based on the column drive signal from the column drive circuit 252.

[0240] (Differentizer configuration example)

[0241] Figure 11 This is a circuit diagram illustrating an example configuration of the differential 340 according to this embodiment. The differential 340 includes capacitors 341 and 343, an inverter 342, and a switch 344.

[0242] One end of capacitor 341 is connected to the output of buffer 330, and the other end is connected to the input of inverter 342. Capacitor 343 is connected in parallel to inverter 342. Switch 344 opens and closes the path connecting the two ends of capacitor 343 according to the row drive signal.

[0243] Inverter 342 inverts the voltage signal input through capacitor 341. Inverter 342 outputs the inverted signal to selection unit 400.

[0244] When switch 344 is turned on, the voltage signal V init The input is given to the buffer 330 side of capacitor 341, making the opposite side a virtual ground terminal. For convenience, assume the potential of the virtual ground terminal is zero. At this time, when the capacitance of capacitor 341 is C1, the accumulated potential Q in capacitor 341... init This is expressed by the following formula (1). On the other hand, since the two ends of capacitor 343 are short-circuited, the accumulated charge is 0.

[0245] Q init =C1×V init (1)

[0246] Next, assume that switch 344 is open and the voltage on the buffer 330 side of capacitor 341 becomes voltage V. after The charge Q accumulated in capacitor 341 after It is represented by the following formula (2).

[0247] Q after =C1×V after (2)

[0248] On the other hand, when the output voltage is V after At that time, the charge Q2 accumulated in capacitor 343 is represented by the following formula (3).

[0249] Q2=-C2×V out (3)

[0250] At this time, since the total charge of capacitors 341 and 343 does not change, the following formula (4) holds true.

[0251] Q init =Q after +Q2 (4)

[0252] When equations (1) to (3) are substituted into equation (4), the result can be transformed into the following equation (5).

[0253] V out =-(C1 / C2)×(V) after -V init (5)

[0254] Equation (5) represents the subtraction operation of the voltage signal, where the gain of the subtraction result is C1 / C2. Since maximum gain is generally desirable, it is preferable to design C1 to be large and C2 to be small. On the other hand, an excessively small C2 will increase kTC noise and lead to a deterioration in noise characteristics. Therefore, the reduction in the capacitance of C2 is limited to the noise tolerance range. Furthermore, since a differential 340 is provided for each pixel, capacitors C1 and C2 have area limitations. Taking these into consideration, for example, C1 is set to a value of 20 to 200 femtofarads (fF), and C2 is set to a value of 1 to 20 femtofarads (fF).

[0255] (Configuration example of the comparison section)

[0256] Figure 12 This is a circuit diagram showing an example configuration of the comparison unit 500 according to this embodiment. The comparison unit 500 includes comparators 510 and 520.

[0257] Comparator 510 compares the differential signal Sout+ from selector 410 with a predetermined upper limit threshold Vrefp. Comparator 510 provides the comparison result as a detection signal DET+ to transmission circuit 360. The detection signal DET+ indicates whether an on event exists. Here, an on event indicates an event where the change in brightness exceeds the predetermined upper limit threshold.

[0258] Comparator 520 compares the differential signal Sout- from selector 420 with the lower threshold Vrefn, which is below the upper threshold Vrefp. Comparator 520 provides the comparison result as a detection signal DET- to transmission circuit 360. The detection signal DET- indicates the presence or absence of a shutdown event. Here, a shutdown event represents an event where the change in brightness is less than a predetermined lower threshold. It should be noted that although comparator 500 detects both the presence and absence of an on / off event, it may also detect only one of the on / off events.

[0259] It should be noted that, for example, comparator 510 may be an example of the first comparator described in the claims, and comparator 520 may be an example of the second comparator described in the claims. For example, the upper threshold may be an example of the first threshold described in the claims, and the lower threshold may be an example of the second threshold described in the claims.

[0260] 1.6.1 Configuration examples of differentials, selectors, and comparators

[0261] Figure 13 This is a circuit diagram showing an example configuration of the differential 340, selector 410, and comparator 510 in the detection block 320 according to this embodiment.

[0262] Differential transistor 340 includes capacitors 341 and 343, pMOS transistors 345 and 346, and nMOS transistor 347. pMOS transistors 345 and 347 are connected in series between the power supply terminal and the ground terminal, with pMOS transistor 345 as the power supply side. Capacitor 341 is inserted between the gate of pMOS transistor 345 / nMOS transistor 347 and the buffer 330. The connection point of pMOS transistors 345 and 347 is connected to selector 410. With this connection configuration, pMOS transistors 345 and 347 function as inverter 342.

[0263] Furthermore, capacitor 341 and pMOS transistor 345 are connected in parallel between the junction of pMOS transistor 346 and nMOS transistor 347 and capacitor 343. pMOS transistor 346 serves as switch 344.

[0264] In addition, selector 410 is provided with multiple pMOS transistors 411. PMOS transistors 411 are arranged for each differential 340.

[0265] pMOS transistors 411 are inserted between the corresponding differential 340 and comparator 510. Furthermore, a selection signal SEL is individually input to the gate of each pMOS transistor 411. The selection signal SEL of the m-th pMOS transistor 411 is called SELm. Through these selection signals SEL, the row drive circuit 251 can control the switching on of one of the M pMOS transistors 411 and the switching off of the remaining transistors. Additionally, the differential signal Sout+ is output to comparator 510 as a selection signal through the pMOS transistor 411 in the on state. Note that the circuit configuration of selector 420 is similar to that of selector 410.

[0266] Comparator 510 includes a pMOS transistor 511 and an nMOS transistor 512. The pMOS transistor 511 and nMOS transistor 512 are connected in series between a power supply terminal and a ground terminal. Furthermore, a differential signal Sout+ is input to the gate of the pMOS transistor 511, while the upper threshold voltage Vrefp is input to the gate of the nMOS transistor 512. A detection signal DET+ is output from the junction of the pMOS transistor 511 and the nMOS transistor 512. Note that the circuit configuration of comparator 520 is similar to that of comparator 510.

[0267] It should be noted that the circuit configurations of the differential 340, selector 410, and comparator 510 are not limited to those specified in the original text. Figure 13 The circuit configurations shown herein, provided they have a reference Figure 10 The described function is sufficient. For example, nMOS transistors and pMOS transistors are interchangeable.

[0268] 1.7 Example of line drive circuit control

[0269] Next, a control example of the row drive circuit 251 according to this embodiment will be described. In this embodiment, the row drive circuit 251 performs the operation of switching between an operation mode for detecting address events (hereinafter referred to as EVS mode) and an operation mode for acquiring grayscale or color image data (hereinafter referred to as grayscale image data) (hereinafter referred to as CIS mode).

[0270] 1.7.1 EVS Mode

[0271] Figure 14 This is a timing diagram illustrating an example of the control of the row drive circuit in EVS mode according to this embodiment. At time T0, the row drive circuit 251 selects the first row via the row drive signal L1 and drives the differential 340 of the selected row. The row drive signal L1 initializes the capacitor 343 in the differential 340 of the first row. Furthermore, the row drive circuit 251 selects the upper left of the 2-row × 2-column pattern in the shared block 221 via the selection signal SEL1 for a certain period of time and drives the selection unit 400. Through this drive, the presence or absence of address events is detected in the odd-numbered columns of the first row.

[0272] Next, at time T1, the row drive circuit 251 drives the differential 340 of the first row again via the row drive signal L1. Furthermore, the row drive circuit 251 selects the upper right corner of the 2-row × 2-column pattern in the shared block 221 within a certain time period via the selection signal SEL2. Therefore, the presence or absence of address events is detected in the even-numbered columns of the first row.

[0273] At time T2, the row drive circuit 251 drives the differential 340 in the second row via the row drive signal L2. The row drive signal L2 initializes the capacitor 343 in the differential 340 in the second row. Furthermore, the row drive circuit 251 selects the lower left of the 2-row × 2-column pattern in the shared block 221 via the selection signal SEL3 for a certain period of time. This drive is used to detect the presence or absence of address events in the odd-numbered columns of the second row.

[0274] Subsequently, at time T3, the row drive circuit 251 drives the differential 340 in the second row again via the row drive signal L2. Furthermore, the row drive circuit 251 selects the lower right corner of the 2-row × 2-column pattern in the shared block 221 for a certain time period via the selection signal SEL4. Therefore, the presence or absence of address events is detected in the even-numbered columns of the second row.

[0275] Subsequently, similarly, the row driving circuit 251 sequentially selects the rows in which the response circuit 301 is arranged, and drives the selected rows via the row driving signal. Furthermore, each time a row is selected, the row driving circuit 251 sequentially selects each detection pixel 300 in the shared block 221 of the selected row via the selection signal. For example, in the case where the detection pixels 300 are arranged in a 2-row × 2-column pattern in the shared block 221, each time a row is selected, the odd-numbered columns and even-numbered columns in that row are selected sequentially.

[0276] Note that the row driving circuit 251 can also sequentially select rows in which the shared block 221 is arranged (in other words, the two rows of the response circuit 301). In this case, each time a row is selected, four detection pixels in the shared block 221 of that row are selected in sequence.

[0277] 1.7.2 CIS Mode

[0278] Figure 15 This is a timing diagram illustrating an example of control of the row drive circuit in CIS mode according to this embodiment. (e.g.) Figure 15 As shown, the line drive circuit 251 first resets the charge accumulated in the photoelectric conversion element 311. Specifically, during the time period from time T11 to T12, the line drive circuit 251 sets the reset signal RST and the transmission signal TRG to a high level, thereby releasing the charge accumulated in the photoelectric conversion element 311 to the power supply (VDD) side through the transmission transistor 372 and the reset transistor 373 (PD reset).

[0279] Next, for example, the row drive circuit 251 sets the selection signal SEL high at time T13 and sets the reset signal RST high during the time period between time T13 and T14. This allows the charge accumulated in the floating diffusion region 374 to be released to the power supply (VDD) side through the reset transistor 373, thereby resetting the floating diffusion region 374 (FD reset).

[0280] During the subsequent time period from time T14 to T15, the potential appearing in the vertical signal line VSL in the state where the floating diffusion region 374 is reset is read by the column ADC 270 as a pixel signal (also known as a reset signal) at the reset level (reset level readout). For example, the read reset signal is used for CDS processing in the column ADC 270.

[0281] Next, the line drive circuit 251 sets the transfer signal TRG to a high level during the time period from T15 to T16. This allows the charge accumulated in the photoelectric conversion element 311 to be transferred to the floating diffusion region 374 through the transfer transistor 372. It should be noted that the time period from the falling point of the reset signal RST at time T12 to the rising point of the transfer signal TRG at time T15 is the accumulation period (also known as the exposure period), during which the charge generated by photoelectric conversion accumulates in the photoelectric conversion element 311.

[0282] The subsequent time period from time T16 to T17 is the period during which the charge transferred from the photoelectric conversion element 311 is accumulated in the floating diffusion region 374. In other words, it is the period during which the pixel signal, whose potential appears in the vertical signal line VSL, is read by the column ADC 270 as the signal level, while a voltage based on the amount of charge (i.e., the amount of charge transferred from the photoelectric conversion element 311) is applied to the gate of the amplifying transistor 375. Note that the column ADC 270 performs CDS processing on the pixel signal read during the time period from time T16 to time T17 using an earlier read reset signal, thereby generating a pixel signal with kTC noise and other noise removed.

[0283] 1.8 Example of Pixel and Circuit Detection Configuration

[0284] Figure 16 This is a block diagram illustrating an example configuration of the detection pixel 300 and the detection circuit 305 according to this embodiment. In the detection block 320, which is shared by multiple logarithmic response units 310 in the shared block 221, a circuit including a selection unit 400, a comparison unit 500, and a transmission circuit 360 is defined as the detection circuit 305. Furthermore, a circuit including a logarithmic response unit 310, a buffer 330, and a differential 340 is defined as the detection pixel 300. As shown, the detection circuit 305 is shared by multiple detection pixels 300.

[0285] Each of the plurality of detection pixels 300 in the shared detection circuit 305 generates a voltage signal corresponding to the logarithmic value of the photocurrent. Subsequently, each of the detection pixels 300 outputs a differential signal Sin, indicating the amount of change in the voltage signal, to the detection circuit 305 according to the row drive signal. In each detection pixel 300, the logarithmic response unit 310 generates a voltage signal corresponding to the logarithmic value, while the differential unit 340 generates a differential signal.

[0286] Selection signals such as selection signals SEL1 and SEL2 are commonly input to selectors 410 and 420 in detection circuit 305. Detection circuit 305 selects the differential signal (i.e., change amount) of the detection pixel indicated by the selection signal from a plurality of detection pixels 300, and detects whether the change amount exceeds a predetermined threshold. Detection circuit 305 then transmits the detection signal to signal processing circuit 240 according to a column drive signal. In detection circuit 305, the differential signal is selected by selection unit 400, and a comparison with a threshold is performed by comparison unit 500. Furthermore, the detection signal is transmitted by transmission circuit 360.

[0287] Here, in a typical DVS, the comparator 500 and transmission circuit 360 are arranged together with the logarithmic response unit 310, buffer 330, and differential 340 for each detected pixel. Conversely, in the above configuration where the detection circuit 305, including the comparator 500 and transmission circuit 360, is shared by multiple detected pixels 300, the circuit size of the solid-state imaging device 200 can be reduced compared to a case where the detection circuit is not shared. This facilitates the micro-manufacturing of pixels.

[0288] When a stacked structure is specifically employed, using a conventional configuration without a shared detection circuit 305 results in a larger circuit size for the detection chip 202 compared to the light receiver chip 201. With this configuration, pixel microfabrication is difficult due to the circuitry on the detection chip 202 limiting pixel density. However, by using a configuration where multiple detection pixels 300 share the detection circuit 305, the circuit size of the detection chip 202 can be reduced, facilitating pixel microfabrication.

[0289] Although a buffer 330 is arranged for each detected pixel 300, the configuration is not limited to this configuration, and the buffer 330 may also be omitted.

[0290] Furthermore, although the photoelectric conversion element 311 and nMOS transistors 312 and 313 of the logarithmic response unit 310 are arranged on the light receiving chip 201, and the pMOS transistor 314 and subsequent transistors are arranged on the detection chip 202, the configuration is not limited to this example. For example, the photoelectric conversion element 311 may be arranged solely on the light receiving chip 201, and other devices may be arranged on the detection chip 202. Alternatively, the logarithmic response unit 310 may be arranged solely on the light receiving chip 201, and the buffer 330 and subsequent devices may be arranged on the detection chip 202. Still alternatively, the logarithmic response unit 310 and the buffer 330 may be arranged on the light receiving chip 201, while the differential circuit 340 and subsequent devices may be arranged on the detection chip 202. Furthermore, the logarithmic response unit 310, the buffer 330, and the differential circuit 340 may be arranged on the light receiving chip 201, and the detection circuit 305 and subsequent circuitry may be arranged on the detection chip 202. Alternatively, the portion up to the selection section 400 can be arranged on the optical receiver chip 201, while the comparison section 500 and subsequent sections can be arranged on the detection chip 202.

[0291] 1.8.1 Operational Example of Solid State Imaging Device in EVS Mode

[0292] Figure 17 This is a flowchart illustrating an example of the operation of the solid-state imaging apparatus in EVS mode according to this embodiment. For example, operation begins at a timed start of the execution of a predetermined application for detecting the presence or absence of address events.

[0293] like Figure 17 As shown, in EVS mode, the row driving circuit 251 selects one of the rows (step S901). The row driving circuit 251 selects and drives one of the detection pixels 300 in each shared block 221 of the selected row (step S902). The detection circuit 305 detects whether an address event exists in the selected detection pixel 300 (step S903). After step S903, the solid-state imaging device 200 repeats steps S901 and subsequent steps.

[0294] In this way, this embodiment has a configuration in which the detection circuit 305 for detecting the presence or absence of an address event is shared by multiple detection pixels 300, thereby reducing the circuit size compared to a case where the detection circuit 305 is not shared. This facilitates the micro-manufacturing of the detection pixels 300.

[0295] 1.9 Modifications to the detection pixel and detection circuit

[0296] In the first embodiment described above, the solid-state imaging device 200 selects each of the detection pixels 300 one by one, and simultaneously detects both the on and off events of the detection pixels. Alternatively, the solid-state imaging device 200 may select two detection pixels, detect the on event of one detection pixel, and detect the off event of the other detection pixel. The solid-state imaging device 200 according to a variation of the first embodiment differs from the first embodiment in that it detects the on event of one of the two detection pixels and the off event of the other detection pixel.

[0297] Figure 18 This is a block diagram illustrating an example configuration of the detection pixel 300 and detection circuit 305 according to a variant of this embodiment. The detection circuit 305 according to the variant of the first embodiment differs from the detection circuit of the first embodiment in that a selection signal, such as a selection signal SEL1p or SEL2p, is input to selector 410, while a selection signal, such as a selection signal SEL1n or SEL2n, is input to selector 420. In the variant of the first embodiment, two detection pixels 300 are selected, and selector 410 selects one differential signal based on selection signals SEL1p, SEL2p, etc. Simultaneously, selector 420 selects another differential signal based on selection signals SEL1n, SEL2n, etc.

[0298] 1.9.1 Control Example of Horizontal Drive Circuit According to the Modified Example

[0299] Figure 19 This is a timing diagram illustrating an example of the control of the line drive circuit 251 in a variant of this embodiment. At times T0 to T2, it is assumed that two pixels are selected: the detection pixel 300 that outputs the differential signal Sin1 and the detection pixel 300 that outputs the differential signal Sin2. At times T0 to T1, the line drive circuit 251 sets the selection signals SEL1p and SEL2n to high level and sets the selection signals SEL2p and SEL1n to low level. Using this setting, an on event is detected for the pixel corresponding to the differential signal Sin1, and an off event is detected for the pixel corresponding to the differential signal Sin2.

[0300] Next, between time T1 and T2, the row drive circuit 251 sets the selection signals SEL1p and SEL2n to low level and sets the selection signals SEL2p and SEL1n to high level. Using this setting, an on event is detected for the pixel corresponding to the differential signal Sin2, and an off event is detected for the pixel corresponding to the differential signal Sin1.

[0301] In this way, according to a variation of this embodiment, since an on event is detected for one of the two detection pixels and a off event is detected for the other detection pixel, the on event and the off event can be detected simultaneously and in parallel in space.

[0302] Dead zone during 1.10 mode transition

[0303] Figure 20 This is a waveform diagram showing the dead time period during mode transition. With the above configuration in CIS mode, similar to the floating diffusion region 374, the cathode potential of the photoelectric conversion element 311 is reset to a potential higher than the sensing node SN (PD reset) (e.g., 0.5 volts (V)). Here, the amount of charge generated in the photoelectric conversion element 311 is small at low brightness. Therefore, even at the end of CIS mode, the cathode potential of the photoelectric conversion element 311 remains higher than the sensing node SN (hereinafter referred to as the SN potential). In this state, when the mode transitions to EVS mode and the switching transistor 317 is turned on, the cathode potential of the photoelectric conversion element 311, which is higher than the SN potential, is short-circuited with the sensing node SN, causing an increase in the SN potential. Figure 20 As shown, this disconnects nMOS transistors 312 and 315, causing the voltage level of the voltage signal VPR to remain stuck at ground potential (GND). This results in a dead time period (in other words, the period during which address event detection fails) where there is no response to the photocurrent flowing out of photoconversion element 311. This dead time period lasts until the SN potential stabilizes at a predetermined potential, and can therefore be a long period of time, for example, approximately 100 milliseconds (ms).

[0304] Therefore, in this embodiment, during the mode transition from CIS mode to EVS mode, the SN potential is fixed at a voltage VX that is lower than the SN potential during normal operation. With this configuration, even if the switching transistor 317 turns on, an unexpected rise in the SN potential can be suppressed, preventing the nMOS transistors 312 and 315 from turning off. As a result, dead time periods caused by the voltage level of the voltage signal VPR dropping to ground (GND) can be suppressed.

[0305] 1.11 Example of Response Circuit Configuration

[0306] Figure 21 This is a circuit diagram illustrating an example configuration of the response circuit according to this embodiment. (e.g.) Figure 21 As shown, the response circuit 301A according to this embodiment has the same characteristics as the one described above. Figure 9The described response circuit 301 has a similar configuration, wherein a control transistor 318 is connected to the sensing node SN. For example, the control transistor 318 may be an nMOS transistor. For example, the control transistor 318 may correspond to the first transistor in the claim.

[0307] As described above, the drain of the control transistor 318 is connected to the sensing node SN, and the source is connected to a potential, for example, a fixed potential VX equal to or higher than a reference potential and lower than the power supply voltage VDD. The reference potential can be, for example, the well potential VSS of the device isolation region on which the photoelectric conversion element 311 is formed, or the ground potential (GND). Furthermore, the well potential VSS of the device isolation region can be a negative potential. In this case, the voltage value of the fixed potential VX is, for example, equal to or greater than the anode potential (e.g., VSS or GND) of the photoelectric conversion element 311 and equal to or less than the voltage value of the sensing node SN potential VSN during normal operation. Note that the sensing node SN potential VSN during normal operation can be the sensing node SN potential VSN during normal operation of the logarithmic response unit 310A, and can be, for example, the gate-source voltage VGS of the nMOS transistor 313 determined by the bias current BIAS flowing through the two nMOS transistors 313 and 316 and the threshold voltage of the nMOS transistor 313.

[0308] In addition, for example, a control signal MST for controlling the on / off state of the control transistor 318 is applied from the row drive circuit 251 to the gate of the control transistor 318.

[0309] In this configuration, when transitioning from CIS mode to EVS mode, a high-level control signal MST is applied to the gate of control transistor 318. This turns on control transistor 318 and sets the SN potential of the sensing node SN to a fixed potential VX. Therefore, even if switching transistor 317 turns on, an unexpected increase in the SN potential can be suppressed. This prevents nMOS transistors 312 and 315 from turning off and suppresses dead time periods caused by the voltage level of voltage signal VPR being stuck at ground potential (GND).

[0310] 1.12 Modified Examples of Response Circuits

[0311] Next, variations of the response circuit according to this embodiment will be described through some examples.

[0312] 1.12.1 First Variation Example

[0313] Figure 22 This is a circuit diagram illustrating an example configuration of the response circuit according to a first variation of this embodiment. (As shown...) Figure 22 As shown, the response circuit 301B according to the first variant has a... Figure 21 The response circuit 301A shown has a similar configuration, wherein in the pixel circuit 370, the drain of the control transistor 318 is connected to the drain of the transmission transistor 372.

[0314] In this configuration, when transitioning from CIS mode to EVS mode, switching transistor 317 is turned on while control transistor 318 and transmission transistor 372 are on. This allows a fixed potential VX to be applied to the sensing node SN via control transistor 318, transmission transistor 372, and switching transistor 317, thereby setting the SN potential, which controls the sensing node SN, to a fixed potential VX. That is, even if switching transistor 317 turns on, unexpected increases in the SN potential can be suppressed.

[0315] 1.12.2 Second Variation Example

[0316] Figure 23 This is a circuit diagram illustrating an example configuration of the response circuit according to a second variation of this embodiment. For example... Figure 23 As shown, the response circuit 301C according to the second modification has a... Figure 22 The response circuit 301B shown has a similar configuration, wherein a control transistor 319 is further connected between the drain of the control transistor 318 and the transmission transistor 372 and the sensing node SN. For example, the control transistor 319 may correspond to the sixth transistor in claim 1.

[0317] The source of control transistor 319 is connected to the drain of control transistor 318 and transmission transistor 372, and the drain of control transistor 319 is connected to sensing node SN. Furthermore, for example, a control signal MSM is applied to the gate of control transistor 319 from row drive circuit 251.

[0318] In this configuration, control transistors 318 and 319 are turned on when transitioning from CIS mode to EVS mode. This allows a fixed potential VX to be applied to the sensing node SN via control transistors 318 and 319, thereby setting the SN potential, which controls the sensing node SN, to a fixed potential VX. Thus, even when switching transistor 317 turns on, unexpected rises in the SN potential can be suppressed.

[0319] 1.12.3 Third Variation Example

[0320] Figure 24 This is a circuit diagram illustrating an example configuration of the response circuit according to a third variation of this embodiment. For example... Figure 24 As shown, the response circuit 301D according to the third modification has the same characteristics as... Figure 21The response circuit 301A shown has a similar configuration, in which the drain of the transmission transistor 372 and the drain of the switching transistor 317 are connected to each other via the control transistor 319.

[0321] The source of control transistor 319 is connected to the drain of transmission transistor 372, and the drain of control transistor 319 is connected to the drain of switching transistor 317. Furthermore, for example, a control signal MSM is applied to the gate of control transistor 319 from row drive circuit 251.

[0322] In this configuration, when transitioning from CIS mode to EVS mode, similar to the first variation, control transistor 318 is turned on. This allows a fixed potential VX to be applied to the sensing node SN via control transistor 318, thereby setting the SN potential, which controls the sensing node SN, to a fixed potential VX. Thus, even when switching transistor 317 switches to the on state, unexpected rises in the SN potential can be suppressed.

[0323] 1.12.4 Fourth Variation Example

[0324] Figure 25 This is a circuit diagram illustrating an example configuration of the response circuit according to a fourth variation of this embodiment. (As shown...) Figure 25 As shown, the response circuit 301E according to the fourth modification has the same characteristics as... Figure 9 The response circuit 301 shown has a similar configuration, in which a fixed potential VX is used instead of the power supply voltage VDD as the reset voltage (FD reset voltage and PD reset voltage) of the pixel circuit 370.

[0325] In this configuration, when transitioning from CIS mode to EVS mode, reset transistor 373 and transfer transistor 372 are turned on. This allows a fixed potential VX to be applied to the sensing node SN via reset transistor 373 and transfer transistor 372, such that the SN potential, which controls the sensing node SN, is set to a fixed potential VX. Therefore, even when switching transistor 317 turns on, unexpected rises in the SN potential can be suppressed.

[0326] 1.12.5 Fifth Variation

[0327] Figure 26 This is a circuit diagram illustrating an example configuration of the response circuit according to a fifth variation of this embodiment. For example... Figure 26 As shown, the response circuit 301F according to the fifth modification has the same characteristics as... Figure 25 The response circuit 301E shown has a similar configuration, in which the drain of the transmission transistor 372 and the drain of the switching transistor 317 are connected to each other via the control transistor 319.

[0328] In this configuration, when transitioning from CIS mode to EVS mode, reset transistor 373 and control transistor 319 are turned on. This allows a fixed potential VX to be applied to the sensing node SN via reset transistor 373 and control transistor 319, enabling the SN potential of the sensing node SN to be controlled at a fixed potential VX. Therefore, even when switching transistor 317 switches to the on state, unexpected rises in the SN potential can be suppressed.

[0329] 1.12.6 Sixth Variation

[0330] Figure 27 This is a circuit diagram illustrating an example configuration of the response circuit according to a sixth variation of this embodiment. For example... Figure 27 As shown, the response circuit 301G according to the sixth modification has the same characteristics as... Figure 21 The response circuit 301A shown has a similar configuration, in which the control transistor 318 is connected to the cathode of the photoelectric conversion element 311, rather than the sensing node SN.

[0331] In this configuration, when transitioning from CIS mode to EVS mode, switching transistor 317 and control transistor 318 are turned on. This allows a fixed potential VX to be applied to the sensing node SN via control transistor 318 and switching transistor 317, enabling the SN potential of the sensing node SN to be controlled at a fixed potential VX. Therefore, even when switching transistor 317 is switched on, unexpected rises in the SN potential can be suppressed.

[0332] 1.12.7 Seventh Variation

[0333] Figure 28 This is a circuit diagram illustrating an example configuration of the response circuit according to the seventh variation of this embodiment. (As shown) Figure 28 As shown, the response circuit 301H according to the seventh modification has the same characteristics as... Figure 23 The response circuit 301C shown has a similar configuration, in which the transmission transistor 372 and the switching transistor 317 are connected in series, and the sensing node SN is connected to the cathode of the photoelectric conversion element 311 via the control transistor 319 and the switching transistor 317.

[0334] In this configuration, control transistors 318 and 319 are turned on when transitioning from CIS mode to EVS mode. This allows a fixed potential VX to be applied to the sensing node SN via control transistors 318 and 319, thereby setting the SN potential, which controls the sensing node SN, to a fixed potential VX. Thus, even when switching transistor 317 turns on, unexpected rises in the SN potential can be suppressed.

[0335] 1.12.8 Eighth Variation

[0336] Figure 29 This is a circuit diagram illustrating an example configuration of the response circuit according to the eighth variation of this embodiment. (As shown) Figure 29 As shown, the response circuit 301I according to the eighth modification has a similar Figure 26 The configuration of the response circuit 301F shown is similar to the seventh variation, wherein the transmission transistor 372 and the switching transistor 317 are connected in series, and the sensing node SN is connected to the cathode of the photoelectric conversion element 311 via the control transistor 319 and the switching transistor 317.

[0337] In this configuration, when transitioning from CIS mode to EVS mode, reset transistor 373, transfer transistor 372, and control transistor 319 are turned on. This allows a fixed potential VX to be applied to the sensing node SN via reset transistor 373, transfer transistor 372, and control transistor 319, thereby setting the SN potential, which controls the sensing node SN, to a fixed potential VX. Thus, even when switching transistor 317 turns on, unexpected rises in the SN potential can be suppressed.

[0338] 1.13 The shift from CIS model to EVS model

[0339] Next, the operation of switching from CIS mode to EVS mode will be described. (Refer to...) Figure 21 The response circuit 301A illustrated in this description is given in the example. However, similar operation can also be achieved through variations by appropriately controlling the control transistor 319, the transfer transistor 372, the reset transistor 373, etc., according to the control transistor 318.

[0340] Figure 30 This is a timing diagram illustrating an example of operation when transitioning from CIS mode to EVS mode according to this embodiment. Figure 30 As shown, firstly, during the transition from CIS mode to EVS mode, at the end time t0 of CIS mode, the supply of control signals (TRG, SEL, and RST) from the row drive circuit 251 to the transmission transistor 372, selection transistor 376, and reset transistor 373 constituting the pixel circuit 370 is stopped.

[0341] Next, during the transition period from CIS mode to EVS mode (t0 to t4), the row drive circuit 251 sets the control signal MST high at time t1 to turn on the control transistor 318. This allows the SN potential of the sensing node SN to be fixed at a fixed potential VX. Subsequently, the row drive circuit 251 sets the switching signal TGD high at time t2 to turn on the switching transistor 317. At this time, since the SN potential of the sensing node SN is fixed at a fixed potential VX, the voltage level of the voltage signal VPR is prevented from being stuck at the ground potential (GND).

[0342] Subsequently, the line drive circuit 251 disconnects the control transistor 318 at time t3. Then, the line drive circuit 251 executes EVS mode from time t4 onwards.

[0343] 1.14 Operating Procedures

[0344] Next, an operational example of the imaging apparatus 100 according to this embodiment will be described. Figure 31 This is a flowchart illustrating an operational example of the imaging apparatus according to this embodiment. The following description is an exemplary case where the response circuit 301A is incorporated into the shared block 221X. However, the configuration is not limited to this, and according to variations, the response circuit 301A can be replaced by response circuits 301B to 301I, etc. Furthermore, for example, Figure 31 The operations shown can be terminated by an interrupt operation such as powering off.

[0345] like Figure 31 As shown, in this operation, when the imaging device 100 is activated, for example, the EVS mode is first executed in the solid-state imaging device 200. As described above, the EVS mode detects an on or off event based on the change in photocurrent flowing out of the photoelectric conversion element 311, thereby detecting the motion of an object entering the field of view of the imaging device 100 (step S101). It should be noted that this motion detection can be performed by, for example, the signal processing circuit 240 in the solid-state imaging device 200, or by the control unit 130 connected to the solid-state imaging device 200, or by a server (including a cloud server, etc.) connected to the imaging device 100 via a predetermined network.

[0346] Next, in step S101, it is determined whether motion of the object has been detected (step S102). When no motion of the object is detected ("No" in step S102), the imaging device 100 continues in EVS mode.

[0347] Conversely, when motion of an object is detected ("Yes" in step S102), a transition from EVS mode to CIS mode is performed. During this transition, the line drive circuit 251 first turns off the pMOS transistor 314 in the response circuit 301, thus turning off the bias current BIAS flowing through the nMOS transistors 313 and 316 of the logarithmic response unit 310A (step S103). Subsequently, the line drive circuit 251 turns off the switching transistor (also called the TGD gate) 317 (step S104). As a result, the supply of photocurrent to the logarithmic response unit 310A stops, and the mode changes to CIS mode.

[0348] In CIS mode, the line drive circuit 251 drives the pixel circuit 370 to generate frame data of the captured image of the object (step S105). Subsequently, recognition processing is performed on the generated frame data to identify the captured object (step S106). Note that object recognition processing can be performed on multiple frames instead of just one. It should be noted that object recognition processing can be performed by, for example, the signal processing circuit 240 in the solid-state imaging device 200, or by the control unit 130 connected to the solid-state imaging device 200, or by a server (including a cloud server) connected to the imaging device 100 via a predetermined network.

[0349] When object recognition is completed in this manner, the solid-state imaging device 200 performs a transition from CIS mode to EVS mode. During this transition period, the line drive circuit 251 first turns on the control transistor (also known as the MST gate) 318 (step S107). This allows the SN potential of the sensing node SN of the logarithmic response unit 310A to be controlled at a fixed potential VX. Next, the line drive circuit 251 turns on the switching transistor 317 (step S108), turns off the control transistor 318 (step S109), and then turns on the pMOS transistor 314 in the response circuit 301 to allow the bias current BIAS to flow in the nMOS transistors 313 and 316 of the logarithmic response unit 310A (step S110). This begins to supply photocurrent to the logarithmic response unit 310A, and the mode transitions to EVS mode.

[0350] 1.15 Circuit Sharing

[0351] The above description is an example of a configuration in which each of the multiple response circuits 301X (which may be any of the response circuits 301A to 301I described above and the response circuits 301J to 301N described below) belonging to a shared block 221 includes a logarithmic response unit 310 / 310A and a pixel circuit 370. However, some of the circuits constituting a response circuit 301X may be shared with other response circuits 301X. In the following, examples of circuit configurations of a shared block in which partial circuit configurations are shared among the multiple response circuits 301X will be described by way of examples.

[0352] 1.15.1 First Shared Example

[0353] Figure 32 This is a circuit diagram illustrating an example circuit configuration of a shared block according to a first shared example. It should be noted that the first shared example illustrates a configuration including... Figure 21 The four response circuits 301A shown in the diagram share a portion of the pixel circuit 370 (specifically, excluding the circuit configuration of the photoelectric conversion element 311 and the transmission transistor 372) in the shared block 221. In the following description, the circuit configuration in the pixel circuit 370 excluding the photoelectric conversion element 311 and the transmission transistor 372, i.e., the circuit configuration including the reset transistor 373, the floating diffusion region 374, the amplification transistor 375, and the selection transistor 376, is referred to as the readout circuit 370a.

[0354] like Figure 32 As shown, in the shared block 221A according to the first shared example, the drain of the transfer transistor 372 in each response circuit 301A1 to 301A4 is connected to a common line 3101. The common line 3101 is connected to a readout circuit 370a. The readout circuit 370a is shared by the multiple response circuits 301A1 to 301A4 via the common line 3101. That is, each of the four pixel circuits 370 in each shared block 221A includes the photoelectric conversion element 311 and the transfer transistor 372 of each response circuit 301A1 to 301A4, as well as the shared readout circuit 370a.

[0355] 1.15.2 Second Shared Example

[0356] Figure 33 This is a circuit diagram illustrating an example of a shared block configuration according to the second shared example. The second shared example is in the case of including... Figure 23 The case of the readout circuit 370a of the shared pixel circuit 370 in the shared block 221 of the four response circuits 301C shown.

[0357] like Figure 33As shown, similar to the shared block 221A according to the first shared example, the shared block 221C according to the second shared example has a configuration in which the drain of the transfer transistor 372 in each response circuit 301C1 to 301C4 is connected to the common line 3101, and the readout circuit 370a is connected to the common line 3101. With this configuration, each of the four pixel circuits 370 in each shared block 221C includes the photoelectric conversion element 311 and the transfer transistor 372 of each response circuit 301C1 to 301C4, as well as the shared readout circuit 370a.

[0358] 1.15.3 Third Shared Example

[0359] Figure 34 This is a circuit diagram illustrating an example of a shared block configuration based on a third shared example. The third shared example is in the case of... Figure 24 The case of the readout circuit 370a of the shared pixel circuit 370 in the shared block 221 of the four response circuits 301D shown.

[0360] like Figure 34 As shown, similar to the shared block 221A according to the first shared example, the shared block 221D according to the third shared example has a configuration in which the drain of the transfer transistor 372 in each response circuit 301D1 to 301D4 is connected to the common line 3101, and the readout circuit 370a is connected to the common line 3101. With this configuration, each of the four pixel circuits 370 in each shared block 221D includes the photoelectric conversion element 311 and the transfer transistor 372 of each response circuit 301D1 to 301D4, as well as the shared readout circuit 370a.

[0361] 1.15.4 Fourth Shared Example

[0362] Figure 35 This is a circuit diagram illustrating an example of a shared block configuration according to the fourth shared example. The fourth shared example illustrates... Figure 33 The second shared example shown further illustrates the case of sharing control transistor 318.

[0363] like Figure 35 As shown, the shared block 221CC according to the fourth shared example has a configuration similar to that of the shared block 221C according to the second shared example, wherein the control transistor 318 in each of the response circuits 301C1 to 301C4 is omitted; instead, the source of one control transistor 318 is connected to the common line 3101. With this configuration, the control transistor 318 is shared by the logarithmic response units 310A of each of the response circuits 301B1 to 301B4.

[0364] As described above, by having multiple response circuits 301X share a portion of the circuitry, the area occupied in the light receiving chip 201 and / or the detection chip 202 can be reduced, thereby achieving effects such as miniaturization of the solid-state imaging device 200 and increased sensitivity due to the increased area of ​​the photoelectric conversion element 311.

[0365] 1.16 Uses circuit-shared merge mode and full-pixel mode

[0366] The shared readout circuit 370a and / or control transistor 318 can be used at different times in each response circuit 301X, or they can be used at the same time.

[0367] For example, in the case where the readout circuit 370a is used in each response circuit 301X in the CIS mode at different time periods, in the operating mode (hereinafter referred to as the full pixel mode) in which each shared block 221X has four pixel circuits 370, each shared block 221X is driven (the shared block 221X can be any of the shared blocks 221A to 221D mentioned above, or any of the shared blocks obtained by applying another response circuit 301X to the shared blocks 221A to 221D).

[0368] On the other hand, in CIS mode, when readout circuits 370a are used in each response circuit 301X within the same time period, each shared block 221X is driven in an operation mode (hereinafter referred to as merging mode) where each shared block 221X has a pixel circuit 370. Merging mode allows the charge generated in multiple photoelectric conversion elements 311 to be collected in a floating diffusion region 374, resulting in an expanded dynamic range when grayscale data (pixel signals) is read out, thereby improving image quality at low brightness.

[0369] Furthermore, the full-pixel mode and merge mode can be applied not only to CIS mode but also to EVS mode.

[0370] For example, in the first and fourth shared examples described above, by using the configuration, in EVS mode, where the transmission transistor 372 and the switching transistor 317 in the response circuits 301A1 / 301B1 are turned on, and the transmission transistor 372 in the other response circuits 301A2 / 301B1 to 301A4 / 301B4 are turned on and the switching transistor 317 is turned off, it is possible to allow the photocurrent flowing from the photoelectric conversion element 311 of each response circuit 301A1 / 301B1 to 301A4 / 301B4 to be concentrated in the logarithmic response section 310A of the response circuit 301A1 / 301B1 (merging mode).

[0371] Furthermore, in the second and third shared examples described above, by using this configuration, in EVS mode, where the control transistor 319 and the switch transistor 317 in the response circuits 301C1 / 301D1 are turned on, the transmission transistors 372 in the other response circuits 301C2 / 301D2 to 301C4 / 301D4 are turned on, and the control transistor 319 and the switch transistor 317 are turned off, it is possible to allow the photocurrent flowing from the photoelectric conversion element 311 of each response circuit 301C1 / 301D1 to 301C4 / 301D4 to be concentrated in the logarithmic response section 310A of the response circuit 301C1 / 301D1.

[0372] In this way, by concentrating the photocurrent flowing from each photoelectric conversion element 311 in a logarithmic response section 310 / 310A, the amount of photocurrent flowing at one time can be increased, resulting in an expansion of the dynamic range during address event detection. This allows for improved sensitivity to address events, for example, at low brightness.

[0373] Alternatively, when operating in either CIS or EVS mode, the full-pixel mode and merge mode can be switched appropriately. Even in this case, there is a possibility that the SN potential of the sensing node SN may fluctuate when transitioning from full-pixel mode to merge mode or vice versa. Therefore, similar to the transition from CIS mode to EVS mode described above, it is considered effective to shorten the setup time during mode transition by fixing the SN potential to a fixed potential VX.

[0374] 1.17 Layout of Shared Blocks

[0375] Furthermore, the layout of the light receiving section 220 of the shared block 221X according to this embodiment will be described below by way of example. For ease of description, a schematic layout example on the element forming surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed will be described below. Furthermore, for clarity, the arrangement of each transistor is indicated by the position of the gate.

[0376] 1.17.1 First Layout Example

[0377] As a first layout example, a layout example of shared block 221A based on the first shared example will be described. Figure 36 This is a floor plan showing a layout example of a shared block based on the first layout example. (See attached image.) Figure 36 As shown, on the light receiving chip 201, a pixel region 10 with a response circuit 301A is divided by pixel isolation portions 12 extending in the row and column directions. Each of the response circuits 301A1 to 301A4 includes a photoelectric conversion element 311 and a transistor arranged along the outer periphery of the pixel region; in other words, they are arranged from at least two directions ( Figure 36 The photoelectric conversion element 311 is surrounded by three directions, and the transistors are multiple nMOS transistors 312, 313, 315, and 316, a switching transistor 317, and a control transistor 318. Furthermore, in each of the four pixel regions 10, any one of the three transistors (373, 375, or 376) constituting the readout circuit 370a, or a dummy transistor 972, is also arranged. Incidentally, the dummy transistor 972 is a transistor not included in the response circuit 301A and may, for example, be an electrically floating transistor.

[0378] exist Figure 36 In the layout example shown, the four nMOS transistors 312, 313, 315, and 316 in each logarithmic response section 310A are arranged on one side of the photoelectric conversion element 311. In this way, by arranging the nMOS transistors 312, 313, 315, and 316 constituting the logarithmic response section 310A together on one side of the photoelectric conversion element 311, the time constant formed by the wiring constituting the logarithmic conversion circuit can be reduced, resulting in an improvement in the response speed of the logarithmic conversion circuit.

[0379] 1.17.2 Example of the Second Layout

[0380] As a second layout example, a layout example of shared block 221CC based on the fourth shared example will be described. Figure 37 This is a floor plan showing a layout example of a shared block based on the second layout example. (See attached image.) Figure 37 As shown, the second layout example has a configuration similar to the first layout example, wherein a control transistor 319 is provided in the area where the control transistor 318 is provided in the first layout example, and a shared control transistor 318 is provided in the area where the virtual transistor 972 is provided.

[0381] 1.18 Functions and Effects

[0382] As described above, according to this embodiment, during the mode transition from CIS mode to EVS mode, the SN potential is fixed at a voltage VX that is lower than the SN potential during normal operation. With this configuration, even if the switching transistor 317 turns on, an unexpected rise in the SN potential can be suppressed, preventing the nMOS transistors 312 and 315 from turning off. As a result, dead time periods caused by the voltage level of the voltage signal VPR dropping to ground (GND) can be suppressed.

[0383] 2. Second Implementation Method

[0384] In the first embodiment described above, during the mode transition from CIS mode to EVS mode, the SN potential is fixed at a voltage VX lower than the SN potential during normal operation, thus suppressing unexpected increases in the SN potential and preventing dead time periods. Conversely, in the second embodiment, once the cathode potential of the photoelectric conversion element 311 drops to a level lower than the SN potential during normal operation, the photoelectric conversion element 311 is electrically floated, and then the switching transistor 317 is turned on. In this way, similar to the first embodiment, by lowering the cathode potential of the photoelectric conversion element 311 to a level lower than the SN potential during normal operation and then connecting the cathode of the photoelectric conversion element 311 and the sensing node SN to each other, unexpected increases in the SN potential can be suppressed. This allows the suppression of dead time periods caused by the voltage level of the voltage signal VPR dropping to ground potential (GND). The control of the response circuit 301X during the transition from CIS mode to EVS mode will be described below with some examples.

[0385] Since the configuration of the imaging apparatus, solid-state imaging apparatus, and each part constituting the solid-state imaging apparatus according to this embodiment can be similar to the configuration of the first embodiment, it will be described with reference to this embodiment.

[0386] 2.1 First Control Example

[0387] The first control example is an application of this embodiment to a system based on reference in the first embodiment. Figure 22 An exemplary case of the response circuit 301B of the first modified example described. Figure 38 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the first control example. (See diagram for example.) Figure 38 As shown, in Figure 22 In the configuration shown, during the transition period (t10 to t14) from CIS mode to EVS mode, the line drive circuit 251 turns on the control transistor 318 and the transmission transistor 372 at time t11. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 through the control transistor 318 and the transmission transistor 372, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0388] Subsequently, the line drive circuit 251 disconnects the control transistor 318 and the transmission transistor 372 at time t12 to electrically float the photoelectric conversion element 311, and then turns on the switching transistor 317 at time t13. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX that is lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the switching transistor 317 switches to the on state.

[0389] 2.2 Second Control Example

[0390] The second control example is an application of this embodiment to a system based on reference in the first embodiment. Figure 23 An exemplary case of the response circuit 301C according to the second variation is described. Figure 39 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the second control example. (See diagram for example.) Figure 39 As shown, in Figure 23 In the configuration shown, similar to the first control example, during the transition period (t20 to t25) from CIS mode to EVS mode, the line drive circuit 251 turns on the control transistor 318 and the transmission transistor 372 at time t21. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 through the control transistor 318 and the transmission transistor 372, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0391] Subsequently, similar to the first control example, the line drive circuit 251 disconnects the control transistor 318 and the transmission transistor 372 at time t22 to electrically float the photoelectric conversion element 311, and then turns on the switching transistor 317 at time t23. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the switching transistor 317 switches to the on state.

[0392] It should be noted that, such as Figure 39 As shown, the row drive circuit 251 can turn on the control transistor 318 and the transmission transistor 372 at time t21, and can also turn on the control transistor 319 during the period from time t21 to t24. This also controls the SN potential of the sensing node SN to a fixed potential VX, which further suppresses unexpected increases in the SN potential.

[0393] 2.3 Example of Third Control

[0394] The third control example is an application of this embodiment to reference in the first embodiment. Figure 25 An exemplary case of the response circuit 301E of the fourth modified example described. Figure 40 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the third control example. (See diagram for example.) Figure 40 As shown, in Figure 25In the configuration shown, during the transition period (t30 to t34) from CIS mode to EVS mode, the line drive circuit 251 turns on the reset transistor 373 and the transfer transistor 372 at time t31. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 through the reset transistor 373 and the transfer transistor 372, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0395] Subsequently, the line drive circuit 251 disconnects the reset transistor 373 and the transmission transistor 372 at time t32 to electrically float the photoelectric conversion element 311, and then turns on the switching transistor 317 at time t33. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX that is lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the switching transistor 317 switches to the on state.

[0396] 2.4 Fourth Control Example

[0397] The fourth control example is applied in this embodiment according to the reference in the first embodiment. Figure 26 An exemplary case of the response circuit 301F of the fifth modified example described. Figure 41 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the fourth control example. (See diagram for example.) Figure 41 As shown, in Figure 26 In the configuration shown, during the transition period (t40 to t45) from CIS mode to EVS mode, similar to the third control example, the row drive circuit 251 turns on the reset transistor 373 and the transfer transistor 372 at time t41. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 through the reset transistor 373 and the transfer transistor 372, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0398] Subsequently, similar to the fourth control example, the line drive circuit 251 disconnects the reset transistor 373 and the transmission transistor 372 at time t42 to electrically float the photoelectric conversion element 311, and then turns on the switching transistor 317 at time t23. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX that is lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the switching transistor 317 switches to the on state.

[0399] It should be noted that, such as Figure 41As shown, the row drive circuit 251 can turn on the reset transistor 373 and the transmission transistor 372 at time t41, and can also turn on the control transistor 319 during the time period from time t41 to t44. This also controls the SN potential of the sensing node SN to a fixed potential VX, which further suppresses unexpected increases in the SN potential.

[0400] 2.5 Fifth Control Example

[0401] The fifth control example is an application of this embodiment to the reference in the first embodiment. Figure 27 An exemplary case of the response circuit 301G of the sixth modified example described. Figure 42 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the fifth control example. (See diagram for example.) Figure 42 As shown, in Figure 27 In the configuration shown, during the transition period (t50 to t54) from CIS mode to EVS mode, the row drive circuit 251 turns on the control transistor 318 at time t51. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 via the control transistor 318, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0402] Subsequently, the line drive circuit 251 disconnects the control transistor 318 at time t52 to electrically float the photoelectric conversion element 311, and then turns on the switching transistor 317 at time t53. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX that is lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the switching transistor 317 switches to the on state.

[0403] 2.6 Sixth Control Example

[0404] The sixth control example is an application of this embodiment to the reference in the first embodiment. Figure 28 An exemplary case of the response circuit 301H according to the seventh variation is described. Figure 43 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the sixth control example. (See diagram for example.) Figure 43 As shown, in Figure 28 In the configuration shown, during the transition period (t60 to t64) from CIS mode to EVS mode, the line drive circuit 251 turns on the control transistor 318 and the switching transistor 317 at time t61. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 by the control transistor 318 and the switching transistor 317, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0405] Subsequently, the line drive circuit 251 disconnects the control transistor 318 at time t62 to electrically float the photoelectric conversion element 311 and the switching transistor 317, and then turns on the control transistor 319 at time t63. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX below the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the control transistor 319 switches to the on state.

[0406] Note that the row drive circuit 251 can turn on the control transistor 318 and the switching transistor 317 at time t61, and simultaneously, it can also turn on the control transistor 319. This will also control the SN potential of the sensing node SN to a fixed potential VX, thereby further suppressing any unexpected increases in the SN potential.

[0407] 2.7 Seventh Control Example

[0408] The seventh control example is an application of this embodiment to the reference in the first embodiment. Figure 29 An exemplary case of the response circuit 3011 of the eighth modified example described. Figure 44 This is a timing diagram illustrating an operational example of transitioning from CIS mode to EVS mode according to the seventh control example. (See diagram for example.) Figure 44 As shown, in Figure 29 In the configuration shown, during the transition period (t70 to t74) from CIS mode to EVS mode, the line drive circuit 251 turns on the reset transistor 373, the transfer transistor 372, and the switch transistor 317 at time t71. This allows a fixed potential VX to be applied to the cathode of the photoelectric conversion element 311 through the reset transistor 373, the transfer transistor 372, and the switch transistor 317, so that the cathode potential of the photoelectric conversion element 311 can be controlled to be set to the fixed potential VX.

[0409] Subsequently, at time t72, the line drive circuit 251 disconnects the reset transistor 373 and the transmission transistor 372 to electrically float the photoelectric conversion element 311 and the switching transistor 317, and then turns on the control transistor 319 at time t73. In this case, since the cathode potential of the photoelectric conversion element 311 is suppressed to a fixed potential VX lower than the SN potential during normal operation, an unexpected increase in the SN potential can be suppressed even when the control transistor 319 switches to the on state.

[0410] Note that the row drive circuit 251 can turn on the reset transistor 373, the transmission transistor 372, and the switching transistor 317 at time t71, and can also turn on the control transistor 319 at the same time. This will also control the SN potential of the sensing node SN to a fixed potential VX, so that unexpected increases in the SN potential can be further suppressed.

[0411] 2.8 Functions and Effects

[0412] As described above, according to this embodiment, similar to the first embodiment, once the cathode potential of the photoelectric conversion element 311 drops to a potential lower than the SN potential during normal operation, the photoelectric conversion element 311 is electrically floated, and then the switching transistor 317 is turned on. This allows for the suppression of unexpected increases in the SN potential, thereby suppressing dead time periods caused by the voltage level of the voltage signal VPR dropping to ground potential (GND).

[0413] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0414] 3. Third Implementation Method

[0415] In the third embodiment, the bias current BIAS of nMOS transistors 313 / 313 and 316 in the logarithmic conversion circuit of the logarithmic response unit 310 / 310A is controlled to suppress the unexpected rise of the SN potential, thereby suppressing the dead time period caused by the voltage level of the voltage signal VPR stuck at the ground potential (GND).

[0416] Since the configuration of the imaging apparatus, solid-state imaging apparatus, and each part constituting the solid-state imaging apparatus according to this embodiment can be similar to the configuration of the first embodiment, it will be described with reference to this embodiment. However, in this embodiment, the response circuit 301X constituting the shared block 221X is replaced with the response circuit described below. The following description uses the reference circuit from the first embodiment. Figure 7 The description illustrates an exemplary case of the response circuit of the logarithmic response unit 310A. However, the configuration is not limited to this, and other configurations such as those described in the reference diagram may also be used. Figure 6 Other logarithmic response parts of the described logarithmic response part 310.

[0417] 3.1 Example of Response Circuit Configuration

[0418] Figure 45 This is a circuit diagram illustrating an example configuration of the response circuit according to this embodiment. (e.g.) Figure 45 As shown, the response circuit 301J according to this embodiment has a similar function to that in the first embodiment. Figure 9 The described configuration of the response circuit 301, for example, wherein the pMOS transistor 314 (also called a load MOS transistor or load resistor) in the logarithmic response section 310A, which serves as a constant current circuit, is replaced by a bias circuit 314A.

[0419] The bias circuit 314A includes: two pMOS transistors forming the current mirror circuit, namely pMOS transistors 314a and 314b; and a digital-to-analog converter (DAC) 314c, which generates a voltage for controlling the bias current BIAS flowing through the current mirror circuit according to the control signal CTL input from the row drive circuit 251.

[0420] DAC 314c converts the digital control signal CTL input from the row drive circuit 251 into an analog voltage and applies the obtained analog voltage to the source of pMOS transistor 314b, thereby controlling the bias current BIAS flowing through the nMOS transistors 313 and 316 of the logarithmic converter circuit connected to the source of another pMOS transistor 314a.

[0421] Specifically, for example, when a control signal CTL representing "1" is input from the row drive circuit 251, the DAC 314c provides a reference current to the current mirror circuit. This, along with the bias current BIAS corresponding to the reference current, flows through the nMOS transistors 313 and 316 of the logarithmic converter circuit.

[0422] On the other hand, when the control signal CTL representing "0" is input from the row drive circuit 251, the DAC 314c cuts off the supply of reference current to the current mirror circuit. This cuts off the bias current BIAS flowing through the nMOS transistors 313 and 316 of the logarithmic conversion circuit.

[0423] The bias circuit 314A can be provided, for example, on the detection chip 202 side. Furthermore, the DAC 314c can be formed using a binary system with an R-2R ladder, a current mirror using an nMOS transistor (hereinafter also referred to as an nMOS current mirror), etc. When using an nMOS current mirror, a reference current can be generated using a bandgap reference circuit.

[0424] 3.1.1 Variations of the response circuit

[0425] Figure 46 This is a circuit diagram illustrating a modified example of the response circuit according to this embodiment. For example... Figure 46 As shown, the response circuit 301K according to the modified example has the same characteristics as the one referenced above. Figure 45 The configuration of the described response circuit 301J is similar, wherein, for example, the bias circuit 314A is replaced by the bias circuit 314B.

[0426] The bias circuit 314B has a configuration similar to that of the bias circuit 314A, wherein the DAC 314c is replaced by a constant current source 314e, and the bias control transistor 314d is added to the source of the pMOS transistor 314a that constitutes the current mirror circuit.

[0427] When the bias current is supplied to the logarithmic conversion circuit in this configuration, for example, the row drive circuit 251 applies a high-level control signal CTL to the gate of the bias control transistor 314d. This forms a current path from the current mirror circuit to the logarithmic conversion circuit, enabling the bias current BIAS, which uses the current flowing through the constant current source 314e as a reference current, to be supplied to the logarithmic conversion circuit. Conversely, when the bias current is not supplied to the logarithmic conversion circuit, for example, the row drive circuit 251 applies a low-level control signal CTL to the gate of the bias control transistor 314d. This cuts off the current path from the current mirror circuit to the logarithmic conversion circuit, thereby cutting off the supply of the bias current BIAS to the logarithmic conversion circuit.

[0428] The bias control transistor 314d can be arranged on the optical receiver chip 201 or on the detection chip 202. Other configurations can be similar to the configuration of the response circuit 301J described above.

[0429] In the above configuration, when transitioning from CIS mode to EVS mode, the control signal CTL provided to DAC314c or bias control transistor 314d is used to cut off the bias current BIAS flowing through nMOS transistors 313 and 316 of the logarithmic conversion circuit. Thus, similar to the above embodiment, it is possible to suppress the unexpected increase in the SN potential when switching transistor 317 transitions to the on state. This prevents nMOS transistors 312 and 315 from turning off, thereby suppressing the dead time period caused by the voltage level of voltage signal VPR being stuck at ground potential (GND).

[0430] Furthermore, by controlling the flow of the bias current BIAS in the logarithmic conversion circuit as in this embodiment, the limitations on the circuit design required for the response circuit 301J can be alleviated. This allows for the design of the response circuit 301J, and more specifically, increases the design freedom of the solid-state imaging device 200.

[0431] 3.2 The shift from CIS model to EVS model

[0432] Next, the operation of switching from CIS mode to EVS mode will be described. Although this description uses Figure 45 The response circuit 301J shown is for reference only, but this description can also be applied similarly. Figure 46 The response circuit 301K shown is illustrated.

[0433] Figure 47 This is a timing diagram illustrating an example of operation when transitioning from CIS mode to EVS mode according to this embodiment. Figure 47As shown, firstly, during the transition from CIS mode to EVS mode, at the end time t80 of CIS mode, the supply of control signals (TRG, SEL, and RST) from the row drive circuit 251 to the transmission transistor 372, selection transistor 376, and reset transistor 373 constituting the pixel circuit 370 is stopped.

[0434] Next, during the transition from CIS mode to EVS mode (t80 to t82), the line drive circuit 251 turns on the switching transistor 317 at time t81. The control signal CTL indicates "0" during the transition period (t80 to t82), thus cutting off the bias current BIAS (low level) flowing through the logarithmic conversion circuit.

[0435] Subsequently, the line drive circuit 251 sets the control signal CTL to "1" at time t82. This allows the bias current BIAS to be supplied to the logarithmic conversion circuit (high level) via the bias circuits 314A / 314B. Then, the line drive circuit 251 executes EVS mode from time t82.

[0436] 3.3 Operating Procedures

[0437] Next, an operational example of the imaging apparatus 100 according to this embodiment will be described. Figure 48 This is a flowchart illustrating an operational example of the imaging apparatus according to this embodiment. The following description is an exemplary case where the response circuit 301J is incorporated into the shared block 221X. However, the configuration is not limited to this, and according to variations, the response circuit 301J can be replaced by a response circuit 301K, etc. Furthermore, for example, Figure 48 The operations shown can be terminated by an interrupt operation such as powering off.

[0438] like Figure 48 As shown, in this operation, when the imaging device 100 is activated, for example, the EVS mode is activated and motion detection processing (step S301) is performed, similar to the first embodiment. Figure 31 Steps S101 to S102 determine whether motion of the object is detected (step S302).

[0439] When motion of the object is detected in step S302 (Yes in step S302), a transition from EVS mode to CIS mode is performed. During this transition, firstly, the line drive circuit 251 disconnects the bias circuit 314A of the response circuit 301J, thereby disconnecting the bias current BIAS flowing through the nMOS transistors 313 and 316 of the logarithmic response unit 310A (step S303). Note that the bias circuit 314A can be disconnected by inputting the control signal CTL indicating "0" to the DAC 314c.

[0440] Subsequently, the line drive circuit 251 disconnects the switching transistor (TGD gate) 317 (step S304). This stops supplying photocurrent to the logarithmic response unit 310A, and the mode changes to CIS mode.

[0441] In this CIS mode, with Figure 31 Steps S105 to S106 are similar, the line drive circuit 251 generates frame data of the captured image of the object (step S305), and identifies the captured object (step S306).

[0442] When object recognition is completed in this manner, the solid-state imaging device 200 performs a transition from CIS mode to EVS mode. During this transition, the line drive circuit 251 first turns on the switching transistor 317 (step S307), and then turns on the bias circuit 314A in the response circuit 301, so that the bias current BIAS flows to the nMOS transistors 313 and 316 of the logarithmic response unit 310A (step S308). This begins to supply photocurrent to the logarithmic response unit 310A, and the mode transitions to EVS mode. Note that the bias circuit 314A can be turned on by inputting the control signal CTL indicating "1" into the DAC 314c.

[0443] 3.4 Functions and Effects

[0444] As described above, according to this embodiment, the supply of bias current BIAS to the logarithmic conversion circuit is cut off during the transition from CIS mode to EVS mode. Therefore, similar to the embodiment described above, it is possible to suppress the unexpected increase in SN potential when the switching transistor 317 transitions to the ON state. This prevents nMOS transistors 312 and 315 from turning off, thereby suppressing the dead time period caused by the voltage level of the voltage signal VPR being stuck at ground potential (GND).

[0445] Furthermore, by controlling the flow of the bias current BIAS in the logarithmic conversion circuit as in this embodiment, the limitations of the circuit design required for the response circuit 301J can be alleviated. This allows for a greater degree of design freedom in designing the response circuit 301J, and more specifically, in designing the solid-state imaging device 200.

[0446] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0447] 4. Fourth Implementation Method

[0448] The fourth embodiment will describe exemplary cases in which the configurations according to the first and / or second embodiments described above are combined with the configurations according to the third embodiment.

[0449] Because the configuration of the imaging apparatus, solid-state imaging apparatus, and each part constituting the solid-state imaging apparatus according to this embodiment can be similar to the configuration of any of the first to third embodiments, it will be described with reference to this embodiment. However, in this embodiment, the response circuit 301X constituting the shared block 221X is replaced with the response circuit described below. The following description uses reference to the first embodiment. Figure 7 The description illustrates an exemplary case of the response circuit of the logarithmic response unit 310A. However, the configuration is not limited to this, and other configurations such as those described in the reference diagram may also be used. Figure 6 Other logarithmic response parts of the described logarithmic response part 310.

[0450] 4.1 Example of Response Circuit Configuration

[0451] Figure 49 This is a circuit diagram illustrating an example configuration of the response circuit according to this embodiment. (e.g.) Figure 49 As shown, the response circuit 301L according to this embodiment has a combination of the reference circuits in the first embodiment or the second embodiment. Figure 21 The described response circuit 301A is the same as the reference in the third embodiment. Figure 45 The configuration of the described response circuit 301J is shown. Specifically, the response circuit 301L has a control transistor 318 connected to the reference in the third embodiment. Figure 45 The configuration of the sensing node SN in the described response circuit 301J.

[0452] 4.1.1 Variations of the response circuit

[0453] Figure 50 This is a circuit diagram showing a modified example of the response circuit according to this embodiment. For example... Figure 50 As shown, the response circuit 301M according to the modified example has, for example, a reference in the first or second embodiment. Figure 21 The described response circuit 301A is the same as the reference in the third embodiment. Figure 46 The configuration of the described response circuit 301K combination is shown. Specifically, the response circuit 301M has a control transistor 318 connected to the reference in the third embodiment. Figure 46 The configuration of the sensing node SN in the described response circuit 301K.

[0454] With this configuration, when transitioning from CIS mode to EVS mode, the SN potential of the sensing node SN and / or the cathode potential of the photoelectric conversion element 311 can be fixed to a fixed potential VX lower than the SN potential during normal operation, and the supply of bias current to the logarithmic response circuit in the logarithmic response unit 310A can be cut off, thereby further suppressing unexpected increases in the SN potential. This allows for further suppression of dead time periods caused by the voltage level of the voltage signal VPR at ground potential (GND).

[0455] Note that the configuration combined with the response circuits 301J / 301K according to the third embodiment is not limited to... Figure 21 The response circuit 301A shown in the figure can be, for example, Figures 22 to 29 Any one of the response circuits 301B to 3011 shown.

[0456] 4.2 The shift from CIS model to EVS model

[0457] Next, the operation of switching from CIS mode to EVS mode will be described. (Refer to...) Figure 49 The response circuit 301L in the example is given in this description. However, similar operation can also be achieved through variations by appropriately controlling the control transistor 319, the transfer transistor 372, the reset transistor 373, etc., according to the control transistor 318.

[0458] Figure 51 This is a timing diagram illustrating an example of operation when transitioning from CIS mode to EVS mode according to this embodiment. Figure 51 As shown, firstly, during the transition from CIS mode to EVS mode, at the end time t90 of CIS mode, the supply of control signals (TRG, SEL, and RST) from the row drive circuit 251 to the transmission transistor 372, selection transistor 376, and reset transistor 373 constituting the pixel circuit 370 is stopped.

[0459] Next, during the transition period from CIS mode to EVS mode (t90 to t94), the row drive circuit 251 sets the control signal MST high at time t91 to turn on the control transistor 318. This allows the SN potential of the sensing node SN to be fixed to a fixed potential VX. The control signal CTL indicates "0" during the transition period (t90 to t92), thus cutting off the bias current BIAS flowing through the logarithmic conversion circuit (low level).

[0460] Next, the row drive circuit 251 sets the switching signal TGD to a high level at time t92 to turn on the switching transistor 317. At this time, since the SN potential of the sensing node SN is fixed at a fixed potential VX, the voltage level of the voltage signal VPR can be prevented from hitting the ground potential (GND).

[0461] Subsequently, the line drive circuit 251 disconnects the control transistor 318 at time t93, and then sets the control signal CTL to "1" at time t94. As a result, the bias current BIAS is supplied to the logarithmic converter circuit (high level) via the bias circuits 314A / 314B. Then, the line drive circuit 251 executes EVS mode from time t94.

[0462] 4.3 Operating Procedures

[0463] Next, an operational example of the imaging apparatus 100 according to this embodiment will be described. Figure 52 This is a flowchart illustrating an operational example of the imaging apparatus according to this embodiment. The following description is an exemplary case where the response circuit 301L is included in the shared block 221X. However, the configuration is not limited to this, and according to variations, the response circuit 301L may be replaced by a response circuit 301M, etc. Furthermore, for example, Figure 52 The operations shown can be terminated by an interrupt operation such as powering off.

[0464] like Figure 52 As shown, in this operation, when the imaging device 100 is activated, for example, the EVS mode is activated and motion detection processing is performed (step S401) to determine whether motion of the object is detected (step S402). This is similar to the first embodiment. Figure 31 Steps S101 to S102.

[0465] When motion of the object is detected in step S402 ("Yes" in step S402), a transition from EVS mode to CIS mode is performed. During this transition, for example, with the third embodiment... Figure 48 Similarly, in steps S303 to S304, the line drive circuit 251 disconnects the bias circuit 314A of the response circuit 301L to cut off the bias current BIAS (step S403), and then disconnects the switching transistor (TGD gate) 317 (step S404). As a result, the supply of photocurrent to the logarithmic response unit 310A is stopped, and the mode is switched to CIS mode.

[0466] The first embodiment Figure 31 Steps S105-S106 or the third embodiment Figure 48Similarly, in steps S305-S306, in this CIS mode, the line drive circuit 251 generates frame data of the captured image of the object (step S405) and identifies the captured object (step S406).

[0467] When object recognition is completed in this manner, the solid-state imaging device 200 performs a transition from CIS mode to EVS mode. During this transition period, the line drive circuit 251 turns on the control transistor (also referred to as the MST gate) 318 and the switching transistor 317 (steps S407 to S408), and turns off the control transistor 318 (step S409), similar to the first embodiment. Figure 31 Steps S107 to S109 in the third embodiment. Next, [following the third embodiment]... Figure 48 Similar to step S308, the row drive circuit 251 turns on the bias circuit 314A of the response circuit 301L, so that the bias current BIAS flows to the nMOS transistors 313 and 316 of the logarithmic response unit 310A (step S410). This begins to supply photocurrent to the logarithmic response unit 310A, and the mode changes to EVS mode.

[0468] 4.4 Functions and Effects

[0469] As described above, according to this embodiment, when switching from CIS mode to EVS mode, the SN potential of the sensing node SN and / or the cathode potential of the photoelectric conversion element 311 can be fixed to a fixed potential VX that is lower than the SN potential during normal operation, and the supply of bias current to the logarithmic response circuit in the logarithmic response unit 310A can be cut off, thereby further suppressing unexpected increases in the SN potential. This allows for further suppression of dead time periods caused by the voltage level of the voltage signal VPR at ground potential (GND).

[0470] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0471] 5. Fifth Implementation Method

[0472] In the above embodiments, the case of suppressing the dead time period that occurs when transitioning from CIS mode to EVS mode was described. In this embodiment, for example, the case of suppressing the dead time period that may occur when transitioning from full-pixel mode to merged mode or from merged mode to full-pixel mode during EVS operation (which may be EVS mode) is described.

[0473] As described above, when the solid-state imaging device 200 operates in EVS mode, the SN potential of the sensing node SN can fluctuate when transitioning from full-pixel mode to pixel-binding mode or vice versa. In such cases, a dead time period may occur, during which an address event cannot be detected until the SN potential stabilizes at the voltage level required for normal operation. Therefore, in this embodiment, a configuration capable of suppressing the occurrence of dead time periods is illustrated by the following example.

[0474] The following description describes a case where the solid-state imaging device 200 does not include a CIS mode (i.e., the solid-state imaging device 200 does not include the pixel circuit 370 for acquiring grayscale data). However, this embodiment is not limited thereto. Similar to the embodiments described above, this embodiment can be applied when the solid-state imaging device 200 including the pixel circuit 370 is operating in EVS mode, when transitioning from full-pixel mode to binning mode, or when transitioning from binning mode to full-pixel mode.

[0475] Because the configuration of the imaging apparatus, solid-state imaging apparatus, and each component constituting the solid-state imaging apparatus according to this embodiment can be similar to the configuration of any of the first to fourth embodiments, it will be described with reference to this embodiment. However, in this embodiment, the detection chip 202 is replaced by the detection chip described below, and the shared block 221X is replaced by the shared block described below. The following description uses reference to the first embodiment. Figure 7 The described example is the logarithmic response unit 310A. However, the configuration is not limited to this, and other configurations such as those described in the reference section can also be used. Figure 6 Other logarithmic response parts of the described logarithmic response part 310.

[0476] 5.1 Example of chip layout

[0477] Figure 53 This is an example of a plan view of the detection chip according to this embodiment. For example... Figure 53 As shown, the detection chip 202A according to this embodiment has a configuration in which, similar to that in the first embodiment, reference... Figure 4 In the configuration of the described detection chip 202, the column ADC 270 used to read lower-order working data is omitted.

[0478] 5.2 Basic Configuration Example of Shared Blocks

[0479] Figure 54 This is a circuit diagram illustrating an example configuration of the shared block according to this embodiment. For example... Figure 54As shown, the shared block 821 according to this embodiment includes a plurality of response circuits 801A1 to 801A4 (hereinafter, when the response circuits 801A1 to 801A4 are not distinguished from each other, they are referred to as 801A). Note that the total number of response circuits 801A in the shared block 821 is not limited to four in a 2x2 pattern, and can be an integer of 2 or greater.

[0480] Each response circuit 801A has a reference in the first embodiment Figure 21 The described response circuit 301A has a similar configuration, for example, in which the transmission transistor 372, reset transistor 373, floating diffusion region 374, amplification transistor 375 and selection transistor 376 constituting the pixel circuit 370 are omitted.

[0481] In this configuration, when suppressing the SN potential swing of the sensing node SN in each response circuit 801, the control transistor 318 is turned on, and a fixed potential VX is applied to the sensing node SN. This controls the SN potential of the sensing node SN to be set to a fixed potential VX, thereby shortening the settling time caused by the SN potential swing.

[0482] 5.3 Merging Mode via Circuit Sharing

[0483] exist Figure 54 In the configuration shown, for example, by enabling the formation of current paths connecting the sensing nodes SN of each response circuit 801A, a configuration capable of switching between full-pixel mode and merging mode can be obtained. Therefore, examples of the circuit configuration of the shared block 821 that enables switching between full-pixel mode and merging mode are described below with some examples.

[0484] 5.3.1 First Shared Example

[0485] Figure 55 A circuit diagram illustrating an example circuit configuration of a shared block according to a first shared example. The first shared example is an exemplary case in which, according to the first embodiment, reference... Figure 33 The shared block 221C of the second shared example described is used as the basis.

[0486] like Figure 55 As shown, the shared block 821C according to the first shared example has such a configuration, wherein from a similar reference Figure 33The readout circuit 370a connected to the common line 3101 is omitted in the described configuration of shared block 221C. More specifically, shared block 821C has a configuration in which the sensing nodes SN of a plurality of response circuits 801C1 to 801C4 are connected to each other via control transistor 319 and common line 3101. However, shared block 821C retains transmission transistor 372 in each response circuit 801C1 to 801C4 to control the connection between photoelectric conversion element 311 and common line 3101.

[0487] In this configuration, when the shared block 821C is driven in full-pixel mode, the row drive circuit 251 disconnects the transmission transistor 372 and control transistor 319 of each response circuit 801C1-801C4. This allows the photoelectric conversion element 311 of each response circuit 801C1-801C4 to be connected to each sensing node SN, enabling address events to be detected in full-pixel mode.

[0488] Furthermore, when suppressing the SN potential swing of the sensing node SN in full-pixel mode, the control transistors 318 and 319 of the response circuits 801C1 to 801C4 are turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801C1 to 801C4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the transmission transistor 372 and / or the switching transistor 317 of each of the response circuits 801C1 to 801C4.

[0489] Furthermore, when driving the shared block 821C in merged mode, the row drive circuit 251 turns on the switching transistor 317 and control transistor 319 of the response circuit 801C1, turns off the switching transistors 317 and control transistors 319 in the other response circuits 801C2 to 801C4, and turns on the transmission transistor 372. This results in the formation of a current path from the photoelectric conversion element 311 of each response circuit 801C1 to 801C4 to the sensing node SN of the response circuit 801C1, enabling the detection of address events in merged mode.

[0490] Furthermore, when suppressing the SN potential swing of the sensing node SN in the merging mode, the control transistors 318 and 319 of the response circuits 801C1 to 801C4 are turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801C1 to 801C4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the transmission transistor 372 and / or the switching transistor 317 of each of the response circuits 801C1 to 801C4.

[0491] 5.3.2 Second Shared Example

[0492] Figure 56 A circuit diagram illustrating an example circuit configuration of a shared block according to the second sharing example. The second sharing example is based on reference to the first embodiment. Figure 34 The exemplary case of shared block 221D in the third shared example described.

[0493] like Figure 56 As shown, the shared block 821D according to the second shared example has the following configuration: wherein, from a similar reference Figure 34 The readout circuit 370a connected to the common line 3101 is omitted in the configuration of the shared block 221D. More specifically, the shared block 821D has a configuration in which the sensing nodes SN of a plurality of response circuits 801D1 to 801D4 are connected to each other via control transistor 319 and common line 3101. However, the shared block 821D retains a transmission transistor 372 in each response circuit 801D1 to 801D4 to control the connection between the photoelectric conversion element 311 and the common line 3101.

[0494] In this configuration, when the shared block 821D is driven in full-pixel mode, the row drive circuit 251 disconnects the transmission transistor 372 and control transistor 319 of each of the response circuits 801D1 to 801D4. This allows the photoelectric conversion element 311 of each response circuit 801D1 to 801D4 to be connected to each sensing node SN, enabling address events to be detected in full-pixel mode.

[0495] Furthermore, when suppressing the SN potential swing of the sensing node SN in full-pixel mode, the control transistor 318 of the response circuits 801D1 to 801D4 is turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801D1 to 801D4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the switching transistor 317 of each of the response circuits 801D1 to 801D4.

[0496] Furthermore, when driving the shared block 821D in merged mode, the row drive circuit 251 turns on the switching transistor 317 and control transistor 319 of the response circuit 801D1, turns off the switching transistors 317 and control transistors 319 in the other response circuits 801D2 to 801D4, and turns on the transmission transistor 372. This results in the formation of a current path from the photoelectric conversion element 311 of each response circuit 801D1 to 801D4 to the sensing node SN of the response circuit 801D1, enabling the detection of address events in merged mode.

[0497] Furthermore, when suppressing the SN potential swing of the sensing node SN in the merging mode, the control transistor 318 of the response circuits 801D1 to 801D4 is turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801D1 to 801D4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the switching transistor 317 of each of the response circuits 801D1 to 801D4.

[0498] 5.3.3 Third Shared Example

[0499] Figure 57 A circuit diagram illustrating an example circuit configuration of a shared block according to a third sharing example. The third sharing example is an exemplary case in which, according to the first embodiment, reference... Figure 35 The shared block 221CC, which describes the fourth shared example, is used as the basis.

[0500] like Figure 57 As shown, the shared block 821CC according to the third shared example has such a configuration, wherein from a similar reference Figure 35 The readout circuit 370a connected to the common line 3101 is omitted in the configuration of the shared block 221CC. More specifically, the shared block 821CC has a configuration in which the sensing nodes SN of a plurality of response circuits 801C1 to 801C4 are connected to each other via control transistor 319 and common line 3101. However, the shared block 821CC retains a transmission transistor 372 in each response circuit 801C1 to 801C4 to control the connection between the photoelectric conversion element 311 and the common line 3101. This is similar to that described in reference [reference missing]. Figure 55 The configuration of the control transistor 318 in each of the response circuits 801C1 to 801C4 is replaced by a common control transistor 318 connected to the common line 3101 in the first shared example described.

[0501] In this configuration, when the shared block 821D is driven in full-pixel mode, the row drive circuit 251 disconnects the transmission transistor 372 and control transistor 319 of each response circuit 801C1-801C4. This allows the photoelectric conversion element 311 of each response circuit 801C1-801C4 to be connected to each sensing node SN, enabling address events to be detected in full-pixel mode.

[0502] Furthermore, when suppressing the SN potential swing of the sensing node SN in full-pixel mode, the control transistor 318 connected to the common line 3101 is turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801C1 to 801C4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the switching transistor 317 of each of the response circuits 801C1 to 801C4.

[0503] Furthermore, when driving the shared block 821D in merged mode, the row drive circuit 251 turns on the switching transistor 317 and control transistor 319 of the response circuit 801D1, turns off the switching transistors 317 and control transistors 319 in the other response circuits 801D2 to 801D4, and turns on the transmission transistor 372. This results in the formation of a current path from the photoelectric conversion element 311 of each response circuit 801D1 to 801D4 to the sensing node SN of the response circuit 801D1, enabling the detection of address events in merged mode.

[0504] Furthermore, when suppressing the SN potential swing of the sensing node SN in the merging mode, the control transistor 318 connected to the common line 3101 is turned on. This allows a fixed potential VX to be applied to the sensing node SN of each of the response circuits 801C1 to 801C4, thereby shortening the settling time caused by the SN potential swing. At this time, the cathode potential of the photoelectric conversion element 311 can be controlled to a fixed potential VX by turning on the switching transistor 317 of each of the response circuits 801C1 to 801C4.

[0505] 5.4 Functions and Effects

[0506] As described above, even when the solid-state imaging device is operating in EVS mode, by fixing the SN potential of the sensing node SN to a fixed potential VX when switching from full-pixel mode to merged mode or from merged mode to full-pixel mode, the setup time caused by the SN potential swing and the time period required for mode switching can be shortened.

[0507] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0508] 6. Sixth Implementation Method

[0509] The sixth embodiment will describe an example of another configuration for fixing the SN potential of the sensing node SN during mode transition.

[0510] Because the configuration of the imaging apparatus, solid-state imaging apparatus, and each part constituting the solid-state imaging apparatus according to this embodiment can be similar to the configuration of any of the first to third embodiments, it will be described with reference to this embodiment. However, in this embodiment, the response circuit 301X constituting the shared block 221X is replaced with the response circuit described below. The following description is based on the first embodiment. Figure 7 The description illustrates an exemplary case of the response circuit of the logarithmic response unit 310A. However, the configuration is not limited to this, and other configurations such as those described in the reference diagram may also be used. Figure 6 Other logarithmic response parts of the described logarithmic response part 310.

[0511] 6.1 Example of Response Circuit Configuration

[0512] Figure 58 This is a circuit diagram illustrating an example configuration of the response circuit according to this embodiment. (e.g.) Figure 58 As shown, the response circuit 301N according to this embodiment has the same characteristics as the reference circuit in the first embodiment. Figure 21 The described response circuit 301A is configured similarly, for example, in which a control transistor 318 is connected between the gate of an nMOS transistor 312 and the gate of an nMOS transistor 313 constituting a logarithmic conversion circuit (corresponding to the sensing node SN).

[0513] 6.2 Functions and Effects

[0514] In the above configuration, when the control transistor 318 is turned on, the SN potential of the sensing node SN can be determined by the bias current BIAS flowing through the nMOS transistor 313. Therefore, in this embodiment, for example, when transitioning from CIS mode to EVS mode, or switching between full-pixel mode and merge mode, the control transistor 318 is turned on while the supply of bias current BIAS to the nMOS transistor 313 is disconnected, and then the switching transistor 317 is turned on while the control transistor 318 is turned on. This allows for a lower SN potential than the SN potential during normal operation, thereby suppressing the dead time period caused by the voltage level of the voltage signal VPR being stuck at ground potential (GND). When EVS mode is started, the bias current BIAS is supplied to the nMOS transistor 313.

[0515] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0516] 7. Seventh Implementation Method

[0517] While the above implementation is an exemplary case of applying Synchronous EVS to a solid-state imaging device 200, the configuration is not limited to this example, where Synchronous EVS does not require arbitration of requests to read out detection signals output from each shared block 221, etc. For example, as Figure 59 The solid-state imaging device shown also allows for the application of an asynchronous EVS including a row arbitrator 280, which arbitrates the requests from each row output from the address event detection unit 260 and determines the order of reading the detection signals. It should be noted that... Figure 59 The detection chip 1202 in the solid-state imaging apparatus according to this embodiment is shown.

[0518] In this way, even when applying asynchronous EVS, it is possible to suppress the dead time period during mode transitions by utilizing configurations and operations similar to those in the above-described implementation to achieve fast mode transitions.

[0519] Since other configurations, operations, and effects can be similar to those in the above embodiments, their detailed descriptions will be omitted here. Furthermore, the configuration according to this embodiment can be appropriately combined with the above embodiments and / or the embodiments described below.

[0520] 8. Eighth Implementation Method

[0521] When the response circuit 301 / 801, etc., as in the above embodiments includes control transistors 318 and / or 319, it will be necessary to add wiring to the existing response circuit. In this case, the wiring capacitance changes before and after the additional arrangement of control transistors 318 and / or 319, potentially affecting quantum efficiency, EVS operating characteristics, etc., of the incident light. Therefore, the eighth embodiment will describe an example of a pixel layout that can suppress the effects on quantum efficiency, operating characteristics, etc., even with the addition of control transistors 318 and / or 319.

[0522] The following description will be a layout example according to this embodiment, as a basic layout example of the optical receiver 220 of the shared block 221X illustrated in the first embodiment (see reference). Figure 36 or Figure 37 A variation thereof. Furthermore, similar to the first embodiment. Figure 36 or Figure 37 The following description illustrates a schematic layout example on the element formation surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed. Additionally, for clarity, the arrangement of each transistor is indicated by the position of its gate.

[0523] 8.1 Example of a variation of the first layout

[0524] In the first layout variation, the shared block 221A according to the first shared example of the first embodiment will be described (refer to...). Figure 32 The layout example is shown below. Specifically, the first layout variation illustrates the case where each of the response circuits 301A1 to 301A4 includes a separate control transistor 318. Figure 60 This is a plan view showing an example layout of a shared block according to a first layout variation.

[0525] like Figure 60 As shown, in the first layout variation, similar to the reference above... Figure 36 In the first layout example, response circuits 301A1 to 301A4 are arranged in pixel regions 10 formed by a 2×2 pixel pattern constituting shared block 221A. The response circuits 301A1 to 301A4 arranged in each pixel region 10 are arranged symmetrically in the vertical direction (e.g., column direction).

[0526] In each pixel region 10, a control transistor 318 is positioned near the peripheral portion of the pixel region 10. In other words, in the first layout variation, the control transistor 318 is located in an isolation region that electrically isolates adjacent photoelectric conversion elements 311 from each other. This allows the photoelectric conversion elements 311 to be arranged at the center of the pixel region 10, resulting in suppression of degradation of quantum efficiency depending on the angle of light incidence. Furthermore, this arrangement allows maintaining the distance between adjacent photoelectric conversion elements 311, resulting in a reduction in color mixing due to incident light leakage into adjacent pixels.

[0527] Furthermore, in the first layout variation, the reset transistor 373, amplification transistor 375, and selection transistor 376 constituting the pixel circuit 370 are arranged at the center of the 2×2 pixel layout constituting the shared block 221A. This configuration can shorten the length of the wiring connecting the floating diffusion region 374 to the amplification transistor 375 and the reset transistor 373 (and the virtual transistor 972), which facilitates the optimization of the capacitance (FD capacitor) of the floating diffusion region 374.

[0528] In the first layout variation, Figure 7 The logarithmic response unit 310A shown is configured by connecting nMOS transistors 312 and 315 to nMOS transistors 313 and 316 arranged close to each other on opposite sides in adjacent pixel regions 10. This shortens the length of the wiring connecting nMOS transistors 312, 315 and nMOS transistors 313, 316, thereby achieving effects such as improved operating performance due to reduced coupling capacitance.

[0529] Other configurations and effects can be referenced similarly to the above. Figure 36 or Figure 37The layout example described is configured and its effect, and therefore its detailed description is omitted here.

[0530] 8.2 Second Layout Variation Example

[0531] In the second layout variation, the shared block 221CC of the fourth shared example according to the first embodiment will be described (see reference). Figure 35 The layout example is shown below. Specifically, the second layout variation illustrates a case where the response circuits 301C1 to 301C4 include a common control transistor 318, and each of the response circuits 301C1 to 301C4 includes a separate control transistor 319. Figure 61 This is a plan view showing a layout example of a shared block according to a second layout variation.

[0532] like Figure 61 As shown, the second layout variant has a similar design to the reference above. Figure 60 The layout of the first layout variant described is such that each control transistor 319 is disposed at the location of each control transistor 318, and the common control transistor 318 is disposed at the location of the dummy transistor 972.

[0533] By adopting this layout, similar to the first layout variant, effects such as suppressing quantum efficiency degradation and reducing color mixing can be achieved.

[0534] Furthermore, the second layout variation has a configuration in which the common control transistor 318 is disposed at the center of the 2×2 pixel layout. Therefore, in a configuration that can switch between EVS mode and CIS mode, the operational stability when switching between EVS mode and CIS mode can be improved, while suppressing the reduction of light receiving area, aperture ratio, saturation charge, etc. in the photoelectric conversion element 311.

[0535] Other configurations and effects can be referenced similarly to the above. Figure 60 The configuration and effect of the first layout variation are described, and therefore, its detailed description will be omitted here.

[0536] 8.3 Third Layout Variation Example

[0537] In the third layout variation, similar to the second layout variation, the shared block 221CC of the fourth shared example according to the first embodiment will be described (refer to...). Figure 35 Here is a layout example. Figure 62 This is a plan view showing a layout example of a shared block according to a third layout variation.

[0538] like Figure 62 As shown, the third layout variation uses the same reference above. Figure 61The second layout variation described is similar to the layout in which a separate control transistor 319 is located at the center of the 2×2 pixel layout constituting the shared block 221CC, and the pixel circuit 370 and the control transistor 318 are located in the region adjacent to another shared block 221CC.

[0539] By adopting this layout, similar to the second layout variant, operational stability can be improved when switching between EVS and CIS modes, and effects such as suppressing quantum efficiency degradation and reducing color mixing can be achieved.

[0540] Furthermore, because the individual control transistor 319 is positioned at the center of the 2×2 pixel layout in the third layout variation, the wiring length of the sensing node SN can be shortened. This allows for suppression of latency degradation in the merging mode.

[0541] Other configurations and effects can be referenced similarly to the above. Figure 61 The configuration and effects of the second layout variation are described, and therefore, its detailed description will be omitted here.

[0542] 8.4 Fourth Layout Variation Example

[0543] In the fourth layout variation, similar to the first layout variation, the shared block 221A (reference) of the first shared example according to the first embodiment will be described. Figure 32 Here is a layout example. Figure 63 This is a plan view showing a layout example of a shared block according to the fourth layout variation.

[0544] like Figure 63 As shown, in the fourth layout variation, all response circuits 301A1 to 301A4 arranged in the pixel region 10 are arranged to face the same direction. That is, in the fourth layout variation, response circuits with the same layout are periodically arranged throughout the light receiving section 220.

[0545] By adopting this layout, in the fourth layout variation, the misalignment of the photoelectric conversion element 311 relative to the optical axis of the incident light and the differences between pixels in the wiring layout can be reduced, thereby reducing the sensitivity difference between adjacent pixels and the variation in the amount of light leaked to adjacent pixels, thereby improving the uniformity of pixel sensitivity in the entire light receiving section 220.

[0546] Other configurations and effects can be referenced similarly to the above. Figure 60 The configuration and effect of the first layout variation are described, and therefore, its detailed description will be omitted here.

[0547] 8.5 Fifth Layout Variation Example

[0548] In the fifth layout variation, a layout example will be described where the pixel circuit 370 is not included in the shared block (i.e., where the response circuit is designed as an EVS). In this case, the response circuit 301Y (refer to...) Figure 64 (This may include reference in the first embodiment) Figure 7 The logarithmic response unit 310 / 310A is described. Figure 64 This is a plan view showing a layout example of a shared block according to the fifth layout variation.

[0549] like Figure 64 As shown, in the fifth layout variation, the photoelectric conversion element 311 is arranged at the center of the pixel region 10, and nMOS transistors 312 and 315, as well as nMOS transistors 313 and 316, are arranged to clamp the photoelectric conversion element 311. A diffusion region of the nMOS transistor 313 is continuous with the photoelectric conversion element 311. Furthermore, a response circuit 301Y is configured by connecting the nMOS transistors 312 and 315 with the nMOS transistors 313 and 316 arranged in two adjacent pixel regions 10.

[0550] By adopting this layout, response circuits 301Y with the same layout can be arranged periodically relative to the entire light receiver 220. Therefore, similar to the fourth layout variation, the misalignment of the photoelectric conversion element 311 relative to the optical axis of the incident light and the differences between pixels in the wiring layout can be reduced. As a result, the sensitivity difference between adjacent pixels and the deviation in the amount of light leaked to adjacent pixels can be reduced, and the uniformity of pixel sensitivity of the light receiver 220 as a whole can be improved.

[0551] Other configurations and effects can be referenced similarly to the above. Figure 36 or Figure 37 The layout example described is configured and its effect, and therefore its detailed description is omitted here.

[0552] 8.6 Sixth Layout Variation Example

[0553] In the sixth layout variation, the shared block 821C (reference) of the first shared example according to the fifth embodiment will be described. Figure 55 The layout example is shown below. Specifically, the sixth layout variation illustrates the case where the shared block 821C is designed as a shared block for EVS, and each of the response circuits 301C1 to 301C4 includes a separate control transistor 318 and a separate control transistor 319. Figure 65 This is a plan view showing a layout example of a shared block according to the sixth layout variation.

[0554] like Figure 65 As shown, the sixth layout variation uses the same reference above. Figure 60The first layout variation described is similar to the layout in which a separate control transistor 319 is arranged in place of the pixel circuit 370 and the virtual transistor 972.

[0555] This layout allows the photoelectric conversion element 311 to be positioned at the center of the pixel region 10, enabling effects such as suppressing quantum efficiency degradation and reducing color mixing. Furthermore, since the individual control transistor 318 is positioned at the center of the 2×2 pixel layout, the degradation of latency in the merging mode caused by the shortened wiring length of the sensing node SN can be suppressed.

[0556] Other configurations and effects can be referenced similarly to the above. Figure 60 The configuration and effect of the first layout variation are described, and therefore, its detailed description will be omitted here.

[0557] 8.7 Seventh Layout Variation Example

[0558] In the seventh layout variation, the shared block 821CC (reference) of the third shared example according to the fifth embodiment will be described. Figure 57 The layout example is shown below. Specifically, the seventh layout variation illustrates the case where the shared block 821C is designed as a shared block for EVS, and each of the response circuits 301C1 to 301C4 includes a common control transistor 318 and a separate control transistor 319. Figure 66 This is a plan view showing a layout example of a shared block according to the seventh layout variation.

[0559] like Figure 66 As shown, the seventh layout variation uses a similar approach to the reference above. Figure 65 The sixth layout variation described herein is in which three of the four control transistors 318 are replaced by dummy transistors 973. Note that the gate of the dummy transistor 973 may be in a normally off state.

[0560] By adopting this layout, similar to the sixth layout variant, in addition to suppressing quantum efficiency degradation and reducing color mixing effects, it can also suppress latency degradation in the merging mode.

[0561] Other configurations and effects can be referenced similarly to the above. Figure 65 The configuration and effects of the sixth layout variation are described, and therefore its detailed description will be omitted here.

[0562] 9. Ninth Implementation Method

[0563] Next, the ninth embodiment of this disclosure will be described. In EVS, false detection may occur due to noise even when there is no change in brightness. The occurrence rate of this false detection is called the background rate (BGR). When the detection sensitivity of brightness change increases, this BGR is considered to increase.

[0564] For example, in the above embodiments, it is known that the main noise causing BGR is thermal noise generated in the reset transistor 373, amplification transistor 375, and selection transistor 376 constituting the pixel circuit 370, as well as thermal noise generated in the nMOS transistors 312 and 316 included in the logarithmic conversion circuit. Furthermore, since BGR is caused by noise propagating to the comparator, it is evident that the frequency bandwidth of the circuit from the pixel to the comparator is a determining factor for BGR.

[0565] Since the frequency band is determined by the pixel capacitance on the light receiving chip 201 side and the frequency band of the source follower (e.g., buffer 330) and the comparison unit 500 block formed on the detection chip 202 side, it can also be seen from the simulation results that it is sensitive to the pixel capacitance.

[0566] Here, as Figure 18 As shown, the EVS according to the above embodiment includes: a detection pixel 300 including a logarithmic response unit 310 / 310A, a buffer 330, and a differential 340; and a detection circuit 305, which includes, for example, a selection unit 400, a comparison unit 500, and a transmission circuit 360. For simplicity, an exemplary case using the logarithmic response unit 310A will be described below.

[0567] The logarithmic response unit 310A converts the photocurrent flowing from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value of the photocurrent, and outputs the obtained voltage signal to the output node (referred to as node N4) connected to the gate of the nMOS transistor 315. Figure 7 Note that the configuration of the logarithmic response unit 310 / 310A is not limited to this example. For example, the number of nMOS transistors connected in series is... Figure 6 The example shown has two, and Figure 7 The example shown has three. However, the number of nMOS transistors connected in series can be four or more. Furthermore, the number of nMOS transistors connected in series with the photoelectric conversion element 311 can differ from the number of nMOS transistors connected in series with the opposite element.

[0568] In the logarithmic response section 310 / 310A with this configuration, noise can be generated from the nMOS transistors 312, 313, 315, and 316 that constitute the logarithmic conversion circuit. The generated noise is input to the detection circuit 305 through node N4. Therefore, the detection circuit 305 reacts to voltage fluctuations caused by the noise, and thus, there is a possibility that a detection signal (false detection) may be output even when the incident light amount does not change.

[0569] Regarding this problem, the inventors have discovered that the coupling capacitance between nodes N1 and N4 (refer to...) Figure 7 The coupling capacitance between each of nodes N1 to N4 and the power supply (VDD, GND, and VSS) is related to BGR.

[0570] Therefore, in this embodiment, the structural and positional relationships between nodes N1-M4 and the power lines are controlled to satisfy one or more of the conditions illustrated below. In this embodiment, it is assumed that nodes N1-M4 and the power lines include two or more wiring layers M1, M2, ...

[0571] (first condition)

[0572] Each capacitor is formed such that the N1-N2, N1-N3, N1-N4 and N3-N4 capacitors formed by the second wiring layer M2 or higher are greater than the N1-N2, N1-N3, N1-N4 and N3-N4 capacitors formed by the first wiring layer M1 between wirings in the same layer.

[0573] (Second condition)

[0574] A shielding layer is disposed between the N1-N2, N1-N3, N1-N4, and N3-N4 capacitors formed by a second wiring layer or higher, and the semiconductor substrate on which various transistors are formed, in order to reduce the capacitance between the N1 wiring / N3 wiring and the semiconductor substrate. The shielding layer may be wiring that includes another wiring layer (e.g., power lines, etc.), or it may be residual insulating layer obtained by removing the wiring pattern from another wiring layer.

[0575] (Third condition)

[0576] By using a configuration in which capacitors N1-N2, N1-N3, N1-N4, and N3-N4 are formed from a metal oxide metal (MOM) structure such as a comb structure or a metal insulator metal (MIM) structure using an interlayer insulating film for the wiring layers, and by arranging the N4 wiring on the substrate side, the coupling capacitance between node N4 and the semiconductor substrate (hereinafter referred to as the N4-substrate capacitance) increases, while the coupling capacitance between node N1 and the semiconductor substrate (hereinafter referred to as the N1-substrate capacitance) and the coupling capacitance between node N3 and the semiconductor substrate (hereinafter referred to as the N3-substrate capacitance) decrease. In this case, for example, the first wiring layer or the gate of various transistors can be used for the N4 wiring.

[0577] 9.1 Wiring Structure Example

[0578] Next, a wiring structure that satisfies at least one of the above conditions will be described by way of some examples. For simplicity, the semiconductor substrate (semiconductor substrate 1001 described below) and the wiring layer (interlayer insulating film 1010 described below) on which nodes N1-N4 are arranged will be described below. Furthermore, in this specification, node N1 may represent the aforementioned sensing node SN.

[0579] Figures 67 to 70 This is a diagram illustrating an example of a wiring structure designed to satisfy at least one of the above conditions. Specifically, Figure 67 This shows a cross-sectional view of the wiring structure according to the first example; Figure 68 This shows a cross-sectional view of the wiring structure according to the second example; Figure 69 This is a cross-sectional view showing the wiring structure according to the third example; and Figure 70 This is a cross-sectional view showing the wiring structure according to the fourth example. In the first to fourth examples, the wiring constituting nodes N1 to N4 (hereinafter referred to as N1 wiring, N2 wiring, N3 wiring, and N4 wiring, respectively) and power lines (VDD, GND, and VSS) are arranged on three wiring layers M1 to M3. However, Figures 67 to 70 This is a cross-sectional view of the unexposed N2 wiring, and therefore, the N2 wiring is not shown.

[0580] like Figures 67 to 70 As shown, in the first to fourth examples, various transistors 1004 constituting the pixel circuit 370 and / or the logarithmic response unit 310 / 310A are formed in a p-type well layer 1002, which is disposed across the gate insulating film 1003 on the device formation surface side of the semiconductor substrate 1001. On the device formation surface on which the various transistors 1004 are formed, there is an interlayer insulating film 1010 including N1 wiring, N2 wiring, N3 wiring, N4 wiring, and power lines (VDD, GND, and VSS).

[0581] (First wiring layer M1)

[0582] Of the three wiring layers M1 to M3 disposed in the interlayer insulating film 1010, the first wiring layer M1, which is closest to the semiconductor substrate 1001, is the layer where the N4 wiring is mainly disposed. Note that some or all of the other wiring (N1 to N3 wiring, power lines, etc.) may be disposed in the first wiring layer M1 to establish connections with various transistors 1004 disposed on the component forming surface.

[0583] The N4 wiring arranged in the first wiring layer M1 may have, for example, a comb structure comprising two or more comb teeth extending in a direction parallel to the component forming surface (hereinafter referred to as comb wiring), such as in Figure 67 In the first example shown, it could also be a solid pattern comprising a main plane parallel to the element forming surface, as in Figure 68 The second example shown is illustrated. However, the configuration is not limited to this and allows for various variations, such as solid patterns that partially have comb-like structures, openings, etc.

[0584] In this way, by arranging the N4 wiring in the first wiring layer M1 closest to the semiconductor substrate 1001, the coupling capacitance (N4-substrate capacitance) between the N4 wiring and the semiconductor substrate 1001 (including the well layer 1002; this also applies hereinafter) can be increased. Furthermore, since the N4 wiring can be used as a shielding layer relative to other wirings formed in the second wiring layer M2 or higher, the increase in the coupling capacitance (N1-substrate capacitance, N2-substrate capacitance, and N3-substrate capacitance) between the N1 to N3 wirings and the semiconductor substrate 1001 can be suppressed.

[0585] However, this configuration is not limited to this, and as in Figure 69 In the third example shown, a configuration in which the N1 to N4 wirings are not arranged in the first wiring layer M1 (reference area R2-2) is permissible. This allows the distance between the N1 to N3 wirings formed in the second wiring layer M2 or higher and the semiconductor substrate 1001 to be maintained, resulting in suppression of the increase in coupling capacitance between the N1 to N3 wirings and the semiconductor substrate 1001.

[0586] Furthermore, when as in Figure 70 In the fourth example shown, when the gate 1005 disposed on the semiconductor substrate 1001 is used as node N4, other wirings (N1, N2 and N3 wirings) can be arranged in the region on the gate 1005 in the first wiring layer M1, and the N1-N4 capacitor and the N3-N4 capacitor can be formed by MIM capacitors.

[0587] (Second wiring layer M2)

[0588] One or more wirings primarily selected from N1, N2, and N3 can be arranged in a second wiring layer M2 above the first wiring layer M1. However, for purposes such as adjusting the coupling capacitance between wirings, some or all other wirings (N4 wiring, power lines, etc.) can be arranged in the second wiring layer M2. For example, as Figures 67 to 70 As shown, by arranging the comb-tooth wiring forming the N4 wiring between the comb-tooth wirings that constitute the N1, N2, and N3 wirings respectively, and forming comb-tooth capacitors between the N1, N2, and N3 wirings and the N4 wiring, it is possible to increase the N1-N4 capacitor, the N2-N4 capacitor, and the N3-N4 capacitor.

[0589] exist Figure 68 In the second example shown, the MIM capacitor may be formed between the N1 wiring disposed in the second wiring layer M2 and the N4 wiring disposed in the first wiring layer M1. Furthermore, in Figure 70 In the fourth example shown, MIM capacitors may be formed between the N3 wiring disposed in the second wiring layer M2 and the gate 1005 disposed in the first wiring layer M1, and between the N1 wiring disposed in the second wiring layer M2 and the gate 1005 disposed in the first wiring layer M1.

[0590] (Third wiring layer M3 and higher)

[0591] When the third wiring layer M3 and higher wiring layers are placed on the second wiring layer M2, similar to the second wiring layer M2, comb-tooth capacitance can be formed by setting the N1 to N4 wirings and / or power lines according to the coupling capacitance required for each wiring.

[0592] At this point, the power lines (VDD, GND, and VSS) are preferably located on the top layer (in this example, the third wiring layer M3). This allows the power lines to act as a shielding layer against electromagnetic interference from external sources (such as the detection chip 202), thereby improving operational stability.

[0593] In addition, the N4 wiring can be placed on the top layer to form a comb-tooth capacitor between the N4 wiring and the power line.

[0594] Furthermore, in the comb capacitor configured as described above, the comb capacitor consisting of the N4 wiring and another wiring is preferably configured such that the N4 wiring is located at the outermost periphery. Additionally, the power line can be configured to be immediately adjacent to the N4 wiring located at the outermost periphery.

[0595] 9.2 Effect

[0596] By designing the wiring and power lines (VDD, GND, and VSS) of N1 to N4 to satisfy at least one of the first to third conditions as described above, the following effect can be achieved.

[0597] By placing the N4 wiring in the first wiring layer M1 and setting the comb capacitor having the N1 to N3 wirings as a side electrode in the second wiring layer M2 or a higher layer, the first wiring layer M1 can be used as a shielding layer to shield the electric field between the N1 to N3 wirings and the power lines (VDD, GND, and VSS). This reduces the coupling capacitance between the N1 to N3 wirings and the semiconductor substrate 1001, thereby reducing the bottom resistance temperature (BGR).

[0598] By arranging the N4 wiring in the first wiring layer M1 and forming an N4-substrate capacitor with a large area, an N4-substrate capacitor with a large capacitance is formed, which makes it possible to significantly reduce BGR.

[0599] By arranging the N3-N4, N2-N4, N1-N4, N1-N3, N1-N2 and N4 power line capacitors as comb capacitors in the second wiring layer M2 or higher, these capacitors can be increased without increasing the coupling capacitance between the N1 to N4 wirings and the semiconductor substrate 1001, thereby reducing the BGR.

[0600] By arranging the N4 wiring in the first wiring layer M1 and arranging the N1 to N3 wirings in the second wiring layer M2, the coupling capacitance between the N1 to N3 wirings and the N4 wiring is formed by the interlayer insulating film constituting the interlayer insulating film 1010, thereby reducing the BGR.

[0601] By utilizing the outermost periphery of the comb-like capacitor formed by the N4 wiring, the coupling between the N1 to N3 wirings in the same layer and the power line is shielded by the N4 wiring in the same layer. This allows for a reduction in the coupling capacitance between the N1 to N3 wirings and the power line while increasing the N4-power line capacitance. This allows for a reduction in BGR.

[0602] 9.3 Specific examples of wiring layout

[0603] Next, a specific layout example of the N1 to N4 wiring and power lines (VDD, GND, and VSS) according to this embodiment will be described. For simplicity, the following description focuses on the N1 to N4 wiring and power lines (VDD, GND, and VSS) arranged for the response circuit 301. Furthermore, this example will describe an exemplary case in which the interlayer insulating film 1010 includes four layers: the first wiring layer M1 to the fourth wiring layer M4.

[0604] Figure 71 This is a plan view showing an example of the wiring layout of the first wiring layer M1; Figure 72 This is a plan view showing an example of the wiring layout for the second wiring layer M2; Figure 73 This is a plan view showing an example of the wiring layout for the third wiring layer M3; and Figure 74This is a plan view showing an example of the wiring layout for the fourth wiring layer M4. Furthermore, Figure 75 It shows along Figures 71 to 74 A cross-sectional view of an example structure cut by line A-A'. Furthermore, Figure 76 This is a plan view showing an example of the wiring layout of the first wiring layer M1 according to a variant.

[0605] like Figures 71 to 75 As shown, the first wiring layer M1 is configured such that an N4 wiring layer with a comb-like structure is disposed over most of the pixel region 10, and power lines (VDD, GND, and VSS) are arranged to surround the outer periphery of the N4 wiring. In the first wiring layer M1, portions of the N1 to N3 wirings are arranged to be electrically connected to various transistors constituting the response circuit 301.

[0606] In the second wiring layer M2, the corresponding comb-tooth wiring is arranged such that N4 wiring and either N1 or N3 wiring are arranged alternately. At this time, N4 wiring is arranged on the outermost perimeter. In the third wiring layer M3, the power line VDD is arranged around N4 wiring.

[0607] In the fourth wiring layer M4, which is the topmost layer, the comb-tooth wirings are arranged such that the N4 and N3 wirings are arranged alternately, and their outer periphery is surrounded by the power line GND.

[0608] like Figure 71 and Figure 72 As shown, the extension directions of the comb-tooth wiring disposed in a specific wiring layer (the first wiring layer M1 in this example) and the extension directions of the comb-tooth wiring disposed in another wiring layer (the second wiring layer M2 in this example) are preferably not parallel to each other (perpendicular in this example). With this configuration, light that has passed through the photoelectric conversion element 311 and entered the interlayer insulating film 1010 can be reflected by the N1 to N4 wiring and the power line and returned to the photoelectric conversion element 311, thereby resulting in an improvement in quantum efficiency.

[0609] like Figure 76 As shown, the N4 wiring in the first wiring layer M1 can be a solid (non-hollow) pattern, rather than the comb structure described above.

[0610] 10. Tenth Implementation Method

[0611] Next, a tenth embodiment of this disclosure will be described. In the above embodiment, when the EVS mode and CIS mode are driven simultaneously, there is a possibility that the potential of the sensing node SN may fluctuate due to the potential change of the transmission signal TRG when the transmission transistor 372 of the pixel circuit 370 is driven, and this fluctuation may cause false detection and dead time periods in EVS operation. This will use Figure 77The circuit configuration example of the shared block shown and Figure 78 The example shown, in which the transmission transistor 372 and the switching transistor 317 are connected to drive lines TG11 to TG42, is described. Although Figure 77 The shared block 221Z shown has reference from above. Figure 32 The configuration of the control transistor 318 is omitted in the described shared block 221A, but this is only an example, and the configuration of the shared block 221Z is not limited to this example.

[0612] like Figure 77 As shown, in a hybrid mode that simultaneously drives EVS mode and CIS mode, one pixel (e.g., response circuit 301A1) of the total four pixels constituting the shared block 221X (e.g., response circuits 301A1 to 301A4) operates in EVS mode to constantly detect brightness changes, while the remaining three pixels (e.g., response circuits 301A2 to 301A4) operate in CIS mode to generate a grayscale image at a predetermined frame rate. This allows grayscale images to be acquired for regions where brightness changes are detected in EVS mode when brightness changes occur.

[0613] However, as Figure 78 As shown, in the hybrid mode, a transmission signal for transferring signal charge from photoelectric conversion element 311 to floating diffusion region 374 is repeatedly applied to drive lines TG22, TG32, and TG42 at a predetermined period. Drive lines TG22, TG32, and TG42 are connected to the gate of the transmission transistor 372 of the three pixels (response circuits 301A2 to 301A4) operating in CIS mode; hereinafter, the pixels operating in CIS mode are also referred to as CIS pixels (corresponding to the grayscale pixels mentioned above). Meanwhile, a cut-off voltage is constantly applied to drive line TG12, which is connected to the gate of the transmission transistor 372 of the pixel (response circuit 301A1) operating in EVS mode; hereinafter, the pixels operating in EVS mode are also referred to as EVS pixels (corresponding to the detection pixels mentioned above).

[0614] Therefore, when coupling capacitance exists between the drive lines TG22, TG32, and TG42 connected to the CIS pixels (response circuits 301A2 to 301A4) and the sensing node SN (response circuit 301A1) in the EVS pixel, the SN potential of the sensing node SN fluctuates due to electrostatic induction caused by potential changes in the transmission signals applied to the drive lines TG22, TG32, and TG42. This will affect the operation of the logarithmic response section 310 / 310A of the EVS pixel, similar to the SN potential fluctuation when switching from CIS mode to EVS mode, potentially leading to false detection or dead time periods. Incidentally, for example, this fluctuation of the SN potential of the sensing node SN can also occur through selection signals or reset signals, in addition to transmission signals.

[0615] Therefore, this embodiment reduces the coupling capacitance between the drive line of the gate of each of the transmission transistor 372, selection transistor 376, and reset transistor 373 connected to the CIS pixel and the sensing node SN of the EVS pixel, thereby avoiding problems caused by fluctuations in the SN potential of the sensing node SN due to the transmission signal.

[0616] 10.1 Example of cross-sectional structure and wiring layout

[0617] Figure 79 This is a cross-sectional view showing an example of a wiring structure according to this embodiment. For the sake of simplicity, Figure 79 An excerpt is shown of a semiconductor substrate 1001 and an interlayer insulating film 1010 on which nodes N1 to N4 are arranged. Figure 80 This is a plan view showing an example of the wiring layout of the first wiring layer M1; Figure 81 This is a plan view showing an example of the wiring layout for the second wiring layer M2; Figure 82 This is a plan view showing an example of the wiring layout for the third wiring layer M3; and Figure 83 This is a plan view showing an example of the wiring layout for the fourth wiring layer M2.

[0618] like Figures 79 to 83 As shown, in this embodiment, the drive line LD connected to the gate of the transmission transistor 372, the reset transistor 373, and the select transistor 376 constituting the pixel circuit 370 is disposed in a wiring layer different from that of the sensing node SN. Figures 79 to 83 The example shows a case where the drive line TG11 of the drive line LD is arranged in the fourth wiring layer M4 (which is the uppermost layer in the interlayer insulating film 1010), and the sensing node SN is arranged in the first wiring layer M1 and the second wiring layer M2.

[0619] Furthermore, in this embodiment, a wiring (hereinafter also referred to as shielding wiring) 1012 for electromagnetic shielding is provided between the drive line LD and the sensing node SN. Figure 79 The example illustrates a case where shielded wiring 1012 is arranged in a third wiring layer M3 between a first wiring layer M1 and a second wiring layer M2 in which a sensing node SN is arranged, and a fourth wiring layer M4 in which a drive line LD is arranged. Shielded wiring 1012 can be, for example, N2 to N4 wiring, power lines (VDD, GND, and VSS), etc.

[0620] Furthermore, the drive line LD is connected to the pixel circuit 370 disposed on the element forming surface of the semiconductor substrate 1001 via a through-hole wiring 1011 formed in the interlayer insulating film 1010. Figures 79 to 83 (Transmission transistor 372 in the example shown). Therefore, when the drive line LD is disposed in the wiring layer above the sensing node SN, the wiring (also part of the drive line LD) connecting the drive line LD and the pixel circuit 370 to each other passes through the wiring layer where the sensing node SN is disposed. Therefore, in this embodiment, in the same layer as the wiring layer where the sensing node SN is disposed, a shielding wiring 1012 that serves as electromagnetic shielding is disposed between the drive line LD and the sensing node SN, which penetrates the wiring layer. Figures 79 to 83 In the example shown, the shielded wiring is arranged in region R12 between the drive line LD and the sensing node SN in another response circuit 301A2 (and 301A3, 301A4). The drive line LD is in region R13 and connects the drive line TG11 of the fourth wiring layer M4 and the gate of the transmission transistor 372 in the response circuit 301A1 to each other. The shielded wiring can be, for example, the N2 to N4 wiring, power lines (VDD, GND, and VSS), etc.

[0621] By providing a shielded wiring 1012 between the sensing node SN and the drive line LD in this manner, the coupling capacitance between the sensing node SN and the drive line LD can be reduced. This suppresses fluctuations in the SN potential caused by potential changes in the drive signal applied to the drive line LD, thereby suppressing false detections and dead time periods.

[0622] Furthermore, in this embodiment, the wiring connecting the drive line LD to the gates of various transistors on the semiconductor substrate 1001 (e.g., Figures 79 to 83 In the example shown, the drive line LD in region R13 is approximately perpendicular to the element formation surface of the semiconductor substrate 1001. This allows for a reduction in the opposing area between the sensing node SN and the drive line LD, resulting in a reduction in the coupling capacitance between the sensing node SN and the drive line LD. Consequently, fluctuations in the SN potential caused by the drive signal applied to the drive line LD can be suppressed, thereby suppressing false detections and dead time periods.

[0623] 11. Examples of application to moving bodies

[0624] The technology disclosed herein (the Technology) can be applied to a variety of products. The Technology disclosed herein can be applied to devices mounted on any mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0625] Figure 84 This is a block diagram illustrating an example configuration of a vehicle control system as an example of a mobile body control system to which the technology of embodiments of the present disclosure can be applied.

[0626] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 84 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional configurations of the comprehensive control unit 12050, examples include a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0627] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0628] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are substitutes for keys, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0629] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to an imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives these captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, and text on the road surface, or detecting their distances.

[0630] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0631] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0632] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior, wherein the information about the vehicle's interior or exterior is obtained by the external information detection unit 12030 or the internal information detection unit 12040, and the microcomputer 12051 outputs control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to realize functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, vehicle speed maintenance driving, vehicle collision warning, and vehicle lane departure warning, etc.

[0633] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the inside or outside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0634] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicles detected by the exterior information detection unit 12030.

[0635] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 85 In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0636] Figure 85 This is a schematic diagram illustrating an example of the mounting position of the imaging unit 12031.

[0637] exist Figure 85 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0638] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose and imaging unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0639] Incidentally, Figure 85Examples of the shooting ranges of imaging units 12101 to 12104 are described. Shooting range 12111 represents the shooting range of imaging unit 12101 installed at the front nose. Shooting ranges 12112 and 12113 represent the shooting ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Shooting range 12114 represents the shooting range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0640] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0641] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to maintain in front of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, cooperative control for autonomous driving can be performed, enabling the vehicle to drive automatically without relying on driver operation.

[0642] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0643] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104 (which are infrared cameras) and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian is displayed at a desired location.

[0644] Examples of vehicle control systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure can be appropriately applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, micro-manufacturing of pixels and higher visibility in captured images can be achieved, thereby alleviating driver fatigue.

[0645] It should be noted that the above embodiments illustrate examples of the present technology, and the matters in the embodiments correspond to the matters specified in the claims. Similarly, the matters specified in the claims correspond to the matters in the embodiments of the present technology represented by the same names as the matters specifying the present invention. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope and spirit of the present technology.

[0646] The effects described in this specification are merely examples, and therefore, other effects may exist, not limited to the exemplary effects.

[0647] It should be noted that this technology may also have the following configurations.

[0648] (1) A solid-state imaging device, comprising:

[0649] Multiple pixels, each outputting the brightness change of the incident light; and

[0650] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0651] Each pixel includes:

[0652] Photoelectric conversion element, which generates charge according to the amount of incident light;

[0653] A logarithmic conversion circuit, connected to the photoelectric conversion element, converts the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent; and

[0654] A first transistor, the drain of which is connected to the sensing node of the logarithmic conversion circuit.

[0655] (2) The solid-state imaging device according to (1),

[0656] In this configuration, the source of the first transistor is connected to a first potential that is equal to or higher than the reference potential and lower than the power supply voltage.

[0657] (3) The solid-state imaging device according to (2),

[0658] Each pixel further includes a first circuit, which outputs the brightness change of the incident light that has entered the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit.

[0659] The detection circuit includes a second circuit that outputs the event signal based on the brightness change output from each of the pixels.

[0660] (4) The solid-state imaging device according to (2), wherein the reference potential is a negative potential or ground potential.

[0661] (5) The solid-state imaging apparatus according to (2), wherein the first potential is a lower potential than the potential of the sensing node during normal operation of the logarithmic conversion circuit.

[0662] (6) The solid-state imaging apparatus according to any one of (2) to (5),

[0663] The logarithmic conversion circuit includes:

[0664] The second transistor has a gate connected to the photoelectric conversion element; and

[0665] The third transistor has a source electrode connected to the photoelectric conversion element.

[0666] The gate of the third transistor is connected to the drain of the second transistor, and

[0667] The sensing node is a wiring connected to the gate of the second transistor.

[0668] (7) The solid-state imaging apparatus according to (6), wherein each pixel further includes a fourth transistor, the drain of the fourth transistor being connected to the gate of the second transistor and the source of the third transistor, and the source of the fourth transistor being connected to a photoelectric conversion element.

[0669] (8) The solid-state imaging device according to (7),

[0670] Each of the pixels further includes:

[0671] A fifth transistor, the source of which is connected to the photoelectric conversion element; and

[0672] A readout circuit is connected to the drain of the fifth transistor and generates a pixel signal based on the charge generated in the photoelectric conversion element.

[0673] (9) The solid-state imaging apparatus according to (8), wherein the first transistor is connected to the sensing node via the fifth transistor and the fourth transistor.

[0674] (10) The solid-state imaging apparatus according to (8) or (9), wherein each of the pixels further comprises a sixth transistor connected to the drain of the fourth transistor and the drain of the fifth transistor.

[0675] (11) The solid-state imaging apparatus according to (10), wherein the first transistor is connected to the sensing node via the sixth transistor.

[0676] (12) The solid-state imaging apparatus according to any one of (8) to (11),

[0677] The readout circuit includes the first transistor, the source of which is connected to the drain of the fifth transistor and the drain of which is connected to the first potential.

[0678] (13) The solid-state imaging apparatus according to (12), wherein each of the pixels further includes a sixth transistor connected to the drain of the fourth transistor and the drain of the fifth transistor.

[0679] (14) The solid-state imaging apparatus according to any one of (8) to (13), wherein the first transistor is connected to the sensing node via the fourth transistor.

[0680] (15) The solid-state imaging device according to (7),

[0681] Each of the pixels further includes:

[0682] A fifth transistor, the source of which is connected to the drain of the fourth transistor; and

[0683] A sixth transistor, the drain of which is connected to the drain of the fourth transistor, the source of the third transistor, and the gate of the second transistor, and the source of which is connected to the drain of the fifth transistor, and

[0684] The first transistor is connected to the sensing node via the sixth transistor.

[0685] (16) The solid-state imaging device according to (15),

[0686] Each pixel further includes a readout circuit connected to the drain of the fifth transistor and generating a pixel signal based on the charge generated in the photoelectric conversion element.

[0687] The readout circuit includes a source connected to the drain of the fifth transistor and a drain connected to the first transistor at the first potential.

[0688] (17) The solid-state imaging apparatus according to any one of (1) to (16), wherein the logarithmic conversion circuit includes a bias circuit for controlling the current flowing through the logarithmic conversion circuit.

[0689] (18) The solid-state imaging apparatus according to any one of (1) to (17),

[0690] Each pixel further includes a fifth transistor, the source of which is connected to the photoelectric conversion element.

[0691] The solid-state imaging device also includes a common line that connects the drain of the fifth transistor among the plurality of pixels.

[0692] (19) The solid-state imaging apparatus according to (18) further includes a readout circuit connected to a common line and generating a pixel signal based on the charge generated in the photoelectric conversion element of each pixel.

[0693] (20) The solid-state imaging apparatus according to (18) or (19), wherein the first transistor is connected to the common line and is shared by the plurality of pixels.

[0694] (21) The solid-state imaging apparatus according to any one of (1) to (20),

[0695] The photoelectric conversion elements, including those in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0696] The first transistor is disposed on the element forming surface between the photoelectric conversion elements arranged in the matrix.

[0697] (22) The solid-state imaging device according to (10),

[0698] The photoelectric conversion elements, including those in each of the multiple pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0699] The sixth transistor is disposed on the element forming surface between the photoelectric conversion elements arranged in the matrix.

[0700] (23) The solid-state imaging device according to (21) or (22), wherein the photoelectric conversion element and the first transistor are periodically arranged in a matrix on the element forming surface.

[0701] (24) A solid-state imaging device, comprising:

[0702] Multiple pixels, each outputting the brightness change of the incident light; and

[0703] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0704] Each pixel includes:

[0705] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0706] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0707] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0708] The logarithmic conversion circuit includes:

[0709] The first transistor has its gate connected to the photoelectric conversion element;

[0710] The second transistor has its source connected to the photoelectric conversion element and its gate connected to the drain of the first transistor;

[0711] A third transistor, the source of which is connected to the drain of the first transistor and the gate of the second transistor, the gate of which is connected to the drain of the second transistor; and

[0712] A fourth transistor, the source of which is connected to the drain of the second transistor and the gate of the third transistor, and the gate of which is connected to the drain of the third transistor.

[0713] The solid-state imaging device also includes:

[0714] The first wiring is connected to the gate of the first transistor;

[0715] The second wiring connects the gate of the second transistor and the drain of the first transistor to each other;

[0716] The third wiring connects the gate of the third transistor and the drain of the second transistor to each other; and

[0717] The fourth wiring connects the gate of the fourth transistor and the drain of the third transistor to each other.

[0718] The first to fourth wirings are dispersedly arranged into multiple wiring layers in the interlayer insulating film disposed on the device forming surface side of the semiconductor substrate, and

[0719] At least a portion of the fourth wiring is disposed in the wiring layer closest to the semiconductor substrate among the plurality of wiring layers disposed in the interlayer insulating film.

[0720] (25) A solid-state imaging device, comprising:

[0721] Multiple pixels, each outputting the brightness change of the incident light; and

[0722] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0723] Each pixel includes:

[0724] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0725] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0726] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0727] The logarithmic conversion circuit includes:

[0728] The first transistor has its gate connected to the photoelectric conversion element;

[0729] The second transistor has its source connected to the source of the photoelectric conversion element and its gate connected to the drain of the first transistor.

[0730] A third transistor, the source of which is connected to the drain of the first transistor and the gate of the second transistor, the gate of which is connected to the drain of the second transistor; and

[0731] A fourth transistor, the source of which is connected to the drain of the second transistor and the gate of the third transistor, and the gate of which is connected to the drain of the third transistor.

[0732] The solid-state imaging device also includes:

[0733] The first wiring is connected to the gate of the first transistor;

[0734] The second wiring connects the gate of the second transistor and the drain of the first transistor to each other;

[0735] The third wiring connects the gate of the third transistor and the drain of the second transistor to each other; and

[0736] The fourth wiring connects the gate of the fourth transistor and the drain of the third transistor to each other.

[0737] The first to fourth wirings are dispersedly arranged in multiple wiring layers within the interlayer insulating film disposed on the device forming surface side of the semiconductor substrate, and

[0738] At least one of the first to fourth wirings has a comb-like structure.

[0739] (26) A solid-state imaging device, comprising:

[0740] Multiple pixels, each outputting the brightness change of the incident light; and

[0741] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0742] Each pixel includes:

[0743] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0744] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0745] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0746] The logarithmic conversion circuit includes:

[0747] The first transistor has its gate connected to the photoelectric conversion element;

[0748] The second transistor has its source connected to the photoelectric conversion element and its gate connected to the drain of the first transistor;

[0749] A third transistor, the source of which is connected to the drain of the first transistor and the gate of the second transistor, the gate of which is connected to the drain of the second transistor; and

[0750] A fourth transistor, the source of which is connected to the drain of the second transistor and the gate of the third transistor, and the gate of which is connected to the drain of the third transistor.

[0751] The solid-state imaging device also includes:

[0752] The first wiring is connected to the gate of the first transistor;

[0753] The second wiring connects the gate of the second transistor and the drain of the first transistor to each other;

[0754] The third wiring connects the gate of the third transistor and the drain of the second transistor to each other; and

[0755] The fourth wiring connects the gate of the fourth transistor and the drain of the third transistor to each other.

[0756] The first to fourth wirings are dispersedly arranged in multiple wiring layers in an interlayer insulating film disposed on the device forming surface side of the semiconductor substrate.

[0757] At least a portion of the fourth wiring is disposed in the wiring layer closest to the semiconductor substrate among the plurality of wiring layers disposed in the interlayer insulating film, and

[0758] At least a portion of the fourth wiring in the wiring layer located on the side closest to the semiconductor substrate has a solid pattern.

[0759] (27) A solid-state imaging device, comprising:

[0760] Multiple pixels, each outputting the brightness change of the incident light; and

[0761] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0762] Each pixel includes:

[0763] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0764] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0765] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0766] The logarithmic conversion circuit includes:

[0767] The first transistor has its gate connected to the photoelectric conversion element;

[0768] The second transistor has its source connected to the photoelectric conversion element and its gate connected to the drain of the first transistor;

[0769] A third transistor, the source of which is connected to the drain of the first transistor and the gate of the second transistor, the gate of which is connected to the drain of the second transistor; and

[0770] A fourth transistor, the source of which is connected to the drain of the second transistor and the gate of the third transistor, and the gate of which is connected to the drain of the third transistor.

[0771] The solid-state imaging device also includes:

[0772] The first wiring is connected to the gate of the first transistor;

[0773] The second wiring connects the gate of the second transistor and the drain of the first transistor to each other;

[0774] The third wiring connects the gate of the third transistor and the drain of the second transistor to each other; and

[0775] The fourth wiring connects the gate of the fourth transistor and the drain of the third transistor to each other.

[0776] The first to fourth wirings are dispersedly arranged in multiple wiring layers in the interlayer insulating film disposed on the device forming surface side of the semiconductor substrate.

[0777] The wiring layer closest to the semiconductor substrate includes the gates of one or more transistors formed on the element formation surface of the semiconductor substrate, and

[0778] At least a portion of the fourth wiring is the gate of at least one of the one or more transistors.

[0779] (28) A solid-state imaging device, comprising:

[0780] Multiple pixels, each outputting the brightness change of the incident light; and

[0781] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0782] Each pixel includes:

[0783] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0784] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0785] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0786] The logarithmic conversion circuit includes:

[0787] The first transistor has its gate connected to the photoelectric conversion element;

[0788] The second transistor has its source connected to the photoelectric conversion element and its gate connected to the drain of the first transistor;

[0789] A third transistor, the source of which is connected to the drain of the first transistor and the gate of the second transistor, the gate of which is connected to the drain of the second transistor; and

[0790] A fourth transistor, the source of which is connected to the drain of the second transistor and the gate of the third transistor, and the gate of which is connected to the drain of the third transistor.

[0791] The solid-state imaging device also includes:

[0792] The first wiring is connected to the gate of the first transistor;

[0793] The second wiring connects the gate of the second transistor and the drain of the first transistor to each other;

[0794] The third wiring connects the gate of the third transistor and the drain of the second transistor to each other;

[0795] The fourth wiring connects the gate of the fourth transistor and the drain of the third transistor to each other; and

[0796] A power line is disposed within the interlayer insulation film and connected to one of the power supply voltage, ground, and a predetermined potential.

[0797] The first to fourth wirings are dispersedly arranged in multiple wiring layers within the interlayer insulating film disposed on the device forming surface side of the semiconductor substrate, and

[0798] At least a portion of the fourth wiring is located closer to the semiconductor substrate than the layer in which the power lines are arranged.

[0799] (29) The solid-state imaging apparatus according to any one of (24) to (28), wherein the coupling capacitance formed between the wirings in the wiring layer closest to the semiconductor substrate side of the first to fourth wirings is smaller than the coupling capacitance formed between the wirings in the wiring layer located above the wiring layer closest to the semiconductor substrate side.

[0800] (30) A solid-state imaging device, comprising:

[0801] Multiple pixels, each outputting the brightness change of the incident light; and

[0802] The detection circuit outputs an event signal based on the brightness change output from each of the pixels.

[0803] Each pixel includes:

[0804] Photoelectric conversion elements generate charge based on the amount of incident light; and

[0805] A logarithmic conversion circuit is connected to the photoelectric conversion element and converts the photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0806] The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate.

[0807] The logarithmic conversion circuit includes:

[0808] The first transistor has its gate connected to the photoelectric conversion element;

[0809] A second transistor, the source of which is connected to the photoelectric conversion element and the gate of which is connected to the drain of the first transistor; and

[0810] A sensing node, the sensing node being connected to the gate of the first transistor.

[0811] Each of the pixels also includes:

[0812] The third transistor has its drain connected to the gate of the first transistor and the source of the second transistor, and its source connected to the photoelectric conversion element.

[0813] A fourth transistor, the source of which is connected to the photoelectric conversion element; and

[0814] A readout circuit, connected to the drain of the fourth transistor, generates pixel signals based on the charge generated in the photoelectric conversion element.

[0815] The solid-state imaging device also includes:

[0816] A first driving line is connected to the gate of the third transistor;

[0817] The second drive line is connected to the gate of the fourth transistor; and

[0818] One or more third drive lines are connected to the gates of one or more transistors constituting the readout circuit.

[0819] The first to third driving lines and the sensing nodes are dispersedly arranged in multiple wiring layers in an interlayer insulating film disposed on one side of the element formation surface of the semiconductor substrate, and

[0820] The first drive line to the third drive line and the sensing node are located in different layers of the plurality of wiring layers.

[0821] (31) The solid-state imaging device according to (30) further includes a shielding layer disposed between the sensing node and the first to third driving lines.

[0822] (32) The solid-state imaging apparatus according to (31), wherein the shielding layer includes at least one of the following: a power line connected to a power supply voltage, a ground voltage or a predetermined potential; and wiring in the wiring constituting the logarithmic conversion circuit other than the sensing node.

[0823] (33) The solid-state imaging apparatus according to any one of (30) to (32), wherein the first drive line to the third drive line are arranged in the uppermost layer of a plurality of wiring layers.

[0824] (34) The solid-state imaging apparatus according to any one of (30) to (32), wherein the wiring connecting at least one of the first drive line to the third drive line to the gate extends substantially perpendicular to the element forming surface.

[0825] (35) An imaging device, comprising:

[0826] According to the solid-state imaging device described in (2); and

[0827] The control unit controls the solid-state imaging device.

[0828] The solid-state imaging device includes multiple operating modes, and

[0829] The control unit controls the potential of the sensing node when switching the operating mode of the solid-state imaging device.

[0830] (36) The imaging apparatus according to (35),

[0831] When switching the operating mode of the solid-state imaging device, the control unit applies a first potential to the cathode of the sensing node and / or the photoelectric conversion element via a first transistor.

[0832] (37) The imaging apparatus according to (35) or (36), wherein the control unit cuts off the current flowing through the logarithmic conversion circuit when switching the operating mode of the solid-state imaging apparatus.

[0833] Reference number list

[0834] 100 Imaging Device

[0835] 110 Optics Department

[0836] 120 Recording Department

[0837] 130 Control Department

[0838] 200 Solid-State Imaging Device

[0839] 201 Optical Receiver Chip

[0840] 202, 202A, 1202 detection chips

[0841] Through-hole arrangement section 211~213, 231~233

[0842] 220 Optical Receiver

[0843] 221, 221A, 221C, 221CC, 221D, 821, 821C, 821CC, 821D, shared block

[0844] 240 Signal Processing Circuit

[0845] 251-line drive circuit

[0846] 252-column drive circuit

[0847] 260 Address Event Detection Department

[0848] 270 lines of ADC

[0849] 280-line arbitrator

[0850] 300 detection pixels

[0851] Response circuits for 301, 301A-301N, 301Y, 801A, 801C, and 801D

[0852] 305 detection circuit

[0853] 310, 310A Logarithmic Response Unit

[0854] 311 Photoelectric conversion element

[0855] 312, 313, 315, 316, 347, 512 nMOS transistors

[0856] 314, 314a, 314b, 345, 346, 411, 511 pMOS transistors

[0857] 314A, 314B bias circuits

[0858] 314c DAC

[0859] 314d bias control transistor

[0860] 314e Constant Current Source

[0861] 317 Switching Transistor

[0862] 318, 319 control transistors

[0863] 320 detection block

[0864] 370 pixel circuit

[0865] 370a Readout Circuit

[0866] 372 Transmission Transistors

[0867] 373 Reset Transistor

[0868] 374 Floating Diffusion Zone

[0869] 375 Amplifying Transistor

[0870] 376 Select Transistor

[0871] 330 buffer

[0872] 340 Differential

[0873] 341 and 343 capacitors

[0874] 342 Inverter

[0875] 344 Switch

[0876] 360° transmission circuit

[0877] 400 Selection Department

[0878] 410, 420 selectors

[0879] 500 Comparative Section

[0880] 510 and 520 comparators

[0881] 972 and 973 virtual transistors

[0882] 1001 Semiconductor Substrate

[0883] 1002 well layer

[0884] 1003 gate insulating film

[0885] 1004 transistors

[0886] 1010 interlayer insulating film

[0887] 1011 Through-hole wiring

[0888] 1012 Shielded Wiring

[0889] 3101 Public Line

[0890] LD, TG11~TG42 drive lines

[0891] M1 First Wiring Layer

[0892] M2 Second Wiring Layer

[0893] M3 Third Wiring Layer

[0894] M4 Fourth Wiring Layer

[0895] N1 node (N1 wiring)

[0896] N2 node (N2 wiring)

[0897] N3 Node (N3 Wiring)

[0898] N4 node (N4 wiring)

[0899] SN sensing node

[0900] VSL Vertical Signal Line

Claims

1. A solid-state imaging device, comprising: Multiple pixels, each of which outputs a change in the brightness of the incident light; as well as The detection circuit outputs an event signal based on the brightness change output from each of the pixels. Each of the pixels includes: Photoelectric conversion element, which generates charge according to the amount of incident light; A logarithmic conversion circuit, connected to the photoelectric conversion element, converts the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent; and A first transistor, the drain of which is connected to the sensing node of the logarithmic converter circuit. The source of the first transistor is connected to a first potential that is equal to or higher than the reference potential and lower than the power supply voltage.

2. The solid-state imaging device according to claim 1, in, Each pixel further includes a first circuit that outputs the brightness change of the incident light entering the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit. The detection circuit includes a second circuit that outputs the event signal based on the brightness change output from each of the pixels.

3. The solid-state imaging device according to claim 1, wherein, The reference potential is a negative potential or ground potential.

4. The solid-state imaging device according to claim 1, wherein, The first potential is a lower potential than the potential of the sensing node when the logarithmic conversion circuit is operating normally.

5. The solid-state imaging device according to claim 1, in, The logarithmic conversion circuit includes: A second transistor, the gate of which is connected to the photoelectric conversion element; and A third transistor, the source of which is connected to the photoelectric conversion element. The gate of the third transistor is connected to the drain of the second transistor, and The sensing node is a wiring connected to the gate of the second transistor.

6. The solid-state imaging device according to claim 5, wherein, Each pixel further includes a fourth transistor, the drain of which is connected to the gate of the second transistor and the source of the third transistor, and the source of which is connected to the photoelectric conversion element.

7. The solid-state imaging device according to claim 6, in, Each of the pixels also includes: A fifth transistor, the source of which is connected to the photoelectric conversion element; and A readout circuit is connected to the drain of the fifth transistor and generates a pixel signal based on the charge generated in the photoelectric conversion element.

8. The solid-state imaging device according to claim 7, wherein, The first transistor is connected to the sensing node via the fifth transistor and the fourth transistor.

9. The solid-state imaging device according to claim 7, wherein, Each pixel also includes a sixth transistor connected to the drain of the fourth transistor and the drain of the fifth transistor.

10. The solid-state imaging device according to claim 9, wherein, The first transistor is connected to the sensing node via the sixth transistor.

11. The solid-state imaging device according to claim 7, in, The readout circuit includes a source connected to the drain of the fifth transistor and a drain connected to the first transistor at the first potential.

12. The solid-state imaging device according to claim 11, wherein, Each pixel also includes a sixth transistor connected to the drain of the fourth transistor and the drain of the fifth transistor.

13. The solid-state imaging device according to claim 7, wherein, The first transistor is connected to the sensing node via the fourth transistor.

14. The solid-state imaging device according to claim 6, in, Each of the pixels also includes: A fifth transistor, the source of which is connected to the drain of the fourth transistor; and A sixth transistor, the drain of which is connected to the drain of the fourth transistor, the source of the third transistor, and the gate of the second transistor, and the source of which is connected to the drain of the fifth transistor, and The first transistor is connected to the sensing node via the sixth transistor.

15. The solid-state imaging device according to claim 14, in, Each pixel further includes a readout circuit connected to the drain of the fifth transistor and generating a pixel signal based on the charge generated in the photoelectric conversion element. The readout circuit includes a source connected to the drain of the fifth transistor and a drain connected to the first transistor at the first potential.

16. The solid-state imaging device according to claim 1, in, Each pixel further includes a fifth transistor, the source of which is connected to the photoelectric conversion element. The solid-state imaging device also includes a common line that connects the drains of the fifth transistor in the plurality of pixels.

17. The solid-state imaging apparatus according to claim 16, further comprising: A readout circuit is connected to the common line and generates a pixel signal based on the charge generated in the photoelectric conversion element of each pixel.

18. The solid-state imaging device according to claim 16, wherein, The first transistor is connected to the common line and is shared by the plurality of pixels.

19. The solid-state imaging device according to claim 1, in, The photoelectric conversion elements, including in each of the plurality of pixels, are arranged in a matrix on the element forming surface of the semiconductor substrate, and The first transistor is disposed on the element forming surface between the photoelectric conversion elements arranged in the matrix.

Images