Gate voltage regulation system and device

Abstract

This invention provides a gate voltage regulation system and apparatus. The system includes: a power modulation module, a gate level locking module, and a gate voltage driving module. The first input terminal of the power modulation module is connected to an external power supply; the second input terminal of the power modulation module is connected to a first output terminal of an externally supplied logic level; the first output terminal of the power modulation module is connected to a power amplifier; the second output terminal of the power modulation module is connected to the first input terminal of the gate level locking module; the second input terminal of the gate level locking module is connected to a second output terminal of the externally supplied logic level; the output terminal of the gate level locking module is connected to the input terminal of the gate voltage driving module; and the output terminal of the gate voltage driving module is connected to the power amplifier. This invention achieves both wide applicability and ease of operation when configuring the bias circuit of the power amplifier.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and more particularly to a gate voltage regulation system and device. Background Technology

[0002] Power amplifiers are an indispensable key component in various communication technologies, and gate regulation of power amplifiers is of paramount importance.

[0003] In existing technologies, power amplifier devices include integrated power amplifier devices and discrete component amplifier circuits. Integrated power amplifier devices are mostly used in low-power applications, while discrete component amplifier circuits have a wider range of applications. Correspondingly, there are also various forms of bias circuits for power amplifiers. Specifically, some use voltage divider resistors as bias circuits, but due to the influence of the power supply, the gate voltage is unstable and the driving capability is limited. Some use a closed-loop negative feedback method to form a bias circuit, which adjusts the gate voltage of the power amplifier by comparing the acquired output voltage of the power amplifier with a preset voltage to achieve gate voltage stability. However, due to the limitations of the power amplifier structure, the range of applications is limited. Still others use independent voltage regulators in the form of digital lookup tables as bias circuits for voltage regulation. Independent voltage regulators have a large output range and can flexibly adjust the output bias voltage, but they require subsequent debugging of the chip in conjunction with the power amplifier, which is cumbersome.

[0004] Therefore, there is an urgent need for a gate voltage regulator system that can balance wide application range and ease of operation. Summary of the Invention

[0005] This invention provides a gate voltage regulation system and apparatus to solve the problem in the prior art that it is impossible to balance wide application range and ease of operation when setting the bias circuit of a power amplifier.

[0006] In a first aspect, embodiments of the present invention provide a gate voltage regulator system, comprising:

[0007] Power modulation module, gear locking module, and gate voltage drive module;

[0008] The first input terminal of the power modulation module is used to connect to an external power supply, and the second input terminal of the power modulation module is used to connect to the first output terminal of the external logic level so as to perform power modulation according to the level signal transmitted by the external logic level; the first output terminal of the power modulation module is used to connect to the power amplifier to supply power to the power amplifier.

[0009] The second output terminal of the power modulation module is connected to the first input terminal of the gear position locking module. The gear position locking module is used to collect the current of the power modulation module to obtain the sampling current. The second input terminal of the gear position locking module is used to connect to the second output terminal of the external logic level so as to determine the counting information according to the external logic level. The output terminal of the gear position locking module is connected to the input terminal of the gate voltage driving module. The gear position locking module is used to determine the gate voltage reference signal according to the counting information and the sampling current, and transmit the gate voltage reference signal to the gate voltage driving module.

[0010] The output of the gate voltage drive module is used to connect to a power amplifier so as to provide a voltage to the gate of the power amplifier according to the received gate voltage reference signal.

[0011] In one possible implementation, the power modulation module includes a power switch modulation unit and a switch array;

[0012] The input terminal of the power switch modulation unit serves as the second input terminal of the power modulation module in order to receive the level signal of the externally supplied logic level.

[0013] The output terminal of the power switch modulation unit is connected to the first input terminal of the switch array, and is used to output a voltage signal to drive the switch array according to the level signal;

[0014] The second input terminal of the switch array is used to connect to an external power supply; the first output terminal of the switch array serves as the first output terminal of the power modulation module; and the second output terminal of the switch array serves as the second output terminal of the power modulation module.

[0015] In one possible implementation, the gear locking module includes a current sampling unit, a square wave generating unit, a fuse unit, a counting unit, a multiplexer unit, and a digital-to-analog converter unit;

[0016] The input terminal of the current sampling unit serves as the first input terminal of the gear locking module, used to sample the current of the switch array to obtain the sampled current; the first output terminal of the current sampling unit is connected to an external resistor and grounded, used to lock the sampled current to obtain the first voltage; the second output terminal of the current sampling unit is connected to the first input terminal of the square wave generator, used to transmit the voltage digital signal corresponding to the first voltage to the square wave generator.

[0017] The third output terminal of the current sampling unit is connected to the second input terminal of the square wave generating unit, and is used to sample the first voltage when the voltage digital signal received by the square wave generating unit meets the preset conditions; the output terminal of the square wave generating unit is connected to the first input terminal of the fuse unit, and is used to transmit the square wave signal generated according to the first voltage to the fuse unit so that the fuse unit can perform the corresponding operation.

[0018] The first output terminal of the counting unit is connected to the second input terminal of the fuse unit, and the fuse unit is used to receive the filtering information transmitted by the counting unit. The output terminal of the fuse unit is connected to the second input terminal of the counting unit and the second input terminal of the multiplexing unit respectively, so that when the fuse unit completes the corresponding operation, it transmits the generated locking signal to the counting unit, and at the same time, transmits the generated switching signal and the fuse digital signal determined according to the square wave signal to the multiplexing unit.

[0019] The first input terminal of the counting unit serves as the second input terminal of the gear locking module, used to determine the counting information based on the level signal transmitted by the external logic level and to determine the filtering information based on the counting information; the first output terminal of the counting unit is connected to the multiplexing unit, used to transmit the counting signal corresponding to the counting information to the multiplexing unit;

[0020] The output of the multiplexing unit is connected to the input of the digital-to-analog converter. The multiplexing unit is used to determine the voltage reference signal based on the counting signal and the switching signal, and then transmit the voltage reference signal to the digital-to-analog converter.

[0021] The output of the digital-to-analog converter unit serves as the output of the gear locking module, which transmits the gate voltage reference signal determined based on the voltage reference signal to the gate voltage drive module.

[0022] In one possible implementation, when the fuse unit has completed its corresponding operation, it is used to blow the fuse inside the fuse unit according to the square wave signal and the filtering information.

[0023] In one possible implementation, the switch array includes MOSFETs M n ;

[0024] The current sampling unit includes MOSFETs M1, M2, M3, and M4, a first constant current source I1, a second constant current source I2, an amplifier AMP, and a comparator COMP.

[0025] The gate of MOSFET M1 is connected to MOSFET M n The gate of MOSFET M1 is used to sample the current, which is a multiple of the current mirror of the switching array, to obtain the gate sampling current. The source of MOSFET M1 is connected to the source of MOSFET M... n The source of MOSFET M1 is connected to the source of MOSFET M2, and the drain of MOSFET M4 is connected to the drain of MOSFET M2 and the gate of MOSFET M4.

[0026] The drain of MOSFET M4 is connected to the source of MOSFET M1 and the drain of MOSFET M2. n The source of MOSFET M4 is connected to the non-inverting input of amplifier AMP and the input of the second constant current source I2, respectively; the output of the second constant current source I2 is grounded.

[0027] The gates of MOSFET M3 are connected to MOSFET M... n The drain of MOSFET M3 and the power amplifier are connected, with the drain of MOSFET M3 connected to the source of MOSFET M1 and the source of MOSFET M2 respectively. n The source of MOSFET M3 is connected to the inverting input of amplifier AMP and the input of the first constant current source I1, respectively; the output of the first constant current source I1 is grounded.

[0028] The output of amplifier AMP is connected to the gate of MOSFET M2;

[0029] The source of MOSFET M2 is connected to an external resistor and the first input terminal of comparator COMP, respectively, to input the first voltage locked by the external resistor to comparator COMP;

[0030] The second input terminal of comparator COMP is used to input the zero temperature coefficient voltage; the output terminal of comparator COMP serves as the second output terminal of the current sampling unit, used to compare the first voltage with the zero temperature coefficient voltage, and outputs a high-level digital signal when the first voltage is greater than or equal to the zero temperature coefficient voltage, and outputs a low-level digital signal when the first voltage is less than the zero temperature coefficient voltage.

[0031] In one possible implementation, when the voltage digital signal received by the square wave generating unit meets the preset conditions, the square wave generating unit acquires the first voltage, which is used when the voltage digital signal received by the square wave generating unit is a high-level digital signal.

[0032] In one possible implementation, current locking is applied to the sampled current to obtain a first voltage, including:

[0033] according to Determine the resistance value of the external resistor;

[0034] The sampling current is locked based on the resistance value of the external resistor to obtain the first voltage;

[0035] Where R is the resistance of the external resistor, V ref Where is the zero temperature coefficient voltage, I is the operating current of the power amplifier, and n is the current mirror factor.

[0036] In one possible implementation, the current mirror factor is:

[0037] In one possible implementation, the gate voltage driver module is a Class AB amplifier.

[0038] In a second aspect, embodiments of the present invention provide a gate voltage regulator device, including a silicon wafer and a gate voltage regulator system disposed on the silicon wafer in a first aspect or any possible implementation thereof.

[0039] This invention provides a gate voltage regulator system. A power modulation module modulates the power supply of a power amplifier, a range locking module acquires the current from the power modulation module to obtain a sampling current, and the range locking module determines counting information. Based on the counting information and the sampling current, a gate voltage reference signal is determined. Finally, a gate voltage drive module provides a gate voltage to the power amplifier's gate based on the gate voltage reference signal. This gate voltage is related to the current flowing into the power amplifier, thus enabling a stable gate voltage to be provided. Because this gate voltage is related to the current flowing into the power amplifier, no further debugging with the power amplifier is required, simplifying operation. The gate voltage drive module provides sufficient current driving capability, making the gate voltage regulator system widely applicable. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a first structural schematic diagram of the gate voltage regulator system provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the second structure of the gate voltage regulator system provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the structure of the current sampling unit provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the gate voltage regulator device provided in an embodiment of the present invention. Detailed Implementation

[0045] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0047] Figure 1A first structural schematic diagram of the gate voltage regulator system provided in an embodiment of the present invention is described in detail below:

[0048] like Figure 1 As shown, the gate voltage regulation system includes: a power modulation module 1, a gate position locking module 2, and a gate voltage driving module 3.

[0049] The first input terminal of the power modulation module 1 is used to connect to the external power supply 4, and the second input terminal of the power modulation module 1 is used to connect to the first output terminal of the external logic level 5 so as to perform power modulation according to the level signal transmitted by the external logic level 5; the first output terminal of the power modulation module 1 is used to connect to the power amplifier 6 to supply power to the power amplifier 6.

[0050] In this embodiment, the power modulation module 1 modulates the power according to the level signal transmitted by the external logic level 5, and uses the modulated voltage to power the power amplifier 6.

[0051] The second output terminal of the power modulation module 1 is connected to the first input terminal of the gear position locking module 2. The gear position locking module 2 is used to collect the current of the power modulation module 1 to obtain the sampling current. The second input terminal of the gear position locking module 2 is used to connect to the second output terminal of the external logic level 5 so as to determine the counting information according to the external logic level 5. The output terminal of the gear position locking module 2 is connected to the input terminal of the gate voltage driving module 3. The gear position locking module 2 is used to determine the gate voltage reference signal according to the counting information and the sampling current, and transmit the gate voltage reference signal to the gate voltage driving module 3.

[0052] In this embodiment, the gear locking module 2 collects the current of the power modulation module 1 to obtain the sampling current, which also includes the current supplying power to the power amplifier 6. Based on this, the sampling current is processed, and the final gate voltage reference signal obtained is related to the current flowing into the power amplifier 6. Moreover, the current modulated by the power modulation module 1 is stable, so the sampling current collected from the power modulation module 1 is also stable. Therefore, there is no need to debug the power amplifier in the future, and it can be used directly to provide a stable voltage to the gate of the power amplifier.

[0053] The output of the gate voltage drive module 3 is used to connect to the power amplifier 6 so as to provide a voltage to the gate of the power amplifier 6 according to the received gate voltage reference signal.

[0054] In this embodiment, the gate voltage driving module 3 provides a stable voltage to the gate of the power amplifier 6 based on the received gate voltage reference signal, thereby stabilizing the gate voltage of the power amplifier 6.

[0055] Furthermore, the gate voltage drive module is an AB class amplifier; using an AB class amplifier to charge and discharge the gate of the power amplifier 6 can provide sufficient driving capability and ensure the range of the output voltage, thereby enabling the gate voltage system of the present invention to be applied to the gates of various power amplifiers.

[0056] In this embodiment of the invention, the power supply of the power amplifier is modulated by a power modulation module, and the current of the power modulation module is collected by a range locking module to obtain a sampling current. The range locking module also determines counting information and determines a gate voltage reference signal based on the counting information and the sampling current. Finally, the gate voltage drive module provides a gate voltage to the gate of the power amplifier based on the gate voltage reference signal. This gate voltage is related to the current flowing into the power amplifier, thereby enabling the provision of a stable gate voltage to the power amplifier. Since the gate voltage is related to the current flowing into the power amplifier, no further debugging with the power amplifier is required, making the operation simple. The gate voltage drive module can provide sufficient current driving capability, making the gate voltage regulation system widely applicable.

[0057] In one possible implementation, see Figure 2 The diagram shows a second structural schematic of the gate voltage regulator system. The power modulation module 1 includes a power switch modulation unit 11 and a switch array 12. The input terminal of the power switch modulation unit 11 serves as the second input terminal of the power modulation module 1 to receive the level signal of the external logic level 5. The output terminal of the power switch modulation unit 11 is connected to the first input terminal of the switch array 12 and is used to output a voltage signal to drive the switch array 12 according to the level signal. The second input terminal of the switch array 12 is used to connect to the external power supply 4. The first output terminal of the switch array 12 serves as the first output terminal of the power modulation module 1. The second output terminal of the switch array 12 serves as the second output terminal of the power modulation module 1.

[0058] In this embodiment, the power switch modulation unit 11 receives the level signal of the external logic level 5, determines the voltage signal to drive the switch array 12 based on the level signal, and the switch array 12 supplies power to the power amplifier 6 based on the voltage signal and the power supply of the external power supply 4.

[0059] Specifically, the two power supply terminals of the power switch modulation unit can be 23V and 28V respectively, so that it can be modulated according to the received level signal, thereby outputting the corresponding voltage signal to drive the switch array 12; in addition, the resistance of the switch array is less than or equal to 100 milliohms, and a switch array with a resistance of 40 milliohms can be selected to avoid the switch array from overheating due to long-term use, which would affect the stability of the power supply.

[0060] In one possible implementation, the gear locking module 2 includes a current sampling unit 21, a square wave generating unit 22, a fuse unit 23, a counting unit 24, a multiplexing unit 25, and a digital-to-analog conversion unit 26.

[0061] The input terminal of the current sampling unit 21 serves as the first input terminal of the gear locking module 2, used to sample the current of the switch array 12 to obtain the sampled current; the first output terminal of the current sampling unit 21 is connected to the external resistor 27 and grounded, used to lock the sampled current to obtain the first voltage; the second output terminal of the current sampling unit 21 is connected to the first input terminal of the square wave generating unit 22, used to transmit the voltage digital signal corresponding to the first voltage to the square wave generating unit 22.

[0062] In this embodiment, the current sampling unit 21 samples the current of the switch array 12 to obtain the sampled current, which also includes the current supplied by the switch array 12 to the power amplifier 6. The current sampling unit 21 locks the sampled current through the external resistor 27 to obtain the first voltage, and then performs subsequent processing based on the voltage digital signal determined by the first voltage, thereby providing a stable gate voltage for the power amplifier 6.

[0063] The third output terminal of the current sampling unit 21 is connected to the second input terminal of the square wave generating unit 22, and is used to sample the first voltage when the voltage digital signal received by the square wave generating unit 22 meets the preset conditions; the output terminal of the square wave generating unit 22 is connected to the first input terminal of the fuse unit 23, and is used to transmit the square wave signal generated according to the first voltage to the fuse unit 23 so that the fuse unit 23 can perform the corresponding operation.

[0064] In this application, the square wave generating unit 22 determines whether to acquire the first voltage based on the voltage digital signal; if the square wave generating unit 22 does not acquire the first voltage, it will not transmit a signal to the fuse unit 23; when the square wave generating unit 22 acquires the first voltage, it will transmit a square wave signal to the fuse unit 23, thereby enabling the fuse unit to perform the next operation.

[0065] The first output terminal of the counting unit 24 is connected to the second input terminal of the fuse unit 23, which is used to receive the filtering information transmitted by the counting unit 24. The output terminal of the fuse unit 23 is connected to the second input terminal of the counting unit 24 and the second input terminal of the multiplexing unit 25, respectively. When the fuse unit 23 completes the corresponding operation, it transmits the generated locking signal to the counting unit 24, and at the same time, transmits the generated switching signal and the fuse digital signal determined according to the square wave signal to the multiplexing unit 25.

[0066] In this embodiment, the fuse unit 23 receives the filtering information transmitted by the counting unit 24 and filters the fuses inside the fuse unit according to the filtering information, so that after receiving the square wave signal, the corresponding operation can be performed on the filtered fuses according to the square wave signal. When the fuse unit 23 completes the corresponding operation, it generates a locking signal and a switching signal. The locking signal is used to lock the counting unit 24. After receiving the locking signal, the counting unit 24 will lock, and the counting information of the locking unit 24 will no longer change. The fuse unit 23 transmits the switching signal and the fuse digital signal determined according to the square wave signal to the multiplexing unit 25 so that the multiplexing unit 25 can perform signal switching and signal output.

[0067] Furthermore, when the corresponding operation is completed, the fuse unit 23 is used to blow the fuse inside the fuse unit 23 according to the square wave signal and the screening information; the fuse unit 23 selects the fuse that needs to be blown according to the screening information, and blows the corresponding fuse according to the square wave signal. When the fuse is blown, the corresponding operation is completed.

[0068] The first input terminal of the counting unit 24 serves as the second input terminal of the gear locking module 2, and is used to determine the counting information and the filtering information based on the level signal transmitted by the external logic level 5. The first output terminal of the counting unit 24 is connected to the multiplexing unit 25 and is used to transmit the counting signal corresponding to the counting information to the multiplexing unit 25.

[0069] In this embodiment, the counting unit 24 determines the counting information based on the level signal transmitted by the external logic level 5, and determines the filtering information based on the counting information. Before receiving the lock signal, the counting unit 24 transmits the filtering information to the fuse unit 23 and the counting signal corresponding to the counting information to the multiplexing unit 25. At this time, the voltage is subsequently provided to the gate of the power amplifier 6 based on the counting signal. When the counting unit 24 receives the lock signal, the counting unit 24 locks the counting information, that is, it no longer updates the counting information based on the level signal. Subsequently, the voltage is no longer provided to the gate of the power amplifier 6 based on the counting signal determined by the counting information of the counting unit 24, but rather based on the fuse digital signal determined by the fuse unit 23.

[0070] The output of the multiplexing unit 25 is connected to the input of the digital-to-analog converter 26. The multiplexing unit 25 is used to determine the voltage reference signal based on the counting signal and the switching signal, and transmit the voltage reference signal to the digital-to-analog converter 26.

[0071] In this embodiment, the multiplexing unit 25 receives a counting signal, a fuse digital signal, and a switching signal. Based on the switching signal, it determines the fuse digital signal as a new voltage reference signal and transmits it to the digital-to-analog converter 26. Specifically, before the fuse unit 23 completes its corresponding operation, the multiplexing unit 25 does not receive the switching signal, but only the counting signal. At this time, the multiplexing unit 25 determines the counting signal as the voltage reference signal and transmits it to the digital-to-analog converter 26 so that the gate of the power amplifier 6 can be supplied with voltage based on the counting signal. When the fuse unit 23 completes its corresponding operation, the multiplexing unit 25 receives the switching signal and the fuse digital signal. At this time, the multiplexing unit 25 switches the counting signal to the fuse digital signal based on the switching signal, that is, it determines the voltage reference signal based on the fuse digital signal and transmits it to the digital-to-analog converter 26.

[0072] The output terminal of the digital-to-analog converter unit 26 serves as the output terminal of the gear locking module 2, and is used to transmit the gate voltage reference signal determined according to the voltage reference signal to the gate voltage drive module 3.

[0073] In this embodiment, the digital-to-analog converter 26 determines the gate voltage reference signal based on the received voltage reference signal in order to provide a voltage to the gate of the power amplifier 6.

[0074] In addition, the fuse unit 23, the counting unit 24 and the multiplexing unit 25 each have eight bits. That is, the fuse unit 23 is an eight-bit fuse, the counting unit 24 is an eight-bit counter and the multiplexing unit 25 is also eight-bit. The number of bits in the above three units corresponds, which can transmit signals clearly and accurately.

[0075] In one possible implementation, see Figure 3 The schematic diagram of the current sampling unit shown shows that the switching array includes MOS transistors M n The current sampling unit includes MOSFETs M1, M2, M3, and M4, a first constant current source I1, a second constant current source I2, an amplifier AMP, and a comparator COMP.

[0076] The gate of MOSFET M1 is connected to MOSFET M n The gate of MOSFET M1 is used to acquire the current mirrored by the current of switch array 12 to obtain the gate sampling current. The source of MOSFET M1 is connected to the source of MOSFET M2. n The source of MOSFET M1 is connected to the source of MOSFET M2, and the drain of MOSFET M4 is connected to the drain of MOSFET M2 and the gate of MOSFET M4.

[0077] In this embodiment, the gate acquisition switch array 12 of MOS transistor M1 is used to acquire the gate of MOS transistor M1. nThe gate current is measured to obtain the gate sampling current. This sampling current is obtained by directly sampling the three ports of the switching array, proportionally replicating the current in the switching array. The gate sampling current is related to the MOSFET M... n The ratio of the gate current to the current mirror value is the current mirror factor. Specifically, the current mirror factor can be...

[0078] The drain of MOSFET M4 is connected to the source of MOSFET M1 and the drain of MOSFET M2. n The source of MOSFET M4 is connected to the non-inverting input of amplifier AMP and the input of the second constant current source I2, respectively; the output of the second constant current source I2 is grounded.

[0079] The gates of MOSFET M3 are connected to MOSFET M... n The drain of MOSFET M3 and the power amplifier 6 are connected to the source of MOSFET M1 and the source of MOSFET M2, respectively. n The source of MOSFET M3 is connected to the inverting input of amplifier AMP and the input of the first constant current source I1, respectively; the output of the first constant current source I1 is grounded.

[0080] The output of amplifier AMP is connected to the gate of MOSFET M2.

[0081] In this embodiment, the drain of MOSFET M4 collects data from MOSFET M in the switch array 12. n The source current is measured to obtain the source sampling current, which is also a proportional replication of the current in the switch array; the gate of MOSFET M3 samples the current of MOSFET M in switch array 12. n The drain current is obtained by sampling the drain current, which is also a proportional replication of the current in the switch array; the source of MOSFET M4 is connected to the non-inverting input of amplifier AMP, and the source of MOSFET M3 is connected to the inverting input of amplifier AMP, so that it can be clamped by amplifier AMP and fed back to the drain of MOSFET M1 through MOSFET M2.

[0082] The source of MOSFET M2 is connected to an external resistor and the first input terminal of comparator COMP, respectively, to input the first voltage locked by external resistor 27 to comparator COMP.

[0083] The second input terminal of comparator COMP is used to input the zero temperature coefficient voltage; the output terminal of comparator COMP serves as the second output terminal of the current sampling unit 21, used to compare the first voltage with the zero temperature coefficient voltage, and output a high-level digital signal when the first voltage is greater than or equal to the zero temperature coefficient voltage, and output a low-level digital signal when the first voltage is less than the zero temperature coefficient voltage.

[0084] In this embodiment, the source of MOSFET M2 is connected to an external resistor, so that all the current flowing out of the source of MOSFET M2 flows into the external resistor for current locking, thereby obtaining the first voltage. Figure 3 V is adopted in China out The first voltage is represented and input to the first input terminal of comparator COMP. The first voltage is compared with a predetermined zero temperature coefficient voltage. Figure 3 V is adopted in China ref This indicates the zero temperature coefficient voltage. When the first voltage is greater than or equal to the zero temperature coefficient voltage, it means that the sampling current has been preliminarily automatically adjusted and can provide a stable voltage to the gate of the power amplifier 6 based on the sampling current.

[0085] Furthermore, current locking is applied to the sampled current to obtain the first voltage, including: according to Determine the resistance value of external resistor 27; lock the sampling current based on the resistance value of external resistor 27 to obtain the first voltage; where R is the resistance value of external resistor 27, and V... ref The zero temperature coefficient voltage is I, the operating current of the power amplifier 6, which can be calculated using 600mV. n is the current mirror factor, so that the corresponding first voltage can be determined based on the sampled current, and the first voltage and the zero temperature coefficient voltage can be accurately compared. Furthermore, the external resistor 27 can be set outside the gear locking module 2, which can be easily adjusted.

[0086] In addition, when the voltage digital signal received by the square wave generating unit 22 meets the preset conditions, the square wave generating unit 22 acquires the first voltage, which is used when the voltage digital signal received by the square wave generating unit 22 is a high-level digital signal.

[0087] During initial power supply, the gate voltage of the power amplifier 6 is provided based on the counting information determined by the counting unit 24. The sampling current is then collected to determine the first voltage. At this time, the first voltage is small and less than the zero temperature coefficient voltage, and the comparator COMP outputs a low-level digital signal. As the counting information increases, the first voltage gradually increases. When the first voltage is equal to or greater than the zero temperature coefficient voltage, the comparator COMP reverses and outputs a high-level digital signal, indicating that the gate voltage of the power amplifier 6 has been initially adjusted and a stable gate voltage can be determined based on the sampling current. Therefore, the comparator COMP reverses and transmits the high-level digital signal to the square wave generation unit 22. The square wave generation unit 22 starts to collect the first voltage based on the received high-level digital signal, thereby providing a stable voltage for the gate of the power amplifier 6 in the future.

[0088] In one specific embodiment, the external logic level frequency is 10kHz, the output gate voltage variation range is -3.2 to -0.4V, and the sensitivity is 11mV. After the gate voltage regulation system is powered on, the counting unit 24 first determines the counting information based on the external logic level 5 and provides the gate voltage for the power amplifier 6. The provided gate voltage increases as the counting information increases. The current sampling unit 21 collects the current provided to the power amplifier 6 by the switch array 12. As the collected current gradually increases, the first voltage also gradually increases. When the first voltage is equal to or greater than the zero temperature coefficient, the gate voltage is provided to the power amplifier 6 based on the first voltage. Since the first voltage is determined based on the collected current related to the power amplifier 6, it can continuously provide a stable gate voltage for the power amplifier 6. Furthermore, after the gate voltage regulation system is powered on, it performs an adaptive process. Without manual operation, it can automatically determine the gate voltage of the power amplifier, avoiding the need for additional adjustments to the power amplifier gate voltage by the staff and saving a lot of manpower.

[0089] In this embodiment of the invention, the power supply of the power amplifier is modulated by a power modulation module, and the current of the power modulation module is collected by a range locking module to obtain a sampling current. The range locking module is also used to determine counting information and determine a gate voltage reference signal based on the counting information and the sampling current. Finally, the gate voltage driving module provides a gate voltage to the gate of the power amplifier based on the gate voltage reference signal. Specifically, the current of the three ports of the switch array is collected by a current sampling unit. When the first voltage corresponding to the sampling current is less than a preset zero temperature coefficient voltage, a voltage is provided to the gate of the power amplifier based on the gate voltage reference signal determined by the counting information of the counting unit. As the sampling current increases, when the first voltage corresponding to the sampling current is equal to or greater than the preset zero temperature coefficient voltage, a high-level voltage signal is output. The square wave generation unit collects the received high-level voltage signal. The first voltage is applied, and a square wave signal is generated and transmitted to the fuse unit. The fuse unit blows the fuse according to the selection information transmitted by the counting unit. When the fuse blows, the counting unit is locked, the signal output by the multiplexer is switched, and the fuse digital signal determined by the fuse unit according to the square wave signal is transmitted to the next step. The gate voltage reference signal determined by the fuse digital signal provides a voltage to the gate of the power amplifier. At this time, the gate voltage of the power amplifier is related to the current flowing into the power amplifier, thereby enabling the provision of a stable gate voltage to the power amplifier. Furthermore, after the initial adaptive process, the gate voltage of the power amplifier can be made related to the current flowing into the power amplifier, eliminating the need for subsequent debugging with the power amplifier, making the operation simple. The gate voltage drive module has sufficient driving capability to provide sufficient gate voltage to the power amplifier, making the gate voltage regulation system widely applicable.

[0090] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0091] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0092] Figure 4 A schematic diagram of the gate voltage regulator device provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0093] like Figure 4 As shown, the gate voltage regulator 7 includes a silicon wafer 71 and a gate voltage regulator system 72 disposed on the silicon wafer; the gate voltage regulator system 72 adopts the gate voltage regulator system as described in any of the above embodiments and has the beneficial effects brought by the above gate voltage regulator system.

[0094] In one possible implementation, the circuitry in the gate regulator system 72 can be fabricated using a 0.25μm CMOS process.

[0095] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A gate voltage regulator system, characterized in that, include: Power modulation module, gear locking module, and gate voltage drive module; The first input terminal of the power modulation module is used to connect to an external power supply, and the second input terminal of the power modulation module is used to connect to the first output terminal of the externally supplied logic level, so as to perform power modulation according to the level signal transmitted by the externally supplied logic level. The first output terminal of the power modulation module is used to connect to the power amplifier and supply power to the power amplifier. The second output terminal of the power modulation module is connected to the first input terminal of the gear locking module. The gear locking module is used to collect the current of the power modulation module to obtain the sampling current. The second input terminal of the gear locking module is used to connect to the second output terminal of the external logic level so as to determine the counting information according to the external logic level; The output terminal of the gear locking module is connected to the input terminal of the gate voltage driving module. The gear locking module is used to determine the gate voltage reference signal based on the counting information and the sampling current, and transmit the gate voltage reference signal to the gate voltage driving module. The output of the gate voltage driving module is used to connect to the power amplifier so as to provide a voltage to the gate of the power amplifier according to the received gate voltage reference signal; The gear locking module includes a current sampling unit, a square wave generating unit, a fuse unit, a counting unit, a multiplexer unit, and a digital-to-analog converter unit; The current sampling unit is used to collect the current of the power modulation module, obtain the sampled current, and perform current locking on the sampled current to obtain a first voltage, and transmit the voltage digital signal corresponding to the first voltage to the square wave generating unit; The square wave generating unit is used to acquire the first voltage when the received voltage digital signal meets the preset conditions, and transmit the square wave signal generated according to the first voltage to the fuse unit. The fuse unit is used to receive the filtering information transmitted by the counting unit, and to perform corresponding operations according to the square wave signal and the filtering information; Furthermore, upon completion of the corresponding operation, the generated locking signal is transmitted to the counting unit, and the generated switching signal and the fuse digital signal determined according to the square wave signal are transmitted to the multiplexing unit. The counting unit is used to determine counting information based on the level signal transmitted by the external logic level, and to determine the filtering information based on the counting information, and to transmit the counting signal corresponding to the counting information to the multiplexing unit; The multiplexing unit is used to determine the voltage reference signal based on the counting signal, the switching signal, and the fuse digital signal, and transmit the voltage reference signal to the digital-to-analog converter unit; The digital-to-analog converter unit is used to transmit the gate voltage reference signal determined according to the voltage reference signal to the gate voltage drive module.

2. The gate voltage regulator system according to claim 1, characterized in that, The power modulation module includes a power switch modulation unit and a switch array; The input terminal of the power switch modulation unit serves as the second input terminal of the power modulation module, so as to receive the level signal of the externally supplied logic level; The output terminal of the power switch modulation unit is connected to the first input terminal of the switch array, and is used to output a voltage signal to drive the switch array according to the level signal; The second input terminal of the switch array is used to connect to the external power supply; the first output terminal of the switch array serves as the first output terminal of the power modulation module; and the second output terminal of the switch array serves as the second output terminal of the power modulation module.

3. The gate voltage regulator system according to claim 2, characterized in that, The gear locking module includes a current sampling unit, a square wave generating unit, a fuse unit, a counting unit, a multiplexer unit, and a digital-to-analog converter unit; The input terminal of the current sampling unit serves as the first input terminal of the gear locking module, used to sample the current of the switch array to obtain the sampled current; the first output terminal of the current sampling unit is connected to an external resistor and grounded, used to perform current locking on the sampled current to obtain a first voltage; The second output terminal of the current sampling unit is connected to the first input terminal of the square wave generating unit, and is used to transmit the voltage digital signal corresponding to the first voltage to the square wave generating unit. The third output terminal of the current sampling unit is connected to the second input terminal of the square wave generating unit, and is used to allow the square wave generating unit to sample the first voltage when the voltage digital signal received by the square wave generating unit meets the preset conditions. The output terminal of the square wave generating unit is connected to the first input terminal of the fuse unit, and is used to transmit the square wave signal generated according to the first voltage to the fuse unit so that the fuse unit can perform the corresponding operation. The first output terminal of the counting unit is connected to the second input terminal of the fuse unit, and the fuse unit is used to receive the filtering information transmitted by the counting unit; the output terminal of the fuse unit is connected to the second input terminal of the counting unit and the second input terminal of the multiplexing unit respectively, and is used to transmit the generated locking signal to the counting unit when the fuse unit completes the corresponding operation, and at the same time, transmit the generated switching signal and the fuse digital signal determined according to the square wave signal to the multiplexing unit; The first input terminal of the counting unit serves as the second input terminal of the gear locking module, used to determine the counting information based on the level signal transmitted by the external logic level and to determine the filtering information based on the counting information; the first output terminal of the counting unit is connected to the multiplexing unit, used to transmit the counting signal corresponding to the counting information to the multiplexing unit; The output of the multiplexing unit is connected to the input of the digital-to-analog converter. The multiplexing unit is used to determine the voltage reference signal based on the counting signal, the switching signal, and the fuse digital signal, and transmit the voltage reference signal to the digital-to-analog converter. The output terminal of the digital-to-analog converter unit serves as the output terminal of the gear locking module, and is used to transmit the gate voltage reference signal determined according to the voltage reference signal to the gate voltage drive module.

4. The gate voltage regulator system according to claim 3, characterized in that, When the fuse unit completes the corresponding operation, it is used to melt the fuse inside the fuse unit according to the square wave signal and the screening information.

5. The gate voltage regulator system according to claim 3, characterized in that, The switching array includes MOSFETs M n ; The current sampling unit includes MOSFETs M1, M2, M3, and M4, a first constant current source I1, a second constant current source I2, an amplifier AMP, and a comparator COMP. The gate of the MOS transistor M1 is connected to the gate of the MOS transistor M. n The gate of the MOSFET M1 is used to collect the current as a multiple of the current mirror of the switch array to obtain the gate sampling current. The source of the MOSFET M1 is connected to the source of the MOSFET M... n The source of the MOS transistor M1 is connected to the source of the MOS transistor M2, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M2 and the gate of the MOS transistor M4. The drain of the MOS transistor M4 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M2. n The source of the MOS transistor M4 is connected to the non-inverting input of the amplifier AMP and the input of the second constant current source I2, respectively; the output of the second constant current source I2 is grounded. The gate of the MOS transistor M3 is connected to the gate of the MOS transistor M. n The drain of the MOSFET M3 is connected to the source of the MOSFET M1 and the power amplifier, respectively. n The source of the MOS transistor M3 is connected to the inverting input terminal of the amplifier AMP and the input terminal of the first constant current source I1, respectively; the output terminal of the first constant current source I1 is grounded. The output terminal of the amplifier AMP is connected to the gate of the MOS transistor M2; The source of the MOSFET M2 is connected to the external resistor and the first input terminal of the comparator COMP, respectively, and is used to input the first voltage locked by the external resistor to the comparator COMP. The second input terminal of the comparator COMP is used to input a zero temperature coefficient voltage; the output terminal of the comparator COMP serves as the second output terminal of the current sampling unit, used to compare the first voltage with the zero temperature coefficient voltage, and output a high-level digital signal when the first voltage is greater than or equal to the zero temperature coefficient voltage, and output a low-level digital signal when the first voltage is less than the zero temperature coefficient voltage.

6. The gate voltage regulator system according to claim 5, characterized in that, When the voltage digital signal received by the square wave generating unit meets the preset conditions, the square wave generating unit acquires the first voltage. This is used when the voltage digital signal received by the square wave generating unit is the high-level digital signal.

7. The gate voltage regulator system according to claim 5, characterized in that, To obtain a first voltage by current-locking the sampled current, the following steps are included: according to Determine the resistance value of the external resistor; The sampling current is locked based on the resistance value of the external resistor to obtain the first voltage; in This is the resistance value of the external resistor. Zero temperature coefficient voltage This refers to the operating current of the power amplifier. It is the current mirror ratio.

8. The gate voltage regulator system according to claim 5, characterized in that, The current mirror factor is .

9. The gate voltage regulator system according to claim 1, characterized in that, The gate voltage drive module is a Class AB amplifier.

10. A gate voltage regulator, characterized in that, Includes a silicon wafer and a gate voltage regulator system as described in any one of claims 1-9 disposed on the silicon wafer.

Images