Display device, data driving circuit and display driving method

Abstract

Embodiments of the present disclosure relate to a display device, a data driving circuit, and a display driving method. Specifically, a display device may be provided, including: a display panel having a plurality of sensing channels connected to a plurality of sub-pixels to detect driving characteristic values; a data driving circuit including an analog-to-digital converter that converts sensing voltages detected through the plurality of sensing channels into digital sensing data and converts a sub-pixel driving voltage detected through at least one pseudo channel into digital pseudo sensing data; and a timing controller that calculates the intensity of a current flowing through the data driving circuit based on the digital pseudo sensing data transmitted from the data driving circuit and compensates for image data transmitted to the data driving circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0111669, filed on August 24, 2021, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device, a data driving circuit, and a display driving method capable of preventing defects and image quality degradation due to variations in sub-pixel driving voltages. Background Art

[0004] As the information society develops, various demands for display devices for displaying images are increasing, and various types of display devices, such as liquid crystal displays (LCDs) and organic light emitting displays, are used.

[0005] Among these display devices, an organic light emitting diode display employs an organic light emitting diode and thus has fast response and various advantages in terms of contrast, light emitting efficiency, brightness, and viewing angle.

[0006] The organic light emitting diode display includes organic light emitting diodes arranged in sub-pixels on a display panel, and controls the brightness represented by each sub-pixel when displaying an image by controlling current flowing to the organic light emitting diodes to make the organic light emitting diodes emit light.

[0007] Such a display device includes a driving voltage supply source for supplying various driving voltages required to drive the display panel to a driving circuit and the display panel and various components for transmitting the driving voltages.

[0008] In order for such a display device to normally display an image, a driving voltage should be normally transmitted along components for transmitting the driving voltage.

[0009] However, since driving voltage lines for transmitting driving voltages are transmitted through a specific driving circuit, high heat may be generated in a region where the driving voltage lines are densely packed, thereby causing errors in the operation of the driving circuit where the driving voltage lines are located.

[0010] Furthermore, if the temperature of the driving circuit increases, a driving voltage transmitted through the driving circuit decreases due to the temperature increase, so that a normal image may not be displayed on the display panel and image quality may be significantly degraded. Summary of the invention

[0011] Specifically, among various driving voltages used in a display device, a sub-pixel driving voltage provided for driving a sub-pixel directly affects the quality of a display panel. There is no method for effectively detecting and compensating for changes in the sub-pixel driving voltage. The inventors of the present disclosure have invented a display device, a data driving circuit, and a display driving method capable of preventing defects and image quality degradation caused by changes in the sub-pixel driving voltage.

[0012] Embodiments of the present disclosure may provide a display device, a data driving circuit, and a display driving method capable of preventing defects and image quality degradation due to variations in subpixel driving voltages by detecting the subpixel driving voltages through sensing lines of a data driving circuit.

[0013] Embodiments of the present disclosure may provide a display device, a data driving circuit, and a display driving method that are capable of effectively detecting changes in subpixel driving voltage and preventing defects and image quality degradation by scaling the subpixel driving voltage to the sensing range of an analog-to-digital converter of a data driving circuit.

[0014] Embodiments of the present disclosure may provide a display device, a data driving circuit, and a display driving method capable of preventing defects and image quality degradation due to variations in subpixel driving voltages by detecting subpixel driving voltages through a dummy channel of a data driving circuit.

[0015] Embodiments of the present disclosure may provide a display device, a data driving circuit, and a display driving method capable of preventing image quality degradation by controlling a data voltage applied to a region where a sub-pixel driving voltage has a significant variation.

[0016] An embodiment of the present disclosure may provide a display device, comprising: a display panel, in which a plurality of sensing channels are provided, the plurality of sensing channels being connected to a plurality of sub-pixels to detect driving characteristic values; a data driving circuit, which comprises an analog-to-digital converter, which converts sensing voltages detected through the plurality of sensing channels into digital sensing data and converts a sub-pixel driving voltage detected through at least one pseudo channel into digital pseudo sensing data; and a timing controller, which calculates the intensity of a current flowing through the data driving circuit based on the digital pseudo sensing data transmitted from the data driving circuit, and compensates for image data transmitted to the data driving circuit.

[0017] An embodiment of the present disclosure may provide a data driving circuit, comprising: a plurality of data lines extending to a display panel provided with a plurality of sub-pixels to provide data voltages; and an analog-to-digital converter that converts sensing voltages detected through a plurality of sensing channels into digital sensing data and converts a sub-pixel driving voltage detected through at least one pseudo channel into digital pseudo sensing data.

[0018] An embodiment of the present disclosure may provide a method for driving a display device, the display device comprising a display panel provided with a plurality of sub-pixels, a data driving circuit comprising an analog-to-digital converter that converts a sensing voltage detected through a plurality of sensing channels into digital sensing data, and a timing controller that provides image data to the data driving circuit, the method comprising detecting a sub-pixel driving voltage through a pseudo channel, calculating a current intensity corresponding to a variation width of the sub-pixel driving voltage, and compensating the image data provided to the data driving circuit according to the calculated current intensity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a view schematically showing a configuration of a display device according to various embodiments of the present disclosure;

[0021] Figure 2 is a view showing an example of a system of a display device according to an embodiment of the present disclosure;

[0022] Figure 3 is a view showing an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure;

[0023] Figure 4 is a view showing an example of a transmission path of a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure;

[0024] Figure 5 is a view showing an example in which a data driving circuit group is composed of a plurality of source driving integrated circuits to provide a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure;

[0025] Figure 6 is a view showing an example in which image quality is degraded due to a temperature rise caused by a sub-pixel driving voltage in a specific area in a display device;

[0026] Figure 7is a view showing an example of a structure for detecting and compensating for a change in a sub-pixel driving voltage through a dummy sensing line in a display device according to an embodiment of the present disclosure;

[0027] Figure 8 is a view showing an example of an input voltage range of an analog-to-digital converter and a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure;

[0028] Fig. 9 is a view showing an example of a switch circuit for transmitting a turn-off sensing voltage and a sub-pixel driving voltage to an analog-to-digital converter in a display device according to an embodiment of the present disclosure;

[0029] Fig.10 is a view showing an example of a configuration of a timing controller for compensating image data according to a change in a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure;

[0030] Fig.11 is a view showing an example of a lookup table for calculating the intensity of a current flowing through a data driving circuit according to a variation width of a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure; and

[0031] Fig.12 is a flowchart illustrating a display driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of examples or embodiments of the present invention, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and the same reference numerals and symbols in the drawings may be used to represent the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present invention, when it is determined that a detailed description of the known functions and components included in this article may make the subject matter in some embodiments of the present invention quite unclear, the description will be omitted. Terms such as "including", "having", "including", "constituting", "consisting of" and "formed by" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0033] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0034] When it is mentioned that a first element is "connected or coupled to", "contacts or overlaps", etc. a second element, it should be understood that not only the first element can be "directly connected or coupled to" or "directly contact or overlaps" the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled to", "contacts or overlaps", etc. each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are "connected or coupled to", "contacts or overlaps", etc. each other.

[0035] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0036] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a view schematically illustrating a configuration of a display device according to various embodiments of the present disclosure.

[0039] Reference Figure 1 A display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driving circuit 120 driving a plurality of gate lines GL, a data driving circuit 130 providing data voltages through a plurality of data lines DL, a timing controller 140 controlling the gate driving circuit 120 and the data driving circuit 130, and a power management circuit 150. In the display panel 110, a plurality of gate lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix form.

[0040] The display panel 110 displays an image based on a scan signal transmitted from the gate driving circuit 120 through a plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through a plurality of data lines DL.

[0041] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. In the case of an organic light emitting display, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a dual emission scheme.

[0042] In the display panel 110, a plurality of pixels may be arranged in a matrix form, and each pixel may include sub-pixels SP having different colors, for example, white sub-pixel, red sub-pixel, green sub-pixel, and blue sub-pixel, and each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0043] One subpixel SP may include, for example, a thin film transistor (TFT) formed at an intersection between one data line DL and one gate line GL, a light emitting element such as an organic light emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain a voltage.

[0044] For example, when the display device 100 having a resolution of 2160x3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL may be connected to 2160 gate lines GL and 4 sub-pixels WRGB, and thus 3840x4=15360 data lines DL may be provided. Each sub-pixel SP is disposed at an intersection between a gate line GL and a data line DL.

[0045] The gate driving circuit 120 may be controlled by the timing controller 140 to sequentially output scan signals to a plurality of gate lines GL disposed in the display panel 110 , thereby controlling driving timings of the plurality of sub-pixels SP.

[0046] In the display device 100 having a resolution of 2160x3840, sequentially outputting scan signals from the first gate line to the 2160th gate line to the 2160 gate lines GL may be referred to as a 2160-phase driving method. Sequentially outputting scan signals to each unit of the four gate lines GL, for example, sequentially outputting scan signals to the fifth gate line to the eighth gate line after sequentially outputting scan signals to the first gate line to the fourth gate line, may be referred to as a 4-phase driving method. In other words, sequentially outputting scan signals to every N gate lines GL may be referred to as an N-phase driving method.

[0047] The gate drive circuit 120 may include one or more gate drive integrated circuits (GDICs). Depending on the driving scheme, the gate drive circuit 120 may be located on only one side or each of two opposite sides of the display panel 110. The gate drive circuit 120 may be implemented in the form of a gate-in-panel (GIP) that is embedded in the bezel area of ​​the display panel 110.

[0048] The data driving circuit 130 receives the image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, as the data voltage is output to each data line DL according to the timing of applying the scan signal through the gate line GL, each sub-pixel SP connected to the data line DL displays a light emitting signal having a brightness corresponding to the data voltage.

[0049] Likewise, the data driving circuit 130 may include one or more source driver integrated circuits SDIC, and the source driver integrated circuits SDIC may be connected to bonding pads of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type, or may be directly disposed on the display panel 110.

[0050] In some cases, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit SDIC may be implemented in a chip on film (COF) type, and in this case, each source driver integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to the data line DL of the display panel 110 through the circuit film.

[0051] The timing controller 140 provides various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. In other words, the timing controller 140 may control the gate driving circuit 120 to output a scan signal according to a timing implemented per frame, and on the other hand, the timing controller 140 transmits image data DATA received from the outside to the data driving circuit 130.

[0052] In this case, the timing controller 140 receives several timing signals including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK, together with the image data DATA from the external host system 200 .

[0053] The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0054] Therefore, the timing controller 140 may generate a control signal according to various timing signals received from the host system 200 and transmit the control signal to the gate driving circuit 120 and the data driving circuit 130 .

[0055] For example, the timing controller 140 outputs several gate control signals, including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE, to control the gate drive circuit 120. The gate start pulse GSP controls the timing at which one or more gate drive integrated circuits GDIC constituting the gate drive circuit 120 start operating. The gate clock GCLK is a clock signal commonly input to one or more gate drive integrated circuits GDIC, and controls the shift timing of the scan signal. The gate output enable signal GOE specifies timing information about one or more gate drive integrated circuits GDIC.

[0056] The timing controller 140 outputs various data control signals, including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE, to control the data driving circuit 130. The source start pulse SSP controls the timing at which one or more source driver integrated circuits SDIC constituting the data driving circuit 130 start data sampling. The source sampling clock SCLK is a clock signal that controls the timing of sampling data in the source driver integrated circuit SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0057] The display device 100 may further include a power management circuit 150 that supplies various voltages or currents to, for example, the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 , or controls the various voltages or currents to be supplied.

[0058] The power management circuit 150 adjusts a direct current (DC) input voltage Vin provided from the host system 200 to generate power required to drive the display panel 100 , the gate driving circuit 120 , and the data driving circuit 130 .

[0059] The sub-pixel SP is located at the intersection between the gate line GL and the data line DL, and a light emitting element may be provided in each sub-pixel SP. For example, an organic light emitting diode display may include a light emitting element such as an organic light emitting diode in each sub-pixel SP, and may display an image by controlling a current flowing to the light emitting element according to a data voltage.

[0060] The display device 100 may be one of various types of devices, such as a liquid crystal display, an organic light emitting display, or a plasma display panel.

[0061] Figure 2is a view showing an example of a system of a display device according to an embodiment of the present disclosure.

[0062] Reference Figure 2 In the display device 100 according to an embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 and the gate driver integrated circuit GDIC included in the gate driver circuit 120 are implemented in a chip on film (COF) type among various types (e.g., TAB, COG, or COF).

[0063] One or more gate driving integrated circuits GDIC included in the gate driving circuit 120 may be mounted on the gate film GF, and one side of the gate film GF may be electrically connected to the display panel 110. Lines for electrically connecting the gate driving integrated circuits GDIC and the display panel 110 may be provided on the gate film GF.

[0064] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be mounted on the source film SF, and one side of the source film SF may be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuit SDIC and the display panel 110 may be provided on the source film SF.

[0065] The display device 100 may include at least one source printed circuit board SPCB for making circuit connections between a plurality of source driving integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control components and various electronic devices.

[0066] The other side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side thereof may be electrically connected to the source printed circuit board SPCB.

[0067] The timing controller 140 and the power management circuit (power management IC) 150 may be mounted on the control printed circuit board CPCB. The timing controller 140 may control the operation of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120 and control the provided voltage or current.

[0068] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected by at least one connecting member. The connecting member may include, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). In this case, the connecting member connecting at least one source printed circuit board SPCB and the control printed circuit board CPCB may be changed according to the size and type of the display device 100. At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into a single printed circuit board.

[0069] In the display device 100 configured in this way, the power management circuit 150 transmits a driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided to emit light or sense a specific sub-pixel SP in the display panel 110 through the source driver integrated circuit SDIC.

[0070] Each of the sub-pixels SP arranged in the display panel 110 in the display device 100 may include an organic light emitting diode as a light emitting element and a circuit element for driving the organic light emitting diode, for example, a driving transistor.

[0071] The type and number of circuit elements constituting each sub-pixel SP may vary depending on the functions to be provided and the design scheme.

[0072] Figure 3 is a diagram illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure.

[0073] Reference Figure 3 , in the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors, a capacitor, and an organic light emitting diode (OLED) as a light emitting element ED.

[0074] For example, the sub-pixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light emitting element ED.

[0075] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node to which a data voltage Vdata is applied from the data driving circuit 130 through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting element ED and may be a source node or a drain node. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL to which a sub-pixel driving voltage EVDD is applied and may be a drain node or a source node.

[0076] In this case, during the display driving period, the sub-pixel driving voltage EVDD required for displaying an image may be supplied to the driving voltage line DVL. For example, the sub-pixel driving voltage EVDD required for displaying an image may be 27V.

[0077] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node of the switching transistor SWT. Therefore, the switching transistor SWT operates according to the scan signal SCAN provided through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata provided through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0078] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node of the sensing transistor SENT. The sensing transistor SENT operates according to the sensing signal SENSE provided through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage Vref provided through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0079] In other words, in a case where the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DRT are controlled so that a current for driving the light emitting element ED can be provided.

[0080] The gate nodes of the switching transistor SWT and the sensing transistor SENT may be connected to one gate line GL in common, or may be connected to different gate lines GL. An example in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL is shown, in which case the switching transistor SWT and the sensing transistor SENT may be independently controlled by the scanning signal SCAN and the sensing signal SENSE transmitted through the different gate lines GL.

[0081] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to one gate line GL, the switching transistor SWT and the sensing transistor SENT may be simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted through one gate line GL, and the aperture ratio of the subpixel SP may be increased.

[0082] The transistor provided in the sub-pixel SP may be an n-type transistor or a p-type transistor, and in the illustrated example, the transistor is an n-type transistor.

[0083] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintains the data voltage Vdata during one frame.

[0084] Depending on the type of the driving transistor DRT, the storage capacitor Cst may also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the light emitting element ED may be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS may be applied to the cathode electrode of the light emitting element ED.

[0085] The base voltage EVSS may be a ground voltage or a voltage higher or lower than the ground voltage. The base voltage EVSS may vary according to a driving state. For example, the base voltage EVSS during display driving and the base voltage EVSS during sensing driving may be set to be different from each other.

[0086] The structure of the sub-pixel SP described above as an example is a 3T (transistor) 1C (capacitor) structure, which is merely an example for description, and may further include one or more transistors, or in some cases, one or more capacitors. A plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0087] In order to effectively sense the characteristic value of the driving transistor DRT, such as a threshold voltage or mobility, the display device 100 according to an embodiment of the present disclosure may use a method for measuring a current flowing through a voltage charged to the storage capacitor Cst during a characteristic value sensing period of the driving transistor DRT, which is referred to as current sensing.

[0088] In other words, the characteristic value or the change in the characteristic value of the driving transistor DRT in the subpixel SP may be derived by measuring the current flowing by the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT.

[0089] In this case, the reference voltage line RVL is not only used to transmit the reference voltage Vref, but also used as a sensing line for sensing a characteristic value of the driving transistor DRT in the sub-pixel SP. Therefore, the reference voltage line RVL may also be referred to as a sensing line.

[0090] In this case, the period for sensing the driving characteristic values ​​(threshold voltage and mobility) of the driving transistor DRT can be performed after the power-on signal is generated and before the display drive starts. For example, if the power-on signal is applied to the display device 100, the timing controller 140 loads the parameters required to drive the display panel 110 and then drives the display. In this case, the parameters required to drive the display panel 110 may include information about the sensing and compensation of the driving characteristic values ​​previously performed on the display panel 110. During the parameter loading process, the sensing of the driving characteristic values ​​(threshold voltage and mobility) of the driving transistor DRT can be performed. As described above, the process of sensing the driving characteristic values ​​during the parameter loading process after the power-on signal is generated is called the start-up sensing process.

[0091] Alternatively, the period of sensing the driving characteristic value of the driving transistor DRT may be performed after the power-off signal of the display device 100 is generated. For example, when the power-off signal is generated in the display device 100, the timing controller 140 may cut off the data voltage supplied to the display panel 110 and may sense the driving characteristic value of the driving transistor DRT within a predetermined time. In this way, the process of sensing the driving characteristic value in a state where the data voltage is cut off due to the generation of the power-off signal is referred to as a turn-off sensing process.

[0092] Alternatively, the sensing period of the driving characteristic value of the driving transistor DRT can be performed in real time when driving the display. This sensing process is called a real-time (RT) sensing process. In the real-time sensing process, the sensing process can be performed on one or more sub-pixels SP in one or more sub-pixel SP rows in each blank period during the display driving period.

[0093] Figure 4 is a view showing an example of a transmission path of a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure. Figure 2 A portion A shown in FIG. 1 is enlarged and shown.

[0094] Reference Figure 4 In the display device 100 according to an embodiment of the present disclosure, a plurality of sub-pixels SP defined by a plurality of data lines DL and a plurality of gate lines GL crossing each other are provided on the display panel 110. In this case, each sub-pixel SP receives a sub-pixel driving voltage EVDD through a plurality of driving voltage lines DVL arranged in a direction parallel to the plurality of data lines DL.

[0095] The plurality of driving voltage lines DVL may be formed between the plurality of data lines DL to be parallel to the plurality of data lines DL, or may be formed to be shared by two sub-pixels adjacent to each other in the left-right direction.

[0096] The plurality of driving voltage lines DVL may be commonly connected to a common driving voltage line 135 formed in an upper non-display area of ​​the display panel 110 .

[0097] The sub-pixel driving voltage EVDD transferred from the power management circuit 150 is provided to the common driving voltage line 135 through the plurality of data driving circuits 130 .

[0098] In order to transmit the sub-pixel driving voltage EVDD to the plurality of driving voltage lines DVL, a first driving voltage supply line 131 , a second driving voltage supply line 132 , a third driving voltage supply line 133 , and a fourth driving voltage supply line 134 may be provided.

[0099] The first driving voltage supply line 131 , the second driving voltage supply line 132 , and the third driving voltage supply line 133 may be electrically connected to the source printed circuit board SPCB.

[0100] The fourth driving voltage supply line 134 may branch to two opposite sides of the source driving integrated circuit SDIC in the data driving circuit 130 , and may electrically connect the third driving voltage supply line 133 with the common driving voltage line 135 .

[0101] The third driving voltage supply line 133 may be disposed in a region adjacent to the source film SF, and may be electrically connected to a fourth driving voltage supply line 134 formed in the data driving circuit 130 .

[0102] Since the first driving voltage supply line 131 corresponds to a portion to which the subpixel driving voltage EVDD supplied from the power management circuit 150 is applied, the first driving voltage supply line 131 may be formed to have a relatively larger area than the third driving voltage supply line 133 .

[0103] The second driving voltage supply line 132 may be branched from the first driving voltage supply line 131 to have a predetermined interval and connected to the third driving voltage supply line 133 .

[0104] In this case, since the second driving voltage supply line 132 is located in a region before the subpixel driving voltage EVDD branches through the plurality of driving voltage lines DVL, the second driving voltage supply line 132 has a relatively high current density compared to the fourth driving voltage supply line 134 and the driving voltage line DVL.

[0105] Therefore, the second driving voltage supply line 132 has a high chance of temperature increase and defects due to high density current.

[0106] Meanwhile, the data driving circuit 130 may form a number of source driving integrated circuits SDIC into a group to provide the sub-pixel driving voltage EVDD on a group basis.

[0107] Figure 5 is a view showing an example in which a data driving circuit group is composed of a plurality of source driving integrated circuits to provide sub-pixel driving voltages in a display device according to an embodiment of the present disclosure.

[0108] Reference Figure 5 , in the display device 100 according to an embodiment of the present disclosure, the sub-pixel driving voltage EVDD generated from the power management circuit 150 is transmitted to the sub-pixel SP through the source printed circuit board SPCB and the data driving circuit 130 .

[0109] Here, an example is shown in which one data driving circuit group 130 # 1 is composed of, for example, four source driving integrated circuits SDIC # 1 to SDIC # 4 .

[0110] In this case, the subpixel driving voltage EVDD provided from the power management circuit 150 may be provided through a source printed circuit board SPCB provided with four source driving integrated circuits SDIC# 1 to SDIC# 4 and branched through four driving voltage lines DVL on the source printed circuit board SPCB.

[0111] The sub-pixel driving voltage EVDD transmitted through four driving voltage lines DVL branched on the source printed circuit board SPCB is supplied to the corresponding sub-pixels SP through the source film SF on which four source driving integrated circuits SDIC# 1 to SDIC# 4 are mounted.

[0112] In this case, since current is most concentrated in the central portion of the source printed circuit board SPCB to which the sub-pixel driving voltage EVDD is supplied from the power management circuit 150 , the temperature may increase and defects may occur.

[0113] Figure 6 is a view showing an example in which image quality is degraded due to a temperature rise caused by a sub-pixel driving voltage in a specific area in a display device.

[0114] Reference Figure 6 , can drive the data driving circuit 130 of the display device 100, wherein several source driving integrated circuits SDIC are bundled into one group.

[0115] As shown here, when four source driving integrated circuits SDIC# 1 to SDIC# 4 are configured as one data driving circuit group 130 # 1 to 130 # 4 , the sub-pixel driving voltage EVDD may be provided per the data driving circuit group 130 # 1 to 130 # 4 .

[0116] In this case, according to the type of image displayed on the display panel 110 , current applied to the source printed circuit board SPCB of a specific area may increase, so that the temperature of the area may rise, and image quality may deteriorate.

[0117] For example, when the current applied to the first data driving circuit group 130 # 1 is higher than the current applied to the other data driving circuit groups 130 # 2 , 130 # 3 , and 130 # 4 , the temperature of the first data driving circuit group 130 # 1 increases.

[0118] When the temperature of the first data driving circuit group 130#1 increases, the first data driving circuit group 130#1 may degrade and the subpixel driving voltage EVDD transmitted by the first data driving circuit group 130#1 decreases, so that a normal image may not be displayed on the display panel 110 and the image quality may be greatly degraded.

[0119] Therefore, image quality may be enhanced by detecting a change in the sub-pixel driving voltage EVDD transmitted through the data driving circuit 130 through the dummy sensing line and reflecting it to control the image data DATA provided to the data driving circuit 130 .

[0120] Figure 7 is a view illustrating an example of a structure for detecting and compensating for a change in a sub-pixel driving voltage through a dummy sensing line in a display device according to an embodiment of the present disclosure.

[0121] Reference Figure 7 , in the display device 100 according to an embodiment of the present disclosure, the analog-to-digital converter 138 included in the data driving circuit 130 may include three sensing channels CH1 , CH2 , and CH3 and one dummy channel CHd.

[0122] The three sensing channels CH1 , CH2 , and CH3 may be connected to the three sensing lines SL1 , SL2 , and SL3 through sampling switches SAM1 , SAM2 , and SAM3 , respectively, and each of the three sensing lines SL1 , SL2 , and SL3 may be connected to four sub-pixels SP.

[0123] In other words, the first sensing line SL1 corresponding to the first sensing channel CH1 can be shared by and connected to the first to fourth sub-pixels SP1, SP2, SP3, and SP4. Similarly, the second sensing line SL2 corresponding to the second sensing channel CH2 can be shared by and connected to the fifth to eighth sub-pixels SP5, SP6, SP7, and SP8. The third sensing line SL3 corresponding to the third sensing channel CH3 can be shared by and connected to the ninth to twelfth sub-pixels SP9, SP10, SP11, and SP12.

[0124] In other words, four sub-pixels SP may constitute one pixel P. For example, the four sub-pixels SP may include a red sub-pixel R, a white sub-pixel W, a green sub-pixel G, and a blue sub-pixel B. For example, the first sub-pixel SP1, the fifth sub-pixel SP5, and the ninth sub-pixel SP9 may be red sub-pixels R. The second sub-pixel SP2, the sixth sub-pixel SP6, and the tenth sub-pixel SP10 may be white sub-pixels W. The third sub-pixel SP3, the seventh sub-pixel SP7, and the eleventh sub-pixel SP11 may be green sub-pixels G. The fourth sub-pixel SP4, the eighth sub-pixel SP8, and the twelfth sub-pixel SP12 may be blue sub-pixels B.

[0125] In one dummy channel CHd, the turn-off sensing voltage VRTA or the sub-pixel driving voltage EVDD may be applied to the analog-to-digital converter 138 through the dummy sampling switch SAMd.

[0126] The turn-off sensing voltage VRTA is a voltage applied separately to detect a gain or offset characteristic of the analog-to-digital converter 138. The turn-off sensing voltage VRTA may have a value within a range that can be converted by the analog-to-digital converter 138.

[0127] In contrast, when the gain or offset characteristic of the analog-to-digital converter 138 is not detected, the off-sensing voltage VRTA may not be applied to the dummy channel CHd.

[0128] Since the dummy channel CHd is not electrically connected to the subpixel SP constituting the display panel 110 , the dummy sensing voltage Vsend detected through the dummy channel CHd may be used to compensate for the gain or offset of the analog-to-digital converter 138 , or may also be used to detect the subpixel driving voltage EVDD.

[0129] In this case, the sub-pixel driving voltage EVDD generally has a high voltage level of 20 V or more. In contrast, the voltage input to the analog-to-digital converter 138 has a range between 0 V and several volts.

[0130] Therefore, preferably, the level of the sub-pixel driving voltage EVDD is converted within the convertible range of the analog-to-digital converter 138 by a first scaler 136 .

[0131] Figure 8 is a view showing an example of an input voltage range of an analog-to-digital converter and a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure.

[0132] Described below is a process for detecting a change in the sub-pixel driving voltage EVDD transmitted through the data driving circuit 130 through the dummy channel CHd during a display driving period and reflecting it to control the image data DATA provided to the data driving circuit 130 .

[0133] Reference Figure 8 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel driving voltage EVDD may be 27V, and the range of the voltage (ADC range) input to the analog-to-digital converter 138 constituting the data driving circuit 130 may be 0V to 3V.

[0134] Therefore, the first scaler 136 may scale the sub-pixel driving voltage EVDD to a value within an input voltage range (ADC range) of the analog-to-digital converter 138 and provide it.

[0135] The sub-pixel driving voltage EVDD_S scaled to a value within the input voltage range of the analog-to-digital converter 138 during the display driving period can be provided to the analog-to-digital converter 138 through the pseudo sampling switch SAMd. In other words, the analog-to-digital converter 138 can detect the scaled sub-pixel driving voltage EVDD_S through the pseudo channel CHd during the display driving period.

[0136] Therefore, the analog-to-digital converter 138 may convert the scaled subpixel driving voltage EVDD_S detected through one dummy channel CHd into digital dummy sensing data DSENd and output the digital dummy sensing data DSENd, and the timing controller 140 may store the digital dummy sensing data DSENd in the memory 144 .

[0137] Therefore, the compensation circuit 142 can detect the variation width of the subpixel driving voltage EVDD according to the digital dummy sensing data DSENd transmitted from the dummy channel CHd, and calculate the intensity of the current transmitted through the data driving circuit 130 and the variation of the temperature of the data driving circuit 130 based on the detected variation width.

[0138] Therefore, the display device 100 according to an embodiment of the present disclosure can detect a high current when a high current flows through the data driving circuit 130 and control the image data DATA applied to the data driving circuit 130, thereby reducing the temperature increase of the data driving circuit 130 while preventing defects in signal lines such as the data driving circuit 130 and the source film SF.

[0139] In this case, the current intensity and temperature variation of the data driving circuit 130 corresponding to the variation width of the sub-pixel driving voltage EVDD may be stored in the memory 144 in the form of a lookup table.

[0140] The compensation circuit 142 may exist inside or outside the timing controller 140. The memory 144 may be located outside the timing controller 140, or may be implemented inside the timing controller 140 in the form of a register.

[0141] Although the first scaler 136 for adjusting the range of the sub-pixel driving voltage EVDD and the switching circuit 137 capable of selecting the scaled sub-pixel driving voltage EVDD_S are shown to be located outside the data driving circuit 130, the first scaler 136 and the switching circuit 137 may be located inside the data driving circuit 130, or may be configured as a circuit system on the source printed circuit board SPCB.

[0142] Wherein, when both the change of the sub-pixel driving voltage EVDD and the offset of the analog-to-digital converter ADC are detected through the pseudo channel CHd, the turn-off sensing voltage VRTA and the scaled sub-pixel driving voltage EVDD_S may be provided to the switch circuit 137. As described above, when the gain or offset characteristics of the analog-to-digital converter 138 are not detected, the turn-off sensing voltage VRTA may not be applied to the pseudo channel CHd.

[0143] The switch circuit 137 may provide the off sensing voltage VRTA or the scaled sub-pixel driving voltage EVDD_S to the analog-to-digital converter 138 at different times.

[0144] For example, the turn-off sensing voltage VRTA may be applied to the analog-to-digital converter 138 during a period in which a power-off signal is applied to the display device 100 and a turn-off sensing process for detecting a characteristic value of the driving transistor DRT is performed.

[0145] In contrast, the scaled sub-pixel driving voltage EVDD_S may be applied to the analog-to-digital converter 138 during the display driving period.

[0146] When the shutdown sensing process is performed, the analog-to-digital converter 138 can detect the sensing voltage Vsen1 of one sub-pixel (e.g., SP1) among the four sub-pixels SP1, SP2, SP3, and SP4 connected to the first sensing line SL1 at the first time. Similarly, the analog-to-digital converter 138 can detect the sensing voltage Vsen2 of one sub-pixel (e.g., SP5) among the four sub-pixels SP5, SP6, SP7, and SP8 connected to the second sensing line SL2, and can detect the sensing voltage Vsen3 of one sub-pixel (e.g., SP9) among the four sub-pixels SP9, SP10, SP11, and SP12 connected to the third sensing line SL3.

[0147] At a second time after the first time, the analog-to-digital converter 138 may detect a sensing voltage Vsen1 of another sub-pixel (e.g., SP2) among the four sub-pixels SP1, SP2, SP3, and SP4 connected to the first sensing line SL1. Similarly, the analog-to-digital converter 138 may detect a sensing voltage Vsen2 of another sub-pixel (e.g., SP6) among the four sub-pixels SP5, SP6, SP7, and SP8 connected to the second sensing line SL2, and may detect a sensing voltage Vsen3 of another sub-pixel (e.g., SP10) among the four sub-pixels SP9, SP10, SP11, and SP12 connected to the third sensing line SL3.

[0148] In this case, the analog-to-digital converter 138 may control the sampling switches SAM1 , SAM2 , and SAM3 to detect the sensing voltages Vsen of the three sub-pixels simultaneously or individually through the three sensing lines SL1 , SL2 , and SL3 .

[0149] For example, at the first time, the analog-to-digital converter 138 can simultaneously turn on the sampling switches SAM1, SAM2 and SAM3, thereby simultaneously detecting the sensing voltages Vsen1, Vsen2 and Vsen3 of the first sub-pixel SP1, the fifth sub-pixel SP5 and the ninth sub-pixel SP9 corresponding to the red sub-pixel R through the first sensing line SL1, the second sensing line SL2 and the third sensing line SL3, respectively.

[0150] In addition, at the second time, the analog-to-digital converter 138 can simultaneously turn on the sampling switches SAM1, SAM2 and SAM3, thereby simultaneously detecting the sensing voltages Vsen1, Vsen2 and Vsen3 of the second sub-pixel SP2, the sixth sub-pixel SP6 and the tenth sub-pixel SP10 corresponding to the white sub-pixel W through the first sensing line SL1, the second sensing line SL2 and the third sensing line SL3, respectively.

[0151] In addition, at the third time, the analog-to-digital converter 138 can simultaneously turn on the sampling switches SAM1, SAM2 and SAM3, thereby simultaneously detecting the sensing voltages Vsen1, Vsen2 and Vsen3 of the third sub-pixel SP3, the seventh sub-pixel SP7 and the eleventh sub-pixel SP11 corresponding to the green sub-pixel G through the first sensing line SL1, the second sensing line SL2 and the third sensing line SL3, respectively.

[0152] At the fourth time, the analog-to-digital converter 138 can simultaneously turn on the sampling switches SAM1, SAM2 and SAM3, thereby simultaneously detecting the sensing voltages Vsen1, Vsen2 and Vsen3 of the fourth sub-pixel SP4, the eighth sub-pixel SP8 and the twelfth sub-pixel SP12 corresponding to the blue sub-pixel B through the first sensing line SL1, the second sensing line SL2 and the third sensing line SL3 respectively.

[0153] In this case, the line capacitors Cline1, Cline2 and Cline3 storing the sensing voltage Vsen of the sensing node of the corresponding sub-pixel are connected to the three sensing lines SL1, SL2 and SL3, respectively. In other words, the sensing voltage Vsen1 of the sub-pixel detected among the four sub-pixels SP1, SP2, SP3 and SP4 connected to the first sensing line SL1 is stored in the first line capacitor Cline1 connected to the first sensing line SL1. In addition, the sensing voltage Vsen2 of the sub-pixel detected among the four sub-pixels SP5, SP6, SP7 and SP8 connected to the second sensing line SL2 is stored in the second line capacitor Cline2 connected to the second sensing line SL2, and the sensing voltage Vsen3 of the sub-pixel detected among the four sub-pixels SP9, SP10, SP11 and SP12 connected to the third sensing line SL3 is stored in the third line capacitor Cline3 connected to the third sensing line SL3.

[0154] Therefore, the analog-to-digital converter 138 can simultaneously or individually detect the sensing voltages Vsen1, Vsen2, and Vsen3 stored in the three line capacitors Cline1, Cline2, and Cline3, thereby measuring the three sensing voltages Vsen1, Vsen2, and Vsen3 through the three sensing channels CH1, CH2, and CH3. Therefore, the analog-to-digital converter 138 can control the pseudo sampling switch SAMd during the turn-off sensing process, thereby detecting the turn-off sensing voltage VRTA through the pseudo channel CHd.

[0155] In this case, the analog-to-digital converter 138 may convert the data voltages Vsen1, Vsen2, and Vsen3 detected through the three sensing channels CH1, CH2, and CH3 into digital sensing data DSEN1, DSEN2, and DSEN3, convert the turn-off sensing voltage VRTA detected through one dummy channel CHd into digital dummy sensing data DSENd, and output the digital dummy sensing data DSENd. The timing controller 140 may store the digital dummy sensing data DSENd in the memory 144.

[0156] The compensation circuit 142 may read the digital sensing data DSEN1 , DSEN2 , and DSEN3 transmitted from the sensing channels CH1 , CH2 , and CH3 , compensate the image data DATA to be provided to the sub-pixels SP, and output the compensated digital image data DATA_comp to the data driving circuit 130 .

[0157] Therefore, during the off sensing process, the compensation circuit 142 may detect the gain or offset of the analog-to-digital converter 138 according to the digital dummy sensing data DSENd transmitted from the dummy channel CHd and change the reference value stored in the memory 144 to compensate for it.

[0158] Fig. 9 is a view showing an example of a switch circuit for transmitting a turn-off sensing voltage and a sub-pixel driving voltage to an analog-to-digital converter in a display device according to an embodiment of the present disclosure.

[0159] The switch circuit 137 may be used to detect a change in the sub-pixel driving voltage EVDD during a display driving period, and to detect a gain or offset of the analog-to-digital converter ADC during an off-sensing process.

[0160] Reference Fig. 9 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel driving voltage EVDD may be scaled to a range of an input voltage of the analog-to-digital converter 138 by the first scaler 136 .

[0161] Therefore, the turn-off sensing voltage VRTA and the scaled sub-pixel driving voltage EVDD_S may be provided to the switching circuit 137 , and the switching circuit 137 may provide the turn-off sensing voltage VRTA or the scaled sub-pixel driving voltage EVDD_S to the analog-to-digital converter 138 at different times.

[0162] To this end, the switch circuit 137 may include a first switch SW1 to which the scaled sub-pixel driving voltage EVDD_S is transmitted and a second switch SW2 to which a turn-off sensing voltage VRTA for detecting a gain or offset of the analog-to-digital converter 138 is transmitted.

[0163] An inverter INV may apply opposite signals so that the first switch SW1 and the second switch SW2 may be turned on at different times.

[0164] In other words, the on-off of the first switch SW1 is controlled by the switch control signal SCS, but the on-off of the second switch SW2 may be controlled by an inverted signal of the switch control signal SCS through the inverter INV.

[0165] In this structure, since the first switch SW1 is turned on by the switch control signal SCS and the second switch SW2 is turned off during the display driving period, the scaled sub-pixel driving voltage EVDD_S is provided to the analog-to-digital converter 138 .

[0166] In contrast, at the end of the display driving period, for example, during a turn-off sensing process, the first switch SW1 is turned off, and the second switch SW2 is turned on, so that the turn-off sensing voltage VRTA may be provided to the analog-to-digital converter 138 .

[0167] Therefore, the switch control signal SCS may be used as a signal for identifying a display driving period of the display device 100 .

[0168] Fig.10 is a view showing an example of a configuration of a timing controller for compensating image data according to a change in a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure.

[0169] Reference Fig.10 , in the display device 100 according to an embodiment of the present disclosure, the timing controller 140 may include a memory 144 , a second scaler 146 , a current calculation circuit 148 , and a compensation circuit 142 .

[0170] The subpixel driving voltage EVDD_S scaled to the input voltage level of the analog-to-digital converter 138 during the display driving period may be detected through the dummy channel CHd. The analog-to-digital converter 138 converts the scaled subpixel driving voltage EVDD_S into digital dummy sensing data DSENd and transmits it to the timing controller 140.

[0171] The timing controller 140 may store the digital dummy sensing data DSENd transmitted from the analog-to-digital converter 138 in the memory 144 .

[0172] In this case, since the digital dummy sensing data DSENd transmitted from the AD converter 138 reflects a value whose level has been adjusted by reflecting the range of the input voltage of the AD converter 138 , it can be scaled back to the range of the subpixel driving voltage EVDD.

[0173] Fig.11 is a view showing an example of a lookup table for calculating the intensity of a current flowing through a data driving circuit according to a variation width of a sub-pixel driving voltage in a display device according to an embodiment of the present disclosure.

[0174] Reference Fig.11 , in the display device 100 according to the embodiment of the present disclosure, the digital pseudo sensing data DSENd corresponding to the scaled sub-pixel driving voltage EVDD_S indicates a value within 3V which is an input voltage range of the analog-to-digital converter 138. Therefore, the second scaler 146 may scale the digital pseudo sensing data DSENd back to the level of the sub-pixel driving voltage EVDD having an amplitude of about 27V.

[0175] The current calculation circuit 148 may calculate the intensity of current transmitted through the data driving circuit 130 in which the digital dummy sensing data DSENd has been detected, based on data scaled to the level of the sub-pixel driving voltage EVDD.

[0176] In this case, the current intensity corresponding to the variation width of the sub-pixel driving voltage EVDD provided from the power management circuit 150 and the sub-pixel driving voltage EVDD detected from the data driving circuit 130 can be stored in the memory 144 in the form of a lookup table, and the current calculation circuit 148 can calculate the current intensity transmitted through the data driving circuit 130 by referring to the lookup table stored in the memory 144.

[0177] The compensation circuit 142 may compensate the image data DATA transmitted to the data driving circuit 130 based on the current intensity of the sub-pixel driving voltage EVDD transmitted from the current calculation circuit 148 , and output the compensated digital image data DATA_comp to the data driving circuit 130 .

[0178] For example, as the intensity of current delivered through the first data driving circuit group 130 # 1 increases, the temperature of the first data driving circuit group 130 # 1 may increase compared to the other data driving circuit groups.

[0179] In this case, the sub-pixel driving voltage EVDD transmitted through the first data driving circuit group 130 # 1 may be reduced due to the increase in temperature of the first data driving circuit group 130 # 1 .

[0180] The subpixel driving voltage EVDD transmitted through the first data driving circuit group 130 # 1 may be detected through the dummy channel CHd, and the timing controller 140 may calculate a variation width by comparing the digital dummy sensing data DSENd detected through the dummy channel CHd with the subpixel driving voltage EVDD provided from the power management circuit 150 .

[0181] Therefore, the timing controller 140 can detect the current intensity and temperature rise transmitted through the first data driving circuit group 130#1 based on the variation width of the subpixel driving voltage EVDD, compensate for it, and provide the compensated digital image data DATA_comp to the first data driving circuit group 130#1.

[0182] Through this process, the quality and temperature variation of the data driving circuit 130 due to the sub-pixel driving voltage EVDD may be compensated, so that defects of the data driving circuit 130 may be prevented and image quality may be enhanced.

[0183] Fig.12 is a flowchart illustrating a display driving method according to an embodiment of the present disclosure.

[0184] Reference Fig.12 , the display driving method according to the embodiment of the present disclosure may include: a step S100 of scaling the sub-pixel driving voltage EVDD, a step S200 of determining whether it is in a display driving period, a step S300 of detecting the sub-pixel driving voltage EVDD_S scaled to the level of the input voltage of the analog-to-digital converter 138 through the pseudo channel CHd during the display driving period, a step S400 of scaling the signal detected through the pseudo channel CHd to the level of the sub-pixel driving voltage EVDD, a step S500 of calculating the current intensity corresponding to the variation width of the sub-pixel driving voltage EVDD, and a step S600 of compensating the image data DATA according to the calculated current intensity.

[0185] For example, if it is determined in step S200 that it is not in the display driving period, that is, in the non-display driving period (step S200 is "No"), the display driving method may further include a step S700 of detecting the turn-off sensing voltage VRTA through the pseudo channel CHd during the non-display driving period. In addition, the display driving method may further include a step S800 of compensating the characteristic value of the analog-to-digital converter 138 based on the turn-off sensing voltage VRTA by the timing controller 140.

[0186] The step S100 of scaling the sub-pixel driving voltage EVDD is a process for scaling the high level of the sub-pixel driving voltage EVDD to fit the input voltage range of the analog-to-digital converter 138 .

[0187] Step S300 of detecting the sub-pixel driving voltage EVDD_S scaled to the level of the input voltage of the analog-to-digital converter 138 through the pseudo channel CHd during the display driving period is a process for the following operation: the sub-pixel driving voltage EVDD_S scaled to the input voltage level of the analog-to-digital converter 138 is provided to the pseudo channel CHd during the period during which an image is displayed on the display panel 110, and the analog-to-digital converter 138 detects the scaled sub-pixel driving voltage EVDD_S.

[0188] Step S400 of scaling the signal detected through the pseudo channel CHd to the level of the sub-pixel driving voltage EVDD is a process in which, if the digital pseudo sensing data DSENd transmitted from the analog-to-digital converter 138 is transmitted to the timing controller 140, the timing controller 140 scales the digital pseudo sensing data DSENd back to the level of the sub-pixel driving voltage EVDD provided from the power management circuit 150.

[0189] Step S500 of calculating the current intensity corresponding to the variation width of the subpixel driving voltage EVDD is a process for calculating the intensity of the current flowing through the data driving circuit 130 according to the variation width of the subpixel driving voltage EVDD provided from the power management circuit 150 and the voltage detected from the data driving circuit 130.

[0190] The step S600 of compensating the image data DATA according to the calculated current intensity is a process for compensating the image data DATA in consideration of the intensity of the current flowing through the data driving circuit 130 so as to be able to reduce the temperature of the data driving circuit 130 .

[0191] The step S700 of detecting the off sensing voltage VRTA through the dummy channel CHd during the non-display driving period is a process for detecting the off sensing voltage VRTA through the dummy channel CHd when the off sensing process is performed.

[0192] The step S800 of compensating the characteristic value of the analog-to-digital converter 138 based on the turn-off sensing voltage VRTA by the timing controller 140 is a process for compensating the gain or offset of the analog-to-digital converter 138 based on the detected turn-off sensing voltage VRTA.

[0193] The foregoing embodiment is briefly described below.

[0194] A display device 100 according to an embodiment of the present disclosure includes: a display panel 110, which includes a plurality of sensing channels CH connected to a plurality of sub-pixels SP to detect driving characteristic values; a data driving circuit 130, which includes an analog-to-digital converter 138 configured to convert a sensing voltage detected through the plurality of sensing channels CH into digital sensing data DSEN and convert a sub-pixel driving voltage EVDD detected through at least one pseudo channel CHd into digital pseudo sensing data DSENd; and a timing controller 140, which is configured to calculate the intensity of a current flowing through the data driving circuit 130 based on the digital pseudo sensing data DSENd transmitted from the data driving circuit 130, and compensate for image data to be transmitted to the data driving circuit 130.

[0195] The data driving circuit 130 includes a first scaler 136 configured to convert the sub-pixel driving voltage EVDD into an input voltage level of the analog-to-digital converter 138 .

[0196] The data driving circuit 130 includes a switch circuit 137 configured to select a sub-pixel driving voltage EVDD or a turn-off sensing voltage VRTA and transfer the selected voltage to at least one dummy channel CHd.

[0197] The switching circuit 137 includes: a first switch SW1, which is configured to transmit the sub-pixel driving voltage EVDD to at least one pseudo channel CHd during a display driving period; a second switch SW2, which is configured to transmit the shutdown sensing voltage VRTA to at least one pseudo channel CHd during a shutdown sensing process period; and an inverter INV, which is configured to invert the signal applied to the first switch SW1 and apply the inverted signal to the second switch SW2.

[0198] The timing controller 140 includes: a memory 144, which is configured to store digital pseudo sensing data DSENd; a current calculation circuit 148, which is configured to compare the sub-pixel driving voltage EVDD transmitted from the power management circuit 150 with the digital pseudo sensing data DSENd to calculate the intensity of the current flowing through the data driving circuit 130; and a compensation circuit 142, which is configured to compensate the image data to be transmitted to the data driving circuit 130 according to the value calculated by the current calculation circuit 148.

[0199] The timing controller 140 also includes a second scaler 146 configured to scale the digital dummy sensing data DSENd back to the level of the sub-pixel driving voltage EVDD.

[0200] The data driving circuit 130 according to an embodiment of the present disclosure includes: a plurality of data lines DL extending to the display panel 110 and configured to provide a data voltage Vdata, the display panel 110 including a plurality of sub-pixels SP; and an analog-to-digital converter 138 configured to convert a sensing voltage Vsen detected through a plurality of sensing channels CH into digital sensing data DSEN and to convert a sub-pixel driving voltage EVDD detected through at least one pseudo channel CHd into digital pseudo sensing data DSENd.

[0201] The data driving circuit 130 further includes a scaler 136 configured to convert the sub-pixel driving voltage EVDD to an input voltage level of the analog-to-digital converter 138 .

[0202] The data driving circuit 130 further includes a switching circuit 137 configured to select the sub-pixel driving voltage EVDD or the off-sensing voltage VRTA and transfer the selected voltage to at least one dummy channel CHd.

[0203] The switching circuit 137 includes: a first switch SW1, which is configured to transmit the sub-pixel driving voltage EVDD to at least one pseudo channel CHd during a display driving period; a second switch SW2, which is configured to transmit the shutdown sensing voltage VRTA to at least one pseudo channel CHd during a shutdown sensing process period; and an inverter INV, which is configured to invert the signal applied to the first switch SW1 and apply the inverted signal to the second switch SW2.

[0204] The data driving circuit 130 receives compensation data for compensating the data voltage Vdata supplied to the display panel 110 according to a comparison result between the sub-pixel driving voltage EVDD output from the power management circuit 150 and the digital dummy sensing data DSENd.

[0205] A method for driving a display device according to an embodiment of the present disclosure includes: detecting a sub-pixel driving voltage EVDD through a pseudo channel CHd; calculating a current intensity corresponding to a variation width of the sub-pixel driving voltage EVDD; and compensating image data DATA provided to a data driving circuit 130 according to the calculated current intensity, wherein the display device includes: a display panel 110 having a plurality of sub-pixels SP; a data driving circuit 130 including an analog-to-digital converter 138, which converts a sensing voltage Vsen detected through a plurality of sensing channels CH into digital sensing data DSEN; and a timing controller 140, which provides the image data DATA to the data driving circuit 130.

[0206] The sub-pixel driving voltage EVDD is a voltage scaled to the level of the input voltage of the analog-to-digital converter 138 .

[0207] The sub-pixel driving voltage EVDD is detected during the display driving period.

[0208] The display driving method further includes detecting a turn-off sensing voltage VRTA through the dummy channel CHd during a non-display driving period, and compensating a characteristic value of the analog-to-digital converter 138 based on the turn-off sensing voltage VRTA.

[0209] Calculating the current intensity also includes scaling the voltage scaled to the level of the input voltage of the analog-to-digital converter 138 back to the level of the sub-pixel driving voltage EVDD.

[0210] The above description is presented to enable any person skilled in the art to make and use the technical ideas of the present invention, and is provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical ideas of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present invention. Therefore, the scope of the present invention is not limited to the embodiments shown, but should conform to the widest scope consistent with the claims. The scope of protection of the present invention should be interpreted based on the attached claims, and all technical ideas within their equivalent ranges should be interpreted as being included within the scope of the present invention.

Claims

1. A display device, comprising: A display panel including a plurality of sensing channels configured to detect driving characteristic values ​​and connected to the plurality of sub-pixels; a data driving circuit including an analog-to-digital converter configured to convert the sensing voltages detected through the plurality of sensing channels into digital sensing data and to convert the sub-pixel driving voltage detected through at least one dummy channel into digital dummy sensing data; as well as a timing controller configured to calculate the intensity of the current flowing through the data driving circuit based on the digital pseudo sensing data transmitted from the data driving circuit, and to compensate the image data to be transmitted to the data driving circuit, The data driving circuit further includes a switch circuit, which is configured to select the sub-pixel driving voltage or turn off the sensing voltage and transmit the selected voltage to the at least one dummy channel.

2. The display device according to claim 1, wherein: The data driving circuit includes a first scaler configured to convert the sub-pixel driving voltage to an input voltage level of the analog-to-digital converter.

3. The display device according to claim 1, wherein: The switch circuit comprises: a first switch configured to transmit the sub-pixel driving voltage to the at least one dummy channel during a display driving period; a second switch configured to transfer the turn-off sensing voltage to the at least one dummy channel during a turn-off sensing process period; and An inverter is configured to invert a signal applied to the first switch and apply the inverted signal to the second switch.

4. The display device according to claim 1, wherein: The timing controller comprises: a memory configured to store the digital pseudo sensing data; a current calculation circuit configured to compare the sub-pixel driving voltage transmitted from the power management circuit with the digital pseudo sensing data to calculate the intensity of the current flowing through the data driving circuit; and A compensation circuit is configured to compensate the image data to be transmitted to the data driving circuit according to the value calculated by the current calculation circuit.

5. The display device according to claim 4, wherein: The timing controller also includes a second scaler configured to scale the digital pseudo sensing data back to a level of the sub-pixel driving voltage.

6. A data driving circuit, comprising: a plurality of data lines extending to a display panel and configured to provide data voltages, the display panel including a plurality of sub-pixels; an analog-to-digital converter configured to convert sensing voltages detected through the plurality of sensing channels into digital sensing data and to convert a sub-pixel driving voltage detected through at least one dummy channel into digital dummy sensing data; as well as A switch circuit is configured to select the sub-pixel driving voltage or turn off the sensing voltage and transmit the selected voltage to the at least one dummy channel. 7 . The data driving circuit according to claim 6 , further comprising a scaler configured to convert the sub-pixel driving voltage into an input voltage level of the analog-to-digital converter.

8. The data driving circuit according to claim 6, wherein: The switch circuit comprises: a first switch configured to transmit the sub-pixel driving voltage to the at least one dummy channel during a display driving period; a second switch configured to transfer the turn-off sensing voltage to the at least one dummy channel during a turn-off sensing process period; and An inverter is configured to invert a signal applied to the first switch and apply the inverted signal to the second switch.

9. The data driving circuit according to claim 6, wherein: The data driving circuit receives compensation data for compensating a data voltage supplied to the display panel according to a comparison result between a sub-pixel driving voltage output from a power management circuit and the digital pseudo sensing data.

10. A method for driving a display device, the display device comprising a display panel in which a plurality of sub-pixels are arranged, a data driving circuit including an analog-to-digital converter that converts sensing voltages detected through a plurality of sensing channels into digital sensing data and a switch circuit configured to select a sub-pixel driving voltage or turn off the sensing voltage and transmit the selected voltage to a dummy channel, and a timing controller that provides image data to the data driving circuit, the method comprising: Detecting the sub-pixel driving voltage through the pseudo channel; Calculating the current intensity corresponding to the variation width of the sub-pixel driving voltage; as well as Image data provided to the data driving circuit is compensated according to the calculated current intensity.

11. The method according to claim 10, wherein: The sub-pixel driving voltage is a voltage scaled to a level of an input voltage of the analog-to-digital converter.

12. The method according to claim 10, wherein: The sub-pixel driving voltage is detected during a display driving period.

13. The method according to claim 12, further comprising: detecting the turn-off sensing voltage through the dummy channel during a non-display driving period; as well as A characteristic value of the analog-to-digital converter is compensated based on the turn-off sensing voltage.

14. The method according to claim 11, wherein: Calculating the current intensity further includes scaling the voltage scaled to the level of the input voltage of the analog-to-digital converter back to the level of the sub-pixel driving voltage.

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