A data access method and a data access system based on SRAM
By setting a check bit for each byte in SRAM and performing an XOR operation for verification during reading, the problem of SRAM data reading errors was solved, and the accuracy of data reading and error location were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AMICRO SEMICONDUCTOR CO LTD
- Filing Date
- 2022-11-21
- Publication Date
- 2026-06-09
AI Technical Summary
In industrial control computers used in industrial applications, SRAM data reading is easily affected by external intrusion and harsh environments, leading to data reading errors that are difficult to locate.
Before writing data to SRAM, a check bit is set for each byte, and the data correctness is verified by an XOR operation during reading to ensure the accuracy of data reading.
It improves the accuracy of data reading, and can detect and save the address of erroneous data, making it easier to locate and modify it later.
Smart Images
Figure CN115719603B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of intelligent robot technology, and specifically to a data access method and system based on SRAM. Background Technology
[0002] In current industrial control computers used in industrial applications, SRAM is an essential component for program execution, and its security requirements are extremely high. During the process of reading data from SRAM, external intrusion and tampering, or harsh application environments, can lead to errors in reading the data stored in SRAM, resulting in unpredictable consequences. Moreover, it is not easy for software to pinpoint the location of the data reading error. Summary of the Invention
[0003] This invention provides a data access method and system based on SRAM. The specific technical solution of this invention is as follows:
[0004] A data access method based on SRAM includes the following steps: S1: A data writing module sets a check bit for each byte of several bytes of data and determines the value of the corresponding check bit according to the data of each byte; S2: The data writing module writes several bytes of data and the corresponding check bit value into SRAM according to the write address of the several bytes of data; S3: A data reading module reads data and the corresponding check bit value from SRAM according to the read address of the data, and determines whether the read data is correct according to the read data and the corresponding check bit value during the reading process; S4: If the data reading module determines that the read data is correct, it reads the data; if the data reading module determines that the read data is incorrect, it stops reading and then saves the incorrect data and the read address of the incorrect data into SRAM.
[0005] Furthermore, in step S1, the data writing module writes 36 bits of data into the SRAM each time. The 36 bits of data include 4 bytes of data and the value of the check bit corresponding to each byte of data. Each byte of data is 8 bits.
[0006] Further, in step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: the data writing module selects one byte of data and performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the check bit corresponding to the data of that byte is 0; if the number of 1s in the XOR operation result is odd, the value of the check bit corresponding to the data of that byte is 1; and so on, the data writing module sequentially obtains the value of the check bit corresponding to the data of each byte.
[0007] Further, in step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: the data writing module selects one byte of data and performs an XOR operation on the 8 bits of the byte with 1 in sequence; if the number of 1s in the XOR operation result is even, the value of the check bit corresponding to the data of that byte is 1; if the number of 1s in the XOR operation result is odd, the value of the check bit corresponding to the data of that byte is 0; and so on, the data writing module sequentially obtains the value of the check bit corresponding to the data of each byte.
[0008] Further, in step S3, the data reading module determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process, including the following steps: During the data reading process, the data reading module reads each byte of data sequentially according to the read address; after reading one byte of data, the data reading module obtains the check bit value based on the data of that byte; the data reading module performs an XOR operation on the check bit data of that byte and the corresponding check bit data; if the result of the XOR operation is 0, then the data being read by the data reading module is correct, and the data reading module reads the data from the SRAM; if the result of the XOR operation is 1, then the data being read by the data reading module is incorrect, the data reading module stops reading, and then saves the incorrect data and the read address of the incorrect data to the SRAM.
[0009] Furthermore, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 0; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 1.
[0010] Furthermore, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 1 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 1; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 0.
[0011] Furthermore, after the data reading module saves the erroneous data and its read address to SRAM, it sends an interrupt signal to the CPU, enabling the CPU to locate the erroneous data byte's position and read address within a set of bytes.
[0012] A data writing method includes the following steps: a data writing module sets a check bit for each byte of several bytes of data, and determines the value of the corresponding check bit according to the data of each byte; the data writing module writes several bytes of data and the value of the corresponding check bit into SRAM according to the write address of several bytes of data.
[0013] A data reading method includes the following steps: a data reading module reads data and the corresponding check bit value from SRAM according to the data read address, and determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process; if the data reading module determines that the read data is correct, it reads the data; if the data reading module determines that the read data is incorrect, it stops reading and then saves the incorrect data and the read address of the incorrect data to SRAM.
[0014] A data access system that executes the above-described SRAM-based data access method, the data storage system comprising a CPU, a data writing module, a data reading module, and an SRAM; the CPU is used to locate the position and read address of the byte of erroneous data within a plurality of bytes of data; the data writing module is used to write data into the SRAM; the data reading module is used to read data from the SRAM; and the SRAM is used to store the data.
[0015] Compared with existing technologies, the advantages of this invention are as follows: Before writing data into SRAM, this application sets the value of the check bit according to the data content of each byte, and then writes the data and check bit together into SRAM. This allows the data reading module to determine whether the read data is correct based on the value of the check bit when reading data from SRAM, thus improving the accuracy of data reading. Each byte of data is checked to ensure that errors occurring in each byte can be detected. When a read error occurs, the address of the erroneous data and the byte's position in the data are saved for subsequent location and modification. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the data access process in one embodiment of the present invention;
[0017] Figure 2 This is a schematic diagram of the data writing structure in one embodiment of the present invention. Figure 1 ;
[0018] Figure 3 This is a schematic diagram of the data writing structure in one embodiment of the present invention. Figure 2 . Detailed Implementation
[0019] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0020] In the description of this invention, it should be noted that the directional terms such as "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this invention.
[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Thus, the use of "first" and "second" to define a feature may explicitly or implicitly include one or more of that feature, and in the description of this invention, "at least" means one or more, unless otherwise explicitly specified.
[0022] In this invention, unless otherwise explicitly specified and limited, the terms "assembly," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to a mechanical connection; they can refer to a direct connection or a connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0023] In this invention, unless otherwise specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "below," and "over" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Above," "below," and "below" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0024] The following description, in conjunction with the accompanying drawings, further illustrates specific embodiments of the present invention, making the technical solution and its beneficial effects clearer and more explicit. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the invention.
[0025] Static Random-Access Memory (SRAM) is a type of random access memory. The term "static" means that the data stored in this type of memory is permanently retained as long as power is supplied. In contrast, the data stored in Dynamic Random-Access Memory (DRAM) needs to be updated periodically. However, when the power supply is interrupted, the data stored in SRAM will still be lost (this is called volatile memory), unlike ROM or flash memory which can retain data even after power is lost. It comes in two forms: one is a cache memory fixed on the motherboard; the other is a cache memory for expansion, inserted into a card slot (COAST). Additionally, the CMOS chip 1468l8 also has a smaller 128-byte SRAM internally, storing the configuration data we set.
[0026] A byte (Byte / bait / n. [C]) is a unit of measurement used in computer information technology to measure storage capacity. Typically, one byte equals eight bits (bit), and it is also used in some computer programming languages to represent data types and language characters. A bit is the smallest unit of data in a computer, namely a binary digit, with values of 0 and 1.
[0027] like Figure 1 As shown, an SRAM-based data access method includes the following steps:
[0028] Step S1: The data writing module sets a check bit for each byte of data and determines the corresponding check bit value based on the data of each byte. A byte typically has 8 bits. If parity checking is required, an additional code element needs to be added. Therefore, during transmission and reception, there are 8 data bits and 1 check bit. Parity checking refers to whether the number of 1s in each frame of data sent and received is odd or even after adding the check code. Parity check codes are a general term for odd and even parity codes, and are a basic type of error detection code. It consists of n-1 information bits and 1 check bit, and can be represented as (n, n-1). If it is an odd parity code, after adding a check element, the number of "1"s in a codeword of length n is odd; if it is an even parity code, after adding a check element, the number of "1"s in a codeword of length n is even. Let: If an even parity code is represented by A=[an-1,an-2,…,a1,a0]. Example: Even parity code consists of 8 data bits and 1 parity bit, totaling 9 data bits, where the number of 1s must be even. Generally, the parity bit can be obtained by directly adding the eight data bits in binary (ignoring carry). For example, the parity bit a of 11001010 is (1+1+0+0+1+0+1+0)=0; therefore, the transmitted data is 110010100. Odd parity code also consists of 8 data bits and 1 parity bit, totaling 9 data bits, where the number of 1s must be odd. Generally, the parity bit can be obtained by directly adding and inverting the eight data bits (again, ignoring carry). For example, the parity bit a of 11001010 is ~(1+1+0+0+1+0+1+0)=1; therefore, the transmitted data is 110010101.
[0029] As one embodiment, such as Figure 2 and Figure 3 As shown, in step S1, the data writing module writes 36 bits of data into the SRAM each time. This 36-bit data includes 4 bytes of data and the parity bit value corresponding to each byte within those 4 bytes. Each byte of data is 8 bits. In the SRAM structure, the original 32-bit data needs to be extended to 36 bits, meaning 4 extra bits are needed, corresponding to the parity bits of the 4 bytes forming a word of data. The written data includes 4 bytes (byte0, byte1, byte2, and byte3) and 4 corresponding parity bits (P0, P1, P2, and P3). Each byte of data and its corresponding parity bit are stored together in the SRAM. Alternatively, the data can be stored according to the byte data arrangement, with the parity bits arranged according to the byte data order before being stored together with the byte data.
[0030] As one embodiment, the parity check bit value can be obtained through XOR operation when setting code data based on binary data. In step S1, the data writing module determines the corresponding check bit value according to the data of each byte, including the following steps: the data writing module selects one byte of data and performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the check bit corresponding to the data of that byte is 0; if the number of 1s in the XOR operation result is odd, the value of the check bit corresponding to the data of that byte is 1; and so on, the data writing module obtains the value of the check bit corresponding to each byte of data in sequence. During even check, each bit of a byte is XORed with 0. The number of 1s is determined by the result of the XOR operation. The data obtained by the XOR operation in even check is the original data. For example, XORing 11001010 with 0 results in 11001010, which has an even number of 1s. Therefore, the value of the check bit is 0, and the data written is 110010100.
[0031] In one embodiment, in step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: The data writing module selects one byte of data and performs an XOR operation on each of the 8 bits of the byte with 1. If the number of 1s in the XOR result is even, the value of the check bit corresponding to the data of that byte is 1; if the number of 1s in the XOR result is odd, the value of the check bit corresponding to the data of that byte is 0; and so on, the data writing module sequentially obtains the value of the check bit corresponding to the data of each byte. When performing odd check, each bit of the data of a byte is XORed with 1, and the number of 1s is determined by the result of the XOR operation. The data obtained by performing the XOR operation for odd check is the inverse of the original data. That is, XORing 11001010 with 0 results in 00110101, the number of 1s is even, the value of the check bit is 1, and the data written is 110010101.
[0032] Step S2: After obtaining the check bit of each byte, the data writing module can write several bytes of data and the corresponding check bit value into the SRAM according to the write address of several bytes of data for data storage.
[0033] Step S3: The data reading module reads data and the corresponding check bit value from the SRAM according to the data read address, and determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process. When reading data, the data reading module uses the above method to obtain a check bit value based on the read data, and then compares the check bit value with the check bit value to determine whether the read data is incorrect.
[0034] In one embodiment, in step S3, the data reading module determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process. This includes the following steps: During the data reading process, the data reading module reads each byte of data sequentially according to the read address; after reading one byte of data, the data reading module obtains the check bit value based on that byte of data; the data reading module performs an XOR operation on the check bit data of that byte and the corresponding check bit data; if the result of the XOR operation is 0, the data being read by the data reading module is correct, and the data reading module reads the data from the SRAM; if the result of the XOR operation is 1, the data being read by the data reading module is incorrect, the data reading module stops reading, and then saves the incorrect data and the read address of the incorrect data to the SRAM. When writing data, if odd check is used to determine the check bit value, then odd check must also be used to determine the check bit value during data reading; similarly, when writing data, if even check is used to determine the check bit value, then even check must also be used to determine the check bit value during data reading. If the data read is correct, the values of the check bit and the verification bit will both be 0 or both be 1. The result of the XOR operation between 0 and 0 or between 1 and 1 will be 0. If the result of the XOR operation between the check bit and the verification bit is 1, it indicates that there is an error in the data read, and reading will stop.
[0035] In one embodiment, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 0; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 1.
[0036] In one embodiment, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 1 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 1; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 0.
[0037] In one embodiment, after the data reading module saves the erroneous data and the read address of the erroneous data to SRAM, it sends an interrupt signal to the CPU, so that the CPU can locate the byte of erroneous data in the arrangement position and read address of several bytes of data.
[0038] A data writing method includes the following steps: a data writing module sets a check bit for each byte of several bytes of data, and determines the value of the corresponding check bit according to the data of each byte; the data writing module writes several bytes of data and the value of the corresponding check bit into SRAM according to the write address of several bytes of data.
[0039] In one embodiment, in step S1, the data writing module writes 36 bits of data into the SRAM each time. The 36 bits of data include 4 bytes of data and the value of the check bit corresponding to each byte of the 4 bytes of data. Each byte of data is 8 bits of data.
[0040] In one embodiment, in step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: the data writing module selects one byte of data and performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the check bit corresponding to the data of that byte is 0; if the number of 1s in the XOR operation result is odd, the value of the check bit corresponding to the data of that byte is 1; and so on, the data writing module sequentially obtains the value of the check bit corresponding to the data of each byte.
[0041] In one embodiment, in step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: the data writing module selects one byte of data and performs an XOR operation on the 8 bits of the byte with 1 in sequence; if the number of 1s in the XOR operation result is even, the value of the check bit corresponding to the data of that byte is 1; if the number of 1s in the XOR operation result is odd, the value of the check bit corresponding to the data of that byte is 0; and so on, the data writing module sequentially obtains the value of the check bit corresponding to the data of each byte.
[0042] A data reading method includes the following steps: a data reading module reads data and the corresponding check bit value from SRAM according to the data read address, and determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process; if the data reading module determines that the read data is correct, it reads the data; if the data reading module determines that the read data is incorrect, it stops reading and then saves the incorrect data and the read address of the incorrect data to SRAM.
[0043] In one embodiment, the data reading module determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process, including the following steps: During the data reading process, the data reading module reads each byte of data sequentially according to the read address; after reading one byte of data, the data reading module obtains the check bit value based on the data of that byte; the data reading module performs an XOR operation on the check bit data of that byte and the corresponding check bit data; if the result of the XOR operation is 0, the data being read by the data reading module is correct, and the data reading module reads the data from SRAM; if the result of the XOR operation is 1, the data being read by the data reading module is incorrect, the data reading module stops reading, and then saves the incorrect data and the read address of the incorrect data to SRAM.
[0044] In one embodiment, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 0 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 0; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 1.
[0045] In one embodiment, the data reading module obtains the value of the detection bit based on the data of the byte, including the following steps: the data reading module performs an XOR operation on the 8 bits of the byte with 1 in sequence; if the number of 1s in the XOR operation result is even, the value of the detection bit corresponding to the data of the byte is 1; if the number of 1s in the XOR operation result is odd, the value of the detection bit corresponding to the data of the byte is 0.
[0046] In one embodiment, after the data reading module saves the erroneous data and the read address of the erroneous data to SRAM, it sends an interrupt signal to the CPU, so that the CPU can locate the byte of erroneous data in the arrangement position and read address of several bytes of data.
[0047] A data access system executes the aforementioned SRAM-based data access method. The data storage system includes a CPU, a data writing module, a data reading module, and SRAM. The CPU is used to locate the position and read address of the byte containing erroneous data within a set of bytes. The data writing module writes data into the SRAM. The data reading module reads data from the SRAM. The SRAM stores the data. The data writing module and the data reading module are hardware circuits; they can be the same module with data writing and storage functions, or they can be two independent modules.
[0048] Compared with existing technologies, the advantages of this invention are as follows: Before writing data into SRAM, this application sets the value of the check bit according to the data content of each byte, and then writes the data and check bit together into SRAM. This allows the data reading module to determine whether the read data is correct based on the value of the check bit when reading data from SRAM, thus improving the accuracy of data reading. Each byte of data is checked to ensure that errors occurring in each byte can be detected. When a read error occurs, the address of the erroneous data and the byte's position in the data are saved for subsequent location and modification.
[0049] In the description of this specification, the terms "in one embodiment," "preferred," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. The connection methods linked in the description of this specification have significant effects and practical utility.
[0050] Based on the above description of the structure and principle, those skilled in the art should understand that the present invention is not limited to the specific embodiments described above. Improvements and substitutions made using techniques known in the art based on the present invention all fall within the protection scope of the present invention and should be defined by the claims.
Claims
1. A data access method based on SRAM, characterized in that, The method includes the following steps: S1: The data writing module sets a check bit for each byte of data and determines the value of the corresponding check bit based on the data of each byte; S2: The data writing module writes several bytes of data and the corresponding check bit value into the SRAM according to the write address of several bytes of data; S3: The data reading module reads data and the corresponding check bit value from SRAM according to the data read address, and determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process; S4: If the data reading module determines that the data being read is correct, it will read the data being read; if the data reading module determines that the data being read is incorrect, it will stop reading and then save the incorrect data and the address of the incorrect data to SRAM. In step S3, the data reading module determines whether the read data is correct based on the read data and the corresponding check bit value, including the following steps: During the data reading process, the data reading module reads each byte of data sequentially according to the read address. After reading one byte of data, the data reading module obtains the value of the detection bit based on that byte of data; The data reading module performs an XOR operation on the detection bit data of the byte and the corresponding check bit data of the byte; If the result of the XOR operation is 0, then the data being read by the data reading module is correct, and the data reading module will read the data from the SRAM. If the result of the XOR operation is 1, then the data reading module is reading incorrect data. The data reading module stops reading and then saves the incorrect data and the address of the incorrect data to SRAM.
2. The SRAM-based data access method according to claim 1, characterized in that, In step S1, the data writing module writes 36 bits of data into the SRAM each time. The 36 bits of data include 4 bytes of data and the value of the check bit corresponding to each byte of data. Each byte of data is 8 bits.
3. The SRAM-based data access method according to claim 1, characterized in that, In step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: The data writing module selects one byte of data and performs an XOR operation on the 8 bits of that byte with 0 in sequence; If the number of 1s in the XOR operation result is even, then the value of the check bit corresponding to the data in that byte is 0; If the number of 1s in the XOR operation result is odd, then the value of the check bit corresponding to the data in that byte is 1; Similarly, the data writing module sequentially obtains the value of the check bit corresponding to each byte of data.
4. The SRAM-based data access method according to claim 1, characterized in that, In step S1, the data writing module determines the value of the corresponding check bit based on the data of each byte, including the following steps: The data writing module selects one byte of data and performs an XOR operation between the 8 bits of that byte and 1 in sequence; If the number of 1s in the XOR operation result is even, then the value of the check bit corresponding to the data in that byte is 1; If the number of 1s in the XOR operation result is odd, then the value of the check bit corresponding to the data in that byte is 0; Similarly, the data writing module sequentially obtains the value of the check bit corresponding to each byte of data.
5. The SRAM-based data access method according to claim 1, characterized in that, The data reading module obtains the value of the detection bit based on the data of this byte, including the following steps: The data reading module performs an XOR operation on each of the 8 bits of the byte with 0. If the number of 1s in the XOR operation result is even, then the value of the detection bit corresponding to the data of that byte is 0; If the number of 1s in the XOR operation result is odd, then the value of the detection bit corresponding to the data in that byte is 1.
6. The SRAM-based data access method according to claim 1, characterized in that, The data reading module obtains the value of the detection bit based on the data of this byte, including the following steps: The data reading module performs an XOR operation on the 8 bits of the byte with 1 in sequence; If the number of 1s in the XOR operation result is even, then the value of the detection bit corresponding to the data in that byte is 1; If the number of 1s in the XOR operation result is odd, then the value of the detection bit corresponding to the data in that byte is 0.
7. The SRAM-based data access method according to claim 1, characterized in that, After the data reading module saves the erroneous data and its read address to SRAM, it sends an interrupt signal to the CPU, enabling the CPU to locate the erroneous data byte's position and read address within a set of bytes.
8. A data writing method, characterized in that, The method includes the following steps: The data writing module sets a check bit for each byte of data and determines the value of the corresponding check bit based on the data of each byte. The data writing module writes several bytes of data and the corresponding check bit value into the SRAM according to the write address of several bytes of data; The data writing module determines the corresponding check bit value based on each byte of data, including the following steps: The data writing module selects one byte of data and performs an XOR operation on the 8 bits of that byte with 0 in sequence; If the number of 1s in the XOR operation result is even, then the value of the check bit corresponding to the data in that byte is 0; If the number of 1s in the XOR operation result is odd, then the value of the check bit corresponding to the data in that byte is 1; Similarly, the data writing module sequentially obtains the value of the check bit corresponding to each byte of data; Alternatively, the data writing module determines the value of the corresponding check bit based on each byte of data, including the following steps: The data writing module selects one byte of data and performs an XOR operation between the 8 bits of that byte and 1 in sequence; If the number of 1s in the XOR operation result is even, then the value of the check bit corresponding to the data in that byte is 1; If the number of 1s in the XOR operation result is odd, then the value of the check bit corresponding to the data in that byte is 0; Similarly, the data writing module sequentially obtains the value of the check bit corresponding to each byte of data.
9. A data reading method, characterized in that, The method includes the following steps: The data reading module reads data and the corresponding check bit value from SRAM according to the data read address, and determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process; If the data reading module determines that the data being read is correct, it will read the data; if the data reading module determines that the data being read is incorrect, it will stop reading and then save the incorrect data and the address of the incorrect data to SRAM. The data reading module determines whether the read data is correct based on the read data and the corresponding check bit value during the reading process, including the following steps: During the data reading process, the data reading module reads each byte of data sequentially according to the read address. After reading one byte of data, the data reading module obtains the value of the detection bit based on that byte of data; The data reading module performs an XOR operation on the detection bit data of the byte and the corresponding check bit data of the byte; If the result of the XOR operation is 0, then the data being read by the data reading module is correct, and the data reading module will read the data from the SRAM. If the result of the XOR operation is 1, then the data reading module is reading incorrect data. The data reading module stops reading and then saves the incorrect data and the address of the incorrect data to SRAM.
10. A data access system, characterized in that, The data access system executes the SRAM-based data access method according to any one of claims 1 to 7, wherein the data access system includes a CPU, a data writing module, a data reading module, and SRAM. The CPU is used to locate the position and read address of the erroneous data byte within a set of bytes of data. The data writing module is used to write data into SRAM; The data reading module is used to read data from SRAM; The SRAM is used to store data.