Three-dimensional flash memory device

Abstract

The present application provides a three-dimensional flash memory device, such as a three-dimensional AND flash memory device. The three-dimensional flash memory device includes a substrate, a conductive layer, a three-dimensional flash memory array, and a through-array conductive structure. The substrate includes a memory cell region and a passive component region. The conductive layer is formed on the substrate and includes: a first circuit disposed in the memory cell region and a second circuit of a passive component disposed in the passive component region. The three-dimensional flash memory array is formed on the first circuit in the memory cell region. The through-array conductive structure is formed on each of the second circuits of the passive component disposed in the passive component region and is connected to at least one end of the second circuit.

Description

Technical Field

[0001] The present invention relates to a flash memory technology, and more particularly to a three-dimensional (3D) flash memory device. Background Art

[0002] Non-volatile memory (eg, flash memory) has become a widely used memory in personal computers and other electronic devices because it has the advantage that stored data will not disappear after power is turned off.

[0003] With the development of process technology, circuit design and programming algorithms, the size of memory devices has been greatly reduced to achieve higher integration. However, due to process limitations, the size of traditional planar memory devices can no longer meet the demand for size reduction.

[0004] Therefore, three-dimensional flash memory devices are currently being developed to address the aforementioned issues faced by planar memory. A three-dimensional (3D) flash memory device architecture comprises a 3D flash memory array and surrounding components. Furthermore, a 3D flash memory device also includes passive components, such as capacitors and resistors. These passive components are typically fabricated above the 3D flash memory array after fabrication.

[0005] However, the aforementioned passive components usually require additional photomask processes, which increases manufacturing costs and increases the probability of defect formation, thereby affecting chip yield.

[0006] Public content

[0007] The present invention provides a three-dimensional flash memory device that can integrate passive components and a three-dimensional flash memory array in the same layer to reduce photomask processes, thereby lowering manufacturing costs and the probability of defect formation.

[0008] The three-dimensional flash memory device of the present invention includes a substrate, a conductive layer, a three-dimensional flash memory array, and a through-array-via (TAV) conductive structure. The substrate includes a memory cell region and a passive component region. The conductive layer is formed on the substrate and includes a first circuit disposed in the memory cell region and a second circuit of passive components disposed in the passive component region. The three-dimensional flash memory array is formed on the first circuit in the memory cell region. The through-array conductive structure is formed on each of the second circuits in the passive component region and connects at least one end of the second circuit.

[0009] Another three-dimensional flash memory device of the present invention includes a substrate, a conductive layer, a three-dimensional flash memory array, and a through array conductive structure (TAV). The substrate includes a memory cell region and a passive component region. The conductive layer is formed on the substrate and includes: passive component circuits disposed in the passive component region and an etch stop layer disposed in the memory cell region. The three-dimensional flash memory array is formed on the etch stop layer in the memory cell region, wherein the three-dimensional flash memory array includes a stacked structure and a plurality of pillar structures. The stacked structure includes alternating multiple insulating layers and multiple gate layers. The pillar structures extend through the stacked structure. Each pillar structure includes an insulating pillar, a source pillar and a drain pillar located on either side of the insulating pillar and extending to the surface of the etch stop layer, a channel layer surrounding the source and drain pillars and contacting the source and drain pillars, and a charge storage layer. The charge storage layer surrounds the channel layer and contacts the multiple gate layers of the stacked structure. The through array conductive structures are formed on the circuits in the passive component region and connect at least one end of the circuits.

[0010] The three-dimensional NAND flash memory device of the present invention includes a substrate, a conductive layer, a three-dimensional inverted NAND flash memory array, and a through-array conductive structure (TAV). The substrate includes a memory cell region and a passive component region. The conductive layer is formed on the substrate and includes passive component circuits disposed in the passive component region and source lines disposed in the memory cell region. The three-dimensional NAND flash memory array is formed on the source lines in the memory cell region. The through-array conductive structures are formed on the circuits in the passive component region and connect at least one end of the circuits.

[0011] In order to make the above features and advantages of the present invention more clearly understood, the following embodiments are specifically described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory device according to a first embodiment of the present invention.

[0013] Figure 2A yes Figure 1 A top view schematic diagram of a passive component in FIG.

[0014] Figure 2B yes Figure 1 Schematic top view of another passive component in .

[0015] Figure 3A FIG. 1 is a cross-sectional schematic diagram of a 3D Flash memory device according to a second embodiment of the present invention.

[0016] Figure 3B yes Figure 3A Equivalent circuit diagram of a three-dimensional flash memory array.

[0017] Figure 4A yes Figure 3A A top view schematic diagram of a passive component in FIG.

[0018] Figure 4B yes Figure 3A Schematic top view of another passive component in .

[0019] Figures 5A to 5H FIG. 4 is a cross-sectional diagram illustrating the manufacturing process of the 3D AND gate flash memory device according to the second embodiment.

[0020] Figure 6 FIG. 1 is a cross-sectional diagram of a three-dimensional NAND flash memory device according to a third embodiment of the present invention.

[0021] Description of Reference Numerals

[0022] 100: Substrate

[0023] 102: Conductive layer

[0024] 104, 300: Three-dimensional flash memory array

[0025] 106, 620: Through array conductive structure

[0026] 110: Storage unit area

[0027] 112: First Line

[0028] 114, 304, 508, 604: laminated structure

[0029] 116, 306, 606: Column structure

[0030] 120: Passive components area

[0031] 122: Second Line

[0032] 130: Complementary Metal Oxide Semiconductor

[0033] 200, 400: Resistors

[0034] 202a, 202b, 206a, 206b: Ring structure

[0035] 204, 404: Capacitors

[0036] 302: Etching stop layer

[0037] 308, 502, 608, 618: Insulation layer

[0038] 310, 318, 610: Gate layer

[0039] 312: Insulation column

[0040] 314: Channel layer

[0041] 316, 614: Charge storage layer

[0042] 320, 622: Barrier layer

[0043] 402, 502a, 502b, 510: Opening

[0044] 500, 524: Internal connection

[0045] 504: Polysilicon layer

[0046] 506: Sacrificial layer

[0047] 512, 616: Insulation materials

[0048] 514: Incision

[0049] 516: Side opening

[0050] 518, ILD1, ILD2: dielectric layer

[0051] 520, 602: Central opening

[0052] 522: Through hole

[0053] 600: Three-dimensional NAND flash memory array

[0054] 612: Channel Column

[0055] BLn, BLn+1: bit lines

[0056] D: Drain column

[0057] d1, d2: diameter

[0058] PD: Passive Component

[0059] S: Source column

[0060] SL, SLn, SLn+1: Source lines

[0061] VC1: Vertical Channel

[0062] WLn, WLn+1: word lines DETAILED DESCRIPTION

[0063] The following provides many different embodiments or examples for implementing different features of the present invention. Moreover, these examples are merely illustrative and are not intended to limit the scope and application of the present invention. Furthermore, for clarity, the relative sizes (such as length, thickness, spacing, etc.) and relative positions of various regions or structural elements may be reduced or exaggerated. In addition, similar or identical element symbols are used in the various drawings to represent similar or identical elements or features.

[0064] Figure 1 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory device according to a first embodiment of the present invention.

[0065] Please refer to Figure 1 The three-dimensional flash memory device of this embodiment includes a substrate 100, a conductive layer 102, a three-dimensional flash memory array 104, and a through-array-via (TAV) 106. The substrate 100 includes a memory cell area 110 and a passive component area 120. The conductive layer 102 is formed on the substrate 100, and the conductive layer 102 includes: a first line 112 arranged in the memory cell area 110 and a second line 122 of a passive component PD arranged in the passive component area 120. The three-dimensional flash memory array 104 is formed on the first line 112 of the memory cell area 110. As for the through-array conductive structure 106, it is respectively formed on the second line 122 of the passive component area 120 and connected to at least one end of the second line 122, serving as a terminal connection of the passive component PD. The passive component PD is, for example, a capacitor or a resistor. Figure 2A and Figure 2B Since the passive device PD can be manufactured together with the circuits in the three-dimensional flash memory array 104, no additional photomask and process are required, thereby reducing manufacturing costs and the probability of defect formation.

[0066] exist Figure 2A In the embodiment, the passive element is a resistor 200, and the second line 122 is a serpentine line. The two ends of the second line 122 may be ring-type structures 202a and 202b, and Figure 1 The through array conductive structure 106 in the embodiment can pass through the central openings of the ring structures 202a and 202b to connect to the lower end element, for example Figure 1 CMOS (Complementary Metal Oxide Semiconductor) 130 in.

[0067] exist Figure 2BIn the embodiment, the passive element is a capacitor 204, and the second line 122 is a forked line, so one end of one second line 122 is a ring structure 206a, and one end of another second line 122 is a ring structure 206b, and Figure 1 The through array conductive structure 106 can pass through the central openings of the ring structures 206a and 206b to connect to the lower end element.

[0068] Please continue to refer to Figure 1 The three-dimensional flash memory array 104 may include a stacked structure 114 and a pillar structure 116. The stacked structure 114 may comprise, for example, alternating multiple insulating layers and multiple gate layers, while the pillar structure 116 extends through the stacked structure 114. The detailed structure of the pillar structure 116 may vary depending on the type of memory device. In one embodiment, the three-dimensional flash memory array 104 is a three-dimensional AND flash memory array, and the first wiring 112 is an etch stop layer at the bottom of the source and drain pillars in the three-dimensional AND flash memory array. In another embodiment, the three-dimensional flash memory array 104 is a three-dimensional NAND flash memory array, and the first wiring 112 is a source line (SL) in the three-dimensional NAND flash memory array. Detailed descriptions of different types of memory devices can be found in the second and third embodiments below. The through-array conductive structure 106 in this embodiment generally refers to a conductive pillar used to connect to each gate layer in the stacked structure 114 after the three-dimensional flash memory array 104 is formed. In addition, the 3D flash memory device of this embodiment may further include common interconnects and dielectric layers ILD1 and ILD2 , and based on process sequence considerations, a portion of the stacked structure 114 (not shown) may be retained in the passive device region 120 .

[0069] Figure 3A FIG2 is a cross-sectional schematic diagram of a 3D Flash memory device according to a second embodiment of the present invention, wherein the same reference numerals as those in the first embodiment are used to represent the same or similar parts and components. For details regarding the same or similar parts and components, reference may be made to the first embodiment and no further description is given.

[0070] Please refer to Figure 3AThe three-dimensional flash memory device of this embodiment includes a substrate 100, a conductive layer 102, a three-dimensional flash memory array 300, and a through-array conductive structure (TAV) 106. The conductive layer 102 includes an etch stop layer 302 disposed in the memory cell region 110 and a (second) line 122 of the passive device PD disposed in the passive device region 120. The three-dimensional flash memory array 300 is formed on the etch stop layer 302 in the memory cell region 110. The three-dimensional flash memory array 300 may include a stacked structure 304 and a plurality of pillar structures 306. The stacked structure 304 includes multiple layers of insulating layers 308 and multiple layers of gate layers 310 arranged alternately. The gate layers 310 serve as word lines WLn, WLn+1, etc. Charge storage layers 316 surround the gate layers 310. Each charge storage layer 316 is located between each gate layer 310 and the insulating layer 308. The pillar structures 306 extend through the stacked structure 304, and each pillar structure 306 includes an insulating pillar 312, a channel layer 314, a source pillar S, and a drain pillar D. The source pillar S and the drain pillar D are located on either side of the insulating pillar 312 and extend to the surface of the etch-stop layer 302. The channel layer 314 surrounds the source pillar S and the drain pillar D and contacts them. The charge storage layer 316 surrounds the channel layer 314 and contacts the gate layer 310 of the stacked structure 304. Since the source pillar S and the drain pillar D are also pillar-shaped structures, through holes must first be etched at the locations where the source pillar S and the drain pillar D are to be formed during the formation process. Therefore, an etch-stop layer 302 must be provided underneath the pillar structures 306. In this embodiment, the source column S and the drain column D are made of, for example, polysilicon or doped polysilicon. Since the etch stop layer 302 is formed together with the circuit 122, the etch stop layer 302 is also made of a conductive material, such as metal, polysilicon, or doped polysilicon. The insulating column 312 is made of, for example, silicon nitride, to prevent the source column S and the drain column D from bridging. The channel layer 314 is made of, for example, a semiconductor material, such as polysilicon or doped polysilicon. The charge storage layer 316 may be, for example, a multilayer film of oxide / nitride / oxide (ONO), or other dielectric material layers with storage functions may be used. In addition, the three-dimensional flash memory array 300 may further include another gate layer 318, which is disposed below the stacked structure 304 and above the etch stop layer 302.

[0071] Figure 3B yes Figure 3A FIG. 3 is an equivalent circuit diagram of a three-dimensional flash memory array 300 , in which only a portion of memory cells are shown to avoid unclearness in the drawing. Figure 3BThe memory cells in each layer (mth, m+1, etc.) are connected in parallel. In other words, the memory cells in each layer and row that share the same source column S are connected to the same source line SLn, SLn+1, etc.; the memory cells in each layer and row that share the same drain column D are connected to the same bit line BLn, BLn+1, etc.

[0072] Please continue to refer to Figure 3A The through array conductive structure 106 is formed on the line 122 of the passive component area 120 and connected to at least one end of the line 122, and the passive component PD, for example, is shown in FIG. Figure 4A The resistor is 400 or above Figure 4B Capacitor 404 in.

[0073] exist Figure 4A In the resistor 400 Figure 2A The resistor 200 is the same as Figure 4A The position of the through array conductive structure 106 is shown, that is, the through array conductive structure 106 passes through the central opening of the ring structures 202a and 202b and is connected to the lower end element (such as Figure 3A CMOS 130). The through array conductive structure 106 is, for example, a tungsten plug. Therefore, a barrier layer 320 (such as Ti / TiN) may be provided between the through array conductive structure 106 and the dielectric layer ILD2. Metal silicide (not shown) may also be formed at the interface between the through array conductive structure 106 and the ring structures 202a and 202b. As for the opening 402 represented by the dotted circle in the figure, it is Figure 3A The pillar structure 306 that penetrates the stacked structure 304 is formed simultaneously, and the detailed process will be described below. Figure 4B In the circuit, capacitor 404 and Figure 2B The capacitor 204 has the same interdigitated lines (122) as the capacitor 204, and the array conductive structure 106 passes through the central openings of the ring structures 206a and 206b to connect to the lower end element.

[0074] Figures 5A to 5H is a cross-sectional view of the manufacturing process of the three-dimensional AND gate flash memory device of the second embodiment, wherein Figure 3A The same reference numerals are used to represent the same or similar parts and components, and the relevant contents of the same or similar parts and components can also refer to Figure 3A The content will not be repeated here.

[0075] Please refer to Figure 5A , a CMOS 130 is formed on the substrate 100 , and then an interconnect structure, such as a dielectric layer ILD1 and an interconnect 500 , is formed.

[0076] Then, please refer to Figure 5BThe circuit 122 and the etch-stop layer 302 are simultaneously formed on the surface of the dielectric layer ILD1. For example, a photomask process is used to form openings 502a and 502b on the surface of the dielectric layer ILD1. Conductive material (e.g., polysilicon) is then filled into the openings. The surface of the etch-stop layer 302 in the memory cell region 110 can be lowered below the surface of the dielectric layer ILD1 by etching back. If a mask is first formed to protect the circuit 122, the circuit 122 will not be recessed. Otherwise, the surface of the circuit 122 may be lower than the surface of the dielectric layer ILD1.

[0077] Next, please refer to Figure 5C , an insulating layer 502, a polysilicon layer 504, and a stacked structure 508 consisting of an insulating layer 308 and a sacrificial layer 506 are sequentially formed on the ILD1, and then a plurality of vertical channel holes VC1 are simultaneously formed in the memory cell area 110 and a plurality of openings 510 are formed in the passive device area 120 through another photomask process, wherein the vertical channel VC1 is a pillar structure (such as Figure 3A The opening 510 is located at the portion 306 of the circuit 122, and exposes the contact of the circuit 122. Therefore, if one or both ends of the circuit 122 have a ring structure, the diameter d1 of the opening 510 will be correspondingly larger and larger than the diameter d2 of the vertical channel VC1 of the memory cell region 110.

[0078] Afterwards, please refer to Figure 5D First, a channel layer 314 is formed on the sidewalls of the vertical channel VC1. At this time, a channel layer 314 is also formed on the sidewalls of the opening 510. The channel layer 314 can be a conformal layer. Specifically, the channel layer 314 can conform to the shape of the vertical channel VC1 / opening 510 and cover the sidewalls thereof, while exposing a portion of the insulating layer 502. Next, an insulating material 512 can be filled into the vertical channel VC1 and the opening 510. The insulating material 512 can be made of a material similar to the insulating layer 502 and the insulating layer 308, such as silicon oxide.

[0079] Then, please refer to Figure 5E The insulating material 512 in the vertical channel VC1 of the memory cell region 110 may be removed first, and the source pillar S, the drain pillar D, and the insulating pillar 312 may be formed therein. For example, the insulating pillar 312 may be formed in the vertical channel VC1 first, and then through holes are etched at the locations where the source pillar S and the drain pillar D are to be formed to the surface of the etch-stop layer 302, and then the source pillar S and the drain pillar D are formed; or, an insulating material (not shown) may be formed in the vertical channel VC1 first, and then through holes are etched at the locations where the source pillar S and the drain pillar D are to be formed to the surface of the etch-stop layer 302, and then the source pillar S and the drain pillar D are formed, and then the insulating pillar 312 is formed between the source pillar S and the drain pillar D.

[0080] Afterwards, please refer to Figure 5F A slit 514 can be formed at the interface between the memory cell region 110 and the passive device region 120 to expose the insulating layer 308 and the sacrificial layer 506 of the stacked structure 508. The sacrificial layer 506 is then removed. The insulating layer 308 and the sacrificial layer 506 are preferably made of materials with a high etching selectivity, such as silicon oxide and silicon nitride. Thus, the exposed sacrificial layer 506 can be completely removed from the slit 514 by dry etching or wet etching to form a lateral opening 516. The lateral opening 516 exposes the insulating layer 308 and a portion of the channel layer 314. Next, a charge storage layer 316 can be formed in the lateral opening 516. The charge storage layer 316 can be, for example, a conformal layer. Specifically, the charge storage layer 316 can conform to the shape of the lateral opening 516 and cover the insulating layer 308 and the channel layer 314 exposed by the lateral opening 516. Then, a gate layer 310 is filled into the lateral opening 516 as a word line (WL). The material of the gate layer 310 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ), cobalt silicide (CoSi x ) etc. The gate layer 310 may be formed by, for example, chemical vapor deposition.

[0081] Afterwards, please refer to Figure 5G A dielectric layer 518 may be formed on the entire substrate 100 to fill the cutout 514 and planarize the surface of the entire structure. The material of the dielectric layer 518 may be, for example, a material similar to that of the insulating layer 502, such as silicon oxide. A through array conductive structure (TAV) 106 is then formed on the circuit 122 of the passive component region 120. The through array conductive structure 106 may pass through the central opening 520 of the ring-shaped structure of the circuit 122 to connect to the lower component, such as the CMOS 130. The steps for fabricating the through array conductive structure 106 include, for example, first forming a through hole 522 in the dielectric layer 512, the dielectric layer 518, the insulating layer 502, and the dielectric layer ILD1. A barrier layer 320 is then conformally formed on the surface of the through hole 522. A metal (e.g., tungsten) is then filled into the through hole 522 and a planarization process is performed to obtain the through array conductive structure 106. Furthermore, the through-array conductive structure 106 can be manufactured together with the through-array conductive structure (not shown) of the three-dimensional flash memory array 300 .

[0082] Then, please refer to Figure 5H A dielectric layer ILD2 may be formed on the entire substrate 100 and the surface of the entire structure may be planarized. Then, interconnects 524 may be fabricated to connect the source pillars S and drain pillars D in the three-dimensional flash memory array 300 and the conductive structure 106 through the array.

[0083] The above is an example of a manufacturing process for a three-dimensional flash memory device, but the present invention is not limited thereto. As long as the circuit 122 of the passive device PD is fabricated together with the etch stop layer 302 of the source pillars S and drain pillars D of the three-dimensional flash memory array 300, the fabrication and sequence of other film layers and structures can be adjusted or increased or decreased as needed.

[0084] Figure 6 FIG2 is a cross-sectional schematic diagram of a three-dimensional NAND flash memory device according to a third embodiment of the present invention, wherein the same reference numerals as those in the first embodiment are used to represent the same or similar parts and components. The relevant contents of the same or similar parts and components can also refer to those of the first embodiment and are not repeated here.

[0085] Please refer to Figure 6 The three-dimensional NAND flash memory device of this embodiment includes a substrate 100, a conductive layer 102, a three-dimensional NAND flash memory array 600, and a through-array conductive structure (TAV) 106. The substrate 100 includes a memory cell region 110 and a passive component region 120. The conductive layer 102 is formed on the substrate 100 and includes: a (second) circuit 122 of a passive component PD disposed in the passive component region 120 and a source line SL disposed in the memory cell region 110. The three-dimensional NAND flash memory array 600 is formed on the source line SL in the memory cell region 110. The through-array conductive structure 106 is formed on each circuit 122 in the passive component region 120 and connects the circuit 122 and the central opening 602 of the ring structure passing through the circuit 122 to a lower-end component, such as a CMOS 130.

[0086] Please continue to refer to Figure 6The three-dimensional NAND flash memory array 600 may include a stacked structure 604 and a pillar structure 606. The stacked structure 604 includes multiple insulating layers 608 and multiple gate layers 610 arranged alternately, wherein the gate layer 610 may be a metal layer, such as tungsten or other metal materials. The charge storage layer 614 surrounds the gate layer 610. Each charge storage layer 614 is located between each gate layer 610 and the insulating layer 608. The pillar structure 606 runs through the stacked structure 604. The pillar structure 606 may include an insulating material 616 formed as an insulating pillar as a central structure and a channel pillar 612 (e.g., polysilicon) surrounding the outer surface of the insulating pillar. The channel pillar 612 extends to the surface of the source line SL. The charge storage layer 614 surrounds a portion of the channel pillar 612 and contacts the gate layer 610 of the stacked structure 604. In addition, an insulating layer 618 may be disposed between the three-dimensional NAND flash memory array 600 and the source lines SL to prevent the source lines SL from interfering with the gate layer 610 of the stacked structure 604. The passive device PD can be described in the first or second embodiment above and will not be further described here. The through-array conductive structure 106 can be formed together with another through-array conductive structure 620 connected to the source lines SL, thus eliminating the need for additional photomasking processes. In this embodiment, the through-array conductive structure 106 is, for example, a tungsten plug. Therefore, a barrier layer 622 (e.g., Ti / TiN) may be disposed between the through-array conductive structure 106 and the dielectric layer ILD2.

[0087] In summary, the present invention utilizes process design to fabricate passive components (such as capacitors or resistors) together with the circuits in a three-dimensional flash memory array. This eliminates the need for additional photomasks and processes, thereby reducing manufacturing costs. Furthermore, compared to conventional methods that fabricate passive components separately, the probability of defect formation is also reduced.

[0088] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A three-dimensional flash memory device, comprising: A substrate including a memory cell region and a passive component region; a conductive layer formed on the substrate, the conductive layer comprising: a first circuit disposed in the memory cell region and a second circuit of a passive element disposed in the passive element region; a three-dimensional flash memory array formed on the first line of the memory cell region; and A plurality of through array conductive structures are respectively formed on the second circuit of the passive component disposed in the passive component area and connected to at least one end of the second circuit.

2. The 3D flash memory device of claim 1 , wherein the 3D flash memory array is a 3D AND flash memory array, and the first circuit is an etch stop layer at the bottom of source pillars and drain pillars in the 3D AND flash memory array. 3 . The 3D flash memory device according to claim 1 , wherein the 3D flash memory array is a 3D NAND flash memory array, and the first line is a source line in the 3D NAND flash memory array. The three-dimensional flash memory device of claim 1 , wherein the passive element comprises a capacitor or a resistor. 5 . The three-dimensional flash memory device according to claim 1 , wherein the second circuit of the passive element comprises a serpentine circuit or an interdigitated circuit. 6 . The three-dimensional flash memory device according to claim 1 , wherein the at least one end of the second line is a ring structure, and the through array conductive structure further passes through a central opening of the ring structure to connect to a lower element.

7. A three-dimensional flash memory device comprising: A substrate including a memory cell region and a passive component region; a conductive layer formed on the substrate, the conductive layer comprising: a circuit of a passive component disposed in the passive component region and an etch stop layer disposed in the memory cell region; A three-dimensional flash memory array is formed on the etch stop layer of the memory cell area, wherein the three-dimensional flash memory array comprises: A stacked structure comprising multiple insulating layers and multiple gate layers arranged alternately; and A plurality of column structures running through the stacked structure, each of the column structures comprising: Insulation columns; a source column and a drain column, located on both sides of the insulating column and extending to the surface of the etching stop layer; a channel layer surrounding the source column and the drain column and contacting the source column and the drain column; and a charge storage layer surrounding the channel layer and contacting the multi-layer gate layer of the stacked structure; and A plurality of through array conductive structures are respectively formed on the circuits in the passive component area and connected to at least one end of the circuits. 8 . The three-dimensional flash memory device of claim 7 , wherein the passive element comprises a capacitor or a resistor.

9. The three-dimensional flash memory device according to claim 7, wherein the at least one end of the circuit is a ring structure, and the through array conductive structure further passes through a central opening of the ring structure to connect to a lower element.

10. A three-dimensional NAND flash memory device, comprising: A substrate including a memory cell region and a passive component region; a conductive layer formed on the substrate, the conductive layer including: a circuit of a passive component disposed in the passive component region and a source line disposed in the memory cell region; A three-dimensional NAND flash memory array, wherein the source line is formed in the memory cell region; and A plurality of through array conductive structures are respectively formed on the circuits in the passive component area and connected to at least one end of the circuits.

Images