Speed governor and control method thereof

Abstract

The present application relates to a speed governor and a control method thereof. The speed governor includes: two control circuits, each of the control circuits includes two processors, and the four processors are connected to each other. The types of the two processors in the same control circuit are different; when a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to a first target processor in the slave control circuit, so that the first target processor and a second target processor are connected to form a target data transmission path to implement data transmission; wherein, the first target processor is a processor in the slave control circuit having the same type as the faulty processor, and the type of the second target processor is different from that of the first target processor. Using this speed governor can avoid the occurrence of system failures caused by single-point failures.

Description

Technical Field

[0001] This application relates to the technical field of nuclear power plant speed equipment control, and particularly to a governor and a control method for the governor. Background Art

[0002] In the design of the nuclear power plant process system, the feedwater flow control system controls the water demand of the entire secondary loop of the nuclear power plant. This feedwater flow control system adjusts the supply water flow and pressure based on the speed regulation of the steam-driven main feedwater pump to supply water to three steam generators, and at the same time eliminates the feedwater coupling phenomenon between the three steam generators, so as to ensure that the pressure difference between the feedwater header and the steam header of the steam generator is equal to a set value that changes with the unit load. Therefore, the speed regulation of the steam-driven main feedwater pump plays a crucial role in maintaining the stable water level of the steam generator and ensuring the safety of the unit.

[0003] Currently, most of the governors of steam turbines are controlled by electronic governors or single control systems, and the reliability of the system is low, and shutdowns are often caused by single-point failures. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a governor and a control method for the governor with a high degree of redundancy that can avoid single-point failures.

[0005] To achieve the above and other objects, one aspect of the present application provides a governor, including: two control circuits, each of the control circuits includes two processors, and the four processors are connected to each other, and the types of the two processors in the same control circuit are different;

[0006] When a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor and the second target processor are connected to form a target data transmission path to realize data transmission;

[0007] Wherein, the first target processor is the processor in the slave control circuit with the same type as the faulty processor, the second target processor is different from the first target processor in type, the main control circuit is one of the two control circuits, and the slave control circuit is the other of the two control circuits.

[0008] In one embodiment, when one processor in the main control circuit fails, the second target processor is the normal processor in the main control circuit; when both processors in the main control circuit fail, the second target processor is the processor in the slave control circuit.

[0009] In one embodiment, the processor to be diagnosed in the main control circuit sends inspection information to the other three processors respectively, so that the other three processors generate diagnostic information according to the inspection information;

[0010] The speed governor further includes:

[0011] An arbitration module, which is respectively connected to the four processors, and is used to determine whether the processor to be diagnosed is faulty according to the diagnostic information output by the other three processors, and output the diagnostic result of the processor to be diagnosed to the other three processors. The processor to be diagnosed is each processor in the main control circuit;

[0012] When the diagnostic result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

[0013] In one embodiment, the arbitration module includes four arbitration circuits. Each processor to be diagnosed is configured with one arbitration circuit, and each arbitration circuit is respectively connected to the other three processors. The other three processors are the processors other than the processor to be diagnosed configured by the arbitration circuit; The arbitration circuit includes: three arbitration units. Two input terminals of each arbitration unit are respectively connected to two of the other three processors correspondingly. Output terminals of each arbitration unit are respectively connected to the other three processors, and one input terminal of every two arbitration units is connected to the same processor. Each arbitration unit respectively includes: a NAND gate and an inverter, wherein,

[0014] Two input terminals of the NAND gate are respectively connected to two of the other three processors correspondingly, and an output terminal of the NAND gate is connected to an input terminal of the inverter;

[0015] An output terminal of the inverter is respectively connected to the other three processors.

[0016] In one embodiment, the speed governor further includes a first isolation circuit. Two processors in the main control circuit are respectively connected to two processors in the slave control circuit through the first isolation circuit; The first isolation circuit includes:

[0017] A first isolation unit, which is respectively connected to the first processor in the main control circuit and the first processor in the slave control circuit;

[0018] A second isolation unit, which is respectively connected to the first processor in the main control circuit and the second processor in the slave control circuit;

[0019] A third isolation unit, which is respectively connected to the second processor in the main control circuit and the first processor in the slave control circuit;

[0020] A fourth isolation unit, which is respectively connected to the second processor of the main control circuit and the second processor of the slave control circuit; wherein, the first processor of the main control circuit and the first processor of the slave control circuit are of the same type;

[0021] When the diagnosis result indicates that the processor to be diagnosed is a faulty processor, the other three processors respectively control the isolation units connected to the faulty processor according to the diagnosis result, so as to respectively disconnect the data transmission paths connected to the faulty processor.

[0022] In one embodiment, the speed governor further includes:

[0023] A first input acquisition circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to acquire and process the received analog input signal, and transmit the processed analog input signal to the target control circuit;

[0024] A first output processing circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to receive and process the analog output signal from the target control circuit;

[0025] A second input acquisition circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to acquire and process the received digital input signal, and transmit the processed digital input signal to the target control circuit;

[0026] A second output processing circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to receive and process the digital output signal from the target control circuit; wherein, the target control circuit is one of the two control circuits.

[0027] In one embodiment, the speed governor further includes:

[0028] A second isolation circuit, which is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the main control circuit;

[0029] A third isolation circuit, which is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the slave control circuit; wherein, the second processor of the main control circuit and the second processor of the slave control circuit are of the same type;

[0030] When the processor in the main control circuit is free of faults, the main control circuit controls the third isolation circuit to be in a locked state;

[0031] When the second processor in the main control circuit fails, the main control circuit controls the second isolation circuit to be in a locked state.

[0032] In one embodiment, the second input acquisition circuit includes a first opto-isolator for isolating the acquired switch input signal; the second output processing circuit includes a second opto-isolator for isolating the received switch output signal; the second isolation circuit includes:

[0033] A first magnetic isolator is respectively connected to the first input acquisition circuit and the second processor of the main control circuit;

[0034] A second magnetic isolator is respectively connected to the first output processing circuit and the second processor of the main control circuit;

[0035] A third magnetic isolator is respectively connected to the first opto-isolator, the second opto-isolator, and the second processor of the main control circuit;

[0036] The third isolation circuit includes:

[0037] A fourth magnetic isolator is respectively connected to the first input acquisition circuit and the second processor of the slave control circuit;

[0038] A fifth magnetic isolator is respectively connected to the first output processing circuit and the second processor of the slave control circuit;

[0039] A sixth magnetic isolator is respectively connected to the first opto-isolator, the second opto-isolator, and the second processor of the slave control circuit.

[0040] In one embodiment, the speed governor further includes:

[0041] A power supply module is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and each control circuit for providing a power supply voltage;

[0042] Wherein, the power supply module includes:

[0043] An inverter unit for receiving an external power supply voltage and performing a voltage drop process on the power supply voltage to obtain a voltage-drop voltage;

[0044] A first system power supply unit is connected to the inverter unit for rectifying, regulating voltage, and filtering the voltage-drop voltage to obtain a first power supply voltage and outputting it to the main control circuit;

[0045] The second system power supply unit is connected to the inverter unit and is used to rectify, regulate the voltage, and filter the voltage drop voltage to obtain a second power supply voltage, and output it to the slave control circuit;

[0046] The interface power supply unit is connected to the inverter unit and is used to rectify, regulate the voltage, and filter the voltage drop voltage to obtain a third power supply voltage, and output it to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, and the second output processing circuit.

[0047] In one embodiment, when a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor is connected to the second target processor in the main control circuit through another processor in the slave control circuit to form a target data transmission path to realize data transmission.

[0048] In one embodiment, the speed governor further includes:

[0049] The verification module is respectively connected to the four processors and is used to judge whether the processor to be diagnosed is faulty and output the diagnosis result of the processor to be diagnosed to the other three processors, and the processor to be diagnosed is each processor in the main control circuit;

[0050] When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

[0051] On the other hand, the present application provides a control method for a speed governor, which is applied to the speed governor described in any one of the above embodiments. The method includes:

[0052] Obtain a temperature value according to the signal to be started to judge the start state;

[0053] If it is in a hot start state, control the speed of the steam turbine to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to a first preset speed;

[0054] If it is in a cold start state, control the speed of the steam turbine to increase at a second preset rate until the real-time speed of the steam turbine is greater than or equal to a second preset speed and then enter a warm-up state. After a preset time, control the speed of the steam turbine to continue to increase at the second preset rate until the real-time speed of the steam turbine is greater than or equal to a third preset speed, and then control the speed of the steam turbine to increase at the first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed;

[0055] Adjust the speed of the steam turbine according to the set speed according to the start completion signal.

[0056] For the speed governor and the control method of the speed governor in the above embodiments, data transmission is realized by two different types of processors in the main control circuit. Through the setting of the slave control circuit, when a processor in the main control circuit fails, a processor of the same type as the faulty processor in the slave control circuit is used for replacement, and the data that the faulty processor is about to process is continued to be processed, and data transmission is realized with the fault-free processors in the main control circuit. If all the processors in the main control circuit fail, data processing and transmission are performed by the two processors in the slave control circuit. By designing the dual control circuit, the situation of system failure caused by single-point failure is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.

[0058] Figure 1 It is the structural block diagram of the speed governor provided in the first embodiment of the present application;

[0059] Figure 2 It is the structural block diagram of the speed governor provided in the second embodiment of the present application;

[0060] Figure 3 It is the schematic structural diagram of the first arbitration circuit provided in an embodiment of the present application;

[0061] Figure 4 It is the structural block diagram of the speed governor provided in the third embodiment of the present application;

[0062] Figure 5 It is the structural block diagram of the speed governor provided in the fourth embodiment of the present application;

[0063] Figure 6 It is the schematic diagram of the principle of the first input acquisition circuit provided in an embodiment of the present application;

[0064] Figure 7 It is the schematic diagram of the principle of the first output processing circuit provided in an embodiment of the present application;

[0065] Figure 8 It is the schematic diagram of the principle of the second input acquisition circuit provided in an embodiment of the present application;

[0066] Figure 9 It is the schematic diagram of the principle of the second output processing circuit provided in an embodiment of the present application;

[0067] Figure 10It is the structural block diagram of the speed governor provided in the fifth embodiment of the present application;

[0068] Figure 11 It is the structural block diagram of the power supply module provided in an embodiment of the present application;

[0069] Figure 12 It is the structural block diagram of the speed governor provided in the sixth embodiment of the present application

[0070] Figure 13 It is the schematic flowchart of the control method of the speed governor provided in an embodiment of the present application.

[0071] Explanation of reference numerals:

[0072] 10. Speed governor; 11. Main control circuit; 111. First processor; 112. Second processor; 12. Slave control circuit; 121. Third processor; 122. Fourth processor; 13. Arbitration module; 131. Arbitration circuit; 1311. First arbitration unit; 1312. Second arbitration unit; 1313. Third arbitration unit; 132. NAND gate; 133. Inverter; 14. First isolation circuit; 141. First isolation unit; 142. Second isolation unit; 143. Third isolation unit; 144. Fourth isolation unit; 15. First input acquisition circuit; 151. Analog-to-digital converter; 152. First field effect transistor; 153. Voltage dividing circuit; 154. First operational amplifier; 155. Voltage follower; 16. First output processing circuit; 161. Digital-to-analog converter; 162. Second operational amplifier; 163. Third operational amplifier; 164. Fourth operational amplifier; 165. Fifth operational amplifier; 166. Second field effect transistor; 167. Third field effect transistor; 17. Second input acquisition circuit; 171. First opto-isolator; 18. Second output processing circuit; 181. Second opto-isolator; 19. Second isolation circuit; 191. First magnetic isolator; 192. Second magnetic isolator; 193. Third magnetic isolator; 20. Third isolation circuit; 201. Fourth magnetic isolator; 202. Fifth magnetic isolator; 203. Sixth magnetic isolator; 21. Power supply module; 211. Inverter unit; 212. First system power supply unit; 213. Second system power supply unit; 214. Interface power supply unit. Detailed implementation manners

[0073] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0076] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or connected to the other element through an intermediate element. In addition, in the following embodiments, "connection", if there is a transmission of electrical signals or data between the connected objects, should be understood as "electrical connection", "communication connection", etc.

[0077] As Figure 1 , in one embodiment, a speed governor 10 is provided. The speed governor 10 includes two control circuits. Each control circuit includes two processors. The four processors are connected to each other, and the types of the two processors in the same control circuit are different.

[0078] The types of the two processors in the main control circuit 11 are different, and the types of the two processors in the slave control circuit 12 are different. The two processors in the slave control circuit 12 respectively correspond to the two processors in the main control circuit 11 with the same type. For example, the first processor in the main control circuit 11 is of the same type as the first processor in the slave control circuit 12, and the second processor in the main control circuit 11 is of the same type as the second processor in the slave control circuit 12. The processor includes at least a central processing unit (CPU) and a field programmable gate array (FPGA).

[0079] Exemplarily, the two processors in the main control circuit 11 can be respectively used as the first processor 111 and the second processor 112 of the speed governor 10, and the two processors in the slave control circuit that the first CPU is connected to the first FPGA, the second CPU, and the second FPGA respectively; the first FPGA is connected to the second CPU and the second FPGA respectively; the second CPU is connected to the second FPGA.

[0080] When the system starts to operate, the main control circuit 11 includes a target data transmission path, that is, the first CPU and the first FPGA are connected to form a target data transmission path to realize data transmission. The slave control circuit 12 can also include a target data transmission path, that is, the second CPU and the second FPGA are connected to form a target data transmission path to realize data transmission.

[0081] Optionally, when a processor in the main control circuit 11 fails, the faulty processor in the main control circuit 11 sends synchronization information to the first target processor in the slave control circuit 12, so that the first target processor is connected to the second target processor in the main control circuit 11 through another processor in the slave control circuit 12 to form a target data transmission path to realize data transmission.

[0082] Taking the main control circuit 11 as the target data transmission path as an example, when a processor in the main control circuit 11 fails, the faulty processor in the main control circuit 11 sends synchronization information to the first target processor in the slave control circuit 12, so that the first target processor is connected to the second target processor to form a target data transmission path to realize data transmission.

[0083] Among them, the first target processor is the processor in the slave control circuit 12 with the same type as the faulty processor, and the second target processor is of a different type from the first target processor. The synchronization information is information that can characterize the data processed or transmitted by the faulty processor before the failure. Among the four processors, since only synchronization information needs to be transmitted between two of the same type, serial communication is used for communication; since data needs to be transmitted between two processors of different types and the amount of data transmitted is large, in order to ensure the data transmission efficiency, parallel communication is used for communication.

[0084] Optionally, when a processor in the main control circuit 11 fails, the second target processor is the normal processor in the main control circuit 11. For example, when the first CPU fails, the first target processor is the second CPU, and the second target processor is the first FPGA. The first CPU sends synchronization information to the second CPU in the slave control circuit 12, so that the second CPU is connected to the first FPGA to form a target data transmission path to realize data transmission; when the first FPGA fails, the first target processor is the second FPGA, and the second target processor is the first CPU. The first FPGA sends synchronization information to the second FPGA in the slave control circuit 12, so that the first CPU is connected to the second FPGA to form a target data transmission path to realize data transmission.

[0085] Optionally, when both processors in the main control circuit 11 fail, the second target processor is the processor in the slave control circuit 12. For example, when both the first CPU and the first FPGA fail, the first CPU sends synchronization information to the second CPU, and the first FPGA sends synchronization information to the second FPGA, so that the second CPU and the second FPGA are connected to form a target data transmission path to achieve data transmission.

[0086] In the above speed governor 10, two different types of processors in the main control circuit 11 achieve data transmission through parallel port communication. Through the setting of the slave control circuit 12, when a processor in the main control circuit 11 fails, the faulty processor transmits synchronization information to the processor of the same type as the faulty processor in the slave control circuit 12 through serial communication, and uses the processor of the same type as the faulty processor in the slave control circuit 12 to replace it, and continues to process the data that the faulty processor is about to process, and realizes data transmission with the non-faulty processors in the main control circuit 11. If all the processors in the main control circuit 11 fail, data processing and transmission are performed by the two processors in the slave control circuit 12. Through the design of the dual control circuit, the situation of system failure caused by single point failure is avoided.

[0087] Such as Figure 2 , in an embodiment, the speed governor 10 further includes an arbitration module 13, which is respectively connected to the four processors. The blanking module includes four arbitration circuits, each of the processors to be diagnosed is configured with one of the arbitration circuits, and each of the arbitration circuits is respectively connected to the other three processors, and the other three processors are the processors other than the processor to be diagnosed configured by the arbitration circuit. The arbitration circuit includes three arbitration units, two input terminals of each arbitration unit are respectively connected to two of the other three processors correspondingly, output terminals of each arbitration unit are respectively connected to the other three processors, and one input terminal of every two arbitration units is connected to the same processor. Each of the arbitration units respectively includes a NAND gate 132 and an inverter 133.

[0088] Taking the first processor 111 as the processor to be diagnosed for illustration, the first processor 111 in the main control circuit 11 respectively sends inspection information to the second processor 112, the third processor 121, and the fourth processor 122, and the second processor 112, the third processor 121, and the fourth processor 122 generate diagnostic information according to the inspection information. The arbitration circuit 131 configured by the first processor 111 is as Figure 3As shown in the figure, if the diagnostic results of the other three processors for the first processor 111 are faulty, a high level is output. The NAND gates 132 in the first arbitration unit 1311 are respectively connected to the second processor 112 and the fourth processor 122. The NAND gates 132 in the second arbitration unit 1312 are respectively connected to the second processor 112 and the third processor 121. The NAND gates 132 in the third arbitration unit 1313 are respectively connected to the third processor 121 and the fourth processor 122. The three arbitration circuits 131 use a two-out-of-three method to determine whether the first processor 111 is faulty. For example, if the second processor 112, the third processor 121, and the fourth processor 122 all judge normal and output a low level, then in the first arbitration circuit 131, the second arbitration circuit 131, and the third arbitration circuit 131, the NAND gate 132 outputs a high level, the inverter 133 outputs a low level, and finally the first arbitration circuit 131 outputs a low level, indicating that the first processor 111 is not faulty. If the second processor 112 and the third processor 121 judge normal and output a low level, and the fourth processor 122 judges faulty and outputs a high level, then in the first arbitration circuit 131, the second arbitration circuit 131, and the third arbitration circuit 131, the NAND gate 132 outputs a high level, the inverter 133 outputs a low level, and finally the first arbitration circuit 131 outputs a low level, indicating that the first processor 111 is not faulty. If the second processor 112 and the third processor 121 judge faulty and output a high level, and the fourth processor 122 judges normal and outputs a low level, then in the first arbitration circuit 131 and the third arbitration circuit 131, the NAND gate 132 outputs a high level, the inverter 133 outputs a low level, but in the second arbitration circuit 131, the NAND gate 132 outputs a low level, the inverter 133 outputs a high level, and finally the first arbitration circuit 131 outputs a high level, indicating that the first processor 111 is faulty. That is, among the other three processors except the processor to be diagnosed, if two of them judge the processor to be diagnosed as faulty, then the processor to be diagnosed is faulty.

[0089] After the fault detection, the arbitration module 13 outputs the diagnostic result of the first processor 111 to the second processor 112, the third processor 121, and the fourth processor 122. If the diagnostic result is that the first processor 111 is faulty, then the third processor 121 is the first target processor, the second processor 112 is the second target processor, the first processor 111 sends synchronization information to the third processor 121, and the third processor 121 connects to the second processor 112 according to the synchronization information to form a target data transmission path to realize data transmission.

[0090] When the main control circuit 11 includes a target data transmission path, both the first processor 111 and the second processor 112 can be used as the processors to be diagnosed; when the slave control circuit 12 includes a target data transmission path, both the third processor 121 and the fourth processor 122 can be used as the processors to be diagnosed.

[0091] Optionally, the speed governor 10 further includes a verification module for determining whether the processor to be diagnosed is faulty and outputting the diagnosis result of the processor to be diagnosed to the other three processors, where the processor to be diagnosed is each processor in the main control circuit 11; when the diagnosis result indicates that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

[0092] For the above-mentioned speed governor 10, the processor to be diagnosed sends verification information to the other three processors, and the other three processors determine whether the processor to be diagnosed is faulty according to the verification information, and transmit the diagnosis information to the arbitration module 13 to generate a diagnosis result according to the two-out-of-three method. The two-out-of-three method can prevent the processors that are originally faulty among the other three processors from confusing the diagnosis result of the processor to be diagnosed. If the processor to be diagnosed is faulty, synchronization information is sent to the processors of the same type in the slave control circuit 12, so that the first target processor and the second target processor form a new target data transmission path, thereby avoiding the situation where the system cannot operate due to the single-point failure of the processor to be diagnosed.

[0093] As Figure 4 , in one embodiment, the speed governor 10 further includes a first isolation circuit 14. Two processors in the main control circuit 11 are respectively connected to two processors in the slave control circuit 12 through the first isolation circuit 14. The first isolation circuit 14 includes a first isolation unit 141, a second isolation unit 142, a third isolation unit 143, and a fourth isolation unit 144. The first isolation unit 141 is respectively connected to the first processor in the main control circuit 11 and the first processor in the slave control circuit 12; the second isolation unit 142 is respectively connected to the first processor in the main control circuit 11 and the second processor in the slave control circuit 12; the third isolation unit 143 is respectively connected to the second processor in the main control circuit 11 and the first processor in the slave control circuit 12; the fourth isolation unit 144 is respectively connected to the second processor in the main control circuit 11 and the second processor in the slave control circuit 12; wherein, the first processor in the main control circuit 11 and the first processor in the slave control circuit 12 are of the same type. The first isolation unit 141, the second isolation unit 142, the third isolation unit 143, and the fourth isolation unit 144 each include at least one magnetic isolator.

[0094] Exemplarily, the first processor 111 is connected to the third processor 121 via the first isolation unit 141, and the first processor 111 is connected to the fourth processor 122 via the second isolation unit 142. The second processor 112 is connected to the third processor 121 via the third isolation unit 143, and the second processor 112 is connected to the fourth processor 122 via the fourth isolation unit 144. For example, when the first processor 111 is the processor to be diagnosed, if the diagnosis result is that the first processor 111 is faulty, then after receiving the synchronization information, the third processor 121 controls the first isolation unit 141 to disconnect according to the diagnosis result, and the fourth processor 122 controls the second isolation unit 142 to disconnect according to the diagnosis result. When the second processor 112 is the processor to be diagnosed, if the diagnosis result is that the second processor 112 is faulty, then after receiving the synchronization information, the fourth processor 122 controls the fourth isolation unit 144 to disconnect according to the diagnosis result, and the third processor 121 controls the third isolation unit 143 to disconnect according to the diagnosis result.

[0095] Optionally, the connection path between the first processor 111 and the fourth processor 122 and the connection path between the second processor 112 and the third processor 121 may include the same magnetic isolator; the magnetic isolators in the connection path between the first processor 111 and the fourth processor 122 and the magnetic isolators in the connection path between the second processor 112 and the third processor 121 may be different, which is not limited herein.

[0096] The above speed governor 10 avoids the system being confused by the error information output by the faulty processor by cutting off the output of the isolation unit that disconnects the connection between the other three processors and the faulty processor to be diagnosed.

[0097] Such as Figure 5 , in one embodiment, the speed governor 10 further includes a first input acquisition circuit 15, a first output processing circuit 16, a second input acquisition circuit 17, a second output processing circuit 18, a second isolation circuit 19, and a third isolation circuit 20.

[0098] The first input acquisition circuit 15 is connected to the main control unit via the first magnetic isolator 191 in the second isolation circuit 19 and is connected to the slave control unit via the fourth magnetic isolator 201 in the third isolation circuit 20, and is used for acquiring and processing the received analog input signal and transmitting the processed analog input signal to the target control circuit. The circuit schematic diagram of the first input acquisition circuit 15 is as Figure 6As shown, the first input acquisition circuit 15 includes an analog-to-digital converter 151, and the analog input signal includes a current signal. The current signal input from the printed circuit board passes through the first field-effect transistor 152 and then forms a voltage signal through the voltage division circuit 153. After being conditioned by the first operational amplifier 154, the voltage signal passes through a voltage follower 155 to enhance the robustness and load capacity of the voltage signal for subsequent sampling. Finally, it enters the analog-to-digital converter 151 for analog-to-digital conversion to generate a digital signal, and the digital signal is transmitted to the target control circuit through the SPI interface of the analog-to-digital converter 151.

[0099] Exemplarily, when the main control circuit 11 is the target data transmission path, if the first processor 111 and the second processor 112 are fault-free, the first magnetic isolator 191 is not locked and the fourth magnetic isolator 201 is in the locked state. The digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 through the SPI bus for processing; if only the first processor 111 fails, the third processor 121 is used as the first target processor and the second processor 112 is used as the second target processor, then the first magnetic isolator 191 is not locked and the fourth magnetic isolator 201 is in the locked state. The digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 through the SPI bus for processing; if only the second processor 112 fails, the fourth processor 122 is used as the first target processor and the first processor 111 is used as the second target processor, then the fourth magnetic isolator 201 is not locked and the first magnetic isolator 191 is locked. The digital signal output by the first input acquisition circuit 15 is transmitted to the fourth processor 122 through the SPI bus for processing; if both the first processor 111 and the second processor 112 fail, then the fourth magnetic isolator 201 is not locked and the first magnetic isolator 191 is locked. The digital signal output by the first input acquisition circuit 15 is transmitted to the fourth processor 122 through the SPI bus for processing.

[0100] The first output processing circuit 16 is connected to the main control unit through the second magnetic isolator 192 in the second isolation circuit 19 and is connected to the slave control unit through the fifth magnetic isolator 202 in the third isolation circuit 20, and is used to receive and process the analog output signal from the target control circuit. The circuit schematic diagram of the first output processing circuit 16 is as Figure 7As shown in the figure, the first output circuit includes a digital-to-analog converter 161. The digital-to-analog conversion instruction generated by the second processor 112 of the target control circuit is sent to the digital-to-analog converter 161 via the SPI bus to form an initial signal for digital-to-analog conversion. The initial signal is processed by the second operational amplifier 162 to generate a common voltage for current and voltage output. A part of the common voltage is processed by the fourth operational amplifier 164, the fifth operational amplifier 165, the second field-effect transistor 166 and the third field-effect transistor 167 to generate a standard current signal, and another part of the common voltage is processed by the third operational amplifier 163 to generate a standard voltage signal. The standard current signal and the standard voltage signal are output as analog output signals output by the first output processing circuit 16 from the wiring terminal of the printed circuit board.

[0101] Exemplarily, when the main control circuit 11 is the target data transmission path, if the first processor 111 and the second processor 112 are fault-free, the second magnetic isolator 192 is not locked and the fifth magnetic isolator 202 is in the locked state. The digital-to-analog conversion instruction output by the second processor 112 is input to the first output processing circuit 16 via the SPI bus; if only the first processor 111 is faulty, the third processor 121 is used as the first target processor and the second processor 112 is used as the second target processor, then the second magnetic isolator 192 is not locked and the fifth magnetic isolator 202 is in the locked state. The digital-to-analog conversion instruction output by the second processor 112 is input to the first output processing circuit 16 via the SPI bus; if only the second processor 112 is faulty, the fourth processor 122 is used as the first target processor and the first processor 111 is used as the second target processor, then the fifth magnetic isolator 202 is not locked and the second magnetic isolator 192 is locked. The digital-to-analog conversion instruction output by the fourth processor 122 is input to the first output processing circuit 16 via the SPI bus; if both the first processor 111 and the second processor 112 are faulty, then the fifth magnetic isolator 202 is not locked and the second magnetic isolator 192 is locked. The digital-to-analog conversion instruction output by the fourth processor 122 is input to the first output processing circuit 16 via the SPI bus.

[0102] The second input acquisition circuit 17 is connected to the main control unit via the third magnetic isolator 193 in the second isolation circuit 19 and to the slave control circuit 12 via the sixth magnetic isolator 203 in the third isolation circuit 20. It is used to collect and process the received digital input signals and transmit the processed digital input signals to the target control circuit. The circuit schematic diagram of the second input acquisition circuit 17 is as Figure 8 shown, and the second input acquisition circuit 17 includes a first opto-isolator 171.

[0103] The second output processing circuit 18 is connected to the main control unit via the third magnetic isolator 193 in the second isolation circuit 19 and is connected to the slave control circuit 12 via the sixth magnetic isolator 203 in the third isolation circuit 20, and is configured to receive and process the digital output signal from the target control circuit; wherein, the target control circuit is one of the two control circuits. The circuit schematic diagram of the second output processing circuit 18 is as shown in Figure 9 shown, and the second input acquisition circuit 17 includes a second opto-isolator 181.

[0104] For the above speed governor 10, when the first processor 111 and the second processor 112 serve as the target data transmission path, the first processor 111 outputs a low level to control the locking of the third isolation unit 143, disabling the magnetic isolator in the third isolation unit 143 from outputting, so that the first input acquisition circuit 15, the first output processing circuit 16 and the second processor 112 perform information interaction; when the first processor 111 and the fourth processor 122 serve as the target data transmission path, the first processor 111 outputs a low level to control the locking of the second isolation unit 142, disabling the magnetic isolator in the second isolation unit 142 from outputting, so that the first input acquisition circuit 15, the first output processing circuit 16 and the fourth processor 122 perform information interaction. By controlling the second isolation unit 142 and the third isolation unit 143, the SPI bus permission conflict is avoided.

[0105] As shown in Figure 10 and Figure 11 , in one embodiment, the speed governor 10 further includes a power supply module 21, and the power supply module 21 includes an inverter unit 211, a first system power supply unit 212, a second system power supply unit 213 and an interface power supply unit 214. The schematic diagram of the power supply module 21 is as shown in Figure 11 shown, the inverter unit 211 is configured to receive an external power supply voltage and perform a voltage drop process on the power supply voltage to obtain a voltage drop voltage; the first system power supply unit 212 is connected to the inverter unit 211 and is configured to rectify, regulate and filter the voltage drop voltage to obtain a first power supply voltage and output it to the main control circuit 11; the second system power supply unit 213 is connected to the inverter unit 211 and is configured to rectify, regulate and filter the voltage drop voltage to obtain a second power supply voltage and output it to the slave control circuit 12; the interface power supply unit 214 is connected to the inverter unit 211 and is configured to rectify, regulate and filter the voltage drop voltage to obtain a third power supply voltage and output it to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18.

[0106] The above speed governor 10 supplies power to the main control circuit 11 through the first system power supply, supplies power to the slave control circuit 12 through the second system power supply, and the interface power supply unit 214 supplies power to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18, realizing redundancy of the system working power supply and the interface power supply. When one of the system power supplies fails, the other system power supply supplies power to the control circuit that has not failed, enabling the non-failed control circuit to serve as the target transmission path to achieve data transmission.

[0107] For example Figure 12 , in an embodiment, the speed governor 10 further includes a Human Machine Interface (HMI). The main control circuit 11 includes a first CPU and a first FPGA, and the slave control circuit 12 includes a second CPU and a second FPGA. The first input acquisition circuit 15 includes an analog to digital converter (ADC) 151, and the first output processing circuit 16 includes a digital-to-analog conversion (DAC) 161. The second input acquisition circuit 17 includes a first opto-isolator 171 for primary isolation, and the second output processing circuit 18 includes a second opto-isolator 181 for primary isolation. The first system power supply unit 212 supplies power to the first CPU and the first FPGA, the second system power supply unit 213 supplies power to the second CPU and the second FPGA, and the interface power supply unit 214 supplies power to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18. Since different system power supplies are used between the first CPU and the second CPU and the second FPGA, the first CPU is connected to the second CPU and the first FPGA through a magnetic isolator; since different system power supplies are used between the first FPGA and the second CPU and the second FPGA, the first FPGA is connected to the second CPU and the second FPGA through a magnetic isolator; since the same system power supply is used between the first CPU and the first FPGA, and between the second CPU and the second FPGA, the first CPU is directly connected to the first FPGA, and the second CPU is directly connected to the second FPGA.

[0108] Taking the system power-on and selecting the main control circuit 11 as the target control circuit as an example for illustration, the first CPU sends verification information to the second CPU, the first FPGA, and the second FPGA, and the arbitration circuit diagnoses whether the first CPU is faulty by taking two out of three from the diagnostic information generated by the other three; the first FPGA sends verification information to the first CPU, the second CPU, and the second FPGA, and the arbitration circuit diagnoses whether the first FPGA is faulty by taking two out of three from the diagnostic information generated by the other three.

[0109] If the first CPU fails, the first CPU sends synchronization information to the second CPU through serial communication, so that the second CPU can transmit target data with the first FPGA through parallel port communication; if the first FPGA fails, the first FPGA sends synchronization information to the second FPGA through serial communication, so that the second FPGA can transmit target data with the first CPU through parallel port communication; if both the first CPU and the first FPGA are not faulty, the first CPU outputs a low level to control the third isolation circuit 20 to lock, thereby avoiding bus manipulation authority conflicts, and transmitting target data between the first CPU and the first FPGA; if both the first CPU and the first FPGA fail, the first CPU sends synchronization information to the second CPU through serial communication, and the first FPGA sends synchronization information to the second FPGA through serial communication, so that the second CPU can transmit target data with the second FPGA through parallel port communication.

[0110] In the speed regulator 10, two different types of processors in the main control circuit 11 implement data transmission. Through the configuration of the slave control circuit 12, when a processor in the main control circuit 11 fails, a processor of the same type as the failed processor in the slave control circuit 12 replaces it and continues to process the data that the failed processor was about to process, while implementing data transmission with the healthy processor in the main control circuit 11. If both processors in the main control circuit 11 fail, data processing and transmission are performed by the two processors in the slave control circuit 12. The dual control circuit design prevents single-point failures from causing system failures.

[0111] like Figure 13 In one embodiment, a control method for a speed regulator is provided, which is applied to the speed regulator in any of the above embodiments, and the method includes:

[0112] Step S100: obtaining a temperature value according to a signal to be started to determine a start-up state.

[0113] The waiting-to-start signal is a signal that instructs the speed regulator to start operating, the temperature value is the external ambient temperature, and the start state includes hot start state and cold start state. When the temperature value is greater than or equal to the preset temperature value, it is the hot start state; when the temperature value is less than the preset temperature value, it is the cold start state.

[0114] When the speed regulator is powered on, it first performs a self-test and determines whether the current state meets the state requirements. If so, it obtains the temperature value according to the start-up signal to determine the start-up state of the speed regulator.

[0115] Step S210: If it is a hot start state, the speed of the steam turbine is controlled to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed.

[0116] Among them, the first preset rate can be 500 rpm / min, and the first preset rotational speed can be 4440 rpm.

[0117] After it is judged as the hot start state, the governor outputs an opening signal to control the opening of the regulating valve of the steam turbine so as to control the rotational speed of the steam turbine, and controls the rotational speed of the steam turbine to increase by 500 rpm per minute until the rotational speed of the steam turbine reaches 4440 rpm, and the start is completed.

[0118] Step S220: If it is in the cold start state, control the rotational speed of the steam turbine to increase at a second preset rate until the real-time rotational speed of the steam turbine is greater than or equal to a second preset rotational speed and then enter the warm-up state. After a preset time, control the rotational speed of the steam turbine to continue to increase at a third preset rate until the real-time rotational speed of the steam turbine is greater than or equal to a third preset rotational speed, and then control the rotational speed of the steam turbine to increase at a first preset rate until the real-time rotational speed of the steam turbine is greater than or equal to a first preset rotational speed.

[0119] Among them, the second preset rate can be 125 rpm / min, the second preset rotational speed can be 700 rpm, the third preset rotational speed can be 3100 rpm, and the preset time can be 10 min.

[0120] After it is judged as the cold start state, the governor outputs an opening signal to control the opening of the regulating valve of the steam turbine so as to control the rotational speed of the steam turbine, and controls the rotational speed of the steam turbine to increase by 125 rpm per minute until the rotational speed of the steam turbine reaches 700 rpm. Then the governor enters the warm-up state. After 10 minutes, the governor continues to control the rotational speed of the steam turbine to increase by 125 rpm per minute until the rotational speed of the steam turbine reaches 3100 rpm. Then the governor controls the rotational speed of the steam turbine to increase by 500 rpm per minute until the rotational speed of the steam turbine reaches 4440 rpm, and the start is completed.

[0121] Step S300: According to the start completion signal, adjust the rotational speed of the steam turbine according to the set rotational speed.

[0122] Among them, the set rotational speed is the rotation speed set artificially.

[0123] The control method of the above governor realizes data transmission through two processors of different types in the main control circuit. Through the setting of the slave control circuit, when a processor in the main control circuit fails, a processor of the same type as the faulty processor in the slave control circuit is used for replacement, and the data to be processed by the faulty processor is continued to be processed, and data transmission is realized with the fault-free processors in the main control circuit. If all the processors in the main control circuit fail, data processing and transmission are carried out through the two processors of the slave control circuit. The design of the dual control circuit avoids the occurrence of system failures caused by single-point failures. The governor can normally input and output signals to control the speed regulation of the steam turbine, and change the speed regulation method according to the temperature to better control the speed regulation of the steam turbine.

[0124] It should be understood that although the steps in the flowchart are sequentially shown according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0125] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0126] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0127] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A governor, characterized in that, Including: Two control circuits, each of the control circuits includes two processors, and the four processors are connected to each other, and the types of the two processors in the same control circuit are different; When a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor and the second target processor are connected to form a target data transmission path to realize data transmission; Wherein, the first target processor is a processor in the slave control circuit with the same type as the faulty processor, the second target processor is different from the first target processor in type, the main control circuit is one of the two control circuits, and the slave control circuit is the other of the two control circuits; The processors to be diagnosed in the main control circuit respectively send inspection information to the other three processors, so that the other three processors generate diagnosis information according to the inspection information; The speed governor further includes: An arbitration module, which is respectively connected to the four processors, and is used to determine whether the processor to be diagnosed is faulty according to the diagnosis information output by the other three processors, and output the diagnosis result of the processor to be diagnosed to the other three processors, and the processor to be diagnosed is each processor in the main control circuit; When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor; The arbitration module includes four arbitration circuits, each processor to be diagnosed is configured with one arbitration circuit, and each arbitration circuit is respectively connected to the other three processors, and the other three processors are processors other than the processor to be diagnosed configured by the arbitration circuit; The arbitration circuit includes: three arbitration units, two input terminals of each arbitration unit are respectively connected to two of the other three processors correspondingly, output terminals of each arbitration unit are respectively connected to the other three processors, and one input terminal of every two arbitration units is connected to the same processor, and each arbitration unit respectively includes: a NAND gate and an inverter, wherein, Two input terminals of the NAND gate are respectively connected to two of the other three processors correspondingly, and an output terminal of the NAND gate is connected to an input terminal of the inverter; Output terminals of the inverter are respectively connected to the other three processors.

2. The governor according to claim 1, characterized in that, When one processor in the main control circuit fails, the second target processor is a normal processor in the main control circuit; when both processors in the main control circuit fail, the second target processor is a processor in the slave control circuit.

3. The governor according to claim 1, characterized in that, The speed governor further includes a first isolation circuit, and the two processors in the main control circuit are respectively connected to the two processors in the slave control circuit through the first isolation circuit; The first isolation circuit includes: A first isolation unit, which is respectively connected to the first processor in the main control circuit and the first processor in the slave control circuit; A second isolation unit, which is respectively connected to the first processor of the main control circuit and the second processor of the slave control circuit; A third isolation unit, which is respectively connected to the second processor of the main control circuit and the first processor of the slave control circuit; A fourth isolation unit, which is respectively connected to the second processor of the main control circuit and the second processor of the slave control circuit; wherein, the first processor of the main control circuit and the first processor of the slave control circuit are of the same type; When the diagnosis result indicates that the processor to be diagnosed is a faulty processor, the other three processors respectively control the isolation units connected to the faulty processor according to the diagnosis result to respectively disconnect the data transmission paths connected to the faulty processor.

4. The governor according to claim 1, wherein The speed governor further includes: A first input acquisition circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to acquire and process the received analog input signal, and transmit the processed analog input signal to the target control circuit; A first output processing circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to receive and process the analog output signal from the target control circuit; A second input acquisition circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to acquire and process the received digital input signal, and transmit the processed digital input signal to the target control circuit; A second output processing circuit, which is respectively connected to the main control circuit and the slave control circuit, and is configured to receive and process the digital output signal from the target control circuit; wherein, the target control circuit is one of the two control circuits.

5. The governor according to claim 4, characterized in that The speed governor further includes: A second isolation circuit, which is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the main control circuit; A third isolation circuit, which is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the slave control circuit; wherein, the second processor of the main control circuit and the second processor of the slave control circuit are of the same type; When the processor in the main control circuit is fault-free, the main control circuit controls the third isolation circuit to be in a locked state; When the second processor in the main control circuit is faulty, the main control circuit controls the second isolation circuit to be in a locked state.

6. The governor according to claim 5, characterized in that, The second input acquisition circuit includes a first opto-isolator for isolating the acquired digital input signal; The second output processing circuit includes a second opto-isolator for isolating the received digital output signal; The second isolation circuit includes: A first magnetic isolator, which is respectively connected to the first input acquisition circuit and the second processor of the main control circuit; A second magnetic isolator, which is respectively connected to the first output processing circuit and the second processor of the main control circuit; A third magnetic isolator, which is respectively connected to the first optoelectronic isolator, the second optoelectronic isolator, and the second processor of the main control circuit; The third isolation circuit includes: A fourth magnetic isolator, which is respectively connected to the first input acquisition circuit and the second processor of the slave control circuit; A fifth magnetic isolator, which is respectively connected to the first output processing circuit and the second processor of the slave control circuit; A sixth magnetic isolator, which is respectively connected to the first optoelectronic isolator, the second optoelectronic isolator, and the second processor of the slave control circuit.

7. The governor according to claim 4, characterized in that, The speed governor further includes: A power supply module, which is respectively connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and each of the control circuits, and is used to provide a supply voltage; Wherein, the power supply module includes: An inversion unit, which is used to receive an external power supply voltage and perform a voltage drop process on the power supply voltage to obtain a voltage drop voltage; A first system power supply unit, which is connected to the inversion unit and is used to rectify, regulate voltage, and filter the voltage drop voltage to obtain a first supply voltage and output it to the main control circuit; A second system power supply unit, which is connected to the inversion unit and is used to rectify, regulate voltage, and filter the voltage drop voltage to obtain a second supply voltage and output it to the slave control circuit; An interface power supply unit, which is connected to the inversion unit and is used to rectify, regulate voltage, and filter the voltage drop voltage to obtain a third supply voltage and output it to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, and the second output processing circuit.

8. The governor according to claim 1, characterized in that, When a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor is connected to the second target processor in the main control circuit through another processor in the slave control circuit to form a target data transmission path to realize data transmission.

9. The governor according to claim 1, characterized in that, The speed governor further includes: A verification module, which is respectively connected to the four processors and is used to judge whether the processor to be diagnosed is faulty and output the diagnosis result of the processor to be diagnosed to the other three processors, and the processor to be diagnosed is each processor in the main control circuit; When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

10. A control method for a governor, characterized in that, Applied to the speed governor according to any one of claims 1-9, the method includes: Obtaining a temperature value according to a signal to be started to judge the start state; If it is in a hot start state, control the speed of the steam turbine to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to a first preset speed; In the case of cold start, control the speed of the steam turbine to increase at a second preset rate until the real-time speed of the steam turbine is greater than or equal to the second preset speed and then enter the warm-up state. After a preset time, control the speed of the steam turbine to continue to increase at the second preset rate until the real-time speed of the steam turbine is greater than or equal to the third preset speed, and then control the speed of the steam turbine to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed; According to the start completion signal, adjust the speed of the steam turbine according to the set speed.

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