Reference current source circuit

Abstract

The application discloses a kind of reference current source circuit, including reference current generation module, band gap reference module, process angle detection module and current compensation module.Reference current generation module is used to generate a reference current, the reference current changes with process angle deviation, band gap reference module is used to generate a band gap reference voltage with different voltage values under different process angles, process angle detection module is used to compare the band gap reference voltage with at least one reference voltage, and generate detection signal according to the comparison result, current compensation module is used to provide corresponding compensation current to the reference current generation module according to the detection signal, to compensate the reference current, so that the reference current output by circuit can be substantially consistent under typical process angle TT, slow process angle SS and fast process angle FF, and the reference current not affected by process angle deviation is obtained.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a reference current source circuit. Background Technology

[0002] Reference current sources are indispensable basic modules in integrated circuits, widely used in amplifiers, oscillators, comparators, phase-locked loops, and many mixed-signal circuits such as ADCs / DACs. They can provide a constant bias current to the circuit and also serve as an active load for amplifiers. With technological advancements, the demands on various electronic products are increasing, leading to higher accuracy requirements for circuits, and consequently, higher demands on reference current sources. Therefore, improving the power supply voltage rejection ratio, temperature drift coefficient, and output accuracy of reference current sources is an important task for current technical personnel.

[0003] In recent years, as integrated circuit process dimensions have shrunk, mask fabrication has approached optical limits, leading to deviations in the physical dimensions of various devices within the chip. Simultaneously, due to manufacturing limitations, it's difficult to maintain consistent doping concentrations across different locations on the chip. Therefore, in actual integrated circuit fabrication, device parameters exhibit process deviations due to variations in process corners. A process corner refers to the differences in parameters of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) due to variations in position on the same wafer or between different batches of wafers during chip fabrication. Generally, process corners are categorized into Typical, Slow, and Fast. Deviations in process corners significantly impact the performance of various modules within the chip. For example, a deviation in process corner can cause the output reference current to deviate from its original design value, potentially leading to severe degradation of the temperature coefficient of the output reference current.

[0004] Therefore, it is necessary to improve the existing reference current source to calibrate the output current of the reference current source in order to obtain a reference current that is not affected by process deviations. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a reference current source circuit that can calibrate the reference current according to the process angle deviation, so as to improve the output accuracy of the reference current source.

[0006] According to an embodiment of the present invention, a reference current source circuit is provided, comprising: a reference current generation module for generating a reference current, the reference current varying with process angle deviation; a bandgap reference module for generating a bandgap reference voltage, the bandgap reference voltage having different voltage values ​​at different process angles; a process angle detection module for comparing the bandgap reference voltage with at least one reference voltage and generating a detection signal based on the comparison result; and a current compensation module for providing a corresponding compensation current to the reference current generation module based on the detection signal to compensate the reference current.

[0007] Optionally, the bandgap reference module includes: a first PMOS transistor, with a first terminal connected to a power supply voltage and a control terminal connected to a second terminal; a second PMOS transistor, with a first terminal connected to the power supply voltage and a control terminal connected to the control terminal of the first PMOS transistor; a first NMOS transistor, with a first terminal connected to a second terminal of the first PMOS transistor; a second NMOS transistor, with a first terminal connected to a second terminal of the second PMOS transistor and a control terminal connected to the control terminal of the first NMOS transistor; and a first resistor, with a first terminal connected to a second terminal of the first NMOS transistor. The second terminal of the first resistor is connected to the second terminal of the second NMOS transistor; the second resistor has its first terminal connected to the first terminal of the first resistor, and its second terminal connected to ground; the third PMOS transistor has its first terminal connected to the power supply voltage, its control terminal connected to the second terminal of the second PMOS transistor, and its second terminal connected to the control terminals of the first NMOS transistor and the second NMOS transistor; and the third resistor has its first terminal connected to the second terminal of the third PMOS transistor, and its second terminal connected to ground, wherein the common terminal of the third PMOS transistor and the third resistor is used to provide the bandgap reference voltage.

[0008] Optionally, the process corner detection module includes: a first comparison module for comparing the bandgap reference voltage with a first reference voltage among the at least one reference voltage to generate a first detection signal; and a second comparison module for comparing the bandgap reference voltage with a second reference voltage among the at least one reference voltage to generate a second detection signal.

[0009] Optionally, the first comparison module includes: a first current source, a first terminal of which is connected to a power supply voltage; a fourth PMOS transistor, a first terminal of which is connected to a second terminal of the first current source, and a control terminal for receiving the first reference voltage; a fifth PMOS transistor, a first terminal, a control terminal, and a second terminal of which are connected to the first terminal of the first current source; a sixth PMOS transistor, a first terminal of which is connected to the second terminal of the first current source, and a control terminal for receiving the bandgap reference voltage; a third NMOS transistor, a first terminal of which and a control terminal are connected to the second terminal of the fourth PMOS transistor, and the second terminal is connected to ground; and a fourth NMOS transistor, a first terminal of which is connected to the second terminal of the sixth PMOS transistor, a control terminal of which is connected to the control terminal of the third NMOS transistor, and the second terminal is connected to ground, wherein the common terminal of the sixth PMOS transistor and the fourth NMOS transistor is used to provide the first detection signal.

[0010] Optionally, the second comparison module includes: a second current source, the first terminal of which is connected to a power supply voltage; a seventh PMOS transistor, the first terminal of which is connected to the second terminal of the second current source, and a control terminal for receiving the second reference voltage; an eighth PMOS transistor, the first terminal, control terminal, and second terminal of which are connected to the first terminal of the second current source; a ninth PMOS transistor, the first terminal of which is connected to the second terminal of the second current source, and a control terminal for receiving the bandgap reference voltage; a fifth NMOS transistor, the first terminal and control terminal of which are connected to the second terminal of the seventh PMOS transistor, and the second terminal of which is connected to ground; and a sixth NMOS transistor, the first terminal of which is connected to the second terminal of the ninth PMOS transistor, the control terminal of which is connected to the control terminal of the fifth NMOS transistor, and the second terminal of which is connected to ground, wherein the common terminal of the ninth PMOS transistor and the sixth NMOS transistor is used to provide the second detection signal.

[0011] Optionally, the current compensation module includes: a first compensation branch for providing a first compensation current to the reference current generating module according to the first detection signal; and a second compensation branch for providing a second compensation current to the reference current generating module according to the second detection signal.

[0012] Optionally, the reference current generation module includes: a third current source, the first terminal of which is connected to a power supply voltage to provide an input current that varies with process angle deviation; and a current mirror structure having a current input terminal connected to a second terminal of the third current source and a current output terminal for outputting the reference current, wherein the current mirror structure outputs the reference current at the current output terminal by mirroring the input current.

[0013] Optionally, the current mirror structure includes: a seventh NMOS transistor, the first terminal of which is connected to the second terminal of the third current source; an eighth NMOS transistor, the first terminal of which is connected to the second terminal of the seventh NMOS transistor, and the second terminal of which is connected to ground; a ninth NMOS transistor, the first terminal of which is used to output the reference current, and the control terminal of which is connected to the control terminal of the seventh NMOS transistor; a tenth NMOS transistor, the first terminal of which is connected to the second terminal of the ninth NMOS transistor, the control terminal of which is connected to the control terminal of the eighth NMOS transistor, and the second terminal of which is connected to ground; and an eleventh NMOS transistor, the first and second terminals of which are connected to ground, and the control terminal of which is connected to the control terminals of the eighth and ninth NMOS transistors.

[0014] Optionally, the first compensation branch includes: a tenth PMOS transistor, the first end of which is connected to the current output terminal of the current mirror structure, and the control terminal is used to receive the first detection signal; a twelfth NMOS transistor, the first end of which is connected to the second end of the tenth PMOS transistor, and the control terminal is connected to the control terminal of the seventh NMOS transistor; and a thirteenth NMOS transistor, the first end of which is connected to the second end of the twelfth NMOS transistor, the control terminal of which is connected to the control terminal of the eighth NMOS transistor, and the second end of which is connected to ground.

[0015] Optionally, the second compensation branch includes: an eleventh PMOS transistor, the first terminal of which is connected to the current output terminal of the current mirror structure, and the control terminal for receiving the second detection signal; a fourteenth NMOS transistor, the first terminal of which is connected to the second terminal of the eleventh PMOS transistor, and the control terminal of which is connected to the control terminal of the seventh NMOS transistor; and a fifteenth NMOS transistor, the first terminal of which is connected to the second terminal of the fourth NMOS transistor, and the control terminal of which is connected to the control terminal of the eighth NMOS transistor, with the second terminal connected to ground.

[0016] In summary, the reference current source circuit provided in this embodiment of the invention includes a reference current generation module, a bandgap reference module, a process corner detection module, and a current compensation module. The reference current generation module generates a reference current that varies with process corner deviation. The bandgap reference module generates a bandgap reference voltage with different voltage values ​​at different process corners. The process corner detection module compares the bandgap reference voltage with at least one reference voltage and generates a detection signal based on the comparison result. The current compensation module provides a corresponding compensation current to the reference current generation module based on the detection signal to compensate for the reference current. This ensures that the reference current output by the circuit remains essentially consistent under typical process corners TT, slow process corners SS, and fast process corners FF, obtaining a reference current unaffected by process corner deviations. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a reference current source circuit according to an embodiment of the present invention is shown.

[0019] Figure 2 A circuit diagram of a reference current source circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0021] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 A schematic diagram of a reference current source circuit according to an embodiment of the present invention is shown. Figure 1As shown, the reference current source circuit 100 in this embodiment includes a bandgap reference module 110, a process corner detection module 120, a reference current generation module 130, and a current compensation module 140. The bandgap reference module 110 generates a bandgap reference voltage Vbg that varies with the process corner to track changes in the process corner. In this embodiment, the voltage value of the bandgap reference voltage Vbg generated by the bandgap reference module 110 changes only with the process corner and is essentially unaffected by power supply voltage and temperature. For example, the bandgap reference voltage Vbg is 600mV at the TT process corner (Typical), 700mV at the SS process corner (Slow), and 500mV at the FF process corner (Fast).

[0024] The process corner detection module 120 compares the bandgap reference voltage Vbg with at least one reference voltage and generates a detection signal based on the comparison result. For example, the at least one reference voltage is obtained by voltage division of an external reference voltage. In some embodiments, an external reference voltage can be obtained using an external bandgap reference voltage source based on a BJT (bipolar junction transistor) design. This external reference voltage is substantially unaffected by changes in process corner, temperature, and power supply voltage. This external reference voltage is then divided to obtain a first reference voltage VREF1 and a second reference voltage VREF2. Furthermore, the voltage value of the first reference voltage VREF1 is higher than the voltage value of the second reference voltage VREF2. In some embodiments, the voltage value of the first reference voltage VREF1 is 650mV, and the voltage value of the second reference voltage VREF2 is 550mV. The process corner detection module 120 compares the bandgap reference voltage Vbg with the first reference voltage VREF1 and the second reference voltage VREF2, and generates a first detection signal CTRL1 and a second detection signal CTRL2 based on the comparison result.

[0025] The reference current generation module 130 generates a reference current that remains largely unchanged with variations in temperature and supply voltage, but varies with process corner deviations. For example, the reference current tends to be larger at the FF process corner than at the TT process corner, and smaller at the SS process corner than at the TT process corner.

[0026] The current compensation module 140 provides corresponding compensation currents Iss and / or Iff to the reference current generation module based on the detection signal output by the process corner detection module 120, thereby compensating the reference current generated by the reference current generation module 130 to output a more accurate reference current Iref. This allows the reference current source circuit 100 to achieve a more accurate current output, reducing deviations caused by the process corner. Furthermore, the current compensation module 140 has a first compensation branch and a second compensation branch (not shown in the figure). The first compensation branch provides a first compensation current Iss to the reference current generation module 130 based on the first detection signal CTRL1, and the second compensation branch provides a second compensation current If to the reference current generation module 130 based on the second detection signal CTRL2.

[0027] Figure 2 A circuit diagram of a reference current source circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the bandgap reference module 110 of this embodiment includes PMOS transistors Mp1 to Mp3, NMOS transistors Mn1 to Mn2, and resistors R1 to R3. The sources of PMOS transistors Mp1 to Mp3 are electrically connected to the power supply voltage VDD. The gate of PMOS transistor Mp1 is electrically connected to the gate of PMOS transistor Mp2, and the gate and drain of PMOS transistor Mp1 are shorted together. The gate of PMOS transistor Mp3 is electrically connected to the drain of PMOS transistor Mp2. The drain of NMOS transistor Mn1 is electrically connected to the gate and drain of PMOS transistor Mp1, and the gate of NMOS transistor Mn1 is electrically connected to the gate of NMOS transistor Mn2 and the drain of PMOS transistor Mp3. Resistor R1 has a first terminal and a second terminal; its first terminal is electrically connected to the source of NMOS transistor Mn1, and its second terminal is electrically connected to the source of NMOS transistor Mn2. Resistor R2 has a first terminal and a second terminal. Its first terminal is electrically connected to the first terminal of resistor R1, and its second terminal is electrically connected to ground (GND). Resistor R3 has a first terminal and a second terminal. Its first terminal is electrically connected to the drain of PMOS transistor Mp3, and its second terminal is electrically connected to ground (GND). The common terminal of the drain of PMOS transistor Mp3 and resistor R3 is used to output the bandgap reference voltage Vbg.

[0028] The process corner detection module 120 includes a first comparison module 121 and a second comparison module 122. The first comparison module 121 is used to compare the bandgap reference voltage Vbg with a first reference voltage VREF1 among the at least one reference voltage to generate a first detection signal CTRL1. The second comparison module 122 is used to compare the bandgap reference voltage Vbg with a second reference voltage VREF2 among the at least one reference voltage to generate a second detection signal CTRL2.

[0029] The first comparison module 121 includes a current source 101, PMOS transistors Mp4 to Mp6, and NMOS transistors Mn3 to Mn4. The first terminal of the current source 101 is electrically connected to the power supply voltage VDD, and the second terminal is electrically connected to the source of PMOS transistors Mp4 to Mp6. The gate of PMOS transistor Mp4 receives a first reference voltage VREF1. The gate and drain of PMOS transistor Mp5 are electrically connected to the second terminal of the current source 101. The gate of PMOS transistor Mp6 receives the bandgap reference voltage Vbg. The drain of NMOS transistor Mn3 is electrically connected to the drain of PMOS transistor Mp4, the gate of NMOS transistor Mn3 is shorted to its drain, and the source of NMOS transistor Mn3 is electrically connected to ground. The drain of NMOS transistor Mn4 is electrically connected to the drain of PMOS transistor Mp6, the gate of NMOS transistor Mn4 is electrically connected to the gate of NMOS transistor Mn3, and the source of NMOS transistor Mn4 is electrically connected to ground. The common terminal of the drains of PMOS transistor Mp6 and NMOS transistor Mn4 is used to output the first detection signal CTRL1.

[0030] The second comparison module 122 includes a current source 102, PMOS transistors Mp7 to Mp9, and NMOS transistors Mn5 to Mn6. The first terminal of the current source 102 is electrically connected to the power supply voltage VDD, and the second terminal is electrically connected to the source of PMOS transistors Mp7 to Mp9. The gate of PMOS transistor Mp7 receives the second reference voltage VREF2. The gate and drain of PMOS transistor Mp8 are electrically connected to the second terminal of the current source 102. The gate of PMOS transistor Mp9 receives the bandgap reference voltage Vbg. The drain of NMOS transistor Mn5 is electrically connected to the drain of PMOS transistor Mp7, the gate of NMOS transistor Mn5 is shorted to its drain, and the source of NMOS transistor Mn5 is electrically connected to ground. The drain of NMOS transistor Mn6 is electrically connected to the drain of PMOS transistor Mp9, the gate of NMOS transistor Mn6 is electrically connected to the gate of NMOS transistor Mn5, and the source of NMOS transistor Mn6 is electrically connected to ground. The common terminal of the drains of PMOS transistor Mp9 and NMOS transistor Mn6 is used to output the second detection signal CTRL2.

[0031] The reference current generation module 130 includes a current source 103 and a current mirror structure 104. The first terminal of the current source 103 is electrically connected to the power supply voltage VDD, providing an input current Iin that varies with process angle deviation, and this input current Iin remains almost unchanged with temperature and power supply voltage variations. The current mirror structure 104 has a current input terminal electrically connected to the second terminal of the current source 103, and a current output terminal for outputting a reference current Iref0. The current mirror structure 104 generates the reference current Iref0 at its current output terminal by replicating the input current Iin at a certain ratio. Because the input current Iin varies with the process angle, the reference current Iref0 also varies with the process angle. For example, the reference current Iref0 tends to be larger at the FF process angle than at the TT process angle, and smaller at the SS process angle than at the TT process angle.

[0032] Furthermore, the current mirror structure 104 is implemented, for example, by a cascode current mirror, including NMOS transistors Mn7 to Mn11. The drain of NMOS transistor Mn7 serves as the current input terminal of the current mirror structure 104 and is electrically connected to the second terminal of the current source 103. The gate of NMOS transistor Mn7 is electrically connected to the gate of NMOS transistor Mn9. The drain of NMOS transistor Mn9 serves as the current output terminal of the current mirror structure 104 for generating the reference current Iref0. The drain of NMOS transistor Mn8 is connected to the gate of NMOS transistor Mn11. The source of N7 is electrically connected. The gate of NMOS transistor Mn8 is electrically connected to the gate of NMOS transistor Mn10 and the drain of NMOS transistor Mn7. The source of NMOS transistor Mn8 is electrically connected to ground. The drain of NMOS transistor Mn10 is electrically connected to the source of NMOS transistor Mn9. The source of NMOS transistor Mn10 is electrically connected to ground. The gate of NMOS transistor Mn11 is electrically connected to the gate of NMOS transistor Mn8 and the gate of NMOS transistor Mn10. The drain and source of NMOS transistor Mn11 are electrically connected to ground.

[0033] The current compensation module 140 includes a first compensation branch 141 and a second compensation branch 142. The first compensation branch 141 includes a PMOS transistor Mp10, an NMOS transistor Mn12, and an NMOS transistor Mn13. The source of the PMOS transistor Mp10 is electrically connected to the current output terminal of the current mirror structure 104. The gate of the PMOS transistor Mp10 is used to receive the first detection signal CTRL1. The drain of the PMOS transistor Mp10 is electrically connected to the drain of the NMOS transistor Mn12. The gate of the NMOS transistor Mn12 is electrically connected to the gate of the NMOS transistor Mn7 in the current mirror structure 104. The source of the NMOS transistor Mn12 is electrically connected to the drain of the NMOS transistor Mn13. The gate of the NMOS transistor Mn13 is electrically connected to the gate of the NMOS transistor Mn8 in the current mirror structure 104. The source of the NMOS transistor Mn13 is electrically connected to ground. In the first compensation branch 141, the PMOS transistor Mp10 serves as a switching element, controlled by the first detection signal CTRL1 to turn on or off. The NMOS transistors Mn12 and Mn13, together with the NMOS transistors Mn7 and Mn8, form a cascode current mirror. When the PMOS transistor Mp10 is turned on, it replicates the input current Iin according to a certain ratio to obtain the first compensation current Iss. Then, the PMOS transistor Mp10 provides the first compensation current Iss to the current output terminal of the current mirror structure 104 to compensate the reference current Iref0, thereby obtaining the final accurate reference current Iref.

[0034] The second compensation branch 142 includes a PMOS transistor Mp11, an NMOS transistor Mn14, and an NMOS transistor Mn15. The source of the PMOS transistor Mp11 is electrically connected to the current output terminal of the current mirror structure 104. The gate of the PMOS transistor Mp11 is used to receive the second detection signal CTRL2. The drain of the PMOS transistor Mp11 is electrically connected to the drain of the NMOS transistor Mn14. The gate of the NMOS transistor Mn14 is electrically connected to the gate of the NMOS transistor Mn7 in the current mirror structure 104. The source of the NMOS transistor Mn14 is electrically connected to the drain of the NMOS transistor Mn15. The gate of the NMOS transistor Mn15 is electrically connected to the gate of the NMOS transistor Mn8 in the current mirror structure 104. The source of the NMOS transistor Mn15 is electrically connected to ground. In the second compensation branch 142, the PMOS transistor Mp11 acts as a switching element, which is controlled by the second detection signal CTRL2 to turn on or off. The NMOS transistors Mn14 and Mn15, together with the NMOS transistors Mn7 and Mn8, form a cascode current mirror. When the PMOS transistor Mp11 is turned on, it is used to obtain the second compensation current Iff by replicating the input current Iin according to a certain ratio. Then, the second compensation current Iff is provided to the current output terminal of the current mirror structure 104 through the PMOS transistor Mp11 to compensate the reference current Iref0, so as to obtain the final accurate reference current Iref.

[0035] The following analysis uses an example to illustrate the operation of the reference current source 100 in this embodiment. In this embodiment, the bandgap reference voltage Vbg has a voltage value of 600mV at the TT process angle (Typical), a voltage value of 700mV at the SS process angle (Slow), and a voltage value of 500mV at the FF process angle (Fast). The voltage value of the first reference voltage VREF1 is 650mV, and the voltage value of the second reference voltage VREF2 is 550mV.

[0036] When the process corner of the circuit is the typical process corner TT, the voltage value of the bandgap reference voltage Vbg is 600mV, which is lower than the first reference voltage VREF1 (voltage value is 650mV) and higher than the second reference voltage VREF2 (voltage value is 550mV). Therefore, the first detection signal CTRL1 output by the first comparison module 121 is high level, and the second detection signal CTRL2 output by the second comparison module 122 is low level. As a result, the PMOS transistor Mp10 in the first compensation branch 141 is turned off and the PMOS transistor Mp11 in the second compensation branch 142 is turned on. The PMOS transistor Mp11 provides the second compensation current Iff to the current output terminal to compensate the reference current Iref0. The final current Iref = Iref0 + Iff is obtained.

[0037] When the process angle of the circuit is the slow process angle SS, the voltage value of the bandgap reference voltage Vbg is 700mV, which is higher than the first reference voltage VREF1 and the second reference voltage VREF2. Therefore, the first detection signal CTRL1 and the second detection signal CTRL2 output by the first comparison module 121 and the second comparison module 122 are both at low level. As a result, the PMOS transistor Mp10 in the first compensation branch 141 and the PMOS transistor Mp11 in the second compensation branch 142 are both turned on. The PMOS transistor Mp10 provides the first compensation current Iss to the current output terminal, and the PMOS transistor Mp11 provides the second compensation current Iff to the current output terminal. The final reference current Iref = Iref0 + Iss + Iff is obtained.

[0038] When the process angle of the circuit is the fast process angle FF, the voltage value of the bandgap reference voltage Vbg is 500mV, which is lower than the first reference voltage VREF1 and the second reference voltage VREF2. Therefore, the first detection signal CTRL1 and the second detection signal CTRL2 output by the first comparison module 121 and the second comparison module 122 are both at high level. As a result, the PMOS transistor Mp10 in the first compensation branch 141 and the PMOS transistor Mp11 in the second compensation branch 142 are both turned off, and the reference current Iref = Iref0 is finally obtained by the circuit.

[0039] As can be seen from the above analysis of the working process, the reference current source circuit 100 in this embodiment obtains the reference current Iref0, the first compensation current Iss, and the second compensation current Iff by replicating the input current Iin according to a certain ratio through a cascode current mirror. Since the input current Iin changes with the process angle, and the trend is that the current value under the slow process angle SS is smaller than the current value under the typical process angle TT, and the current under the fast process angle FF is larger than the current under the typical process angle TT, the comparison module detects the change of the circuit process angle. Under the slow process angle SS, a part of the current is added to the reference current output by the circuit, and under the fast process angle FF, a part of the current is reduced from the reference current output by the circuit. This ensures that the reference current Iref output by the circuit remains basically consistent under the typical process angle TT, the slow process angle SS, and the fast process angle FF, thereby improving the accuracy of the reference current output by the circuit. Furthermore, since the output reference current Iref is only a proportional amplification or reduction of the input current Iin and does not change the original temperature characteristics of the input current Iin, the temperature characteristics of the input current Iin can be adjusted according to design requirements to finally obtain a reference current with a positive temperature coefficient (PTAT), a negative temperature coefficient (CTAT), or a zero temperature coefficient (OTC).

[0040] In summary, the reference current source circuit provided in this embodiment of the invention includes a reference current generation module, a bandgap reference module, a process corner detection module, and a current compensation module. The reference current generation module generates a reference current that varies with process corner deviation. The bandgap reference module generates a bandgap reference voltage with different voltage values ​​at different process corners. The process corner detection module compares the bandgap reference voltage with at least one reference voltage and generates a detection signal based on the comparison result. The current compensation module provides a corresponding compensation current to the reference current generation module based on the detection signal to compensate for the reference current. This ensures that the reference current output by the circuit remains essentially consistent under typical process corners TT, slow process corners SS, and fast process corners FF, obtaining a reference current unaffected by process corner deviations.

[0041] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A reference current source circuit, comprising: A reference current generation module is used to generate a reference current that varies with process angle deviation; A bandgap reference module is used to generate a bandgap reference voltage, which has different voltage values ​​at different process angles; A process corner detection module is used to compare the bandgap reference voltage with at least one reference voltage and generate a detection signal based on the comparison result. as well as The current compensation module is used to provide a corresponding compensation current to the reference current generation module according to the detection signal, so as to compensate the reference current. The process corner detection module includes: A first comparison module is used to compare the bandgap reference voltage with a first reference voltage among the at least one reference voltage to generate a first detection signal. The first comparison module includes: a first current source, a first terminal of which is connected to a power supply voltage; a fourth PMOS transistor, a first terminal of which is connected to a second terminal of the first current source, and a control terminal for receiving the first reference voltage; a fifth PMOS transistor, a first terminal, a control terminal, and a second terminal of which are connected to the first terminal of the first current source; a sixth PMOS transistor, a first terminal of which is connected to the second terminal of the first current source, and a control terminal for receiving the bandgap reference voltage; a third NMOS transistor, a first terminal of which and a control terminal are connected to the second terminal of the fourth PMOS transistor, and the second terminal is connected to ground; and a fourth NMOS transistor, a first terminal of which is connected to the second terminal of the sixth PMOS transistor, a control terminal of which is connected to the control terminal of the third NMOS transistor, and the second terminal is connected to ground, wherein the common terminal of the sixth PMOS transistor and the fourth NMOS transistor is used to provide the first detection signal; and A second comparison module is used to compare the bandgap reference voltage with a second reference voltage among the at least one reference voltage to generate a second detection signal. The second comparison module includes: a second current source, a first terminal of which is connected to a power supply voltage; a seventh PMOS transistor, a first terminal of which is connected to a second terminal of the second current source, and a control terminal for receiving the second reference voltage; an eighth PMOS transistor, a first terminal, a control terminal, and a second terminal of which are connected to the first terminal of the second current source; a ninth PMOS transistor, a first terminal of which is connected to the second terminal of the second current source, and a control terminal for receiving the bandgap reference voltage; a fifth NMOS transistor, a first terminal of which and a control terminal of which are connected to the second terminal of the seventh PMOS transistor, and the second terminal of which is connected to ground; and a sixth NMOS transistor, a first terminal of which is connected to the second terminal of the ninth PMOS transistor, a control terminal of which is connected to the control terminal of the fifth NMOS transistor, and the second terminal of which is connected to ground, wherein the common terminal of the ninth PMOS transistor and the sixth NMOS transistor is used to provide the second detection signal.

2. The reference current source circuit according to claim 1, wherein, The bandgap reference module includes: The first PMOS transistor has its first terminal connected to the power supply voltage and its control terminal connected to its second terminal. The second PMOS transistor has its first terminal connected to the power supply voltage and its control terminal connected to the control terminal of the first PMOS transistor. The first NMOS transistor, wherein the first terminal of the first NMOS transistor is connected to the second terminal of the first PMOS transistor; The second NMOS transistor has its first terminal connected to the second terminal of the second PMOS transistor, and its control terminal connected to the control terminal of the first NMOS transistor. A first resistor, wherein a first end of the first resistor is connected to a second end of the first NMOS transistor, and a second end of the first resistor is connected to a second end of the second NMOS transistor; The second resistor has a first end connected to the first end of the first resistor and a second end connected to ground. A third PMOS transistor, wherein its first terminal is connected to the power supply voltage, its control terminal is connected to the second terminal of the second PMOS transistor, and its second terminal is connected to the control terminals of the first NMOS transistor and the second NMOS transistor; and The third resistor has its first terminal connected to the second terminal of the third PMOS transistor, and its second terminal connected to ground. The common terminal of the third PMOS transistor and the third resistor is used to provide the bandgap reference voltage.

3. The reference current source circuit according to claim 1, wherein, The current compensation module includes: A first compensation branch is used to provide a first compensation current to the reference current generating module based on the first detection signal; and The second compensation branch is used to provide a second compensation current to the reference current generation module according to the second detection signal.

4. The reference current source circuit according to claim 3, wherein, The reference current generation module includes: A third current source, the first terminal of which is connected to the power supply voltage, is used to provide an input current that varies with process angle deviation; A current mirror structure has a current input terminal connected to a second terminal of the third current source, and a current output terminal for outputting the reference current. The current mirror structure mirrors the input current to output the reference current at the current output terminal.

5. The reference current source circuit according to claim 4, wherein, The current mirror structure includes: The seventh NMOS transistor, the first terminal of which is connected to the second terminal of the third current source; The eighth NMOS transistor has its first terminal connected to the second terminal of the seventh NMOS transistor, and its second terminal is connected to ground. The ninth NMOS transistor has its first terminal used to output the reference current, and its control terminal is connected to the control terminal of the seventh NMOS transistor. The tenth NMOS transistor, wherein its first terminal is connected to the second terminal of the ninth NMOS transistor, its control terminal is connected to the control terminal of the eighth NMOS transistor, and its second terminal is connected to ground; and The eleventh NMOS transistor has its first and second terminals connected to ground, and its control terminal connected to the control terminals of the eighth and ninth NMOS transistors.

6. The reference current source circuit according to claim 5, wherein, The first compensation branch includes: The tenth PMOS transistor has its first terminal connected to the current output terminal of the current mirror structure, and its control terminal is used to receive the first detection signal. The twelfth NMOS transistor has its first terminal connected to the second terminal of the tenth PMOS transistor, and its control terminal connected to the control terminal of the seventh NMOS transistor. The thirteenth NMOS transistor has its first terminal connected to the second terminal of the twelfth NMOS transistor, its control terminal connected to the control terminal of the eighth NMOS transistor, and its second terminal connected to ground.

7. The reference current source circuit according to claim 5, wherein, The second compensation branch includes: The eleventh PMOS transistor has its first terminal connected to the current output terminal of the current mirror structure, and its control terminal is used to receive the second detection signal. The fourteenth NMOS transistor, the first terminal of which is connected to the second terminal of the eleventh PMOS transistor, and the control terminal of which is connected to the control terminal of the seventh NMOS transistor; The fifteenth NMOS transistor has its first terminal connected to the second terminal of the fourteenth NMOS transistor, its control terminal connected to the control terminal of the eighth NMOS transistor, and its second terminal connected to ground.

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