A High-Resolution TDC Implementation Method Based on FPGA

Abstract

The present invention discloses a method for implementing a high-resolution TDC based on FPGA. The method for implementing the high-resolution TDC includes: performing multi-channel parallel interleaved sampling on a timing signal and centrally analyzing the sampled data, thereby improving the timing resolution ability of the signal and achieving high-resolution TDC conversion.

Description

Technical Field

[0001] The present invention belongs to the field of timing signal interfaces based on FPGA, and particularly relates to a method for implementing a high-resolution TDC based on FPGA. Background Art

[0002] Timing signals generally access the ordinary IO pins of FPGA. There are currently three methods for collecting timing signals based on FPGA: SDR single-edge sampling, DDR double-edge sampling, and ISERDES serial-parallel receiving sampling.

[0003] Taking the 7-series FPGA of Xilinx Corporation as an example, the sampling rate of SDR single-edge sampling is generally not higher than 400 Msps (M million samplings per second), the sampling rate of DDR double-edge sampling is generally not higher than 800 Msps, and the sampling rate of ISERDES serial-parallel receiving sampling is generally not higher than 1800 Msps. When higher timing resolution capabilities are required, the existing three methods cannot be achieved. Summary of the Invention

[0004] The purpose of the present invention is to disclose a method for implementing a high-resolution TDC based on FPGA in order to overcome the problems of the prior art. The method of the present invention performs multi-channel parallel interleaved sampling on timing signals, thereby improving the timing resolution ability of the signals and achieving high-resolution TDC conversion.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] A method for implementing a high-resolution TDC based on FPGA, the high-resolution TDC implementation method includes: performing multi-channel parallel interleaved sampling on timing signals and centrally analyzing the sampled data, thereby improving the timing resolution ability of the signals and achieving high-resolution TDC conversion.

[0007] According to a preferred embodiment, performing multi-channel parallel interleaved sampling on timing signals specifically includes: using the IDELAY and ISERDES resources on the internal IOB of FPGA, using multiple IDELAYs with different delay values to make one input timing signal into a multi-phase timing signal, and then using the same number of ISERDESs for serial-parallel conversion to form single-bit interleaved sampled data.

[0008] According to a preferred embodiment, the number of interleaved ISERDESs is less than or equal to the number of taps TAP of IDELAY.

[0009] The main solution of the present invention and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and claimed by the present invention. Those skilled in the art can understand that there are various combinations based on the prior art and common knowledge after understanding the solution of the present invention, all of which are the technical solutions to be protected by the present invention, and will not be exhaustively listed here.

[0010] Advantages of the present invention:

[0011] In 7-series FPGAs, the minimum interval of the TAP of IDELAY is 39 ps (400 MHz reference clock). When using 800 MHz high-speed clock (HCLK) single sampling in ISE ERDES and using 32-way parallel interleaved acquisition to comprehensively analyze serial and parallel data, a timing resolution of 39 ps can be theoretically achieved, and the equivalent sampling rate is 32×800 Msps, which is equivalent to the resolution ability of GTY in UltraScale series FPGAs.

[0012] In actual use, the wiring delay of the input signal has a certain randomness, and it is impossible to ensure the concentrated distribution of the delay while having a large number of fan-outs. Therefore, the parallel resources are generally distributed within a group (T) in the same IOBank, and the number does not exceed 10. In the case of saving resources and power consumption, using 4 channels of 1.6 Gsps can achieve a sampling rate of 6.4 Gsps, and the timing resolution ability is 156 ps. Brief Description of the Drawings

[0013] Figure 1 It is a block diagram of multi-phase interleaved sampling of FPGA timing signals for the FPGA-based high-resolution TDC implementation method of the present invention;

[0014] Figure 2 It is a schematic diagram of a timing analysis example of the present invention. Detailed Embodiments

[0015] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0016] It should be noted that: similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0017] Refer to Figure 1As shown in the figure, a method for implementing a high-resolution TDC based on FPGA is shown. The method for implementing the high-resolution TDC includes: performing multi-channel parallel interleaved sampling on the timing signal and centrally analyzing the sampled data, so as to improve the timing resolution ability of the signal and achieve high-resolution TDC conversion.

[0018] Specifically, the method for implementing the high-resolution TDC of the present invention includes: using the IDELAY and ISERDES resources on the internal IOB of the FPGA, using multiple IDELAYs with different delay values to make an input timing signal become a multi-phase timing signal, and then using the same number of ISERDES for serial-to-parallel conversion to form single-bit interleaved sampled data; then centrally analyzing the data after serial-to-parallel conversion can multiply the resolution ability of the occurrence time of the timing signal edge.

[0019] In theory, the maximum number of interleaved ISERDES can reach the number of taps TAP of IDELAY. For example, the IDELAY of 7-series FPGA has 32 taps, and at most 32 ISERDES can be used for interleaved sampling. The method of the present invention can multiply the timing resolution ability without changing the original hardware circuit.

[0020] Figure 2 For the timing analysis example schematic diagram, in the figure, the upper half is the input pulse signal, which is fanned out into 4 paths, and is delayed by IDELAYs of 0-TAP, n-TAP, 2n-TAP, and 3n-TAP respectively, and then 4 1:4 ISERDES are used for serial-to-parallel reception conversion. The lower half is the timing diagram of ISERDES conversion. The thick vertical lines are the parallel conversion output moments, and the thin vertical lines are the serial sampling interval moments. The delay interval unit n-TAP of IDELAY is 1 / 4 of a serial clock period.

[0021] For the pulse rising edge, Figure 2 From the lower half, 4 serial-to-parallel conversion data are obtained from top to bottom: 0011, 0011, 0011, and 0001.

[0022] According to the first data "0011", it can be known that the rising edge is between the 2nd serial clock and the 1st serial clock before the parallel clock. Further analyzing the change process of these 4 data, the output data remains unchanged when the signal is delayed by 1 / 4 of a serial clock period and 1 / 2 of a serial clock period, and the data changes when the signal is delayed by 3 / 4 of a serial clock period. It can be known that the signal rising edge is in the time slice of 1 / 2 to 3 / 4 of a serial clock period before the 1st serial clock.

[0023] Taking the serial clock of 1 GHz and the parallel clock of 250 MHz as an example, it can be known that Figure 2The rising edge is within the time interval of 1.5 ns to 1.75 ns before the immediately following parallel clock.

[0024] Similarly, it can be known that the falling edge is within the time interval of 3.25 ns to 3.5 ns before the immediately following parallel clock. The equivalent resolution ability of time is 4 Gsps (G samples per second).

[0025] Application case:

[0026] During the debugging of a certain vehicle-mounted system, the FPGA uses two IDELAYs with a time delay of 208 ps (4 TAPs of 52 ps) to distribute to the ISERDES of two 1.2 GHz serial clocks (equivalent to 2.4 Gsps time-resolved sampling) to implement the TDC function for synchronizing with the ADC, measure the synchronous reference signal of the acquisition system, and at the same time measure the second pulse in the same way to obtain the timing difference between the synchronous reference signals of different workshops and the second pulse of the relatively unified timing system. In the system application, the timing difference value can be compensated and corrected, so as to obtain the synchronous acquisition ability of a single sampling period of 2.4 Gsps between vehicles in a wireless manner.

[0027] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A high-resolution TDC implementation method based on FPGA, characterized in that: The high-resolution TDC implementation method includes: performing multi-channel parallel interleaved sampling on the time series signal and centrally analyzing the sampled data, thereby improving the time series resolution capability of the signal and realizing high-resolution TDC conversion; The multi-channel parallel interleaved sampling of the timing signal specifically includes: By utilizing the IDELAY and ISERDES resources on the IOB inside the FPGA and using multiple IDELAYs with different delay values, one input timing signal becomes a multi-phase timing signal, and then the same number of ISERDES are used for serial-to-parallel conversion to form single-bit interleaved sampling data.

2. The high-resolution TDC implementation method according to claim 1, wherein: The number of interleaved ISERDES is less than or equal to the number of taps TAP in IDELAY.

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