A display substrate, a driving method of a pixel driving circuit, and a display device

Abstract

The embodiment of the present application provides a display substrate, a driving method of a pixel driving circuit and a display device, the display substrate comprises a pixel driving circuit; the pixel driving circuit comprises a compensation sub-circuit and a control sub-circuit; a reset signal input end of the compensation sub-circuit is connected with a data signal voltage end, a reset signal control end is connected with a first reset signal end, a first charging signal input end is connected with a first voltage end, a first charging signal control end is connected with a first control signal end, a second charging signal input end is connected with a second voltage end, a second charging signal control end is connected with a second control signal end, a control signal output end is connected with a first control end of the control sub-circuit, a compensation signal output end is connected with a compensation signal input end of the control sub-circuit, and a compensation signal control end is connected with a third control signal end; a data signal input end of the control sub-circuit is connected with the data signal voltage end, a data signal control end is connected with the third control signal end, and the uniformity of compensation is enhanced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a display substrate, a driving method for a pixel driving circuit, and a display device. Background Technology

[0002] In the current 7T1C (7 transistors, 1 capacitor) pixel driver circuit's compensation circuit, the initial voltage written to the capacitor during initialization is a fixed Vint voltage, for example, -3V. Different pixel brightness levels correspond to different data signal voltages, resulting in varying voltage drops across the capacitor plates corresponding to pixels of different brightness levels during voltage compensation, leading to poor voltage compensation uniformity. Summary of the Invention

[0003] The purpose of this application is to provide a display substrate, a driving method for a pixel driving circuit, and a display device to enhance the uniformity of voltage compensation. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a display substrate, the display substrate comprising:

[0005] A pixel driving circuit and a light-emitting device; the pixel driving circuit includes a compensation sub-circuit and a control sub-circuit.

[0006] The reset signal input terminal of the compensation sub-circuit is connected to the data signal voltage terminal, and the reset signal control terminal of the compensation sub-circuit is connected to the first reset signal terminal; the first charging signal input terminal of the compensation sub-circuit is connected to the first voltage terminal, and the first charging signal control terminal of the compensation sub-circuit is connected to the first control signal terminal; the second charging signal input terminal of the compensation sub-circuit is connected to the second voltage terminal, and the second charging signal control terminal of the compensation sub-circuit is connected to the second control signal terminal; the control signal output terminal of the compensation sub-circuit is connected to the first control terminal of the control sub-circuit; the compensation signal output terminal of the compensation sub-circuit is connected to the compensation signal input terminal of the control sub-circuit, and the compensation signal control terminal of the compensation sub-circuit is connected to the third control signal terminal.

[0007] The data signal input terminal of the control sub-circuit is connected to the data signal voltage terminal, and the data signal control terminal of the control sub-circuit is connected to the third control signal terminal; the second control terminal and the third control terminal of the control sub-circuit are respectively connected to the fourth control signal terminal; the fixed voltage input terminal of the control sub-circuit is connected to the third voltage terminal; and the data signal output terminal of the control sub-circuit is connected to the first electrode of the light-emitting device.

[0008] In one possible implementation, the compensation sub-circuit includes a first transistor, a second transistor, an eighth transistor, a ninth transistor, and a capacitor;

[0009] The gate of the first transistor is connected to the first reset signal terminal, the first terminal of the first transistor is connected to the second terminal of the capacitor, the second terminal of the second transistor, and the control signal output terminal of the compensation sub-circuit, respectively, and the second terminal of the first transistor is connected to the reset signal input terminal of the compensation sub-circuit.

[0010] The gate of the second transistor is connected to the third control signal terminal, and the first terminal of the second transistor is connected to the compensation signal output terminal of the compensation sub-circuit.

[0011] The gate of the eighth transistor is connected to the first control signal terminal, the first terminal of the eighth transistor is connected to the first voltage terminal, and the second terminal of the eighth transistor is connected to the first terminal of the capacitor and the second terminal of the ninth transistor, respectively.

[0012] The gate of the ninth transistor is connected to the second control signal terminal, and the first terminal of the ninth transistor is connected to the second voltage terminal.

[0013] In one possible implementation, the control sub-circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0014] The gate of the third transistor is connected to the first control terminal of the control sub-circuit, the first terminal of the third transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, and the second terminal of the third transistor is connected to the compensation signal input terminal of the control sub-circuit and the first terminal of the sixth transistor.

[0015] The gate of the fourth transistor is connected to the third control signal terminal, and the first terminal of the fourth transistor is connected to the data signal voltage terminal.

[0016] The gate of the fifth transistor is connected to the fourth control signal terminal, and the first terminal of the fifth transistor is connected to the third voltage terminal.

[0017] The gate of the sixth transistor is connected to the fourth control signal terminal, and the second terminal of the sixth transistor is connected to the first electrode of the light-emitting device.

[0018] In one possible implementation, the pixel driving circuit further includes a reset sub-circuit, wherein the reset signal input terminal of the reset sub-circuit is connected to ground, and the reset signal output terminal of the reset sub-circuit is connected to the first electrode of the light-emitting device.

[0019] In one possible implementation, the reset sub-circuit includes a seventh transistor;

[0020] The gate of the seventh transistor is connected to the second reset signal terminal, the first terminal of the seventh transistor is connected to the first electrode of the light-emitting device, and the second terminal of the seventh transistor is connected to the ground terminal.

[0021] Secondly, embodiments of this application provide a driving method for a pixel driving circuit, used to drive any of the pixel driving circuits described in the first aspect above, the driving method comprising:

[0022] In the first initialization phase, the first reset signal terminal outputs a first voltage signal; the first control signal terminal outputs a first voltage signal; the reset signal input terminal outputs a first voltage signal; the data signal voltage terminal outputs a first voltage signal; the third control signal terminal outputs a second voltage signal; the second reset signal terminal outputs a second voltage signal; the fourth control signal terminal outputs a second voltage signal; and the second control signal terminal outputs a second voltage signal.

[0023] During the second initialization phase, the first reset signal terminal outputs a second voltage signal; the first control signal terminal outputs a second voltage signal; the reset signal input terminal outputs a first voltage signal; the data signal voltage terminal outputs a first voltage signal; the third control signal terminal outputs a second voltage signal; the second reset signal terminal outputs a second voltage signal; the fourth control signal terminal outputs a second voltage signal; and the second control signal terminal outputs a first voltage signal.

[0024] During the signal writing phase, the first reset signal terminal outputs a second voltage signal; the first control signal terminal outputs a second voltage signal; the reset signal input terminal outputs a second voltage signal; the data signal voltage terminal outputs a second voltage signal; the third control signal terminal outputs a first voltage signal; the second reset signal terminal outputs a first voltage signal; the fourth control signal terminal outputs a second voltage signal; and the second control signal terminal outputs a first voltage signal.

[0025] During the light-emitting phase, the first reset signal terminal outputs a second voltage signal; the first control signal terminal outputs a second voltage signal; the reset signal input terminal outputs a second voltage signal; the data signal voltage terminal outputs a second voltage signal; the third control signal terminal outputs a second voltage signal; the second reset signal terminal outputs a second voltage signal; the fourth control signal terminal outputs a first voltage signal; and the second control signal terminal outputs a first voltage signal.

[0026] The first voltage signal and the second voltage signal are signals with opposite high and low levels.

[0027] In one possible implementation, each transistor is a P-type transistor; the first voltage signal is low and the second voltage signal is high.

[0028] In one possible implementation, the first voltage V DD1 and the second voltage V DD2 Satisfy: V DD1 -V DD2 >|Vth|; where Vth is the threshold voltage of the third transistor.

[0029] In one possible implementation, the third voltage V DD The range is 3V-7V.

[0030] Thirdly, embodiments of this application provide a display device, the display device comprising:

[0031] Display substrates as described in any of the first aspects above.

[0032] Beneficial effects of the embodiments in this application:

[0033] This application provides a display substrate, a pixel driving circuit driving method, and a display device. The display substrate includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a compensation sub-circuit and a control sub-circuit. The reset signal input terminal of the compensation sub-circuit is connected to a data signal voltage terminal, and the reset signal control terminal of the compensation sub-circuit is connected to a first reset signal terminal. The first charging signal input terminal of the compensation sub-circuit is connected to a first voltage terminal, and the first charging signal control terminal of the compensation sub-circuit is connected to a first control signal terminal. The second charging signal input terminal of the compensation sub-circuit is connected to a second voltage terminal, and the second charging signal control terminal of the compensation sub-circuit is connected to a second control signal terminal. The control signal output terminal of the compensation sub-circuit is connected to the first control terminal of the control sub-circuit; the compensation signal output terminal of the compensation sub-circuit is connected to the compensation signal input terminal of the control sub-circuit, and the compensation signal control terminal of the compensation sub-circuit is connected to the third control signal terminal; the data signal input terminal of the control sub-circuit is connected to the data signal voltage terminal, and the data signal control terminal of the control sub-circuit is connected to the third control signal terminal; the second and third control terminals of the control sub-circuit are respectively connected to the fourth control signal terminal; the fixed voltage input terminal of the control sub-circuit is connected to the third voltage terminal; and the data signal output terminal of the control sub-circuit is connected to the first electrode of the light-emitting device. During the initialization phase of the pixel driving circuit, the original fixed initialization voltage is replaced by the voltage of the written data signal, so that the compensation voltage drop corresponding to each pixel with different brightness is basically the same during compensation, thereby enhancing the uniformity of voltage compensation.

[0034] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0036] Figure 1 This is a schematic diagram of an OLED pixel driving circuit in related technologies;

[0037] Figure 2 This is a schematic diagram of another OLED pixel driving circuit in related technologies;

[0038] Figure 3 This is a schematic diagram of a first structure of a display substrate provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of a second structure of a display substrate provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of a third structure of a display substrate provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of a fourth structure of a display substrate provided in an embodiment of this application;

[0042] Figure 7 A schematic diagram of a fifth structure of a display substrate provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of the pixel driving circuit provided in the embodiments of this application during the first initialization stage;

[0044] Figure 9 The signal timing diagram of the pixel driving circuit provided in the embodiment of this application during the first initialization stage;

[0045] Figure 10 This is a schematic diagram comparing the parameters of related technologies with those of the embodiments of this application during the first initialization phase;

[0046] Figure 11 A schematic diagram of the pixel driving circuit provided in the embodiments of this application during the second initialization stage;

[0047] Figure 12 The signal timing diagram of the pixel driving circuit provided in the embodiment of this application during the second initialization stage;

[0048] Figure 13 This is a schematic diagram comparing the parameters of the relevant technologies and the embodiments of this application during the second initialization phase;

[0049] Figure 14 A schematic diagram of the pixel driving circuit provided in the embodiment of this application during the signal writing stage;

[0050] Figure 15 The signal timing diagram of the pixel driving circuit in the signal writing stage provided in the embodiments of this application;

[0051] Figure 16 This is a schematic diagram comparing the parameters of related technologies and embodiments of this application during the signal writing stage;

[0052] Figure 17 A schematic diagram of the pixel driving circuit provided in the embodiment of this application during the light emission stage;

[0053] Figure 18 This is a signal timing diagram of the pixel driving circuit during the light emission stage provided in an embodiment of this application. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0055] First, a brief explanation of the OLED (Organic Light-Emitting Diode) pixel driving circuit in related technologies will be given. For example... Figure 1 As shown, this is an OLED pixel driving circuit in the related technology, with a power supply voltage V. DD A continuous operating voltage is supplied to the OLED. The magnitude of the current flowing through the OLED is controlled by the gate voltage of transistor M1. The gate voltage of M1 is written by the data signal and stored in capacitor C1, ensuring continuous light emission within one scan cycle. The current flowing through the OLED is controlled by M1 and satisfies the following formula: Ids=1 / 2*W / L*μ*Cox*(Vgs-|Vth|). 2 .

[0056] Where Ids is the current flowing through the OLED, W and L are the width and length of the M1 channel, respectively, μ is the effective carrier mobility, Cox is the capacitance per unit area of ​​the gate oxide layer, Vth is the threshold voltage of M1, and Vgs is the gate-source voltage of M1.

[0057] Under current manufacturing processes, all transistors exhibit threshold voltage instability. Under prolonged pressure and high temperature, the threshold voltage drifts. Because different display images result in varying threshold voltage drift across different transistors on the display panel, leading to differences in display brightness and often manifesting as image retention. Therefore, compensation techniques are needed in the pixel drive circuit design to address this issue.

[0058] like Figure 2 As shown, the internal compensation circuit of the pixel driving circuit in related technologies consists of 7 transistors and 1 storage capacitor, hence it is simply referred to as a 7T1C structure. There are also many similar circuit structures such as 6T1C, 5T2C, 8T1C, 8T2C, and 9T2C. Among them, V... DD Vdata is the supply voltage, Vg is the data signal voltage, and Vg is the gate voltage of transistor T1. Pixel driving circuits typically operate in three phases: initialization, signal writing, and emission. The internal compensation circuit works by storing the threshold voltage Vth of transistor T1 within its gate-source voltage Vgs during the signal writing phase. During emission, Vgs-Vth is converted into current. Since Vgs already contains Vth, the effect of Vth is negated during current conversion, thus achieving current consistency. However, during capacitor initialization, the initial voltage written to the capacitor is a fixed value Vint, for example, -3V. Different pixel brightness corresponds to different data signal voltages, leading to different voltage drops across the capacitor plates for pixels of different brightness during compensation, resulting in poor uniformity of voltage compensation.

[0059] In order to enhance the uniformity of voltage compensation, embodiments of this application provide a display substrate, a driving method for a pixel driving circuit, and a display device.

[0060] Next, a display substrate provided in the embodiments of this application will be described in detail. See [link to relevant documentation]. Figure 3 The display substrate includes: a pixel driving circuit 1 and a light-emitting device 2; the pixel driving circuit 1 includes a compensation sub-circuit 11 and a control sub-circuit 12;

[0061] The reset signal input terminal of the compensation sub-circuit 11 is connected to the data signal voltage terminal, and the reset signal control terminal of the compensation sub-circuit 11 is connected to the first reset signal terminal; the first charging signal input terminal of the compensation sub-circuit 11 is connected to the first voltage terminal, and the first charging signal control terminal of the compensation sub-circuit 11 is connected to the first control signal terminal; the second charging signal input terminal of the compensation sub-circuit 11 is connected to the second voltage terminal, and the second charging signal control terminal of the compensation sub-circuit 11 is connected to the second control signal terminal; the control signal output terminal of the compensation sub-circuit 11 is connected to the first control terminal of the control sub-circuit 12; the compensation signal output terminal of the compensation sub-circuit 11 is connected to the compensation signal input terminal of the control sub-circuit 12, and the compensation signal control terminal of the compensation sub-circuit 11 is connected to the third control signal terminal.

[0062] The data signal input terminal of the control sub-circuit 12 is connected to the data signal voltage terminal, and the data signal control terminal of the control sub-circuit 12 is connected to the third control signal terminal; the second control terminal and the third control terminal of the control sub-circuit 12 are respectively connected to the fourth control signal terminal; the fixed voltage input terminal of the control sub-circuit 12 is connected to the third voltage terminal; and the data signal output terminal of the control sub-circuit 12 is connected to the first electrode of the light-emitting device 2.

[0063] The type of light-emitting device can be customized according to the actual situation. In one possible implementation, the light-emitting device is an OLED.

[0064] The reset signal input terminal of the compensation sub-circuit 11 is connected to the data signal voltage terminal. That is, during the initialization phase of the pixel driving circuit 1, the voltage input to the reset signal input terminal is the voltage of the data signal.

[0065] In the above embodiments, during the initialization phase of the pixel driving circuit, the original fixed Vint voltage (e.g., -3V) is replaced by the voltage of the written data signal so that the compensation voltage drop corresponding to each pixel with different brightness is basically the same during compensation, thereby enhancing the uniformity of voltage compensation.

[0066] In one possible implementation, see Figure 4 The compensation sub-circuit 11 includes a first transistor T1, a second transistor T2, an eighth transistor T8, a ninth transistor T9, and a capacitor Cst;

[0067] The gate of the first transistor T1 is connected to the first reset signal Reset n terminal. The first terminal of the first transistor T1 is connected to the second terminal of the capacitor Cst, the second terminal of the second transistor T2, and the control signal output terminal of the compensation sub-circuit 11. The second terminal of the first transistor T1 is connected to the reset signal input Vint terminal of the compensation sub-circuit 11.

[0068] The gate of the second transistor T2 is connected to the third control signal Sn terminal, and the first terminal of the second transistor T2 is connected to the compensation signal output terminal of the compensation sub-circuit 11.

[0069] The gate of the eighth transistor T8 is connected to the first control signal Vg-T8 terminal, and the first terminal of the eighth transistor T8 is connected to the first voltage Vg. DD1 The second terminal of the eighth transistor T8 is connected to the first terminal of the capacitor Cst and the second terminal of the ninth transistor T9, respectively.

[0070] The gate of the ninth transistor T9 is connected to the second control signal Vg-T9 terminal, and the first terminal of the ninth transistor T9 is connected to the second voltage Vg. DD2 End connection.

[0071] The gate of the first transistor T1 is connected to the first reset signal Reset n terminal. The first terminal of the first transistor T1 is connected to the second terminal of the capacitor Cst. The second terminal of the first transistor T1 is connected to the reset signal input Vint terminal of the compensation sub-circuit 11. The reset signal input terminal of the compensation sub-circuit 11 is connected to the data signal voltage Vdata terminal. That is to say, during the initialization phase of the pixel driving circuit, when initializing the capacitor Cst, the voltage written to the capacitor Cst is the data signal voltage Vdata.

[0072] In the above embodiments, when initializing the capacitor, the original fixed Vint voltage is replaced by the voltage of the written data signal, so that the voltage drop on the capacitor plates corresponding to different brightness pixels is basically the same during compensation, which can enhance the uniformity of voltage compensation.

[0073] In one possible implementation, see Figure 5 The control sub-circuit 12 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6;

[0074] The gate of the third transistor T3 is connected to the first control terminal of the control sub-circuit 12. The first terminal of the third transistor T3 is connected to the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5, respectively. The second terminal of the third transistor T3 is connected to the compensation signal input terminal of the control sub-circuit 12 and the first terminal of the sixth transistor T6, respectively.

[0075] The gate of the fourth transistor T4 is connected to the third control signal Sn terminal, and the first terminal of the fourth transistor T4 is connected to the data signal voltage Vdata terminal.

[0076] The gate of the fifth transistor T5 is connected to the fourth control signal EM terminal, and the first terminal of the fifth transistor T5 is connected to the third voltage V. DD End connection;

[0077] The gate of the sixth transistor T6 is connected to the fourth control signal EM terminal, and the second terminal of the sixth transistor T6 is connected to the first electrode of the light-emitting device OLED.

[0078] In the above embodiments, the control of data signal writing and light emission of the light-emitting device is realized through the control sub-circuit.

[0079] In one possible implementation, see Figure 6 The pixel driving circuit 1 further includes a reset sub-circuit 13, wherein the reset signal input terminal of the reset sub-circuit 13 is connected to the ground terminal GND, and the reset signal output terminal of the reset sub-circuit 13 is connected to the first electrode of the light-emitting device OLED.

[0080] The reset sub-circuit is used to reset the OLED light-emitting device so that the OLED light-emitting device is restored to its original state.

[0081] In one possible implementation, see Figure 7 The reset sub-circuit 13 includes a seventh transistor T7;

[0082] The gate of the seventh transistor T7 is connected to the second reset signal Reset n+1 terminal, the first terminal of the seventh transistor T7 is connected to the first electrode of the light-emitting device OLED, and the second terminal of the seventh transistor T7 is connected to the ground terminal GND.

[0083] The second electrode of the light-emitting device OLED is connected to the low voltage terminal V. SS connect.

[0084] In the above embodiments, the light-emitting device is reset by a reset sub-circuit, so that the light-emitting device is restored to its original state.

[0085] This application embodiment also provides a driving method for a pixel driving circuit, used to drive any of the pixel driving circuits 1 described in the above embodiments, the driving method comprising:

[0086] In the first initialization phase, the first reset signal Reset n outputs a first voltage signal; the first control signal Vg-T8 outputs a first voltage signal; the reset signal input outputs a first voltage signal; the data signal voltage Vdata outputs a first voltage signal; the third control signal Sn outputs a second voltage signal; the second reset signal Reset n+1 outputs a second voltage signal; the fourth control signal EM outputs a second voltage signal; and the second control signal Vg-T9 outputs a second voltage signal.

[0087] In the second initialization phase, the first reset signal Reset n outputs a second voltage signal; the first control signal Vg-T8 outputs a second voltage signal; the reset signal input outputs a first voltage signal; the data signal voltage Vdata outputs a first voltage signal; the third control signal Sn outputs a second voltage signal; the second reset signal Reset n+1 outputs a second voltage signal; the fourth control signal EM outputs a second voltage signal; and the second control signal Vg-T9 outputs a first voltage signal.

[0088] During the signal writing phase, the first reset signal Reset n outputs a second voltage signal; the first control signal Vg-T8 outputs a second voltage signal; the reset signal input outputs a second voltage signal; the data signal voltage Vdata outputs a second voltage signal; the third control signal Sn outputs a first voltage signal; the second reset signal Reset n+1 outputs a first voltage signal; the fourth control signal EM outputs a second voltage signal; and the second control signal Vg-T9 outputs a first voltage signal.

[0089] During the light-emitting phase, the first reset signal Reset n terminal outputs a second voltage signal; the first control signal Vg-T8 terminal outputs a second voltage signal; the reset signal input terminal outputs a second voltage signal; the data signal voltage Vdata terminal outputs a second voltage signal; the third control signal Sn terminal outputs a second voltage signal; the second reset signal Reset n+1 terminal outputs a second voltage signal; the fourth control signal EM terminal outputs a first voltage signal; and the second control signal Vg-T9 terminal outputs a first voltage signal.

[0090] The first voltage signal and the second voltage signal are signals with opposite high and low levels.

[0091] In the above embodiments, the working state of the pixel driving circuit at different stages is controlled by outputting different voltage signals at different stages.

[0092] In one possible implementation, each transistor is a P-type transistor; the first voltage signal is low and the second voltage signal is high.

[0093] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all P-type transistors;

[0094] The first terminal of the first transistor T1 is the source of the P-type transistor, and the second terminal of the first transistor T1 is the drain of the P-type transistor.

[0095] The first terminal of the second transistor T2 is the source of the P-type transistor, and the second terminal of the second transistor T2 is the drain of the P-type transistor.

[0096] The first terminal of the third transistor T3 is the source of the P-type transistor, and the second terminal of the third transistor T3 is the drain of the P-type transistor.

[0097] The first terminal of the fourth transistor T4 is the source of the P-type transistor, and the second terminal of the fourth transistor T4 is the drain of the P-type transistor.

[0098] The first terminal of the fifth transistor T5 is the source of the P-type transistor, and the second terminal of the fifth transistor T5 is the drain of the P-type transistor.

[0099] The first terminal of the sixth transistor T6 is the source of the P-type transistor, and the second terminal of the sixth transistor T6 is the drain of the P-type transistor.

[0100] The first terminal of the seventh transistor T7 is the source of the P-type transistor, and the second terminal of the seventh transistor T7 is the drain of the P-type transistor.

[0101] The first terminal of the eighth transistor T8 is the source of the P-type transistor, and the second terminal of the eighth transistor T8 is the drain of the P-type transistor.

[0102] The first terminal of the ninth transistor T9 is the source of the P-type transistor, and the second terminal of the ninth transistor T9 is the drain of the P-type transistor.

[0103] It is understood that any transistor in the circuit of this application can be an N-type transistor or a P-type transistor, whichever is chosen according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal. It is understood that the transistor can be a P-type transistor or an N-type transistor, whichever is chosen according to the actual situation, but the device connection method of the circuit needs to be adjusted accordingly, and the alternative solution is still within the protection scope of this application.

[0104] It is understood that the transistors used in the circuit of this application can be MOS transistors (metal-oxide-semiconductor field-effect transistors), TFT transistors (thin film transistors), or other types of transistors. The specific choice can be made according to the actual situation. The alternative solutions are still within the protection scope of this application. The connection method of TFT transistors or other types of transistors can be referred to the connection method of MOS transistors, which will not be repeated here.

[0105] In the above embodiments, the switching of each P-type transistor is controlled by different voltage signals to control the working state of the pixel driving circuit at different stages.

[0106] The first voltage signal is at a low level, and the second voltage signal is at a high level.

[0107] In one possible implementation, the first voltage V DD1 and the second voltage V DD2 Satisfy: V DD1 -V DD2 >|Vth|; where Vth is the threshold voltage of the third transistor.

[0108] In one possible implementation, the third voltage V DD The range is 3V-7V. In one example, the range of Vdata could be 2-4.5V.

[0109] First voltage V DD1 and the second voltage V DD2 It can be configured according to the actual product requirements to meet V. DD1 -V DD2 >|Vth| is sufficient, the third voltage V DD The range can be 3V-7V, for example, the third voltage V. DD It can be set to 4.6V.

[0110] The driving method of pixel driving circuit 1 is described in detail below:

[0111] See Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the pixel driving circuit during the first initialization stage. Figure 9 This is the signal timing diagram of the pixel driving circuit during the first initialization phase. During the first initialization phase, the first reset signal Reset n is low, the first transistor T1 is turned on, resetting capacitor Cst. The reset signal input Vint is low, the data signal voltage Vdata is low, and Vint = Vdata. Therefore, the voltage at the second terminal of capacitor Cst is Vg = Vdata (the second terminal of capacitor Cst is connected to the gate of the third transistor T3, and Vg is the gate voltage of the third transistor T3). The first control signal Vg-T8 is low, the eighth transistor T8 is turned on, charging capacitor Cst. The second control signal Vg-T9 is high, the ninth transistor T9 is turned off, and the voltage at the first terminal of capacitor Cst is Vg = Vdata. DD1 The voltage drop across capacitor Cst is V. DD1 -Vdata.

[0112] When the third control signal Sn is high, the second transistor T2 and the fourth transistor T4 are turned off; when the second reset signal Reset n+1 is high, the seventh transistor T7 is turned off; when the fourth control signal EM is high, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0113] See Figure 10 This is a schematic diagram comparing the parameters of related technologies with those of the embodiments of this application during the first initialization phase. In one example, the first voltage V... DD1 It can be 4.6V, the second voltage V DD2 It can be 2.0V. In related technologies, Vint is -3V, V DD1 It is 4.6V, no V DD2 Vg is -3V. In this embodiment, Vint is replaced by Vdata, V DD1 4.6V, V DD2 The voltage is 2.0V, and Vg is Vdata. The data signal voltage Vdata replaces the original Vint (-3V). At the end of the first initialization phase, the gate voltage of the third transistor T3 is Vg = Vdata.

[0114] See Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the pixel driving circuit during the second initialization phase. Figure 12This is the signal timing diagram of the pixel driving circuit during the second initialization phase. During the second initialization phase, the first reset signal Reset n is high, the first transistor T1 is off, the first control signal Vg-T8 is high, the eighth transistor T8 is off, the second control signal Vg-T9 is low, and the ninth transistor T9 is on, charging capacitor Cst. The voltage across the first terminal of capacitor Cst is V. DD2 According to the voltage drop across capacitor Cst during the first initialization phase, which is V DD1 -Vdata, In the second initialization phase, the voltage across the second terminal of capacitor Cst is Vg = V DD2 -(V DD1 -Vdata)=Vdata-(V DD1 -V DD2 ).

[0115] When the third control signal Sn is high, the second transistor T2 and the fourth transistor T4 are turned off; when the second reset signal Reset n+1 is high, the seventh transistor T7 is turned off; when the fourth control signal EM is high, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0116] See Figure 13 This is a schematic diagram comparing the parameters of related technologies with those of the embodiments of this application during the second initialization phase. In one example, the first voltage V... DD1 It can be 4.6V, the second voltage V DD2 It can be 2.0V. In the second initialization stage of the related technology, Vint is -3V, V DD1 It is 4.6V, no V DD2 Vg is -3V. In the second initialization stage of this application embodiment, there is no Vint, V DD1 It is 4.6V, V DD2 It is 2.0V, and Vg is Vdata-(V DD1 -V DD2 The data signal voltage Vdata replaces the original Vint (-3V). After the second initialization phase, the gate voltage Vg of the third transistor T3 is Vdata - (V...). DD1 -V DD2 ).

[0117] See Figure 14 and Figure 15 , Figure 14 This is a schematic diagram of the pixel driving circuit during the signal writing stage. Figure 15 This is a timing diagram of the pixel driving circuit during the signal writing phase. During the signal writing phase, the first transistor T1 and the eighth transistor T8 are off, the ninth transistor T9 is on, and the voltage across the first terminal of capacitor Cst is V. DD2The voltage across the second terminal of capacitor Cst is Vg = Vdata - (V DD1 -V DD2 When the third control signal Sn is low, the fourth transistor T4 is turned on; the gate-source voltage of the third transistor T3 is Vgs = Vg - Vdata = Vdata - (V DD1 -V DD2 )-Vdata=-(V DD1 -V DD2 ), due to V DD1 -V DD2 >|Vth|, the third transistor T3 is turned on; the second transistor T2 is turned on. The second reset signal Reset n+1 is low, and the seventh transistor T7 is turned on, which is used to reset the OLED light-emitting device. In one example, the voltage value of Reset can be -6V.

[0118] During the signal writing stage, the data signal voltage Vdata and the threshold voltage Vth of the third transistor T3 are written to the capacitor Cst through the second transistor T2 to compensate for the threshold voltage of the third transistor T3 (after compensation, the gate voltage Vg of the third transistor T3 = Vdata + Vth). The specific principle is explained in the above analysis of related technologies, and will not be repeated here.

[0119] See Figure 16 This is a schematic diagram comparing parameters of related technologies and embodiments of this application during the signal writing stage. In one example, the first voltage V... DD1 It can be 4.6V, the second voltage V DD2 The voltage can be 2.0V. In the signal writing stage of related technologies, before signal writing (compensation), Vg' is -3V; after signal writing (compensation), Vg is Vdata + Vth; the compensation voltage drop ΔV = Vg - Vg' = Vdata + Vth + 3V. In the signal writing stage of this application embodiment, before signal writing (compensation), Vg' is Vdata - 2.6V; after signal writing (compensation), Vg is Vdata + Vth; the compensation voltage drop ΔV = Vg - Vg' = Vth + 2.6V. The voltage Vdata of the data signal replaces the original Vint (-3V). After the signal writing stage ends, the gate voltage of the third transistor T3 is Vg = Vdata + Vth, and the compensation voltage drop ΔV = Vg - Vg' = Vth + 2.6V.

[0120] During compensation, the voltage drop during the discharge process of capacitor Cst is uniformly Vth + 2.6V. After discharge, the voltage retained at the second terminal of capacitor Cst is still Vdata + Vth, which contains the data signal. Subsequently, the brightness of the light is precisely controlled through the data signal.

[0121] pass Figure 16A comparison reveals that in this embodiment, the voltage drop is essentially the same for each pixel with different brightness levels, meaning the discharge amount is essentially the same, which enhances the uniformity of voltage compensation. The compensation voltage drop Vth+2.6V is reduced compared to the compensation voltage drop Vdata+Vth+3V in related technologies, improving compensation efficiency. Because the compensation voltage drop is reduced, the timing length of the signal writing stage can be shortened, thereby increasing the upper frequency limit. Furthermore, compensation can be completed even at low grayscale levels.

[0122] See Figure 17 and Figure 18 , Figure 17 This is a schematic diagram of the pixel driving circuit during the light-emitting stage. Figure 18 This is the signal timing diagram of the pixel driving circuit during the light-emitting stage. During the light-emitting stage, the first transistor T1 is off, the eighth transistor T8 is off, the ninth transistor T9 is on, and the voltage across the first terminal of capacitor Cst is V. DD2 The voltage at the second terminal of capacitor Cst is Vg = Vdata + Vth. When the third control signal Sn is high, the second transistor T2 and the fourth transistor T4 are turned off; when the second reset signal Reset n+1 is high, the seventh transistor T7 is turned off; when the fourth control signal EM is low, the fifth transistor T5 and the sixth transistor T6 are turned on. The gate-source voltage of the third transistor T3 is Vgs = Vdata + Vth - V DD Through Vdata and V DD The value of VDD ensures that the third transistor T3 is turned on. The third voltage VDD provides the operating voltage for the OLED light-emitting device. The magnitude of the current flowing through the OLED is controlled by the gate voltage of the third transistor T3, satisfying the following formula: Ids=1 / 2*W / L*μ*Cox*(Vgs-|Vth|). 2 , that is, Ids=1 / 2*W / L*μ*Cox*(Vdata+Vth-V DD -|Vth|) 2 Therefore, the effect of Vth is offset, thus achieving current uniformity.

[0123] In the above embodiments, during the initialization phase of the pixel driving circuit, the original fixed Vint voltage is replaced by the voltage of the written data signal. This ensures that the compensation voltage drop for pixels with different brightness levels is essentially the same during compensation, enhancing the uniformity of voltage compensation. The compensation voltage drop Vth+2.6V is reduced compared to the compensation voltage drop Vdata+Vth+3V in related technologies, improving compensation efficiency. Because the compensation voltage drop is reduced, the timing length of the signal writing phase can be shortened, thereby increasing the upper frequency limit.

[0124] This application embodiment also provides a display device, the display device comprising:

[0125] The display substrate as described in any of the above embodiments.

[0126] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0127] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0128] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display substrate, characterized by, The display substrate comprises: A pixel driving circuit and a light emitting device; the pixel driving circuit comprises a compensation sub-circuit, a control sub-circuit; The reset signal input end of the compensation sub-circuit is connected with the data signal voltage end, the reset signal control end of the compensation sub-circuit is connected with the first reset signal end; the first charging signal input end of the compensation sub-circuit is connected with the first voltage end, the first charging signal control end of the compensation sub-circuit is connected with the first control signal end; the second charging signal input end of the compensation sub-circuit is connected with the second voltage end, the second charging signal control end of the compensation sub-circuit is connected with the second control signal end; the control signal output end of the compensation sub-circuit is connected with the first control end of the control sub-circuit; the compensation signal output end of the compensation sub-circuit is connected with the compensation signal input end of the control sub-circuit, the compensation signal control end of the compensation sub-circuit is connected with the third control signal end; The data signal input end of the control sub-circuit is connected with the data signal voltage end, the data signal control end of the control sub-circuit is connected with the third control signal end; the second control end and the third control end of the control sub-circuit are respectively connected with the fourth control signal end; the fixed voltage input end of the control sub-circuit is connected with the third voltage end; the data signal output end of the control sub-circuit is connected with the first electrode of the light emitting device.

2. The display substrate of claim 1, wherein, The compensation sub-circuit comprises a first transistor, a second transistor, an eighth transistor, a ninth transistor and a capacitor; The gate of the first transistor is connected with the first reset signal end, the first end of the first transistor is connected with the second end of the capacitor, the second end of the second transistor and the control signal output end of the compensation sub-circuit respectively, and the second end of the first transistor is connected with the reset signal input end of the compensation sub-circuit; The gate of the second transistor is connected with the third control signal end, and the first end of the second transistor is connected with the compensation signal output end of the compensation sub-circuit; The gate of the eighth transistor is connected with the first control signal end, the first end of the eighth transistor is connected with the first voltage end, and the second end of the eighth transistor is connected with the first end of the capacitor and the second end of the ninth transistor respectively; The gate of the ninth transistor is connected with the second control signal end, and the first end of the ninth transistor is connected with the second voltage end. 3.The display substrate of claim 1, wherein, The control sub-circuit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; The gate of the third transistor is connected with the first control end of the control sub-circuit, the first end of the third transistor is connected with the second end of the fourth transistor and the second end of the fifth transistor respectively, and the second end of the third transistor is connected with the compensation signal input end of the control sub-circuit and the first end of the sixth transistor respectively; The gate of the fourth transistor is connected with the third control signal end, and the first end of the fourth transistor is connected with the data signal voltage end; The gate of the fifth transistor is connected with the fourth control signal end, and the first end of the fifth transistor is connected with the third voltage end; The gate of the sixth transistor is connected with the third control signal end. The gate of the sixth transistor is connected with the fourth control signal end, and the second end of the sixth transistor is connected with the first electrode of the light emitting device.

4. The display substrate of claim 1, wherein, The pixel driving circuit further comprises a reset sub-circuit, a reset signal input end of the reset sub-circuit is connected with the ground end, and a reset signal output end of the reset sub-circuit is connected with the first electrode of the light emitting device.

5. The display substrate of claim 4, wherein, The reset sub-circuit comprises a seventh transistor. The gate of the seventh transistor is connected with a second reset signal end, the first end of the seventh transistor is connected with the first electrode of the light emitting device, and the second end of the seventh transistor is connected with the ground end.

6. A driving method of a pixel driving circuit, characterized by, The driving method for driving the pixel driving circuit in any of claims 1-5 comprises: In a first initialization stage, the first reset signal end outputs a first voltage signal; the first control signal end outputs the first voltage signal; the reset signal input end outputs the first voltage signal; the data signal voltage end outputs the first voltage signal; the third control signal end outputs a second voltage signal; the second reset signal end outputs the second voltage signal; the fourth control signal end outputs the second voltage signal; and the second control signal end outputs the second voltage signal; wherein the second reset signal end is connected with the gate of the seventh transistor of the reset sub-circuit in the pixel driving circuit; In a second initialization stage, the first reset signal end outputs the second voltage signal; the first control signal end outputs the second voltage signal; the reset signal input end outputs the first voltage signal; the data signal voltage end outputs the first voltage signal; the third control signal end outputs the second voltage signal; the second reset signal end outputs the second voltage signal; the fourth control signal end outputs the second voltage signal; and the second control signal end outputs the first voltage signal; In a signal writing stage, the first reset signal end outputs the second voltage signal; the first control signal end outputs the second voltage signal; the reset signal input end outputs the second voltage signal; the data signal voltage end outputs the second voltage signal; the third control signal end outputs the first voltage signal; the second reset signal end outputs the first voltage signal; the fourth control signal end outputs the second voltage signal; and the second control signal end outputs the first voltage signal; In a light emitting stage, the first reset signal end outputs the second voltage signal; the first control signal end outputs the second voltage signal; the reset signal input end outputs the second voltage signal; the data signal voltage end outputs the second voltage signal; the third control signal end outputs the second voltage signal; the second reset signal end outputs the second voltage signal; the fourth control signal end outputs the first voltage signal; and the second control signal end outputs the first voltage signal; The first voltage signal and the second voltage signal are signals with opposite high and low levels.

7. The driving method according to claim 6, wherein Each transistor is a P-type transistor; the first voltage signal is a low level, and the second voltage signal is a high level.

8. The driving method according to claim 7, wherein The first voltage V DD1 The second voltage V DD2 Satisfies: V DD1 -V DD2 >|Vth|; wherein Vth is a threshold voltage of the third transistor.

9. The driving method according to claim 8, wherein The third voltage V DD ranges from 3V to 7V.

10. A display device, characterized by comprising: The display device comprises: The display substrate as claimed in any of the above claims 1-5.

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