Memory and method of manufacturing memory

Abstract

The embodiment of the present application relates to the field of memory, and provides a memory and a manufacturing method of the memory, and at least the efficiency of voltage conversion can be improved.The memory comprises a substrate, the substrate has a package shell, the package shell and the substrate form a closed area, a chip has a load on the chip, the chip is located in the closed area, a boost converter, at least part of structures in the boost converter are integrated on the chip, the boost converter is used to provide voltage to the load, the boost converter at least comprises an inductor and a switch welding point, the inductor comprises opposite first and second ends, the second end of the inductor is electrically connected with the switch welding point, the switch welding point is integrated on the chip, and the boost converter is located in the closed area.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a memory and a method for manufacturing the memory. Background Technology

[0002] The memory chip requires multiple internal power supplies for different purposes. These internal power supplies are usually obtained by boosting or bucking the external input voltage using a charge pump.

[0003] The working principle of a charge pump is as follows: charging a capacitor allows it to store energy; discharging the capacitor allows it to provide energy to the load, maintaining the load's operation. However, the equivalent series resistance of the capacitor in current charge pumps is relatively large, resulting in low efficiency.

[0004] Therefore, there is an urgent need for a high-efficiency boost converter to convert the external input voltage and thus provide voltage to the load. Summary of the Invention

[0005] This application provides a memory and a method for manufacturing the memory, which at least helps to improve the efficiency of converting external input voltage.

[0006] According to some embodiments of this application, one aspect of this application provides a memory, comprising: a substrate having a package shell on the substrate, the package shell and the substrate forming a closed region; a chip having a load on the chip; the chip being located within the closed region; a boost converter having at least a portion of its structure integrated on the chip, the boost converter being used to provide voltage to the load; the boost converter including at least an inductor and a switch solder joint, the inductor including a first end and a second end opposite to each other, the second end of the inductor being electrically connected to the switch solder joint, the switch solder joint being integrated on the chip; the boost converter being located within the closed region.

[0007] According to some embodiments of this application, another aspect of this application provides a method for manufacturing a memory, comprising: providing a substrate; mounting a chip and a boost converter on the substrate, the chip having a load; at least a portion of the structure of the boost converter being integrated on the chip, the boost converter being used to provide voltage to the load; the boost converter including at least an inductor and a switch solder joint, the inductor including opposing first and second ends, the second end of the inductor being electrically connected to the switch solder joint, and the switch solder joint being integrated on the chip; mounting a package on the substrate, the package and the substrate forming a closed region, and the chip and the boost converter being located within the closed region.

[0008] The technical solution provided in this application has at least the following advantages: It utilizes a boost converter with an inductor to provide energy to the load; the inductor's equivalent series resistance is small, thus improving efficiency. Furthermore, the inductor and chip are located within the enclosed area formed by the package and the substrate, meaning the inductor and chip are packaged together. Therefore, the inductor and chip are close together, which reduces trace resistance and further improves efficiency. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0010] Figure 1 A schematic diagram of a memory provided according to an embodiment of this application;

[0011] Figure 2 A schematic diagram of another memory provided in an embodiment of this application;

[0012] Figure 3 for Figure 2 A sectional view;

[0013] Figure 4 This is a schematic diagram of a boost converter in a memory provided in an embodiment of this application. Detailed Implementation

[0014] As the background technology indicates, there is an urgent need for a high-efficiency boost converter to convert external input voltage. Analysis has revealed that, in addition to the type of boost converter itself, the packaging of the boost converter and the chip also affects the voltage conversion efficiency. For example, if the traces between the boost converter and the chip are too long, it will increase resistance and reduce efficiency.

[0015] This application provides a memory, including: a substrate and a package, the package and the substrate forming a closed region; a chip and a boost converter, the chip and the boost converter being located within the closed region, the boost converter including an inductor. Compared to the capacitor of a charge pump, the inductor has a smaller equivalent series resistance, which can improve the efficiency of the boost converter. Furthermore, compared to packaging the chip and inductor separately, packaging the chip and inductor together can reduce the trace length between them, thereby reducing resistance and improving efficiency.

[0016] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0017] One embodiment of this application provides a memory, with reference to... Figures 1 to 4 The memory includes: a substrate 100, on which a package shell 110 is provided, the package shell 110 and the substrate 100 forming a closed region; a chip 200, on which a load 201 is provided; the chip 200 is located within the closed region 120; a boost converter 300, at least a portion of the structure of the boost converter 300 is integrated on the chip 200, the boost converter 300 is used to provide voltage to the load 201; the boost converter 300 includes at least an inductor 306 and a switch solder joint 301, the inductor 306 includes a first end 316 and a second end 326 opposite to each other, the second end 326 of the inductor 306 is electrically connected to the switch solder joint 301, the switch solder joint 301 is integrated on the chip 200; the boost converter 300 is located within the closed region 120. The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0018] refer to Figure 1 The substrate 100 can include three main types: rigid substrate, flexible thin film substrate, and co-fired ceramic substrate. The substrate 100 can protect, fix, and support the chip 200 and the inductor 306, and enhance the thermal conductivity and heat dissipation performance of the chip 200 and the inductor 306. In addition, the upper layer of the substrate 100 is connected to the chip 200, and the lower layer is connected to the printed circuit board to realize electrical and physical connections and signal distribution, thereby communicating the internal and external circuits of the chip 200.

[0019] Package 110 (reference) Figure 3 The material can be ceramic, metal or plastic. The encapsulation shell 110 and the substrate 100 form a closed area and together they protect the chip 200 and the boost converter 300.

[0020] Chip 200 can be a dynamic random access memory (DRAM) chip. Accordingly, the load 201 on chip 200 can be a word line driver circuit, and boost converter 300 is used to provide the turn-on voltage for the word lines. In this case, the input voltage of boost converter 300 is 1.2V, and the output voltage of boost converter 300 is 3V. In some other embodiments, load 201 can be an equalization circuit, and boost converter 300 is used to enable the equalization circuit so that the voltages of the bit lines and complementary bit lines are equal. In this case, the input voltage of boost converter 300 is 1.2V, and the output voltage of boost converter 300 is 1.5V.

[0021] The inductor 306 in the boost converter 300 is charged, allowing it to store energy; the inductor 306 is also discharged, providing energy to the load 201. The inductor 306 has a low equivalent series resistance, which improves the conversion efficiency of the boost converter 300.

[0022] Both inductor 306 and chip 200 are located within an enclosed area. The relative positions of inductor 306 and chip 200 within this enclosed area primarily include two examples. Example 1: inductor 306 is integrated onto chip 200; Example 2: inductor 306 is independent of chip 200. These two examples will be explained in detail below.

[0023] Specifically, refer to Figure 1 Example 1: Inductor 306 is integrated on chip 200; substrate 100 is provided with input voltage pin 101, chip 200 is provided with input voltage solder joint 307, first conductive layer 336 and second conductive layer 346; input voltage pin 101 is electrically connected to input voltage solder joint 307; first end 316 of inductor 306 is electrically connected to input voltage solder joint 307 through first conductive layer 336; second end 326 of inductor 306 is electrically connected to switch solder joint 301 through second conductive layer 346.

[0024] The input voltage pin 101 is connected to an external input power supply. Therefore, the input voltage solder joint 307 is electrically connected to the input voltage pin 101 to access an external input power supply, thereby providing operating voltage for the boost converter 300 and the chip 200. In some embodiments, the input voltage pin 101 can be electrically connected to the input voltage solder joint 307 by means of solder ball soldering or wire connection.

[0025] The inductor 306, the first conductive layer 336, and the second conductive layer 346 can be made of metals such as copper, gold, silver, or aluminum. The chip 200 has a metal wiring layer. The inductor 306, the first conductive layer 336, and the second conductive layer 346 can be formed using the same process as the metal wiring layer, thereby reducing process difficulty and shortening process time.

[0026] Compared to inductor 306 being located outside the enclosed area, inductor 306 is integrated onto chip 200, which reduces the distance between inductor 306 and the load of chip 200, thereby reducing trace resistance and further improving the efficiency of boost converter 300. In other words, the manufacturing process of inductor 306 in boost converter 300 can be integrated with the manufacturing process of chip 200, thus simplifying the process and reducing package size.

[0027] refer to Figures 2-3 , Figure 3 for Figure 2The cross-sectional view is shown, with the cross-sectional direction perpendicular to the top surface of the substrate 100. Example 2: Inductor 306 is independent of chip 200 and is formed using a redistribution layer process; input voltage pin 101 is provided on substrate 100; a first interconnect structure 400 and a second interconnect structure 420 are also provided within the enclosed region 120; the first end 316 of inductor 306 is electrically connected to input voltage pin 101 through the first interconnect structure 400; the second end 326 of inductor 306 is electrically connected to switch solder joint 301 through the second interconnect structure 420. That is, inductor 306 and chip 200 can be formed separately and electrically connected.

[0028] Redistribution layer technology refers to depositing metal and dielectric layers on a substrate surface to form corresponding metal wiring patterns, thereby rearranging the chip's I / O ports to new areas with more flexible pitch. Using redistribution layer technology to form inductors allows for compatibility between inductor manufacturing processes and chip packaging processes, improving packaging convenience and reducing package size.

[0029] In some embodiments, chip 200 and inductor 306 are stacked, with inductor 306 located above chip 200. The first interconnect structure 400 includes a first solder ball 401, a conductive via 403, and a second solder ball 402 connected sequentially. The first solder ball 401 is located between inductor 306 and chip 200 and is electrically connected to a first end 316 of inductor 306. The conductive via 403 is located within chip 200 and penetrates through chip 200, with the top and bottom surfaces of the conductive via 403 exposed. The second solder ball 402 is located between chip 200 and substrate 100 and is electrically connected to input voltage pin 101.

[0030] The second interconnection structure 420 includes a third solder ball that electrically connects the second terminal 326 of the inductor 306 to the switch solder joint 301.

[0031] In some other embodiments, the inductor 306 may also be in contact with the substrate 100, that is, the inductor 306 and the chip 200 are disposed side by side on the substrate 100; accordingly, the first end 316 of the inductor 306 is soldered to the input voltage pin 101 of the substrate 100 by solder balls, that is, the first interconnection structure is solder balls; the second end 326 of the inductor 306 is electrically connected to the switch solder joint 301 on the chip 200 by a lead, that is, the second interconnection structure is a lead.

[0032] In the two examples above, both chip 200 and boost converter 300 are located in the enclosed area formed by substrate 100 and package 110, which helps to shorten the trace distance between chip 200 and boost converter 300 and improve efficiency.

[0033] refer to Figure 4 , Figure 4 The diagram shows a boost converter, which also includes an input terminal 308, a switching transistor 302, a freewheeling unit 303, an output capacitor 304, and an output terminal 305. The input terminal 308 is used to receive an external input voltage. The switching transistor 302, the freewheeling unit 303, and the output capacitor 304 are all integrated on the chip 200. The input terminal 308, the inductor 306, the switch solder joint 301, and the switching transistor 302 are connected in sequence, and one end of the switching transistor 302 is connected to ground. The input terminal 308, the inductor 306, the switch solder joint 301, the freewheeling unit 303, and the output terminal 305 are connected in sequence. The output terminal 305 is also connected to the load 201 and provides voltage to the load 201. One end of the output capacitor 304 is connected to the output terminal 305, and the other end of the output capacitor 304 is connected to ground.

[0034] Switch 302 can be a MOSFET. Since a MOSFET is formed during the manufacturing process of chip 200 itself, switch 302 can be formed in the same process as the MOSFET on chip 200, thereby simplifying the manufacturing process.

[0035] In some embodiments, the freewheeling unit 303 may be a freewheeling diode. In other embodiments, the freewheeling unit 303 may also be a MOSFET, thereby being formed in the same process as the MOSFET on chip 200.

[0036] The output capacitor 304 includes an upper electrode and a lower electrode, and the upper electrode and / or the lower electrode includes titanium nitride-doped material. Thus, a large capacitance value can be obtained with a small area of ​​the upper electrode and / or the lower electrode, thereby improving the filtering effect on the output voltage.

[0037] The boost converter operates through charging and discharging processes. During charging, the switching transistor 302 is turned on, essentially connecting the drain and source terminals of the MOSFET directly with a wire. Current flows through the input terminal 308, inductor 306, and switching transistor 302. As charging continues, the current in inductor 306 increases linearly, storing energy over time. During this process, the freewheeling unit 303 is reverse-biased and cut off, while the output capacitor 304 provides energy to the load 201, maintaining its operation.

[0038] The discharge process of the boost converter: When the switching transistor 302 is not conducting, it is equivalent to being open. Due to the back electromotive force of the inductor 306, the current in the inductor 306 cannot change instantaneously, but will discharge slowly and gradually. Since the charging circuit has been broken, the inductor 306 can only discharge through the circuit of the freewheeling unit 303, the load 201, and the output capacitor 304. That is, the inductor 306 begins to charge the output capacitor 304. Since the output capacitor 304 already provides voltage to the load 201 before charging the output capacitor 304, the voltage across the output capacitor 304 increases, that is, the voltage at the output terminal 305 of the boost converter increases.

[0039] In some embodiments, the boost converter further includes a switching transistor control circuit connected to the switching transistor 302 for controlling the switching transistor 302 to open or close. The switching transistor control circuit includes a driver circuit 506, an RS flip-flop 505, a comparator 504, an error amplifier 503, a first voltage divider resistor 501, and a second voltage divider resistor 502. The switching transistor control circuit will be described in detail below.

[0040] One end of the first voltage divider resistor 501 is connected to the output terminal 305 of the boost converter, and the other end of the first voltage divider resistor 501 is connected to one end of the second voltage divider resistor 502. The other end of the second voltage divider resistor 502 is connected to ground. The first input terminal of the error amplifier 503 is connected between the first voltage divider resistor 501 and the second voltage divider resistor 502. The second input terminal of the error amplifier 503 is connected to the reference voltage VREF. The output terminal of the error amplifier 503 is connected to the first input terminal of the comparator 504. The second input terminal of the comparator 504 receives a triangular wave signal. The output terminal of the comparator 504 is connected to the R terminal of the RS flip-flop 505. The S terminal of the RS flip-flop 505 receives a clock signal. The Q terminal of the RS flip-flop 505 is connected to the input terminal of the drive circuit 506. The output terminal of the drive circuit 506 is connected to the gate of the switching transistor 302.

[0041] The output voltage of output terminal 305 is divided by the first voltage divider resistor 501 and the second voltage divider resistor 502, and then compared with the reference voltage VREF to obtain the voltage difference. The voltage difference is amplified by the error amplifier 503 and then input to the first input terminal of comparator 504. The triangular wave signal received at the second input terminal of comparator 504 is a ramp-up voltage generated by the clock. Comparator 504 compares the input voltage at the first input terminal and the ramp-up voltage at the second input terminal. When the ramp-up voltage is greater than the input voltage at the first input terminal, comparator 504 outputs a pulse voltage to the R terminal of the RS flip-flop.

[0042] In some embodiments, when the switching transistor 302 is an NMOS, when the S-terminal of the RS flip-flop receives a clock pulse, the Q-terminal outputs a high level; when the R-terminal receives a pulse, the Q-terminal outputs a low level. Therefore, the output of the Q-terminal alternates between high and low levels, and the duty cycle is determined by the timing of the pulses received by the R-terminal and S-terminal. When the Q-terminal outputs a high level, the driver circuit 506 also maintains a high level, which turns on the gate of the NMOS transistor 302. When the Q-terminal outputs a low level, the switching transistor 302 is turned off.

[0043] Because the gate resistance of switch 302 is relatively large, the RS flip-flop's driving capability is insufficient to drive switch 302. Therefore, the driving capability can be enhanced through drive circuit 506. Within one cycle, the larger the voltage difference, the longer the switch 302 is on, and the larger the current through inductor 306, resulting in more energy to adjust the output voltage of the boost converter.

[0044] In summary, using an inductive boost converter is beneficial for improving voltage conversion efficiency, and the integration of inductor 306 with chip 200 reduces trace resistance, further enhancing efficiency.

[0045] Another embodiment of this application provides a method for manufacturing a memory, which can be used to manufacture the memory provided in the foregoing embodiments. The method for manufacturing the memory is described in detail below.

[0046] refer to Figures 1-3 A substrate 100 is provided; the material of the substrate 100 may include resin, alumina, aluminum nitride, silicon carbide, etc.

[0047] A chip 200 and a boost converter 300 are mounted on a substrate 100. The chip 200 has a load 201. At least a portion of the structure of the boost converter 300 is integrated on the chip 200. The boost converter 300 is used to provide voltage to the load 201. The boost converter 300 includes at least an inductor 306 and a switch solder joint 301. The inductor 306 includes a first end 316 and a second end 326 opposite to each other. The second end 326 of the inductor 306 is electrically connected to the switch solder joint 301, and the switch solder joint 301 is integrated on the chip 200.

[0048] As can be seen from the foregoing embodiments, the inductor 306 of the boost converter 300 can be integrated onto the chip 200 or independent of the chip 200. Accordingly, different forming methods are required to manufacture the inductor 306.

[0049] Example 1: An inductor 306 is formed on a chip 200 using a process for forming a metal wiring layer within the chip 200. Specifically, an initial metal layer is deposited across the entire surface of the chip; the initial metal layer can be formed by electroplating or physical vapor deposition. The initial metal layer is patterned to form the inductor 306; the patterning method can be dry etching. A dielectric layer is formed covering the inductor 306, with the dielectric layer exposing the first end 316 and the second end 326 of the inductor 306. The dielectric layer can be formed using a chemical vapor deposition process. Thus, an inductor can be formed on the chip.

[0050] In addition, the above process can be used to form a first conductive layer 336 and a second conductive layer 346, such that the first conductive layer 336 is electrically connected to the first end 316 of the inductor 306 and the input voltage solder joint 307, and the second conductive layer 346 is electrically connected to the second end 326 of the inductor 306 and the switch solder joint 301.

[0051] Example 2: A substrate is provided, and an inductor 306 is formed on the substrate using a redistribution layer process. The substrate exposes the first end 316 and the second end 326 of the inductor 306. Specifically, an initial metal layer is deposited over the entire surface of the substrate, and the initial metal layer is patterned to form the inductor 306. A dielectric layer is formed on the inductor 306, exposing the first end 316 and the second end 326. After the dielectric layer is formed, the substrate can be placed on the chip 200 with the bottom surface facing up and the top surface of the dielectric layer facing down. The first end 316 is electrically connected to the conductive via 403 in the chip 200 via a first solder ball 401, thereby electrically connecting the first end 316 to the input voltage pin 101 on the substrate 100. The second end 326 is electrically connected to the switch solder joint 301 on the chip 200 via a third solder ball 420.

[0052] The boost converter 300 also includes an output capacitor integrated on the chip 200; the chip also includes a storage capacitor, and the output capacitor and the storage capacitor are formed in the same process. Both the output capacitor and the storage capacitor have an upper electrode and a lower electrode, and the upper electrode and / or the lower electrode comprises doped titanium nitride material.

[0053] After the chip 200 and the boost converter 300 are installed, a package shell 110 is installed on the substrate 100. The package shell 110 and the substrate 100 form a closed area 120, and the chip 200 and the boost converter 300 are located within the closed area 120.

[0054] In summary, packaging the inductor 206 and chip 200 of the boost converter 300 together in a closed area helps to reduce the package size, reduce power consumption on the traces, and thus improve the conversion efficiency.

[0055] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A memory, comprising: The application relates to a substrate with a package shell, a chip with a load, and a boost converter. The boost converter is integrated at least partially on the chip and is used to provide voltage to the load. The boost converter includes a switch tube, an output terminal, and a switch tube control circuit connected to the switch tube for controlling the opening or closing of the switch tube. The switch tube control circuit includes a drive circuit, an RS flip-flop, a comparator, an error amplifier, and first and second voltage dividing resistors. One end of the first voltage dividing resistor is connected to the output terminal of the boost converter, and the other end of the first voltage dividing resistor is connected to one end of the second voltage dividing resistor. The first input terminal of the error amplifier is connected between the first and second voltage dividing resistors. The second input terminal of the error amplifier is connected to a reference voltage. The output terminal of the error amplifier is connected to the first input terminal of the comparator.

2. The memory of claim 1, wherein, The second input terminal of the comparator receives a triangular wave signal.

3. The memory of claim 1, wherein, The output terminal of the comparator is connected to the R terminal of the RS flip-flop. The S terminal of the RS flip-flop receives a clock signal. The Q terminal of the RS flip-flop is connected to the input terminal of the drive circuit. The output terminal of the drive circuit is connected to the switch tube. The inductor is integrated on the chip. The substrate has an input voltage pin, and the chip has an input voltage pad, a first conductive layer, and a second conductive layer. The input voltage pin is electrically connected to the input voltage pad. The first end of the inductor is electrically connected to the input voltage pad through the first conductive layer. The second end of the inductor is electrically connected to the switch pad through the second conductive layer. The inductor is independent of the chip and is formed by a redistribution layer process. The substrate has an input voltage pin. The closed area also has first and second interconnection structures. The first end of the inductor is electrically connected to the input voltage pin through the first interconnection structure. The second end of the inductor is electrically connected to the switch pad through the second interconnection structure.

4. The memory of claim 3, wherein, The chip is arranged with the inductor, and the inductor is above the chip; the first interconnection structure comprises a first solder ball, a conductive via and a second solder ball which are electrically connected in sequence; wherein the first solder ball is between the inductor and the chip and is electrically connected with the first end of the inductor; the conductive via is in the chip; the second solder ball is between the chip and the substrate and is electrically connected with the input voltage pin; the second interconnection structure comprises a third solder ball which electrically connects the second end of the inductor and the switch pad.

5. The memory of claim 1, wherein, The boost converter further comprises an input end, a freewheeling unit and an output capacitor, the input end is used for receiving an external input voltage; the switch tube, the freewheeling unit and the output capacitor are integrated on the chip; the input end, the inductor, the switch pad and the switch tube are connected in sequence, and one end of the switch tube is connected with the ground end; the input end, the inductor, the switch pad, the freewheeling unit and the output end are connected in sequence, the output end is also connected with the load and provides voltage for the load; one end of the output capacitor is connected with the output end, and the other end of the output capacitor is connected with the ground end.

6. The memory of claim 5, wherein, The freewheeling unit comprises a freewheeling diode or a MOS tube.

7. The memory of claim 5, wherein, The output capacitor comprises an upper electrode and a lower electrode, and the upper electrode and / or the lower electrode comprises a doped titanium nitride material.

8. The memory of claim 1, wherein, The chip comprises a dynamic random access memory chip.

9. The memory of claim 8, wherein, The load comprises a word line driving circuit, and the boost converter is used for providing an opening voltage of the word line.

10. The memory of claim 9, wherein, The input voltage of the boost converter is 1.2V, and the output voltage of the boost converter is 3V.

11. The memory of claim 8, wherein, The load comprises an equalization circuit, and the boost converter is used for opening the equalization circuit.

12. A method of manufacturing a memory, characterized by, Comprise: A substrate is provided; A chip and a boost converter are mounted on the substrate, the chip has a load thereon; at least part of structures in the boost converter are integrated on the chip, the boost converter is used for providing voltage for the load; the boost converter at least comprises an inductor and a switch pad, the inductor comprises opposite first and second ends, the second end of the inductor is electrically connected with the switch pad, and the switch pad is integrated on the chip; A package shell is mounted on the substrate, the package shell and the substrate enclose a closed area, and the chip and the boost converter are located in the closed area.

13. The method of manufacturing a memory according to claim 12, wherein, The boost converter further comprises an output capacitor integrated on the chip; the chip further comprises a storage capacitor, and the output capacitor and the storage capacitor are formed in the same process.

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