Memory device including a gate leakage transistor

Abstract

The present disclosure relates to memory devices including a gate leakage transistor. A memory device includes a series-connected memory cell string, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The series-connected memory cell string includes a vertical channel region. Each memory cell in the series-connected memory cell string includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the series-connected memory cell string. The second select transistor is connected between the common source and the series-connected memory cell string. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure that is different from the first gate stack structure.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more particularly, in one or more embodiments, to gate-leaking transistors within a memory device. Background Technology

[0002] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that support high memory density, high reliability, and low power consumption. By programming (often referred to as writing) the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device, so named because of the logical form in which the basic memory cell configuration is arranged. Typically, the memory cell array for NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., between a source select transistor and a drain select transistor). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known. Summary of the Invention

[0005] In one aspect, this disclosure relates to a memory device comprising: a series-connected string of memory cells including a vertical channel region, each memory cell in the series-connected string of memory cells including a first gate stack structure; a data line connected to the vertical channel region; a first selection transistor connected between the data line and the series-connected string of memory cells; a common source; a second selection transistor connected between the common source and the series-connected string of memory cells; and a gate leakage transistor connected between the first selection transistor and the second selection transistor, the gate leakage transistor including a second gate stack structure different from the first gate stack structure.

[0006] In another aspect, this disclosure relates to a three-dimensional NAND memory array comprising: a series-connected string of memory cells connected between a data line and a common source; a semiconductor pillar providing a channel region for the series-connected string of memory cells; a first selection transistor connected between the data line and the series-connected string of memory cells; a second selection transistor connected between the common source and the series-connected string of memory cells; and a gate leakage transistor connected between the first selection transistor and the second selection transistor, the gate leakage transistor being configured to inject holes from the gate of the gate leakage transistor into the channel region during an erase operation of the series-connected string of memory cells.

[0007] In another aspect, this disclosure relates to a memory device comprising: a series-connected string of memory cells connected between a data line and a common source, the series-connected string of memory cells including a channel region; a first selection transistor connected between the data line and the series-connected string of memory cells; a second selection transistor connected between the common source and the series-connected string of memory cells; a gate leakage transistor connected between the first selection transistor and the second selection transistor; and control logic configured to, during an erase operation of the series-connected string of memory cells: bias the data line and the common source to a first voltage level; bias the control gate of the first selection transistor to a second voltage level less than the first voltage level to turn off the first selection transistor; bias the control gate of the second selection transistor to a third voltage level less than the first voltage level to turn off the second selection transistor; and bias the control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to charge the channel region to a positive potential.

[0008] In another aspect, this disclosure relates to a method for manufacturing a memory array, the method comprising: forming a series-connected string of memory cells, the series-connected string of memory cells including a control gate including a first conductor, a first gate stack structure and the vertical channel region along a lower portion of a vertical channel region; and forming a plurality of series-connected select transistors, the plurality of series-connected select transistors including a control gate including a second conductor different from the first conductor, a second gate stack structure different from the first gate stack structure and the vertical channel region along an upper portion of the vertical channel region. Attached Figure Description

[0009] Figure 1 This is a simplified block diagram of a memory that communicates with a processor as part of an electronic system, according to an embodiment.

[0010] Figure 2A and 2B It can be used as a reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0011] Figure 3 It can be used as a reference. Figure 1 A schematic diagram of a portion of a memory cell array in a memory of the described type.

[0012] Figures 4A to 4D This is a cross-sectional view illustrating the structure of a portion of a memory cell array according to an embodiment.

[0013] Figure 5A and 5B This is a flowchart of a method for operating a memory according to an embodiment.

[0014] Figure 6A and 6B This is a flowchart of a method for operating a memory according to another embodiment.

[0015] Figures 7A to 7R This is a cross-sectional view illustrating a method for manufacturing a memory array according to an embodiment.

[0016] Figure 8A and 8B This is a flowchart of a method for manufacturing a memory array according to an embodiment. Detailed Implementation

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part of the invention, and specific embodiments are illustrated in the drawings by way of description. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0018] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, silicon epitaxial layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0019] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0020] This paper recognizes that even when values ​​are expected to be equal, the variability and accuracy of industrial processing and operation can still cause discrepancies between their expected values ​​and reality. These variability and accuracy will generally depend on the techniques used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, they are considered equal regardless of the resulting values.

[0021] Figure 1 This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100, which is part of a third device in the form of an electronic system and communicates with a second device in the form of a processor 130, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The processor 130, such as a controller external to the memory device 100, may be a memory controller or other external host device.

[0022] Memory device 100 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (often referred to as a word line), while memory cells in a logical column are typically selectively connected to the same data line (often referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed as one of at least two target data states.

[0023] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0024] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to an address. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, e.g., a reserved block of memory cells.

[0025] Control logic 116 may also communicate with cache register 118. While memory cell array 104 is busy writing or reading other data, cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store the data. During programming operations (e.g., write operations), data may be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data may be latched from I / O control circuitry system 112 into cache register 118. During read operations, data may be transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; subsequently, new data may be transferred from data register 120 back to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may also include sensing devices ( Figure 1 (Not shown) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines connected to the memory cells in the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0026] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may also be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via the I / O bus 134.

[0027] For example, commands can be received at the input / output (I / O) control circuitry system 112 via I / O pins [7:0] of the I / O bus 134, and then the commands can be written to the command register 124. Addresses can be received at the input / output (I / O) control circuitry system 112 via I / O pins [7:0] of the I / O bus 134, and then the addresses can be written to the address register 114. Data can be received at the I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then the data can be written to the cache register 118. The data can then be written to the data register 120 for programming the memory cell array 104. In another embodiment, the cache register 118 can be omitted, and data can be written directly to the data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, these I / O pins may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0028] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functions of the various block components described may not necessarily need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0029] Additionally, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0030] Figure 2A It can be used as a reference. Figure 1 A schematic diagram of a memory cell array 200A, such as a NAND memory array, used as part of a memory cell array 104 in a memory of the described type. The memory array 200A includes access lines (e.g., word lines) 2020 to 2020. N And data lines (e.g., bit lines) 2040 to 204 MAccess line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or to have a conductivity type such as n-type conductivity to form an n-well, for example.

[0031] The memory array 200A can be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may also include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory, and instead are usually incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0032] The memory cells 208 in each NAND string 206 may be connected in series to select gate 210 (e.g., field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select gate source) and select gate 212 (e.g., a field-effect transistor) (e.g., select gates 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gates 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, wherein each select gate is configured in series to receive the same or independent control signals.

[0033] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0034] The drain of each select gate 212 can be connected to the data line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0035] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the data line 204, and the plane containing the data line is substantially parallel to the plane containing the common source 216.

[0036] like Figure 2A As shown, a typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may also have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. Memory cell 208 connects its control gate 236 to (and in some cases forms) access line 202.

[0037] A column of memory cells 208 may be a NAND string 206 or multiple NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains memory cells 208 commonly connected to a given access line 202 every other one. For example, commonly connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be memory cells 208 that are physical pages (e.g., even-numbered memory cells), while being commonly connected to access lines 202. N Furthermore, the memory cell 208 selectively connected to the odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be a memory cell 208 of another physical page (e.g., an odd-numbered memory cell). Although data lines 2043-2045 are not explicitly depicted in... Figure 2A However, it is obvious from the figure that the data line 204 of the memory cell array 200A can be from data line 2040 to data line 204. M Memory cells 208 that are commonly connected to a given access line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered as a single physical page of memory cells. A portion (in some embodiments, this may still be an entire row) of a physical page of a memory cell (e.g., the upper or lower page of the memory cell) that is read during a single read operation or programmed during a single programmable operation may be considered as a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, a reference to a memory cell page herein refers to the memory cell of the logical page of the memory cell.

[0038] Although it was discussed in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0039] Figure 2B It can be used as a reference. Figure 1 Another schematic diagram of a memory cell array 200B, which is used as part of memory cell array 104 in a memory of the type described. Figure 2B The same numbered elements in the text correspond to about Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected via select lines 2150 to 2150. K Bias selectively activates specific select transistors 212, each located between the NAND string 206 and the data line 204, to connect to their respective data lines 204. Select transistors 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. Multiple rows of memory cells commonly connected to each other via specific access lines 202 can be collectively referred to as a stack.

[0040] A three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS often no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0041] With access line 202 off, the pillars acting as channel regions are isolated from the common source 216 via a source junction (e.g., an n+ junction) and from the corresponding bit line 204 via a drain junction (e.g., an n+ junction). During an erase operation, when an erase bias is applied to the common source 216 and the corresponding bit line 204, junction leakage can be used to charge the pillars to a positive value. To use junction leakage to charge the pillars, the source and / or drain junctions can be designed for high on-current, low off-current, and high off-current during read and program operations, and high off-current during erase operations. Source-gate-source (SGS) gate-induced drain leakage (GIDL) can be difficult to achieve due to significant upward diffusion from the source. Alternatively, source-gate-drain (SGD) GIDL can be optimized for other off-current operations (e.g., read and program operations). Therefore, as disclosed herein, leakage through the gate oxide of the gate-leaking transistor can be used to charge the pillars during erase operations. The leakage of the gate oxide through the gate leakage transistor allows the source and / or drain junctions to be optimized for turn-off current for read and program operations. The gate leakage transistor can be placed anywhere between the bit line and the common source, such as within a string of serially connected memory cells.

[0042] A gate-leaking transistor allows holes to tunnel from the gate of the transistor to the channel region during erase operations, while leakage is minimal during read and program operations. The gate-leaking transistor may include a polysilicon (e.g., P+-doped) gate for hole injection. It may also include a barrier-modified gate stack to provide hole injection from the gate in response to a higher electric field during erase operations and to provide low leakage in response to a lower electric field during read and program operations.

[0043] Figure 3 It can be used as a reference. Figure 1 A schematic diagram of a memory cell array 300, for example, used as part of a memory cell array 104 in a memory of the described type. Figure 3 Elements with the same number in the text correspond to elements about Figure 2A and 2B The description provided. Figure 3 Additional details are provided for an example of a three-dimensional NAND memory array structure. For each data line 204, the three-dimensional NAND memory array 300 may additionally include three source select transistors 210 and three drain select transistors 212. For example, for the data line 2040 and the serially connected memory cell string 2060, the memory array 300 includes select gates 210. 0,0 To 210 0,2 and select door 212 0,0 To 212 0,2 .

[0044] The memory cells 208 of each NAND string 206 can be connected in series to the select gate 210 (e.g., a field-effect transistor). 0,0 To 210 0,2 ) and selector 212 (e.g., field-effect transistor) (e.g., selector 212) 0,0 To 212 0,2 Between ) . Select door 210 0,0 To 210 0,2 Each can be connected to select lines 2140 to 2142, such as source select lines (SGS), and select gate 212. 0,0 To 212 0,2 Each can be connected to select lines 2150 to 2152, for example, drain select lines (SGD). Select gate 210 0,0 To 210 0,2 Connected in series, and select gate 212. 0,0 To 212 0,2 Series connection.

[0045] Select door 210 0,0 The source can be connected to the common source 216. Select gate 210 0,2 The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 2060. 0,0 To 210 0,2 It can be configured to selectively connect the corresponding NAND string 2060 to the common source 216. Each select gate 210 0,0 To 210 0,2 The control gates can be connected to select lines 2140 to 2142 respectively.

[0046] Select door 212 0,0 The drain can be connected to the data line 2040 corresponding to the NAND string 2060. Select gate 212 0,2 The source can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each selection gate 212 0,0 To 212 0,2 It can be configured to selectively connect the corresponding NAND string 2060 to the corresponding data line 2040. Each select gate 212 0,0 To 212 0,2 The control gates can be connected to select lines 2150 to 2152 respectively.

[0047] Select door 210 0,1 and 210 0,2 At least one of them can be a gate leakage transistor, and / or a select gate 212 0,1 and 212 0,2At least one of them can be a gate-leaking transistor. For example, the first selection transistor (e.g., 212) 0,0 A second selection transistor (e.g., 2060) can be connected between a data line (e.g., 2040) and a series-connected string of memory cells (e.g., 2060). As described in more detail below, the series-connected string of memory cells may have a first gate stack structure. 0,0 This can be connected between a common source (e.g., 216) and a series-connected string of memory cells (e.g., 2060). A gate-leaking transistor (e.g., 210) 0,1 and / or 212 0,1 It can be connected to the first selection transistor (e.g., 212). 0,0 ) and the second selection transistor (e.g., 210) 0,0 Between ), as described in more detail below, gate leakage transistors (e.g., 210). 0,1 and / or 212 0,1 It may include a second gate stack structure that is different from the first gate stack structure.

[0048] Figures 4A to 4C A cross-sectional view illustrating the structure of a portion of the memory cell array 400 according to an embodiment. Figure 4A The upper portion of the memory cell array 400 is described, which includes contacts 404, select gates 4150 to 4152, and access lines 402. N Gate stacks 420, 440, and 450, and a vertical channel region 430 (e.g., a semiconductor pillar). The vertical channel region 430 may be a hollow channel region. Data lines may be connected to contact 404. Contact 404 (e.g., an n+ polysilicon plug) is connected to the vertical channel region 430 (e.g., doped polysilicon). Select gate 4150, gate stack 420, and vertical channel region 430 may provide a select transistor, such as... Figure 3 Drain-select transistor 212 0,0 The selector gate 4151, gate stack 420, and vertical channel region 430 can provide a selector transistor, for example... Figure 3 Drain-select transistor 212 0,1 This drain-select transistor can be a gate-leakage transistor. The gate-leakage transistor can be configured to have a first leakage in response to a first electric field, and a second leakage less than the first leakage in response to a second electric field less than the first electric field.

[0049] The selector gate 4152, gate stack 440, and vertical channel region 430 can provide a selector transistor, for example... Figure 3 Drain-select transistor 212 0,2 Access line 402 NGate stack 450 and vertical channel region 430 can provide memory cells, such as Figure 3 memory cell 208 N Gate stack 420 may include a barrier-modified gate stack structure, gate stack 440 may include a silicon dioxide gate stack structure or a barrier-modified gate stack structure, and gate stack 450 may include a replacement gate stack structure.

[0050] Figure 4B The description selects transistor 412, which can provide... Figure 4A The selection transistor 412 may include a selection gate 4150, a gate stack 420, and a vertical channel region 430, and / or a selection gate 4151, a selection transistor 412, a selection transistor 412, a selection transistor 413, and a selection transistor 414. The selection transistor 412 may include a polysilicon (e.g., p+ doped) gate 415, a gate stack 420 including an oxide layer 422, a nitride layer 424, and an oxide layer 426, and a channel region 430. The gate stack 420 may include a barrier-modified gate stack structure.

[0051] Figure 4C The lower portion of the memory cell array 400 is described, including a common source 416, select gates 4140 to 4142, access lines 4020, gate stack 450, and a vertical channel region 430. The common source 416 is connected to the vertical channel region 430. The select gates 4140, gate stack 450, and vertical channel region 430 can provide select transistors, such as... Figure 3 Source selection transistor 210 0,0 The selector gate 4141, gate stack 450, and vertical channel region 430 can provide a selector transistor, for example... Figure 3 Source selection transistor 210 0,1 The selector gate 4142, gate stack 450, and vertical channel region 430 can provide a selector transistor, such as... Figure 3 Source selection transistor 210 0,2 Access lines 4020, gate stack 450, and vertical channel region 430 can provide memory cells, such as... Figure 3 The memory unit 2080.

[0052] Figure 4D The description selects transistor 410, which can provide Figure 4A and 4C The selection transistor having selection gates 4140 to 4142, gate stack 450 and vertical channel region 430 and / or having access lines 4020 to 402 NA memory cell comprising a gate stack 450 and a vertical channel region 430. The selection transistor 410 may include a metal gate 414, a gate stack 450 comprising an oxide layer 452, a nitride layer 454, and an oxide layer 456, and a channel region 430. The gate stack 450 may include an alternative gate stack structure. In other embodiments, the alternative gate stack structure 450 may include an oxide, nitride, oxide, nitride, oxide stack structure.

[0053] refer to Figures 3 to 4D The memory array 300 or 400 may include a series-connected string of memory cells (e.g., 2060) between a data line (e.g., 2040) and a common source (e.g., 216 or 416), and semiconductor pillars providing a channel region (e.g., 430) for the series-connected string of memory cells. A first selection transistor (e.g., 212) 0,0 (Or 4150 / 420 / 430) can be connected between the data lines and the series-connected memory cell string. A second selection transistor (e.g., 210) 0,0 (Or 4140 / 450 / 430) can be connected between a common source and a series-connected string of memory cells. Gate leakage transistors (e.g., 212) 0,1 (Or 4151 / 420 / 430) may be connected between the first selection transistor and the second selection transistor. The gate leakage transistor may be configured to inject holes from the gate of the gate leakage transistor into the channel region during an erase operation of a series-connected string of memory cells, as indicated by arrow 431. In some embodiments, another gate leakage transistor (e.g., 210) 0,1 A gate-leaking transistor can be connected between the first and second selection transistors. Another gate-leaking transistor can be configured to inject holes from the gate of the other gate-leaking transistor into the channel region during an erase operation of a series-connected string of memory cells. The semiconductor pillar providing the channel region can be connected to a data line via contacts (e.g., 404) comprising n-type conductive doped polysilicon. In some embodiments, the semiconductor pillar providing the channel region may comprise polysilicon. Alternatively, the semiconductor pillar providing the channel region may be hollow.

[0054] Figure 5A and 5B This is a flowchart of a method 500 for operating a memory according to an embodiment. Method 500 may at least partially correspond to Figures 3 to 4D For example, Figure 5A and 5B This can represent a leak-assisted erase operation for a string of serially connected memory cells. The method can be, for example, stored in... Figure 1The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0055] Method 500 may be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2B As described. A memory device may include a string of memory cells connected in series (e.g., 2060), comprising a vertical channel region (e.g., 430), a data line (e.g., 2040) connected to the vertical channel region via contacts (e.g., 404), and a common source (e.g., 216 or 416). The control gate of each memory cell in the string of memory cells connected in series may be connected to an access line (e.g., 2020 to 202...). N Or 4020 to 402 N First selection transistor (e.g., 212) 0,0 (Or 4150 / 420 / 430) can be connected between the data lines and the series-connected memory cell string. A second selection transistor (e.g., 210) 0,0 (Or 4140 / 450 / 430) can be connected between a common source and a series-connected string of memory cells. Gate leakage transistors (e.g., 212) 0,1 A third select transistor (e.g., 4151 / 420 / 430) may be connected between the first select transistor and the second select transistor. Each memory cell in the series-connected memory cell string may include a first gate stack structure (e.g., 450). A gate leakage transistor may include a second gate stack structure (e.g., 420) different from the first gate stack structure. In some embodiments, the gate leakage transistor may be directly connected to the first select transistor. 0,2 (Or 4152 / 440 / 430) can be connected between the gate-leaking transistor and the series-connected memory cell string.

[0056] In this embodiment, such as Figure 5AAs described at 502, for an erase operation, the controller can bias the data lines and common source to a first voltage level (e.g., an erase voltage, such as 20V). The controller can bias each access line to 0V. At 504, the controller can bias the control gate of the first select transistor to a second voltage level less than the first voltage level (e.g., erase voltage minus 2V). At 506, the controller can bias the control gate of the second select transistor to a third voltage level less than the first voltage level (e.g., erase voltage minus 9V). At 508, the controller can bias the control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level (e.g., erase voltage plus 7V) to inject holes from the control gate of the gate leakage transistor into the channel region. Figure 5B As described at 510, the controller may additionally bias the control gate of the third selection transistor to a fifth voltage level (e.g., erase voltage minus 4V) that is lower than the second voltage level. The third voltage level may be lower than the second voltage level, and the fifth voltage level may be between the second and third voltage levels.

[0057] Figure 6A and 6B This is a flowchart of a method 600 for operating a memory according to another embodiment. Method 600 may at least partially correspond to Figures 3 to 4D For example, Figure 6A and 6B This can represent a leak-assisted erase operation for a string of serially connected memory cells. The method can be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0058] Method 600 can be implemented within a memory device (e.g., 100) that includes a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2B As described. The memory device may include a series-connected string of memory cells (e.g., 2060) connected between a data line (e.g., 2040) and a common source (e.g., 216 or 416) and including a channel region (e.g., 430). The control gate of each memory cell in the series-connected string of memory cells may be connected to an access line (e.g., 2020 to 202...). N Or 4020 to 402 N First selection transistor (e.g., 212) 0,0 (Or 4150 / 420 / 430) can be connected between the data lines and the series-connected memory cell string. A second selection transistor (e.g., 210)0,0 (Or 4140 / 450 / 430) can be connected between a common source and a series-connected string of memory cells. Gate leakage transistors (e.g., 212) 0,1 (Or 4151 / 420 / 430) may be connected between the first selection transistor and the second selection transistor. In some embodiments, a third selection transistor (e.g., 212) may be connected between the first and second selection transistors. 0,2 (Or 4152 / 440 / 430) can be connected between the gate-leaking transistor and the series-connected string of memory cells. A fourth selection transistor (e.g., 210) 0,1 (Or 4141 / 450 / 430) can be connected between the second selection transistor and the series-connected string of memory cells. The fifth selection transistor (e.g., 210) 0,2 (Or 4142 / 450 / 430) can be connected between the fourth selection transistor and the series-connected memory cell string. In some embodiments, the gate leakage transistor may include a barrier-modified gate stack structure, each memory cell in the series-connected memory cell string may include an alternative gate stack structure, the first selection transistor may include a barrier-modified gate stack structure, the second selection transistor may include an alternative gate stack structure, the third selection transistor may include a barrier-modified gate stack structure, the fourth selection transistor may include an alternative gate stack structure, and the fifth selection transistor stack structure may include an alternative gate stack structure.

[0059] In this embodiment, such as Figure 6A As described at 602, for an erase operation, the controller can bias the data lines and common source to a first voltage level (e.g., an erase voltage, such as 20V). The controller can bias each access line to 0V. At 604, the controller can bias the control gate of the first select transistor to a second voltage level less than the first voltage level (e.g., erase voltage minus 2V) to turn off the first select transistor. At 606, the controller can bias the control gate of the second select transistor to a third voltage level less than the first voltage level (e.g., erase voltage minus 9V) to turn off the second select transistor. At 608, the controller can bias the control gate of the gate-leaking transistor to a fourth voltage level greater than the first voltage level (e.g., erase voltage plus 7V) to charge the channel region to a positive potential.

[0060] like Figure 6BAs described at 610, the controller may further bias the control gate of the third selection transistor to a fifth voltage level that is lower than the second voltage level and higher than the third voltage level (e.g., erase voltage minus 4V). At 612, the controller may further bias the control gate of the fourth selection transistor to a sixth voltage level that is lower than the fifth voltage level and higher than the third voltage level (e.g., erase voltage minus 6V). At 614, the controller may further bias the control gate of the fifth selection transistor to the sixth voltage level.

[0061] Figures 7A to 7R A method for manufacturing a memory array according to an embodiment is described. For example, in Figure 7A As described at location 700A, multiple layers can be deposited on the source material layer 702. A stacked oxide layer 704 can be deposited on the source material layer 702. A stacked nitride layer 706 can be deposited on the stacked oxide layer 704. A stacked oxide layer 708 and a stacked nitride layer 710 can be deposited on the stacked nitride layer 706, respectively. Multiple additional stacked oxide layers and stacked nitride layers (not shown) can be deposited on the stacked nitride layer 710, respectively. A stacked oxide layer 712 and a stacked nitride layer 714 can be deposited on top of the multiple additional stacked oxide layers and stacked nitride layers, respectively. The number of stacked oxide layers and stacked nitride layers can be based on the use of... Figure 4A and 4C The number of transistors (e.g., memory cells and select gates) in the gate stack 450. An oxide layer 716 may be deposited on a stacked nitride layer 714. A polysilicon (e.g., p+ doped) layer 718 may be deposited on the oxide layer 716. An oxide layer 720 may be deposited on the polysilicon layer 718. A polysilicon (e.g., p+ doped) layer 722 may be deposited on the oxide layer 720. An oxide layer 724 may be deposited on the polysilicon layer 722.

[0062] As in Figure 7B As described at location 700B, layers 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, and 724 can be etched to form openings for pillars as indicated at location 730, which terminate in or below the stacked dielectric layer 704. As in Figure 7C The description at location 700C indicates that the blocking dielectric layer 732 (e.g., SiO2 and / or a high-k dielectric, such as AlO) x A storage layer 734 (e.g., Si3N4) may be deposited on the walls and bottom of the opening 730. A barrier dielectric layer 734 (e.g., Si3N4) may be deposited on the barrier dielectric layer 732 within the opening. A tunneling dielectric layer 736 (e.g., SiO2, oxide nitride, Si3N4, or a combination thereof) may be deposited on the storage layer 734 within the opening. A through-hole layer (e.g., polysilicon) 738 may be deposited on the tunneling dielectric layer 736 within the opening. Figure 7DAs described at location 700D, through-hole etching can be used to etch the through-hole layer 738, tunneling dielectric layer 736, storage layer 734, barrier dielectric layer 732 and stacked oxide layer 704 at the bottom of the opening to expose the source material layer 702, as indicated at location 740.

[0063] As in Figure 7E Location 700E indicates that the through-hole layer 738 can be removed (e.g., by wet etching). As in Figure 7F As described at location 700F, channel material 742 (e.g., polysilicon) can be deposited within an opening in the tunneling dielectric layer 736 and deposited on the source material layer 702 to connect to the source material layer. Dielectric material 744 can be deposited on the channel material 742 to fill the opening. (As shown in...) Figure 7G As illustrated at location 700G, dielectric material 744, channel material 742, tunneling dielectric layer 736, storage layer 734, and barrier dielectric layer 732 can be etched back (e.g., by dry and / or wet etching) to form openings exposing polysilicon layers 718 and 722 as indicated at location 746. Figure 7H As illustrated at location 700H, a dielectric layer (e.g., ONO) 748 may be deposited on the walls and bottom of the opening 746. A perforation layer 750 may be deposited on the dielectric layer 748 within the opening.

[0064] As in Figure 7I As indicated at location 700I, through-hole etching can be used to etch the through-hole layer 750 and the dielectric layer 748, as indicated at location 752. Figure 7J Location 700J indicates that the perforation layer 750 can be removed (e.g., by wet etching). Figure 7K As described at location 700K, channel material 754 can be deposited on the walls and bottom of the opening to contact channel material 742. Channel materials 742 and 754 can be referred to as semiconductor pillars. Dielectric material 756 can be deposited on channel material 754 to fill the opening. (As shown in...) Figure 7L As indicated at location 700L, the dielectric material at 756 can be etched back to form an opening as indicated at location 758. Figure 7M The 700M location illustrates that polysilicon (e.g., n+ doped) 760 can be deposited on dielectric material 756 to fill opening 758.

[0065] As in Figure 7N As described at 700N, layers 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, and 724 can be etched to form openings for the gate replacement process, as indicated at 762. (As shown in...) Figure 7O Location 700O indicates that the stacked nitride layers 706, 710, and 714 can be removed. (As shown in...) Figure 7PAs illustrated at location 700P, metal 764 can be deposited to form a gate, wherein stacked nitride layers 706, 710, and 714 are removed. In some embodiments, an additional charge-blocking layer (not shown) may be deposited prior to the deposition of metal 764 in the voids created by removing the stacked nitride layers 706, 710, and 714. Figure 7Q As indicated at location 700Q, metal 764 can be etched (e.g., by dry and / or wet etching) as instructed at location 766 to isolate the gate. As in Figure 7R As described at 700R, dielectric 768 can be deposited to fill the opening. After 700R, contacts with a gate formed of polysilicon 718 and 722 and metal 764 can be formed to complete the fabrication of the memory cell array.

[0066] Figure 8A and 8B This is a flowchart of a method 800 for manufacturing a memory array according to an embodiment. Method 800 may at least partially correspond to Figures 7A to 7R .like Figure 8A As described at 802, method 800 may include forming a string of memory cells connected in series (e.g., Figure 3 (2060), the series-connected memory cell string along the lower portion of the vertical channel region includes: a control gate (e.g., a first conductor (e.g., metal)). Figure 4D 414), first gate stack structure (e.g., Figure 4D 450) and the vertical trench area (e.g., Figure 4C (430). At 804, method 800 may include a plurality of selection transistors forming a series connection (e.g., ). Figure 3 212 0,0 To 212 0,2 The plurality of series-connected selection transistors include, along the upper portion of the vertical channel region, a control gate (e.g., a second conductor different from the first conductor, e.g., polysilicon) in the form of a second conductor (e.g., polysilicon). Figure 4B 415), and a second gate stack structure different from the first gate stack structure (e.g., Figure 4B 420), and the vertical trench area (e.g., Figure 4A (430). In some embodiments, the lower portion of the vertical channel region may be horizontally offset relative to the upper portion of the vertical channel region (e.g., as shown in Figure 430). Figure 7R (As described in the document). Each memory cell in a string of serially connected memory cells may contain an alternative gate stack structure (e.g., Figure 4D (450). Each of the multiple series-connected selection transistors may include a barrier-modified gate stack structure (e.g., Figure 4B (of 420). Figure 8BAs described at point 806, method 800 may additionally include making the lower portion of the vertical channel area (e.g., Figure 7F 742) is in contact with the common source electrode. At 808, method 800 may additionally include making the upper portion of the vertical channel region (e.g., Figure 7O The 754) contacts the data line, for example, through an n-type conductive doped polysilicon contact (e.g., Figure 7O (of 760).

[0067] Conclusion

[0068] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the described embodiments.

Claims

1. A memory device comprising: a series-connected string of memory cells including a vertical channel region, each memory cell in the series-connected string of memory cells including a first gate stack structure; a data line connected to the vertical channel region; a first select transistor connected between the data line and the series-connected string of memory cells; a common source; a second select transistor connected between the common source and the series-connected string of memory cells; and a gate leakage transistor connected between the first select transistor and the second select transistor, the gate leakage transistor including a second gate stack structure different from the first gate stack structure.

2. The memory device of claim 1, wherein the first gate stack structure comprises a replacement gate stack structure, and wherein the second gate stack structure comprises a barrier-engineered gate stack structure.

3. The memory device of claim 1, wherein the gate leakage transistor is configured to have a first leakage in response to a first electric field and a second leakage less than the first leakage in response to a second electric field less than the first electric field.

4. The memory device of claim 1, wherein a control gate of each memory cell in the series-connected string of memory cells comprises a metal gate, and wherein a control gate of the gate leakage transistor comprises a polysilicon gate.

5. The memory device of claim 1, wherein the gate leakage transistor is directly connected to the first select transistor.

6. The memory device of claim 1, further comprising: control logic configured to, during an erase operation of the series-connected string of memory cells: bias the data line and the common source to a first voltage level; bias a control gate of the first select transistor to a second voltage level less than the first voltage level; bias a control gate of the second select transistor to a third voltage level less than the first voltage level; and bias a control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to inject holes from the control gate of the gate leakage transistor into the channel region.

7. The memory device of claim 5, further comprising: a third select transistor connected between the gate leakage transistor and the series-connected string of memory cells.

8. The memory device of claim 7, further comprising: control logic configured to, during an erase operation of the series-connected string of memory cells: bias the data line and the common source to a first voltage level; bias a control gate of the first select transistor to a second voltage level less than the first voltage level; bias a control gate of the second select transistor to a third voltage level less than the first voltage level; and bias a control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to inject holes from the control gate of the gate leakage transistor into the channel region. ​ biasing a control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to inject holes from the control gate of the gate leakage transistor into the channel region; and biasing a control gate of the third select transistor to a fifth voltage level less than the second voltage level.

9. The memory device of claim 8, wherein the third voltage level is less than the second voltage level, and wherein the fifth voltage level is between the second voltage level and the third voltage level.

10. A three-dimensional NAND memory array, comprising: a series-connected string of memory cells connected between a data line and a common source; a semiconductor pillar providing a channel region of the series-connected string of memory cells; a first select transistor connected between the data line and the series-connected string of memory cells; a second select transistor connected between the common source and the series-connected string of memory cells; and a gate leakage transistor connected between the first select transistor and the second select transistor, the gate leakage transistor configured to inject holes from a gate of the gate leakage transistor into the channel region during an erase operation of the series-connected string of memory cells.

11. The memory array of claim 10, wherein the gate leakage transistor comprises a barrier-engineered gate stack structure, and wherein each memory cell in the series-connected string of memory cells comprises a replacement gate stack structure.

12. The memory array of claim 11, wherein the first select transistor comprises the barrier-engineered gate stack structure, and wherein the second select transistor comprises the replacement gate stack structure.

13. The memory array of claim 10, additionally comprising: another gate leakage transistor connected between the first select transistor and the second select transistor, the other gate leakage transistor configured to inject holes from a gate of the other gate leakage transistor into the channel region during the erase operation of the series-connected string of memory cells.

14. The memory array of claim 10, wherein the semiconductor pillar providing the channel region is connected to the data line by a contact comprising n-type conductive doped polysilicon, and wherein the semiconductor pillar providing the channel region comprises polysilicon.

15. The memory array of claim 10, wherein the semiconductor pillar providing the channel region is hollow.

16. A memory device, comprising: a series-connected string of memory cells connected between a data line and a common source, the series-connected string of memory cells comprising a channel region; a first select transistor connected between the data line and the series-connected string of memory cells; a second select transistor connected between the common source and the series-connected string of memory cells; a gate leakage transistor connected between the first select transistor and the second select transistor; and control logic configured to, during an erase operation of the series-connected memory cell string: bias the data line and the common source to a first voltage level; bias a control gate of the first select transistor to a second voltage level less than the first voltage level to turn off the first select transistor; bias a control gate of the second select transistor to a third voltage level less than the first voltage level to turn off the second select transistor; and bias a control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to charge the channel region to a positive potential.

17. The memory device of claim 16, further comprising: a third select transistor connected between the gate leakage transistor and the series-connected memory cell string.

18. The memory device of claim 17, further comprising: a fourth select transistor connected between the second select transistor and the series-connected memory cell string.

19. The memory device of claim 18, further comprising: a fifth select transistor connected between the fourth select transistor and the series-connected memory cell string.

20. The memory device of claim 19, wherein the gate leakage transistor comprises a barrier-engineered gate stack, wherein each memory cell in the series-connected memory cell string comprises a replacement gate stack; wherein the first select transistor comprises the barrier-engineered gate stack; wherein the second select transistor comprises the replacement gate stack; wherein the third select transistor comprises the barrier-engineered gate stack; wherein the fourth select transistor comprises the replacement gate stack; and wherein the fifth select transistor comprises the replacement gate stack.

21. The memory device of claim 19, wherein the control logic is further configured to, during the erase operation of the series-connected memory cell string: bias a control gate of the third select transistor to a fifth voltage level less than the second voltage level and greater than the third voltage level; bias a control gate of the fourth select transistor to a sixth voltage level less than the fifth voltage level and greater than the third voltage level; and bias a control gate of the fifth select transistor to the sixth voltage level.

22. A method for fabricating a memory array, the method comprising: forming a series-connected memory cell string comprising, along a lower portion of a vertical channel region: a control gate comprising a first conductor, a first gate stack, and the vertical channel region; and biasing a control gate of the third select transistor to a fifth voltage level less than the second voltage level and greater than the third voltage level; biasing a control gate of the fourth select transistor to a sixth voltage level less than the fifth voltage level and greater than the third voltage level; and biasing a control gate of the fifth select transistor to the sixth voltage level. forming a plurality of series-connected select transistors along an upper portion of the vertical channel region including a control gate including a second conductor different from the first conductor, a second gate stack structure different from the first gate stack structure, and the vertical channel region, wherein the plurality of series-connected select transistors includes a gate leakage transistor.

23. The method of claim 22 wherein the lower portion of the vertical channel region is horizontally offset relative to the upper portion of the vertical channel region.

24. The method of claim 22 wherein each memory cell in the series-connected string of memory cells includes a replacement gate stack structure, and wherein each select transistor in the plurality of series-connected select transistors includes a barrier-engineered gate stack structure.

25. The method of claim 22 further comprising: contacting the lower portion of the vertical channel region to a common source; and contacting the upper portion of the vertical channel region to a data line.

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