Sense amplifier structure and memory structure

Abstract

Embodiments of the present disclosure provide a sense amplifier structure and a memory structure. The sense amplifier structure includes: a plurality of active area groups arranged along a first direction on a substrate, each active area group including a plurality of active areas arranged along a second direction; a first gate and a second gate arranged along the active areas, wherein the first gate and the second gate on the same active area extend in the same direction, which is a gate extension direction; wherein the gate extension direction is different from both the first and second directions, and for the same active area, in the gate extension direction, the length of the first gate and the length of the second gate are both greater than the maximum length of the active area in the first direction and greater than the maximum length of the active area in the second direction. Embodiments of the present disclosure at least facilitate improving the electrical performance of the sense amplifier.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a sense amplifier structure and a memory structure. Background Art

[0002] As one of the most important peripheral circuits in dynamic random access memory (DRAM), the sense amplifier determines the DRAM's read speed. By activating the sense amplifier at the appropriate time, the sense amplifier can amplify the slight voltage difference between the bit line and the complementary bit line, allowing the data stored in the memory cell to be correctly read.

[0003] At present, due to the continuous reduction in device size, the sensing margin of traditional sense amplifiers is becoming smaller and smaller. At the same time, since the devices that constitute the sense amplifier may have different threshold voltages due to process changes or temperature, there is a threshold voltage mismatch between different devices, and the threshold voltage mismatch will cause mismatch noise. The mismatch noise can easily cause the problem of insufficient sensing margin, making the sense amplifier unable to quickly and effectively amplify the signal, thereby reducing the performance of dynamic random access memory. Summary of the Invention

[0004] The sense amplifier structure and memory structure provided by the embodiments of the present disclosure are at least beneficial to improving the electrical performance of the sense amplifier.

[0005] On the one hand, an embodiment of the present disclosure provides a sense amplifier structure, comprising: a plurality of active area groups arranged at intervals along a first direction on a substrate, each active area group including a plurality of active areas arranged at intervals along a second direction; a first gate and a second gate arranged at intervals on the active areas, the first gate and the second gate located on the same active area both extending in the same direction, the extension direction being a gate extension direction, the first gate and the second gate being respectively used as gates of two pull-up transistors of the sense amplifier or gates of two pull-down transistors of the sense amplifier; wherein the gate extension direction is different from both the first direction and the second direction, and for the same active area, in the gate extension direction, the length of the first gate is a first length, the first length is greater than the maximum length of the active area in the first direction, and the first length is greater than the maximum length of the active area in the second direction; the length of the second gate is a second length, the second length is greater than the maximum length of the active area in the first direction, and the second length is greater than the maximum length of the active area in the second direction.

[0006] In some embodiments, in a gate extension direction, the first length is equal to the second length, and in a direction perpendicular to the gate extension direction, a width of the first gate is the same as a width of the second gate.

[0007] In some embodiments, a cross-section of the active region in a direction parallel to the substrate surface is at least one of a rectangle or a chamfered rectangle, and the gate extends in a diagonal direction of the rectangle or the chamfered rectangle.

[0008] In some embodiments, the active area includes a first drain region, a common source region, and a second drain region arranged in sequence perpendicular to the gate extension direction. The portion of the active area covered by the first gate is located between the first drain region and the common source region, and the portion of the active area covered by the second gate is located between the common source region and the second drain region.

[0009] In some embodiments, it also includes: an interconnection layer, the interconnection layer is located above the substrate; a conductive plug, the conductive plug is located between part of the active area and the interconnection layer, and is used to electrically connect the first drain region and the interconnection layer, electrically connect the common source region and the interconnection layer, and electrically connect the second drain region and the interconnection layer.

[0010] In some embodiments, an isolation structure is provided between adjacent active regions, and the conductive plug is further located on the adjacent isolation structure.

[0011] In some embodiments, among the multiple active areas of an active area group, gates on different active areas have the same extension direction.

[0012] In some embodiments, in active area groups adjacent to each other in the first direction, center points of active areas of different active area groups are staggered in the first direction.

[0013] In some embodiments, in two adjacent active area groups in a first direction, the gate extension directions on the active areas of different active area groups are different, and if the first direction is the x direction and the second direction is the y direction, one of the different gate extension directions is a direction inclined from the +y direction to the +x direction, and the other is a direction inclined from the +y direction to the -x direction.

[0014] In some embodiments, in the groups of active regions adjacent to each other in the first direction, center points of two active regions adjacent to each other in the first direction face each other.

[0015] In some embodiments, in two adjacent active area groups in the first direction, gates of different active area groups extend in the same direction.

[0016] In some embodiments, the active area for forming the pull-up transistor is defined as the first active area, and the active area for forming the pull-down transistor is defined as the second active area. In the first direction, one side of a first active area has an adjacent second active area.

[0017] In some embodiments, in the first direction, a side of the first active region away from the second active region has another first active region.

[0018] In some embodiments, in the first direction, the spacing distance between two adjacent first active regions is a third length, the spacing distance between the first active region and the adjacent second active region is a fourth length, the fourth length is greater than the third length, and there is a bias compensation region between the first active region and the adjacent second active region, and the bias compensation region is used to set the bias compensation transistor.

[0019] On the other hand, an embodiment of the present disclosure further provides a memory structure, comprising: a memory cell; and a sense amplifier structure as described in any one of the above items, for writing storage data to a bit line in a memory cell array or reading storage data from a bit line in a memory cell array.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the active area in the active area group of the sense amplifier structure is used to define two pull-up transistors or two pull-down transistors in the sense amplifier, and the first gate and the second gate on the active area serve as the gates of the two pull-up transistors or the gates of the two pull-down transistors, respectively. If the two transistors formed in the same active area are defined as a first transistor and a second transistor, respectively, the first gate is the gate of the first transistor, and the second gate is the gate of the second transistor. Since the active area group is arranged along the first direction and the active areas in the active area group are arranged along the second direction, the length of the active area in the second direction and the length of the active area in the first direction are limited. The length of the first gate in the gate extension direction depends on the length of the active area covered by the first gate in the gate extension direction, and the length of the second gate in the gate extension direction depends on the length of the active area covered by the second gate in the gate extension direction. The gate extension direction is set to a direction different from the first direction and the second direction, and the length of the first gate or the second gate in the gate extension direction is greater than the length of the active area in the first direction, and the length of the first gate or the second gate in the gate extension direction is also greater than the length of the active area in the second direction. Therefore, compared with the first gate and the second gate extending along the first direction or the second direction, the length of the first gate and the second gate extending along the gate extension direction is longer. It should be noted that, under the condition that the sizes of the first gate and the second gate are approximately the same, the larger the length or width that can be designed for the first gate and the second gate, the smaller the difference between the threshold voltages of the first transistor and the second transistor. Therefore, by setting the first gate and the second gate extending along the gate extension direction and increasing the length of the first gate and the second gate in the gate extension direction, it is beneficial to reduce the difference in threshold voltage between the first transistor and the second transistor, that is, it is beneficial to reduce the difference in threshold voltage between the two pull-up transistors or the two pull-down transistors in the sense amplifier, and thus it is beneficial to increase the sensing margin of the sense amplifier and improve the electrical performance of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of a circuit structure including a sensitive amplifier in the related art;

[0023] Figure 2 A schematic structural diagram of a sensitive amplifier structure provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic structural diagram of an active area provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic structural diagram of another active region provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic structural diagram of another active region provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0028] Figure 7 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0029] Figure 8 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0030] Figure 9 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0031] Figure 10 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0032] Figure 11 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure;

[0033] Figure 12 A schematic structural diagram of another sensitive amplifier structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] As known from the background art, current sense amplifiers have the problem of insufficient sensing margin.

[0035] Figure 1 A schematic diagram of a circuit structure including a sensitive amplifier in the related art is shown in FIG. Figure 1 M1 and M2 form an inverter, and M3 and M4 form another inverter. The input of the first inverter is connected to the output of the second inverter, and the output of the first inverter is connected to the input of the second inverter. VH provides power for the sense amplifier and is connected to the sense amplifier via M5. GND is the ground line of the sense amplifier and is connected to the sense amplifier via M6. M1 and M3 are two pull-up transistors in the sense amplifier, and M2 and M4 are two pull-down transistors in the sense amplifier. M1 and M3 are PMOS (Positive Channel Metal Oxide Semiconductor) transistors, and M2 and M4 are NMOS (Negative Channel Metal Oxide Semiconductor) transistors. Typically, in order to eliminate the deviation in threshold voltage between the two pull-up transistors or the two pull-down transistors, other circuits are generally used to introduce a compensation function to eliminate the impact of the threshold voltage deviation. However, adding other circuits usually requires increasing the number of transistors or other electronic devices, which increases the area occupied by the sense amplifier and is not conducive to smaller volume integration.

[0036] To solve the above problems, embodiments of the present disclosure provide a sense amplifier structure and a memory structure. In the sense amplifier structure, an active area in an active area group is used to define two pull-up transistors or two pull-down transistors in the sense amplifier, and a first gate and a second gate on the active area serve as gates of the two pull-up transistors or gates of the two pull-down transistors, respectively. If two transistors formed in the same active area are defined as a first transistor and a second transistor, respectively, the first gate is the gate of the first transistor, and the second gate is the gate of the second transistor, since the active area group is arranged along a first direction and the active areas in the active area group are arranged along a second direction, the length of the active area in the second direction and the length of the active area in the first direction are respectively The length of the first gate in the gate extension direction depends on the length of the active area covered by the first gate in the gate extension direction, and the length of the second gate in the gate extension direction depends on the length of the active area covered by the second gate in the gate extension direction. The gate extension direction is set to a direction different from the first direction and the second direction. Since the length of the first gate or the second gate in the gate extension direction is greater than the length of the active area in the first direction, the length of the first gate or the second gate in the gate extension direction is also greater than the length of the active area in the second direction. Therefore, compared with the first gate and the second gate extending along the first direction or the second direction, the length of the first gate and the second gate extending along the gate extension direction can be longer. It should be noted that, under the condition that the sizes of the first gate and the second gate are approximately the same, the larger the length or width that can be designed for the first gate and the second gate, the smaller the difference between the threshold voltages of the first transistor and the second transistor. By setting the first gate and the second gate extending along the gate extension direction, the length of the first gate and the second gate is increased without increasing the overall size of the sensitive amplifier structure, which is beneficial to reducing the difference in threshold voltage between the first transistor and the second transistor, that is, it is beneficial to reducing the difference in threshold voltage between the two pull-up transistors or the two pull-down transistors in the sensitive amplifier, and thus it is beneficial to increase the sensing margin of the sensitive amplifier and improve the electrical performance of the sensitive amplifier structure.

[0037] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0038] Figure 2 A schematic structural diagram of a sensitive amplifier structure provided by an embodiment of the present disclosure; Figure 3 A schematic structural diagram of an active area provided in an embodiment of the present disclosure; Figure 4A schematic structural diagram of another active region provided in an embodiment of the present disclosure; Figure 5 A schematic structural diagram of another active region provided in an embodiment of the present disclosure; Figure 6 A schematic structural diagram of another sensitive amplifier structure provided in an embodiment of the present disclosure.

[0039] refer to Figures 2 to 6 The sense amplifier structure includes: a plurality of active area groups 100 arranged at intervals along a first direction X on a substrate 10, each active area group 100 including a plurality of active areas 110 arranged at intervals along a second direction Y; first gates 111 and second gates 112 arranged at intervals on the active areas 110, the first gates 111 and the second gates 112 on the same active area 110 extending in the same direction, which is a gate extension direction, and the first gates 111 and the second gates 112 are respectively used as gates of two pull-up transistors of the sense amplifier or The gates of the two pull-down transistors of the sense amplifier; wherein the gate extension direction is different from both the first direction X and the second direction Y, and for the same active area 110, in the gate extension direction, the length of the first gate 111 is a first length, the first length being greater than the maximum length of the active area 110 in the first direction X, and greater than the maximum length of the active area 110 in the second direction Y; the length of the second gate 112 is a second length, the second length being greater than the maximum length of the active area 110 in the first direction X, and greater than the maximum length of the active area 110 in the second direction Y. It should be noted that the “gate extension direction” involved in the embodiments of the present disclosure is the extension direction of the first gate 111 or the second gate 112. Since for the same active area 110, the gate extension direction of the first gate 111 and the gate extension direction of the second gate 112 on the active area 110 are the same, the active area 110 and the gate extension direction are in a one-to-one correspondence. In order to improve the simplicity of the description, the “extension direction of the first gate 111 or the second gate 112 on the active area 110” has been simplified to “the gate extension direction of the gate on the active area 110”.

[0040] If the two transistors formed in the same active area 110 are defined as a first transistor and a second transistor, the first gate 111 is the gate of the first transistor, and the second gate 112 is the gate of the second transistor. Since the gate extension direction is different from both the first direction X and the second direction Y, and the length of the first gate 111 or the second gate 112 in the gate extension direction is greater than the length of the active area 110 in the first direction X, and the length of the first gate 111 or the second gate 112 in the gate extension direction is also greater than the length of the active area 110 in the second direction Y, the first gate 111 and the second gate 112 extending along the gate extension direction have a longer length in the gate extension direction. It should be noted that, under the condition that the sizes of the first gate 111 and the second gate 112 are approximately the same, the larger the length or width that can be designed for the first gate 111 and the second gate 112, the smaller the difference between the threshold voltages of the first transistor and the second transistor. Therefore, without increasing the overall size of the sense amplifier structure, by providing the first gate 111 and the second gate 112 extending along the gate extension direction, the lengths of the first gate 111 and the second gate 112 are increased, which is beneficial to reducing the difference in threshold voltages between the two pull-up transistors or the two pull-down transistors in the sense amplifier, and further beneficial to increasing the sensing margin of the sense amplifier and improving the electrical performance of the sense amplifier.

[0041] In some embodiments, the material of the substrate 10 may be silicon. In other embodiments, the material of the substrate 10 may also be a material that can be directly used in the manufacturing process of producing semiconductor devices. For example, the material of the substrate 10 may be at least one of silicon on insulating substrate (SOI), germanium, silicon carbide, gallium arsenide, or sapphire.

[0042] The number of active area groups 100 arranged along the first direction X can be 4, 8, 10, or 14. The number of active regions 110 arranged along the second direction Y within an active area group 100 can be 4, 5, 6, 20, or 40. In some embodiments, the first direction X is perpendicular to the second direction Y. Specifically, the number of active area groups 100, the number of active regions 110, the arrangement of the active area groups 100, and the arrangement of the active regions 110 can be appropriately set based on actual needs, taking into account the size of the substrate 10, the size of the transistors formed by the active regions 110, and the structure of the memory array.

[0043] In some embodiments, the material of the active region 110 may be silicon. In other embodiments, the material of the active region 110 may also be one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide). When the active region 110 is composed of the above materials, it is beneficial to improve the mobility of carriers in the semiconductor channel of the transistor, thereby facilitating the semiconductor channel to efficiently transmit electrical signals.

[0044] If two transistors formed in the same active area 110 are defined as a first transistor and a second transistor, the first gate 111 is the gate of the first transistor, and the second gate 112 is the gate of the second transistor, the portion of the active area 110 covered by the first gate 111 is the channel region of the first transistor. In a direction perpendicular to the gate extension, the active area 110 on both sides of the portion of the active area 110 covered by the first gate 111 is the two doped regions of the first transistor. The portion of the active area 110 covered by the second gate 112 is the channel region of the second transistor. In a direction perpendicular to the gate extension, the active area 110 on both sides of the portion of the active area 110 covered by the second gate 112 is the two doped regions of the second transistor. Furthermore, the first transistor and the second transistor share a common doped region.

[0045] In some embodiments, the types of doping ions in different doping regions within the same active region 110 are all the same, the types of doping ions in different channel regions within the same active region 110 are all the same, and the types of doping ions in the doping regions and the types of doping ions in the channel regions within the same active region 110 are different. The active region 110 involved in the embodiments of the present disclosure can correspond to two types of transistors, which can be NMOS transistors and PMOS transistors respectively. When the active region 110 corresponds to two PMOS transistors, the doping ions in the doping regions of the active region 110 can be P-type ions, and the doping ions in the channel region of the active region 110 can be N-type ions. When the active region 110 corresponds to two NMOS transistors, the doping ions in the doping regions of the active region 110 can be N-type ions, and the doping ions in the channel region of the active region 110 can be P-type ions.

[0046] The first gate 111 and the second gate 112 serve as the gate of the first transistor and the gate of the second transistor, respectively, and are configured to conduct the channel region based on a control signal to enable carrier transfer between the source and the drain. The first gate 111 and the second gate 112 are made of a conductive material. For example, the material of the first gate 111 or the material of the second gate 112 may include at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0047] In some embodiments, the material of the first gate 111 is the same as the material of the second gate 112 . This helps reduce the difference between the threshold voltages of the first transistor and the second transistor, thereby improving the performance of the sense amplifier.

[0048] refer to Figure 3 In some embodiments, the first length and the second length are the same in the gate extension direction, and the width of the first gate 111 and the width of the second gate 112 are the same in the direction perpendicular to the gate extension direction. This ensures that the first gate 111 and the second gate 112 have the same size, which helps reduce the difference in threshold voltage between the first transistor and the second transistor, thereby increasing the sensing margin of the sense amplifier and improving the electrical performance of the sense amplifier.

[0049] refer to Figure 3 In some embodiments, the cross-section of the active area 110 in a direction parallel to the surface of the substrate 10 may be at least one of a rectangle or a chamfered rectangle, and the gate extension direction may be a diagonal direction of the rectangle or the chamfered rectangle. Specifically, one of the two connected sides of the rectangle extends along a first direction X, and the other of the two connected sides of the rectangle extends along a second direction Y. Compared to the first gate 111 and the second gate 112 extending along the first direction X or the second direction Y, the first gate 111 and the second gate 112 extending along the diagonal direction within the rectangular active area 110 have a longer dimension in the gate extension direction Z. This helps increase the length of the first gate 111 and the second gate 112, thereby facilitating a reduction in the difference in threshold voltage between the first transistor and the second transistor, that is, reducing the difference in threshold voltage between the two pull-up transistors or the two pull-down transistors in the sense amplifier, thereby facilitating an increase in the sensing margin of the sense amplifier and improving the electrical performance of the sense amplifier.

[0050] refer to Figure 3 In some embodiments, the active region 110 includes a first drain region I, a common source region II, and a second drain region III, which are sequentially spaced apart and arranged perpendicular to the gate extension direction Z. The portion of the active region 110 covered by the first gate 111 is located between the first drain region I and the common source region II, and the portion of the active region 110 covered by the second gate 112 is located between the common source region II and the second drain region III. The first drain region I serves as the drain of the first transistor, the second drain region III serves as the drain of the second transistor, and the common source region II serves as a shared source for the first and second transistors.

[0051] In some embodiments, reference Figures 2 to 3The sense amplifier structure further includes an interconnect layer (not shown), which is located above the substrate 10; and a conductive plug 120, which is located between a portion of the active region 110 and the interconnect layer and electrically connects the first drain region I to the interconnect layer, the common source region II to the interconnect layer, and the second drain region III to the interconnect layer. The first drain region I, the common source region II, and the second drain region III can be led out through the conductive plug 120 and electrically connected to the interconnect layer through the conductive plug 120. Subsequently, a corresponding electrical signal can be provided to the interconnect layer, and the electrical signal can be transmitted to the first drain region I, the common source region II, and the second drain region III through the conductive plug 120.

[0052] In some embodiments, the material of the interconnection layer is a conductive material. For example, the material of the interconnection layer can be copper, tungsten, titanium, or titanium nitride.

[0053] refer to Figure 3 and Figure 4 In the technical solution provided by the embodiment of the present disclosure, the cross-sections of the conductive plug 120 on the side of the first gate 111 away from the second gate 112 and the conductive plug 120 on the side of the second gate 112 away from the first gate 111 in a direction parallel to the surface of the substrate 10 can be set to a triangle, a trapezoid or other irregular shape according to the shape of the active area 110, the shape of the first gate 111 and the shape of the second gate 112. The conductive plug 120 outside the active area 110 extends toward the edge of the active area 110. By increasing the size of the conductive plug 120, the resistance of the conductive plug 120 is reduced, thereby improving the electrical performance of the sensitive amplifier. Furthermore, the first gate 111 and the second gate 112 extend along the gate extension direction Z, so that the conductive plug 120 between the first gate 111 and the second gate 112 can also have a longer length in the gate extension direction Z. This not only helps to reduce the cross-sectional area of ​​the conductive plug 120 between the first gate 111 and the second gate 112 in a direction parallel to the surface of the substrate 10, thereby reducing the resistance of the conductive plug 120, but also helps to reduce the contact area between the conductive plug 120 between the first gate 111 and the second gate 112 and the active area 110, thereby reducing the contact resistance, thereby improving the electrical performance of the sensitive amplifier.

[0054] In some embodiments, reference Figure 5An isolation structure 200 is located between adjacent active areas 110, and a conductive plug 120 adjacent to the isolation structure 200 is also located on the isolation structure 200. The isolation structure 200 is used to isolate the active areas 110 from each other and is made of an insulating material, such as silicon oxide or silicon nitride. Compared to a conductive plug 120 located only on a portion of the active area 110, the conductive plug 120 located on both the portion of the active area 110 and the isolation structure 200 has a larger size, which helps reduce the resistance of the conductive plug 120 and improve the electrical performance of the sense amplifier.

[0055] In some embodiments, reference Figure 2 Adjacent active area groups 100 each have a region for arranging other devices such as a sense amplifier, and the cross-sectional areas of the active areas 110 in the same active area group 100 in a direction parallel to the surface of the substrate 10 are different. Specifically, the transistor types corresponding to the different active areas 110 in the same active area group 100 are the same. If the active area 110 for forming a PMOS transistor is the first active area 201, and the active area 110 for forming an NMOS transistor is the second active area 202, the active area group 100 corresponding to the PMOS transistor may include a first active area 201 with a first cross-sectional area and a first active area 201 with a second cross-sectional area. The active area 110 corresponding to the PMOS transistor has a corresponding active area 110 corresponding to the NMOS transistor. The active area group 100 corresponding to the NMOS transistor may include a second active area 202 with a first cross-sectional area and a second active area 202 with a second cross-sectional area, wherein the first area and the second area are different in size.

[0056] Continue to refer Figure 2If the first area is defined as being greater than the second area, the active area 201 having the first cross-sectional area is used to form two pull-up transistors in the first sense amplifier, and the second active area 202 having the first cross-sectional area corresponding to the first active area 201 having the first cross-sectional area is used to form two pull-down transistors in the first sense amplifier; the first active area 201 having the second cross-sectional area is used to form two pull-up transistors in the second sense amplifier, and the second active area 202 having the second cross-sectional area corresponding to the first active area 201 having the second cross-sectional area is used to form two pull-down transistors in the second sense amplifier. That is, for the same sense amplifier, the two pull-up transistors or the two pull-down transistors have the same size, and the sizes of the pull-up transistors and the pull-down transistors are also the same. This facilitates the formation of sense amplifiers with balanced performance. Furthermore, for different sense amplifiers, the sizes of the transistors forming the sense amplifiers vary. For example, the size of the transistor forming the first sense amplifier is larger than the size of the transistor forming the second sense amplifier, resulting in better performance of the first sense amplifier than the second sense amplifier and better driving capability. Consequently, the first sense amplifier can be used to amplify the storage signal of a memory cell with a longer transmission distance or lower current, thereby improving memory performance. Furthermore, by controlling the size of the transistors to form sense amplifiers with different performances, it is possible to use the better-performing sense amplifier to pre-compensate for memory cells with design defects or defects caused by the manufacturing process, thereby improving memory performance.

[0057] Continue to refer Figure 2 In some embodiments, active regions 110 having a first cross-sectional area and active regions 110 having a second cross-sectional area may be alternately arranged along the second direction Y. In other embodiments, the specific positions and arrangements of the first active regions 201 or the second active regions 202 having different cross-sectional areas may be appropriately set based on the wiring layers in the sense amplifier structure and the electrical connection requirements of the transistors in the sense amplifier.

[0058] In some embodiments, reference Figure 6, there are areas between adjacent active area groups 100 for setting up other devices such as sense amplifiers. Among the multiple active areas 110 of an active area group 100, the transistor types corresponding to different active areas 110 are the same. Generally, the cross-sectional sizes of the active areas 110 corresponding to transistors of the same type in the direction parallel to the surface of the substrate 10 are the same. If the active areas 110 in the active area group 100 are used to form different types of transistors, for example, including a first active area 201 for forming a PMOS transistor and a second active area 202 for forming an NMOS transistor, then the space occupied by the active area 110 for forming the PMOS transistor is different from the space occupied by the active area 110 for forming the NMOS transistor. There will be a large number of irregularly arranged staggered areas between the active areas 110 of different sizes. These irregular staggered areas are difficult to use for setting up other devices, which may result in a waste of space. Therefore, by configuring the active areas 110 in the active area group 100 arranged along the second direction Y as active areas 110 for forming transistors of the same type, space waste can be avoided, thereby facilitating a reduction in the size of the sense amplifier structure. Specifically, among the multiple active areas 110 in an active area group 100, the gates of adjacent active areas 110 extend in different directions. In the first direction X, the first active areas 201 and the second active areas 202 are alternately arranged, and the number of first active areas 201 and the number of second active areas 202 are the same, ensuring that each first active area 201 has a corresponding second active area 202. The corresponding first active areas 201 and second active areas 202 are used to form two pull-up transistors and two pull-down transistors in the sense amplifier.

[0059] Figure 7 A schematic structural diagram of another sensitive amplifier structure provided in an embodiment of the present disclosure.

[0060] In some embodiments, reference Figure 7Adjacent active area groups 100 each have areas for mounting sense amplifiers and other devices. Within a single active area group 100, the transistor types corresponding to different active areas 110 are the same. In the first direction X, the first active areas 201 and the second active areas 202 are arranged alternately, and the number of first active areas 201 and second active areas 202 is the same. Within the same active area group, the gates of different active areas 110 extend in the same direction. If the gates of adjacent active areas 110 within the same active area group 100 extend in different directions, the conductive plugs 120 in adjacent active areas 110 may be too close together in the second direction Y, or even connected to each other. Therefore, setting the gate extension directions of the first gate 111 and the second gate 112 of different active areas 110 in the same active area group 100 to be the same direction is beneficial to ensuring that the conductive plugs 120 in adjacent active areas 110 in the second direction Y are far apart, thereby helping to avoid short-circuiting of conductive plugs 120 that are close to each other and affecting the electrical performance of the sensitive amplifier.

[0061] Figure 8 A schematic structural diagram of another sensitive amplifier structure provided in an embodiment of the present disclosure.

[0062] In some embodiments, reference Figure 8 Adjacent active area groups 100 each have regions for mounting sense amplifiers and other devices. Within each active area group 100, the transistor types corresponding to the different active areas 110 are the same. In the first direction X, the first active areas 201 and the second active areas 202 are arranged alternately, and the number of first active areas 201 and second active areas 202 is the same, ensuring that each first active area 201 has a corresponding second active area 202. In the multiple active areas 110 of an active area group 100, the gate extension directions of different active areas 110 within the same active area group 110 may be different, depending on the required lengths of the first gate 111 and the second gate 112 in the gate extension direction, as well as the position requirements of the first gate 111 and the second gate 112. Furthermore, if the first direction X is the x-direction and the second direction Y is the y-direction, the different gate extension directions are all different directions inclined from the +y-direction toward the +x-direction, or the different gate extension directions are all different directions inclined from the +y-direction toward the −x-direction. In this way, in the second direction Y, the distance between the conductive plugs 120 of adjacent active areas 110 within the same active area group 100 is greater, which helps prevent short circuits between adjacent conductive plugs 120 and the resulting impact on the electrical performance of the sense amplifier.

[0063] Figure 9 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure; Figure 10A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure; Figure 11 A schematic structural diagram of another sense amplifier structure provided by an embodiment of the present disclosure; Figure 12 A schematic structural diagram of another sensitive amplifier structure provided in an embodiment of the present disclosure.

[0064] In some embodiments, reference Figures 9 to 12 The active area 110 used to form the pull-up transistor is the first active area 201, and the active area 110 used to form the pull-down transistor is the second active area 202. The active area group corresponding to the first active area 201 is the first active area group 101, and the active area group corresponding to the second active area 202 is the second active area group 102. In the first direction X, one side of a first active area 201 has an adjacent second active area 202, ensuring that each first active area 201 has a corresponding second active area 202. The corresponding first active areas 201 and second active areas 202 are used to form two pull-up transistors and two pull-down transistors in the sense amplifier. In the first direction X, the first active region 201 has another first active region 201 on the side away from the second active region 202, and the spacing distance between the two adjacent first active regions 201 is a third length, and the spacing distance between the first active region 201 and the adjacent second active region 202 is a fourth length, the fourth length is greater than the third length, and there is a bias compensation region 103 between the first active region 201 and the adjacent second active region 202, that is, there is a bias compensation region 103 between the first active region group 101 and the adjacent second active region group 102, and the bias compensation region 103 can be used to set a bias compensation transistor. The bias compensation transistor is used to improve the performance of the sensitive amplifier, that is, the sensitive amplifier structure provided in the embodiment of the present disclosure can be used to form a bias compensated sensitive amplifier (OCSA). In other embodiments, the sensitive amplifier structure provided in the embodiment of the present disclosure can also be used to form a noise cancellation detection amplifier (NCSA). It should be noted that in order to improve the simplicity of the drawings, only Figure 9 The first active area group 101 , the second active area group 102 and the offset compensation area 103 are marked.

[0065] refer to Figure 9 or Figure 10In some embodiments, in two adjacent first active area groups 101 in the first direction X, the center points of the active areas 110 of different active area groups 100 are staggered in the first direction X. As a result, in adjacent active area groups 100 that are closely spaced, the first gates 111 located in the staggered active areas 110 of different active area groups 100 are staggered in the first direction X, and the second gates 112 located in the staggered active areas 110 of different active area groups 100 are also staggered in the first direction X. In this way, when the first gates 111 or the second gates 112 are led out using an upper wiring layer, the first gates 111 or the second gates 112 that are staggered in the first direction X facilitate the upper wiring layers leading out the first gates 111 or the second gates 112 to be staggered in the first direction X, thereby facilitating the upper wiring layers leading out different first gates 111 or second gates 112 to be prevented from being connected to each other.

[0066] refer to Figure 9 In some embodiments, in two adjacent first active area groups 101 in the first direction X, the gates on the active areas 110 of different active area groups 100 may extend in the same direction. In other embodiments, referring to Figure 10 In two adjacent first active area groups 101 in the first direction X, the gate extension directions of the active areas 110 located in different active area groups 100 may also be different. Moreover, if the first direction X is the x direction and the second direction Y is the y direction, one of the different gate extension directions is inclined from the +y direction to the +x direction, and the other is inclined from the +y direction to the −x direction. In this way, the center points of the conductive plugs 120 in the active areas 110 adjacent in the first direction X are also staggered, which helps to prevent the conductive plugs 120 in the active areas 110 adjacent in the first direction X and separated by the fourth length from being too close to each other. This can prevent the conductive plugs 120 in the active areas 110 adjacent in the first direction X from being short-circuited, thereby helping to prevent the short-circuiting from affecting the electrical performance of the sense amplifier.

[0067] In some embodiments, reference Figure 11 or Figure 12 In two adjacent first active area groups in the first direction X, the center points of the active areas 110 located in different active area groups 100 in the first direction X may also face each other, wherein facing each other means that the line connecting the center points of the two active areas is parallel to the first direction X. Figure 11 In some embodiments, in two adjacent first active area groups in the first direction X, the gate extension directions of different active areas 110 in different active area groups may be different. In other embodiments, referring to Figure 12In two adjacent first active area groups in the first direction X, the gates of different active areas 110 in different active area groups may also extend in the same direction. In this way, relatively adjacent conductive plugs 120 in active areas 110 of different active area groups 100 are staggered in the first direction X. The staggered conductive plugs 120 have a greater spacing, which helps prevent short circuits between the conductive plugs 120 in different active areas 110, thereby preventing the short circuits from affecting the electrical performance of the sense amplifier.

[0068] In some embodiments, reference Figure 9 and Figure 12 In the multiple active regions 110 corresponding to transistors of the same type, the gate extension directions of different active regions 110 are the same. The active regions 110 corresponding to transistors of the same type refer to active regions 110 that are all PMOS transistors or active regions 110 that are all NMOS transistors. Specifically, if the active region 110 used to form the PMOS transistor is the first active region 201 and the active region 110 used to form the NMOS transistor is the second active region 202, the gate extension directions of the first gates 111 or second gates 112 located on different first active regions 201 are all the same, and the gate extension directions of the first gates 111 or second gates 112 located on different second active regions 202 are all the same. In this way, Halo (ring) doping can be achieved for multiple PMOS transistors through a single doping process, and Halo doping can be achieved for multiple NMOS transistors through another doping process. That is, Halo doping can be achieved for all pull-up transistors and pull-down transistors through two doping processes, which helps reduce the process difficulty of Halo doping. Among them, it should be noted that the gate extension direction is related to the direction of Halo doping. If the gate extension direction is different, the transistors corresponding to the gates with different gate extension directions need to be doped separately. Therefore, making the gate extension direction of the first gate 111 or the second gate 112 of the same type of transistors the same is conducive to reducing the difficulty of Halo doping multiple transistors of the same type, and thus helping to reduce the difficulty of preparing sensitive amplifiers.

[0069] In some embodiments, reference Figure 10 and Figure 11 , only the gate extension directions on different second active regions 202 may be set to the same direction, and the gate extension directions on different first active regions 201 may be set to different directions, so as to facilitate Halo doping of transistors formed in the second active regions 202 .

[0070] It is understandable that in other embodiments, only the gate extension directions on different first active regions 201 can be set to the same direction, and the gate extension directions on different second active regions 202 can be set to different directions, so as to facilitate Halo doping of the transistors formed in the first active region 201.

[0071] In the sense amplifier structure provided in the above embodiment, the active area 110 in the active area group 100 is used to define two pull-up transistors or two pull-down transistors in the sense amplifier, and the first gate 111 and the second gate 112 on the active area 110 serve as the gates of the two pull-up transistors or the gates of the two pull-down transistors, respectively. If the two transistors formed in the same active area 110 are defined as the first transistor and the second transistor, respectively, the first gate 111 serves as the gate of the first transistor, and the second gate 112 serves as the gate of the second transistor, since the active area group 100 is arranged along the first direction X and the active area group 100 is arranged along the first direction X, the first gate 111 and the second gate 112 serve as the gate of the second transistor. The active area 110 is arranged along the second direction Y. Therefore, the length of the active area 110 in the second direction Y and the length of the active area 110 in the first direction X are limited. The extension direction of the first gate 111 and the second gate 112 is set to extend in the gate extension direction. Since the gate extension direction is a direction different from both the first direction X and the second direction Y, and the width of the active area 110 in the gate extension direction is greater than the width in the first direction X and greater than the width of the active area 110 in the second direction Y, the lengths of the first gate 111 and the second gate 112 extending along the gate extension direction are longer. It should be noted that, under the condition that the sizes of the first gate 111 and the second gate 112 are approximately the same, the larger the length or width that can be designed for the first gate 111 and the second gate 112, the smaller the difference between the threshold voltages of the first transistor and the second transistor. Therefore, by providing the first gate 111 and the second gate 112 extending along the gate extension direction, the lengths of the first gate 111 and the second gate 112 can be increased without increasing the overall size of the sense amplifier structure, which is beneficial to reducing the difference in threshold voltages between the two pull-up transistors or the two pull-down transistors in the sense amplifier, and further beneficial to increasing the sensing margin of the sense amplifier and improving the electrical performance of the sense amplifier.

[0072] Another aspect of the present disclosure provides a memory device comprising: a plurality of memory cells; and a sense amplifier structure according to any of the above embodiments, configured to write stored data to or read stored data from bit lines in the memory cell array. The sense amplifier is configured to read signals stored in the memory cell structure.

[0073] The memory may be a dynamic random access memory (DRAM), which operates by writing and reading data to a memory cell connected to a bit line (BL) and a complementary bit line (BLB). Turning on a sense amplifier at the appropriate time amplifies the slight voltage difference between the bit line and the complementary bit line, allowing the data stored in the memory cell to be correctly read.

[0074] In the sensitive amplifier structure provided by the above-mentioned embodiment, the difference in threshold voltage between the two pull-up transistors or the two pull-down transistors is small. Therefore, the mismatch noise caused by the threshold voltage mismatch is small. The smaller mismatch noise enables the sensitive amplifier to have a higher sensing margin. The sensitive amplifier with a higher sensing margin has the ability to amplify signals quickly and effectively, which is conducive to improving the performance of the memory.

[0075] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A sensitive amplifier structure, characterized in that: include: A plurality of active area groups arranged at intervals along a first direction on the substrate, each of the active area groups comprising a plurality of active areas arranged at intervals along a second direction; a first gate and a second gate arranged at intervals on the active area, wherein the first gate and the second gate on the same active area extend in the same direction, the extension direction being a gate extension direction, and the first gate and the second gate are respectively used as gates of two pull-up transistors of a sense amplifier or gates of two pull-down transistors of a sense amplifier; In which, the gate extension direction is different from the first direction and the second direction, and for the same active area, in the gate extension direction, the length of the first gate is a first length, the first length is greater than the maximum length of the active area in the first direction, and the first length is greater than the maximum length of the active area in the second direction; the length of the second gate is a second length, the second length is greater than the maximum length of the active area in the first direction, and the second length is greater than the maximum length of the active area in the second direction.

2. The sense amplifier structure according to claim 1, wherein: In the gate extension direction, the first length is equal to the second length, and in a direction perpendicular to the gate extension direction, the width of the first gate is the same as the width of the second gate.

3. The sense amplifier structure according to claim 1, wherein: The cross section of the active region in a direction parallel to the substrate surface is at least one of a rectangle or a chamfered rectangle, and the gate extends in a diagonal direction of the rectangle or the chamfered rectangle.

4. The sense amplifier structure according to claim 1, wherein: The active area includes a first drain area, a common source area and a second drain area arranged in sequence perpendicular to the extension direction of the gate. The part of the active area covered by the first gate is located between the first drain area and the common source area, and the part of the active area covered by the second gate is located between the common source area and the second drain area.

5. The sense amplifier structure according to claim 4, wherein: Also includes: an interconnect layer located above the substrate; A conductive plug is located between part of the active area and the interconnection layer, and is used to electrically connect the first drain area and the interconnection layer, electrically connect the common source area and the interconnection layer, and electrically connect the second drain area and the interconnection layer.

6. The sense amplifier structure according to claim 5, wherein: There is an isolation structure between adjacent active areas, and the conductive plug is also located on the adjacent isolation structure.

7. The sense amplifier structure according to claim 1, wherein: In the plurality of active areas of an active area group, the gates on different active areas have the same extension direction.

8. The sense amplifier structure according to claim 7, wherein: In the active area groups adjacent to each other in the first direction, center points of the active areas of different active area groups are staggered with each other in the first direction.

9. The sense amplifier structure according to claim 8, wherein: In two adjacent active area groups in the first direction, the gate extension directions on the active areas located in different active area groups are different, and if the first direction is the x direction and the second direction is the y direction, one of the different gate extension directions is a direction inclined from the +y direction to the +x direction, and the other is a direction inclined from the +y direction to the -x direction.

10. The sense amplifier structure according to claim 7, wherein: In the active area groups adjacent to each other in the first direction, center points of two active areas adjacent to each other in the first direction face each other.

11. The sense amplifier structure according to claim 10, wherein: In two adjacent active area groups in the first direction, the gates of different active area groups extend in the same direction.

12. The sense amplifier structure according to claim 1, wherein: The active area for forming the pull-up transistor is defined as the first active area, and the active area for forming the pull-down transistor is defined as the second active area. In the first direction, one side of the first active area has an adjacent second active area.

13. The sense amplifier structure according to claim 12, wherein: In the first direction, a side of the first active region away from the second active region has another first active region.

14. The sense amplifier structure according to claim 13, wherein: In the first direction, the spacing distance between two adjacent first active areas is a third length, the spacing distance between the first active area and the adjacent second active area is a fourth length, the fourth length is greater than the third length, and there is a bias compensation area between the first active area and the adjacent second active area, and the bias compensation area is used to set the bias compensation transistor.

15. A memory structure, characterized in that: include: storage unit; The sense amplifier structure according to any one of claims 1 to 14 is used to write storage data to a bit line in the memory cell array or read storage data from a bit line in the memory cell array.

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