Decoder driving circuit and memory chip

Abstract

The present application relates to a decoding and driving circuit and a storage chip. The decoding and driving circuit includes a plurality of sub-driving units and a decoding control module. The sub-driving units are used to generate a main word line driving signal according to a power supply voltage signal, a first decoding input signal, and an intermediate decoding output signal. The decoding control module is connected to the plurality of sub-driving units and is used to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal. Wherein, during the period when the intermediate decoding output signal is in a first state, the main word line driving signal is in a non-driving state. The present application can reduce the volume of the decoding and driving circuit in the row decoding circuit without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor storage chip, thereby relatively increasing the storage capacity per unit area of the semiconductor storage chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and particularly to a decoding drive circuit and a memory chip. Background Art

[0002] With the rapid development of semiconductor and integrated circuit technologies, the market has increasingly higher requirements for the storage capacity per unit area of semiconductor memory chips.

[0003] A semiconductor memory chip generally includes a memory array area and a peripheral circuit area. Among them, a memory cell array including a plurality of memory cells is provided in the memory array area, and a control circuit for controlling reading and writing and a mode register for setting storage parameters are provided in the peripheral circuit area. The control circuit for controlling reading and writing includes a sense amplifier circuit, a data input / output conversion circuit, a row / column decoding circuit and its control circuit, etc.

[0004] If it is possible to reduce the volume of the decoding drive circuit in the row decoding circuit without reducing the storage capacity of the memory array area, it will undoubtedly be able to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, thereby relatively increasing the storage capacity per unit area of the semiconductor memory chip. Summary of the Invention

[0005] Based on this, it is necessary to provide a decoding drive circuit and a memory chip for the technical problems in the above background art, which can reduce the volume of the decoding drive circuit in the row decoding circuit without reducing the storage capacity of the memory array area.

[0006] According to some embodiments, one aspect of this application provides a decoding drive circuit, including a plurality of sub-drive units and a decoding control module. The sub-drive unit is used to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal and an intermediate decoding output signal; the decoding control module is connected to the plurality of sub-drive units and is used to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal; wherein, during the period when the intermediate decoding output signal is in a first state, the main word line drive signal is in a non-driving state.

[0007] In the decoding and driving circuit in the above embodiment, by arranging the decoding control module to be connected to a plurality of sub-driving units, and arranging the decoding control module to generate an intermediate decoding output signal according to the enable control signal and the second decoding input signal and provide it to each sub-driving unit, so that each sub-driving unit generates a main word line driving signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, and the main word line driving signal, together with the word line driving signal and the word line reset signal, realizes the control of a plurality of local word line driving circuits in the row decoding circuit. In this embodiment, it is realized that a decoding control module is used to control a plurality of sub-driving units to control a plurality of local word line driving circuits, and the volume of the decoding and driving circuit in the row decoding circuit can be reduced without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, thereby relatively increasing the storage capacity per unit area of the semiconductor memory chip.

[0008] In one of the embodiments, the sub-driving unit includes a first transistor, a second transistor and a third transistor. The first transistor is configured such that: the source is connected to the power supply voltage signal, and the gate is connected to the first decoding input signal; the second transistor is configured such that: the source is connected to the power supply voltage signal, and the gate is connected to the intermediate decoding output signal; the third transistor is configured such that: the source is connected to the decoding control module, the drain is connected to both the drain of the first transistor and the drain of the second transistor, and the gate is connected to both the gate of the first transistor and the first decoding input signal. In this embodiment, by arranging the first transistor and the third transistor to form an inverter with a control terminal connected to the first decoding input signal, and the output terminal of the inverter is connected to the output terminal of the second transistor, the control terminal of the second transistor is connected to the intermediate decoding output signal and the input terminal is connected to the power supply voltage signal, so that the sub-driving unit generates a main word line driving signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, in order to realize the control of a plurality of local word line driving circuits by using a decoding control module to control a plurality of sub-driving units.

[0009] In one embodiment, the enable control signal includes a first enable control signal and a second enable control signal; the decoding control module includes a first inverter, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a second decoding signal receiving unit. The first inverter is configured such that: its power supply terminal is connected to a first power supply, and its output terminal is connected to the gate of the second transistor; the fourth transistor is configured such that: its source is grounded, its drain is connected to the source of the third transistor, and its gate is connected to both the gate of the second transistor and the output terminal of the first inverter; the fifth transistor is configured such that: its source is connected to the first power supply, its drain is connected to the input terminal of the first inverter, and its gate is connected to both the output terminal of the first inverter and the gate of the second transistor; the sixth transistor is configured such that: its source is connected to the first power supply, its drain is connected to both the input terminal of the first inverter and the drain of the fifth transistor, and its gate is connected to the first enable control signal; the seventh transistor is configured such that: its source is connected to the second decoding signal receiving unit, its drain is connected to both the drain of the sixth transistor and the input terminal of the first inverter, and its gate is connected to the second enable control signal.

[0010] In one embodiment, the second decoding input signal includes a second main decoding input signal and a second sub - decoding input signal; the second decoding signal receiving unit includes an eighth transistor and a ninth transistor. The eighth transistor is configured such that: its drain is connected to the source of the seventh transistor, and its gate is connected to the second main decoding input signal; the ninth transistor is configured such that: its source is grounded, its drain is connected to the source of the eighth transistor, and its gate is connected to the second sub - decoding input signal.

[0011] In one embodiment, the decoding drive circuit further includes an enable control module. The enable control module is connected to a plurality of the decoding control modules and is configured to provide the first enable control signal and the second enable control signal to the plurality of decoding control modules according to a main word line enable signal.

[0012] In one embodiment, the enable control module includes a second inverter, a third inverter, and a fourth inverter. The second inverter is configured such that: its input terminal is connected to the main word line enable signal, and its power supply terminal is connected to the first power supply; the third inverter is configured such that: its input terminal is connected to the output terminal of the second inverter, its power supply terminal is connected to the first power supply, and its output terminal outputs the first enable control signal; the fourth inverter is configured such that: its input terminal is connected to the output terminal of the second inverter, its power supply terminal is connected to a second power supply, and its output terminal outputs the second enable control signal.

[0013] In one embodiment, the amplitude of the output voltage of the first power supply is greater than the amplitude of the output voltage of the second power supply.

[0014] In one embodiment, the decoding and driving circuit further includes a power control module. The power control module is connected to each of the sub-driving units and is configured to provide the power voltage signal to each of the sub-driving units. Wherein, the power control module is further configured to output power voltage signals with different voltage amplitudes according to the power control signal.

[0015] In one embodiment, the power control signal includes a first sub-power control signal and a second sub-power control signal. The power control module includes a first power control unit and a second power control unit. The first power control unit is connected to a third power source, the first sub-power control signal, and the second sub-power control signal, and is configured to generate a power voltage signal with a first amplitude according to the first sub-power control signal and the second sub-power control signal. The second power control unit is connected to the first power source and the inverted signal of the second sub-power control signal, and is configured to generate a power voltage signal with a second amplitude according to the inverted signal of the second sub-power control signal.

[0016] In one embodiment, the power control module further includes a third power control unit. The third power control unit is connected to the first power source and the inverted signal of the first sub-power control signal, and is configured to generate a power voltage signal with a third amplitude according to the inverted signal of the first sub-power control signal.

[0017] In one embodiment, the first power control unit includes a tenth transistor and an eleventh transistor. The tenth transistor is configured such that its source is connected to the third power source and its gate is connected to the first sub-power control signal. The eleventh transistor is configured such that its source is connected to the drain of the tenth transistor, its gate is connected to the second sub-power control signal, and its drain outputs the power voltage signal with the first amplitude.

[0018] In one embodiment, the second power control unit includes a twelfth transistor and a thirteenth transistor. The twelfth transistor is configured such that its source is connected to the first power source and its gate is connected to its drain. The thirteenth transistor is configured such that its source is connected to the drain of the twelfth transistor, its gate is connected to the inverted signal of the second sub-power control signal, and its drain outputs the power voltage signal with the second amplitude.

[0019] In one embodiment, the third power control unit includes a fourteenth transistor. The fourteenth transistor is configured such that its source is connected to the first power source, its gate is connected to the inverted signal of the first sub-power control signal, and its drain outputs the power voltage signal with the third amplitude.

[0020] In one embodiment, the amplitude of the third power supply output voltage is less than that of the first power supply output voltage; the first amplitude is greater than the second amplitude, and the second amplitude is greater than the third amplitude.

[0021] According to some embodiments, another aspect of the present application provides a storage chip, including the decoding and driving circuit described in any embodiment of the present application. By connecting the decoding control module to multiple sub-driving units, and setting the decoding control module to generate an intermediate decoding output signal according to the enable control signal and the second decoding input signal and provide it to each sub-driving unit, so that each sub-driving unit generates a main word line driving signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, and the main word line driving signal, together with the word line driving signal and the word line reset signal, realizes the control of multiple local word line driving circuits in the row decoding circuit. In this embodiment, the control of multiple local word line driving circuits is realized by using a decoding control module to control multiple sub-driving units, which can reduce the volume of the decoding and driving circuit in the row decoding circuit without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor storage chip, thereby relatively increasing the storage capacity per unit area of the semiconductor storage chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0023] Figure 1 It is a structural block diagram of a decoding and driving circuit provided in an embodiment of the present application;

[0024] Figure 2 It is a circuit principle schematic diagram of the i-th sub-driving unit in a decoding and driving circuit provided in an embodiment of the present application, where 1≤i≤n, both i and n are positive integers, and n is the number of sub-driving units;

[0025] Figure 3 It is a circuit principle schematic diagram of a decoding control module in a decoding and driving circuit provided in an embodiment of the present application;

[0026] Figure 4 It is a structural block diagram of a decoding and driving circuit provided in another embodiment of the present application;

[0027] Figure 5 It is a circuit principle schematic diagram of an enable control module in a decoding and driving circuit provided in an embodiment of the present application;

[0028] Figure 6 Schematic diagram of the circuit principle of the power control module in a decoding driving circuit provided in an embodiment of the present application;

[0029] Figure 7 Schematic diagram of the circuit principle of a local word line driving circuit provided in an embodiment of the present application.

[0030] Description of the reference numerals:

[0031] 100, decoding driving circuit; 10, decoding control module; 11, second decoding signal receiving unit; 20, sub-driving unit; 21, first sub-driving unit; 2i, the i-th sub-driving unit; 2n, the n-th sub-driving unit; 30, enable control module; 40, power control module; 41, first power control unit; 42, second power control unit; 43, third power control unit. Detailed implementation manners

[0032] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0034] In addition, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers may refer to elements by different names. This document does not intend to distinguish elements with different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should therefore be construed as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be accomplished through a direct electrical connection or through an indirect electrical connection via other devices and connectors.

[0035] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0036] Please refer to Figure 1 , in an embodiment of the present application, a decoding drive circuit 100 is provided, including a first sub-drive unit 21, an i-th sub-drive unit 2i, an n-th sub-drive unit 2n, and a decoding control module 10. Among them, the i-th sub-drive unit 2i is used to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp; the decoding control module 10 is connected to the first sub-drive unit 21, the i-th sub-drive unit 2i, and the n-th sub-drive unit 2n, and is used to generate an intermediate decoding output signal MIntp according to an enable control signal and a second decoding input signal; wherein, during the period when the intermediate decoding output signal MIntp is in a first state, the main word line drive signal is in a non-driving state. The first sub-drive unit 21 generates a main word line drive signal bMWL0 according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp, the i-th sub-drive unit 2i generates a main word line drive signal bMWLi-1 according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp, and the n-th sub-drive unit 2n generates a main word line drive signal bMWLn-1 according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp. In this embodiment, 1≤i≤n, both i and n are positive integers, and n is the number of sub-drive units.

[0037] Specifically, please continue to refer to Figure 1 , by setting the decoding control module 10 to be connected to multiple sub-drive units, and setting the decoding control module 10 to generate an intermediate decoding output signal MIntp according to an enable control signal and a second decoding input signal and provide it to each sub-drive unit, so that each sub-drive unit generates a main word line drive signal according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp. The main word line drive signal, together with the word line drive signal and the word line reset signal, realizes the control of multiple local word line drive circuits in the row decoding circuit. It can be set that during the period when the intermediate decoding output signal MIntp is in a first state, the main word line drive signal is in a non-driving state, so that the word lines connected to the subsequent stage remain in an inactive state; and it is set that during the period when the intermediate decoding output signal MIntp is in a second state, the main word line drive signal is in a driving state to drive the word lines connected to the subsequent stage to remain in an active state. In this embodiment, it is realized to use a decoding control module 10 to control multiple sub-drive units to realize the control of multiple local word line drive circuits, and it is possible to reduce the volume of the decoding drive circuit 100 in the row decoding circuit without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, thereby relatively increasing the storage capacity per unit area of the semiconductor memory chip.

[0038] For example, refer to Figure 2 , it can be set that the i-th sub-driving unit 2i includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 is configured as follows: the source is connected to the power supply voltage signal PbMWL, and the gate is connected to the first decoding input signal Intp1; the second transistor M2 is configured as follows: the source is connected to the power supply voltage signal PbMWL, and the gate is connected to the intermediate decoding output signal MIntp; the third transistor M3 is configured as follows: the source is connected to the decoding control module 10, the drain is connected to the drains of both the first transistor M1 and the second transistor M2, and the gate is connected to both the gate of the first transistor M1 and the first decoding input signal Intp1, where 1 ≤ i ≤ n, both i and n are positive integers, and n is the number of sub-driving units. In this embodiment, by setting the first transistor M1 and the third transistor M3 to form an inverter whose control terminal is connected to the first decoding input signal Intp1, and the output terminal of this inverter is connected to the output terminal of the second transistor M2, the gate of the second transistor M2 is connected to the intermediate decoding output signal MIntp and the input terminal is connected to the power supply voltage signal, so that the corresponding connected sub-driving unit 20 generates a main word line driving signal according to the power supply voltage signal PbMWL, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp to drive the word line connected to the subsequent stage, realizing the control of multiple local word line driving circuits by using a decoding control module 10 to control multiple sub-driving units 20.

[0039] For example, refer to Figure 3, the enable control signal can be set to include a first enable control signal EN1 and a second enable control signal EN2; the decoding control module 10 includes a first inverter (not shown), a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a second decoding signal receiving unit 11. The first inverter is configured such that: the power supply terminal is connected to the first power supply VDD1, and the output terminal is connected to the gate of the second transistor M2; the fourth transistor M4 is configured such that: the source is grounded, the drain is connected to the source of the third transistor M3, and the gate is connected to both the gate of the second transistor M2 and the output terminal of the first inverter; the fifth transistor M5 is configured such that: the source is connected to the first power supply VDD1, the drain is connected to the input terminal of the first inverter, and the gate is connected to both the output terminal of the first inverter and the gate of the second transistor M2; the sixth transistor M6 is configured such that: the source is connected to the first power supply VDD1, the drain is connected to both the input terminal of the first inverter and the drain of the fifth transistor M5, and the gate is connected to the first enable control signal EN1; the seventh transistor M7 is configured such that: the source is connected to the second decoding signal receiving unit 11, the drain is connected to both the drain of the sixth transistor M6 and the input terminal of the first inverter, and the gate is connected to the second enable control signal EN2. The decoding control module 10 provides a corresponding intermediate decoding output signal MIntp to the sub-driving unit 20 connected to the subsequent stage according to the signals provided by the first enable control signal EN1, the second enable control signal EN2, and the second decoding signal receiving unit 11, so that the sub-driving unit can generate a main word line driving signal according to the power supply voltage signal PbMWL, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp to drive the word line connected to the subsequent stage. In this embodiment, it can be realized that during the period when the intermediate decoding output signal MIntp is in the first state, the main word line driving signals output by the sub-driving units 20 connected to the subsequent stage are in the non-driving state, so that the word lines corresponding to the subsequent stage remain in the non-activated state; and during the period when the intermediate decoding output signal MIntp is in the second state, the main word line driving signals output by the sub-driving units 20 connected to the subsequent stage are in the driving state to drive the word lines corresponding to the subsequent stage to remain in the activated state.

[0040] As an example, please refer to Figure 3 , it can be set that the first inverter includes a transistor Q1 and a transistor Q2. The transistor Q1 is configured such that: the source is connected to the first power supply VDD1, and the gate is connected to the drain of the fifth transistor M5; the transistor Q2 is configured such that: the source is grounded, the drain is connected to the drain of the transistor Q1 and serves as the output terminal of the first inverter, and the gate is connected to the gate of the transistor Q1 and serves as the input terminal of the first inverter.

[0041] As an example, please continue to refer to Figure 3, the second decoding input signal includes a second main decoding input signal Intp2 and a second secondary decoding input signal Intp3; the second decoding signal receiving unit 11 includes an eighth transistor M8 and a ninth transistor M9. The eighth transistor M8 is configured such that its drain is connected to the source of the seventh transistor M7, and its gate is connected to the second main decoding input signal Intp2. The ninth transistor M9 is configured such that its source is grounded, its drain is connected to the source of the eighth transistor M8, and its gate is connected to the second secondary decoding input signal Intp3. The second decoding signal receiving unit 11 provides a source signal to the seventh transistor M7 according to the second main decoding input signal Intp2 and the second secondary decoding input signal Intp3, and cooperates with the first enable control signal EN1 and the second enable control signal EN2 to control the operations of the sixth transistor M6 and the seventh transistor M7, and provides a driving signal to the subsequent circuit, so that the decoding control module 10 provides a corresponding intermediate decoding output signal to the sub-driving unit 20 connected to the subsequent stage, enabling the sub-driving unit 20 to generate a main word line driving signal according to the power supply voltage signal PbMWL, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp to drive the word line connected to the subsequent stage.

[0042] As an example, please refer to Figure 4 , the decoding driving circuit 100 further includes an enable control module 30. The enable control module 30 is connected to a plurality of decoding control modules 10 and is configured to provide a first enable control signal EN1 and a second enable control signal EN2 to the plurality of decoding control modules 10 according to the main word line enable signal bMWLEn.

[0043] As an example, please refer to Figure 5 , the enable control module 30 includes a second inverter Inv2, a third inverter Inv3, and a fourth inverter Inv4. The second inverter Inv2 is configured such that its input terminal is connected to the main word line enable signal bMWLEn, and its power supply terminal is connected to the first power supply VDD1. The third inverter Inv3 is configured such that its input terminal is connected to the output terminal of the second inverter Inv2, its power supply terminal is connected to the first power supply VDD1, and its output terminal outputs the first enable control signal EN1. The fourth inverter Inv4 is configured such that its input terminal is connected to the output terminal of the second inverter Inv2, its power supply terminal is connected to the second power supply VDD2, and its output terminal outputs the second enable control signal EN2. It can be set that the amplitude of the output voltage of the first power supply VDD1 is greater than the amplitude of the output voltage of the second power supply VDD2.

[0044] As an example, please continue to refer to Figure 5 , it can be set that the amplitude of the output voltage of the first power supply VDD1 is 3V, and the amplitude of the output voltage of the second power supply VDD2 is 1.6V.

[0045] As an example, please refer to Figure 6, the decoding and driving circuit 100 further includes a power control module 40. The power control module 40 is connected to each sub-driving unit and is configured to provide a power supply voltage signal to each sub-driving unit. Among them, the power control module 40 is further configured to output power supply voltage signals with different voltage amplitudes according to a power control signal.

[0046] As an example, please continue to refer to Figure 6 , it can be set that the power control signal includes a first sub-power control signal Sel1 and a second sub-power control signal Sela. The power control module 40 includes a first power control unit 41 and a second power control unit 42. The first power control unit 41 is connected to a third power supply VDD3, the first sub-power control signal Sel1, and the second sub-power control signal Sela, and is configured to generate a power supply voltage signal with a first amplitude according to the first sub-power control signal Sel1 and the second sub-power control signal Sela. The second power control unit 42 is connected to a first power supply VDD1 and the inverted signal Selb of the second sub-power control signal, and is configured to generate a power supply voltage signal with a second amplitude according to the inverted signal Selb of the second sub-power control signal.

[0047] As an example, please continue to refer to Figure 6 , it can be set that the first power control unit 41 includes a tenth transistor M10 and an eleventh transistor M11. The tenth transistor M10 is configured as follows: the source is connected to the third power supply VDD3, and the gate is connected to the first sub-power control signal Sel1. The eleventh transistor M11 is configured as follows: the source is connected to the drain of the tenth transistor M10, the gate is connected to the second sub-power control signal Sela, and the drain outputs a power supply voltage signal with a first amplitude.

[0048] As an example, please continue to refer to Figure 6 , it can be set that the second power control unit 42 includes a twelfth transistor M12 and a thirteenth transistor M13. The twelfth transistor M12 is configured as follows: the source is connected to the first power supply VDD1, and the gate is connected to the drain. The thirteenth transistor M13 is configured as follows: the source is connected to the drain of the twelfth transistor M12, the gate is connected to the inverted signal Selb of the second sub-power control signal, and the drain outputs a power supply voltage signal with a second amplitude.

[0049] As an example, please continue to refer to Figure 6 , it can be set that the amplitude of the output voltage of the first power supply VDD1 is 3V, and the amplitude of the output voltage of the third power supply VDD3 is 1.8V, so that the first power control unit 41 can output a power supply voltage signal of 3v - Vt, and the second power control unit 42 can output a power supply voltage signal of 1.8v.

[0050] As an example, please continue to refer to Figure 6, it can be set that the power control module 40 further includes a third power control unit 43. The third power control unit 43 is connected to the first power supply VDD1 and the inverted signal Sel2 of the first sub-power control signal, and is used to generate a power supply voltage signal with a third amplitude according to the inverted signal Sel2 of the first sub-power control signal.

[0051] As an example, please continue to refer to Figure 6 , it can be set that the third power control unit 43 includes a fourteenth transistor M14. The fourteenth transistor M14 is configured as follows: the source is connected to the first power supply VDD1, the gate is connected to the inverted signal Sel2 of the first sub-power control signal, and the drain outputs a power supply voltage signal with a third amplitude. For example, it can be set that the amplitude of the output voltage of the first power supply VDD1 is 3V, so that the third power control unit 43 can output a power supply voltage signal of 3V.

[0052] As an example, please continue to refer to Figure 6 , it can be set that the amplitude of the output voltage of the third power supply VDD3 is less than the amplitude of the output voltage of the first power supply VDD1; the first amplitude is greater than the second amplitude, and the second amplitude is greater than the third amplitude. For example, it can be set that the amplitude of the output voltage of the first power supply VDD1 is 3V, and the amplitude of the output voltage of the third power supply VDD3 is 1.8V, so that the first power control unit 41 can output a power supply voltage signal of 3V-Vt, the second power control unit 42 can output a power supply voltage signal of 1.8V, and the third power control unit 43 can output a power supply voltage signal of 3V. In the state where the power control module 40 drives the circuit to work frequently, the third power control unit 43 can be controlled to output a power supply voltage signal of 3V to reduce the power consumption of frequently switching the power supply voltage signal; when the power control module 40 drives the circuit to be in the standby state, the first power control unit 41 can be controlled to output a power supply voltage signal of 3V-Vt to prepare for the working power consumption of the driving circuit while reducing the power consumption; when the power control module 40 drives the circuit to be in a state of not working for a longer time, the second power control unit 42 can be controlled to output a power supply voltage signal of 1.8V to reduce the circuit power consumption.

[0053] As an example, please continue to refer to Figure 6 , it can be set that the second sub-power control signal Sela is connected to a control circuit (not shown) via an inverter Inv5, and the first sub-power control signal Sel1 is connected to the control circuit via an inverter Inv6, so that the control circuit can control the power control module 40 to output a power supply voltage signal with a corresponding amplitude according to the actual working state of the power control module 40 driving circuit, so as to reduce the circuit power consumption.

[0054] As an example, please refer to Figure 7, the circuit of the local word line driver circuit (Local Word Line Driver, LWD) includes transistor Q3, transistor Q4, and transistor Q5. Transistor Q3 is configured such that its source is connected to the word line drive signal WLDV, its gate is connected to the main word line drive signal bMWL, and its drain is connected to the word line WL. Transistor Q4 is configured such that its source is grounded, its drain is connected to the drain of transistor Q3 and the word line WL, and its gate is connected to the main word line drive signal bMWL. Transistor Q5 is configured such that its source is grounded, its drain is connected to the drain of transistor Q3, the drain of transistor Q4, and the word line WL, and its gate is connected to the word line reset signal WLRst. The circuit of the local word line driver circuit drives the state of the word line WL according to the main word line drive signal bMWL, the word line reset signal WLRst, and the word line drive signal WLDV. For example, during a period when the intermediate decoding output signal is set to the first state, the main word line drive signal bMWL output by the decoding drive circuit is in a non-driving state, so that the word line WL remains in an inactive state. And during a period when the intermediate decoding output signal is set to the second state, the main word line drive signal bMWL output by the decoding drive circuit is in a driving state to drive the word line WL to remain in an active state.

[0055] The word line drive signal WLDV and the word line reset signal WLRst involved in the above embodiments can be implemented using related existing technologies, and the specific implementation principle will not be elaborated in this application.

[0056] According to some embodiments, the present application provides a storage chip, including the decoding drive circuit in any embodiment of the present application. By connecting the decoding control module to multiple sub-driving units, and setting the decoding control module to generate an intermediate decoding output signal according to the enable control signal and the second decoding input signal and provide it to each sub-driving unit, so that each sub-driving unit generates a main word line drive signal according to the power supply voltage signal, the first decoding input signal, and the intermediate decoding output signal. The main word line drive signal, together with the word line drive signal and the word line reset signal, realizes the control of multiple local word line driver circuits in the row decoding circuit. During a period when the intermediate decoding output signal is set to the first state, the main word line drive signal is in a non-driving state, so that the word line connected to the subsequent stage remains in an inactive state. And during a period when the intermediate decoding output signal is set to the second state, the main word line drive signal is in a driving state to drive the word line connected to the subsequent stage to remain in an active state. In this embodiment, it is realized to control multiple local word line driver circuits by using a decoding control module to control multiple sub-driving units, which can reduce the volume of the decoding drive circuit in the row decoding circuit without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor storage chip, and thus can relatively improve the storage capacity per unit area of the semiconductor storage chip.

[0057] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present invention.

[0058] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0059] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A decoding driving circuit, characterized in that: It includes: A plurality of sub-driving units, configured to generate a main word line driving signal according to a power supply voltage signal, a first decoding input signal, and an intermediate decoding output signal; A decoding control module, connected to the plurality of sub-driving units, and configured to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal; Wherein, during the period when the intermediate decoding output signal is in a first state, the main word line driving signal is in a non-driving state; The sub-driving unit includes: A first transistor, configured such that: the source is connected to the power supply voltage signal, and the gate is connected to the first decoding input signal; A second transistor, configured such that: the source is connected to the power supply voltage signal, and the gate is connected to the intermediate decoding output signal; A third transistor, configured such that: the source is connected to the decoding control module, the drain is connected to the drains of the first transistor and the second transistor, and the gate is connected to the gate of the first transistor and the first decoding input signal; The enable control signal includes a first enable control signal and a second enable control signal; the decoding control module includes: A first inverter, configured such that: the power supply terminal is connected to a first power supply, and the output terminal is connected to the gate of the second transistor; A fourth transistor, configured such that: the source is grounded, the drain is connected to the source of the third transistor, and the gate is connected to the gate of the second transistor and the output terminal of the first inverter; A fifth transistor, configured such that: the source is connected to the first power supply, the drain is connected to the input terminal of the first inverter, and the gate is connected to the output terminal of the first inverter and the gate of the second transistor; A sixth transistor, configured such that: the source is connected to the first power supply, the drain is connected to the input terminal of the first inverter and the drain of the fifth transistor, and the gate is connected to the first enable control signal; A seventh transistor, configured such that: the source is connected to a second decoding signal receiving unit, the drain is connected to the drain of the sixth transistor and the input terminal of the first inverter, and the gate is connected to the second enable control signal.

2. The decoding driving circuit according to claim 1, characterized in that: The second decoding input signal includes a second main decoding input signal and a second sub-decoding input signal; The second decoding signal receiving unit includes: An eighth transistor, configured such that: the drain is connected to the source of the seventh transistor, and the gate is connected to the second main decoding input signal; A ninth transistor, configured such that: the source is grounded, the drain is connected to the source of the eighth transistor, and the gate is connected to the second sub-decoding input signal.

3. The decoding driving circuit according to claim 2, characterized in that: It further includes: An enable control module, connected to the plurality of decoding control modules, and configured to provide the first enable control signal and the second enable control signal to the plurality of decoding control modules according to a main word line enable signal.

4. The decoding driving circuit according to claim 3, characterized in that: The enable control module includes: The second inverter is configured such that its input terminal is connected to the main word line enable signal, and its power supply terminal is connected to the first power supply; The third inverter is configured such that its input terminal is connected to the output terminal of the second inverter, its power supply terminal is connected to the first power supply, and its output terminal outputs the first enable control signal; The fourth inverter is configured such that its input terminal is connected to the output terminal of the second inverter, its power supply terminal is connected to the second power supply, and its output terminal outputs the second enable control signal.

5. The decoding and driving circuit according to claim 4, wherein the amplitude of the output voltage of the first power supply is greater than the amplitude of the output voltage of the second power supply.

6. The decoding and driving circuit according to any one of claims 1-5, wherein it further includes: a power supply control module connected to each of the sub-driving units for providing the power supply voltage signal to each of the sub-driving units; wherein the power supply control module is further configured to output power supply voltage signals with different voltage amplitudes according to the power supply control signal.

7. The decoding and driving circuit according to claim 6, wherein the power supply control signal includes a first sub-power supply control signal and a second sub-power supply control signal; the power supply control module includes: a first power supply control unit connected to the third power supply, the first sub-power supply control signal, and the second sub-power supply control signal, and configured to generate a power supply voltage signal with a first amplitude according to the first sub-power supply control signal and the second sub-power supply control signal; a second power supply control unit connected to the first power supply and the inverted signal of the second sub-power supply control signal, and configured to generate a power supply voltage signal with a second amplitude according to the inverted signal of the second sub-power supply control signal.

8. The decoding and driving circuit according to claim 7, wherein the power supply control module further includes: a third power supply control unit connected to the first power supply and the inverted signal of the first sub-power supply control signal, and configured to generate a power supply voltage signal with a third amplitude according to the inverted signal of the first sub-power supply control signal.

9. The decoding and driving circuit according to claim 7, wherein the first power supply control unit includes: a tenth transistor configured such that its source electrode is connected to the third power supply and its gate electrode is connected to the first sub-power supply control signal; an eleventh transistor configured such that its source electrode is connected to the drain electrode of the tenth transistor, its gate electrode is connected to the second sub-power supply control signal, and its drain electrode outputs the power supply voltage signal with the first amplitude.

10. The decoding and driving circuit according to claim 7, wherein the second power supply control unit includes: a twelfth transistor configured such that its source electrode is connected to the first power supply and its gate electrode is connected to its drain electrode; a thirteenth transistor configured such that its source electrode is connected to the drain electrode of the twelfth transistor, its gate electrode is connected to the inverted signal of the second sub-power supply control signal, and its drain electrode outputs the power supply voltage signal with the second amplitude.

11. The decoding and driving circuit according to claim 8, wherein the third power supply control unit includes: The fourteenth transistor is configured such that its source is connected to the first power supply, its gate is connected to the inverted signal of the first sub-power supply control signal, and its drain outputs the power supply voltage signal having the third amplitude.

12. The decoding and driving circuit according to claim 11, wherein: The amplitude of the output voltage of the third power supply is smaller than the amplitude of the output voltage of the first power supply; The first amplitude is greater than the second amplitude, and the second amplitude is greater than the third amplitude.

13. A storage chip, wherein: It includes: The decoding and driving circuit according to any one of claims 1-12.

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