Decoder driving circuit and memory chip

Abstract

The present application relates to a decoding drive circuit and a storage chip. The decoding drive circuit includes a power control module, a plurality of sub-drive units, and a plurality of decoding control modules. The power control module is configured to generate power supply voltage signals with different voltage amplitudes according to a control signal. The sub-drive units are configured to generate main word line drive signals according to the power supply voltage signals, a first decoding input signal, and an intermediate decoding output signal. The decoding control modules are connected to the plurality of sub-drive units and are configured to generate the intermediate decoding output signals according to an enable control signal and a second decoding input signal. The present application can, without reducing the storage capacity of the storage array area, provide main word line drive signals corresponding to different working states according to the energy consumption requirements in different working states of the storage array area, so as to control a plurality of local word line drive circuits in a row decoding circuit, effectively improving the energy saving performance of the decoding drive circuit and its subsequent drive circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and particularly to a decoding drive circuit and a memory chip. Background Art

[0002] A semiconductor memory device generally includes a memory array area and a peripheral circuit area. The memory array area is provided with a memory cell array including a plurality of memory cells, and the peripheral circuit area is provided with a control circuit for controlling reading and writing and a mode register for setting memory parameters. The control circuit for controlling reading and writing includes a sense amplifier circuit, a data input / output conversion circuit, a row / column decoding circuit and its control circuit, etc. The energy consumption sources of the semiconductor memory device mainly include the power consumption of the memory cell array and the power consumption of the peripheral circuit area.

[0003] For the memory cell array, the continuous increase of its storage capacity will inevitably lead to an increase in its power consumption. If the energy consumption of the memory cell array and the energy consumption of the peripheral circuit area can be reduced on the premise of ensuring that the storage capacity does not decrease, the energy saving performance of the semiconductor memory device will be effectively improved. Summary of the Invention

[0004] Based on this, it is necessary to provide a decoding drive circuit and a memory chip for the technical problems in the above background art, which can provide a main word line drive signal corresponding to the corresponding state according to the energy consumption requirements in different working states of the memory array area without reducing the storage capacity of the memory array area, so as to realize the control of a plurality of local word line drive circuits in the row decoding circuit, and effectively improve the energy saving performance of the decoding drive circuit and its subsequent drive circuits.

[0005] According to some embodiments, one aspect of the present application provides a decoding drive circuit, including a power control module, a plurality of sub-drive units and a plurality of decoding control modules. The power control module is used to generate power supply voltage signals with different voltage amplitudes according to control signals; the sub-drive units are used to generate main word line drive signals according to the power supply voltage signals, a first decoding input signal and an intermediate decoding output signal; the decoding control modules are connected to the plurality of sub-drive units and are used to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal.

[0006] In the decoding and driving circuit in the above embodiments, a power control module is provided to generate power supply voltage signals with different voltage amplitudes according to control signals; and a decoding control module is provided to generate intermediate decoding output signals according to the enable control signal and the second decoding input signal and provide them to each sub-driving unit, so that each sub-driving unit generates a main word line driving signal according to the power supply voltage signal, the first decoding input signal, and the intermediate decoding output signal. The main word line driving signal, together with the word line driving signal and the word line reset signal, realizes the control of multiple local word line driving circuits in the row decoding circuit. Without reducing the storage capacity of the storage array area, the present application can provide main word line driving signals corresponding to different working states according to the energy consumption requirements of the storage array area to realize the control of multiple local word line driving circuits in the row decoding circuit, effectively improving the energy saving performance of the decoding and driving circuit and its subsequent driving circuits. Since in this embodiment, a decoding control module is used to control multiple sub-driving units to realize the control of multiple local word line driving circuits, without reducing the storage capacity of the storage array area, the volume of the decoding and driving circuit in the row decoding circuit can be reduced, effectively reducing the volume of the peripheral circuit area of the semiconductor memory chip.

[0007] In one embodiment, the control signals include a first control signal and a second control signal; the power control module includes a first power control unit and a second power control unit. The first power control unit is connected to the first voltage, the first control signal, and the second control signal, and is used to generate a power supply voltage signal with a first amplitude according to the first control signal and the second control signal; the second power control unit is connected to the second voltage and the second control signal, and is used to generate a power supply voltage signal with a second amplitude according to the second control signal.

[0008] In one embodiment, the power control module further includes a third power control unit. The third power control unit is connected to the second voltage and the first control signal, and is used to generate a power supply voltage signal with a third amplitude according to the first control signal.

[0009] In one embodiment, the first power control unit includes a first inverter, a second inverter, a first transistor, and a second transistor. The first inverter is used to generate a first power control signal according to the first control signal; the second inverter is used to generate a second power control signal according to the second control signal; the first transistor is configured such that its source is connected to the first voltage and its gate is connected to the output terminal of the first inverter; the second transistor is configured such that its source is connected to the drain of the first transistor, its gate is connected to the output terminal of the second inverter, and its drain outputs the power supply voltage signal with the first amplitude.

[0010] In one embodiment, the second power control unit includes a third transistor and a fourth transistor. The third transistor is configured such that its source is connected to the second voltage and its gate is connected to its drain. The fourth transistor is configured such that its source is connected to the drain of the third transistor, its gate is connected to the inverted signal of the second power control signal, and its drain outputs the power voltage signal having the second amplitude.

[0011] In one embodiment, the third power control unit includes a fifth transistor. The fifth transistor is configured such that its source is connected to the second voltage, its gate is connected to the inverted signal of the first power control signal, and its drain outputs the power voltage signal having the third amplitude.

[0012] In one embodiment, the first voltage is less than the second voltage; the first amplitude is less than the second amplitude, and the second amplitude is less than or equal to the third amplitude.

[0013] In one embodiment, the decoding control module includes an enable control unit, an output inverter, and a second decoding control unit. The enable control unit is configured to output the second voltage or the voltage of the second decoding output node according to the main word line enable signal. The output inverter is connected to the enable control unit and is configured to output the intermediate decoding output signal. The second decoding control unit is connected to the enable control unit and is configured to provide the voltage of the second decoding output node to the enable control unit according to the second decoding input signal.

[0014] In one embodiment, the second decoding control unit includes a protection transistor and a decoding control transistor. The protection transistor is configured such that its gate is connected to the third voltage and its drain outputs the voltage of the second decoding output node. The decoding control transistor is configured such that its gate is connected to the second decoding input signal, its source is grounded, and its drain is connected to the source of the protection transistor; wherein, the second voltage is greater than the third voltage.

[0015] In one embodiment, the second decoding input signal includes a second main decoding input signal and a second sub-decoding input signal; the decoding control transistor includes a sixth transistor and a seventh transistor. The sixth transistor is configured such that its drain is connected to the source of the protection transistor and its gate is connected to the second main decoding input signal. The seventh transistor is configured such that its source is grounded, its drain is connected to the source of the sixth transistor, and its gate is connected to the second sub-decoding input signal.

[0016] In one embodiment, the sub-driving unit includes an eighth transistor, a ninth transistor, and a tenth transistor. The eighth transistor is configured such that: its source is connected to the power supply voltage signal, and its gate is connected to the first decoding input signal; the ninth transistor is configured such that: its source is connected to the power supply voltage signal, and its gate is connected to the intermediate decoding output signal; the tenth transistor is configured such that: its source is connected to the decoding control module, its drain is connected to the drains of both the eighth transistor and the ninth transistor, and its gate is connected to the gate of the eighth transistor and the first decoding input signal.

[0017] In one embodiment, the enabling control unit includes an eleventh transistor and a twelfth transistor. The eleventh transistor is configured such that: its source is connected to the second voltage, and its gate is connected to the main word line enabling signal; the twelfth transistor is configured such that: its source is connected to the second decoding control unit, and its gate is connected to the gate of the eleventh transistor and the main word line enabling signal.

[0018] In one embodiment, the decoding control module further includes a decoding control power supply unit; the decoding control power supply unit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The thirteenth transistor is configured such that: its source is connected to the second voltage, and its gate is grounded; the fourteenth transistor is configured such that: its source is connected to the drain of the thirteenth transistor, its gate is connected to the output terminal of the output inverter, and its drain is connected to the input terminal of the output inverter; the fifteenth transistor is configured such that: its source is grounded, its gate is connected to the gate of the fourteenth transistor, the output terminal of the output inverter, and the gate of the ninth transistor, and its drain is connected to the source of the tenth transistor.

[0019] In one embodiment, the output inverter includes a sixteenth transistor and a seventeenth transistor. The sixteenth transistor is configured such that: its source is connected to the second voltage, and its gate is connected to the drain of the fourteenth transistor and the output terminal of the enabling control unit; the seventeenth transistor is configured such that: its source is grounded, its gate is connected to the gate of the eleventh transistor, and its drain is connected to the drain of the sixteenth transistor.

[0020] According to some embodiments, another aspect of the present application provides a storage chip, including the decoding and driving circuit described in any embodiment of the present application. By setting a power control module to generate power supply voltage signals with different voltage amplitudes according to control signals; and setting a decoding control module to generate intermediate decoding output signals according to an enable control signal and a second decoding input signal and provide them to each sub-driving unit, so that each sub-driving unit generates a main word line driving signal according to the power supply voltage signal, a first decoding input signal, and the intermediate decoding output signal. The main word line driving signal, together with the word line driving signal and the word line reset signal, realizes the control of multiple local word line driving circuits in the row decoding circuit. The present application can provide main word line driving signals corresponding to different working states according to the energy consumption requirements in the storage array area without reducing the storage capacity of the storage array area, so as to realize the control of multiple local word line driving circuits in the row decoding circuit, effectively improving the energy saving performance of the decoding and driving circuit and its subsequent driving circuits. Since in this embodiment, a decoding control module is used to control multiple sub-driving units to realize the control of multiple local word line driving circuits, the volume of the decoding and driving circuit in the row decoding circuit can be reduced without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor storage chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 FIG. is a schematic structural diagram of a decoding and driving circuit provided in the first embodiment of the present application;

[0023] Figure 2 FIG. is a schematic circuit diagram of a power control module in a decoding and driving circuit provided in an embodiment of the present application;

[0024] Figure 3 FIG. is a schematic structural diagram of a decoding control module in a decoding and driving circuit provided in an embodiment of the present application;

[0025] Figure 4 FIG. is a schematic structural diagram of a decoding control module in a decoding and driving circuit provided in another embodiment of the present application;

[0026] Figure 5 FIG. is a schematic circuit diagram of a decoding control module and the i-th sub-driving unit in a decoding and driving circuit provided in an embodiment of the present application, where 1 ≤ i ≤ n, both i and n are positive integers, and n is the number of sub-driving units;

[0027] Figure 6 This is a schematic diagram of the circuit principle of a local word line driving circuit provided in an embodiment of the present application.

[0028] Description of the reference numerals:

[0029] 100, decoding and driving circuit; 10, decoding control module; 11, enabling control unit; 12, output inverter; 13, second decoding control unit; 14, decoding control power supply unit; 20, sub-driving unit; 30, power control module; 21, first sub-driving unit; 2i, the i-th sub-driving unit; 2n, the n-th sub-driving unit; 131, protection transistor; 132, decoding control transistor; 31, first power control unit; 32, second power control unit; 33, third power control unit. Detailed implementation manners

[0030] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0032] In addition, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish elements that have different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be accomplished by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0033] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0034] Please refer to Figure 1 In one embodiment of the present application, a decoding driving circuit 100 is provided, including a first sub-driving unit 21, an i-th sub-driving unit 2i, an n-th sub-driving unit 2n, and a decoding control module 10. The i-th sub-driving unit 2i is configured to generate a main word line driving signal according to a power supply voltage signal, a first decoding input signal Intp1, and an intermediate decoding output signal MIntp. The decoding control module 10 is connected to the first sub-driving unit 21, the i-th sub-driving unit 2i, and the n-th sub-driving unit 2n, and is configured to generate the intermediate decoding output signal MIntp according to an enable control signal and a second decoding input signal. The power supply control module 30 is configured to generate a power supply voltage signal PbMWL with different voltage amplitudes according to a control signal. In this embodiment, 1 ≤ i ≤ n, both i and n are positive integers, and n is the number of sub-driving units.

[0035] As an example, please continue to refer to Figure 1, by setting the power control module 30 to generate a power supply voltage signal PbMWL with different voltage amplitudes according to the control signal, and setting the decoding control module 10 to generate an intermediate decoding output signal MIntp according to the enable control signal and the second decoding input signal and provide it to the first sub-driving unit 21, the i-th sub-driving unit 2i, and the n-th sub-driving unit 2n, so that the first sub-driving unit 21 generates a main word line driving signal bMWL0 according to the power supply voltage signal, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp, the i-th sub-driving unit 2i generates a main word line driving signal bMWLi-1 according to the power supply voltage signal, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp, and the n-th sub-driving unit 2n generates a main word line driving signal bMWLn-1 according to the power supply voltage signal, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp, so that each sub-driving unit generates a main word line driving signal bMWL according to the power supply voltage signal PbMWL, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp. The main word line driving signal bMWL, together with the word line driving signal and the word line reset signal, realizes the control of multiple local word line driving circuits in the row decoding circuit. The present application can provide the main word line driving signal bMWL in the corresponding state according to the energy consumption requirements in different working states of the storage array area without reducing the storage capacity of the storage array area, so as to realize the control of multiple local word line driving circuits in the row decoding circuit, and effectively improve the energy saving performance of the decoding driving circuit 100 and its subsequent driving circuits. It can be set that during the period when the intermediate decoding output signal MIntp is in the first state, the main word line driving signal is in the non-driving state, so that the word line connected to the subsequent stage remains in the non-activated state; and during the period when the intermediate decoding output signal MIntp is in the second state, the main word line driving signal is in the driving state to drive the word line connected to the subsequent stage to remain in the activated state, realizing the control of multiple sub-driving units 20 by a decoding control module 10 to control multiple local word line driving circuits. Without reducing the storage capacity of the storage array area, the volume of the decoding driving circuit 100 in the row decoding circuit can be reduced, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip.

[0036] Please refer to Figure 2, the control signal can be set to include a first control signal PM1 and a second control signal PM2, and the power control module 30 can be set to include a first power control unit 31 and a second power control unit 32. The first power control unit 31 is connected to the first voltage VDD1, the inverted signal Sel1 of the first control signal PM1, and the inverted signal Sela of the second control signal, and is used to generate a power supply voltage signal PbMWL with a first amplitude according to the inverted signal Sel1 of the first control signal PM1 and the inverted signal Sela of the second control signal and provide it to the corresponding connected i-th sub-driving unit 2i, where 1 ≤ i ≤ n, and both i and n are positive integers, and n is the number of sub-driving units; the second power control unit 32 is connected to the second voltage VDD2 and the second control signal PM2, and is used to generate a power supply voltage signal PbMWL with a second amplitude according to the second control signal PM2.

[0037] As an example, please continue to refer to Figure 2 , the power control module 30 further includes a third power control unit 33. The third power control unit 33 is connected to the second voltage VDD2 and the first control signal PM1, and is used to generate a power supply voltage signal PbMWL with a third amplitude according to the first control signal PM1.

[0038] As an example, please continue to refer to Figure 2 , the first power control unit 31 includes a first inverter Inv1, a second inverter Inv2, a first transistor M1, and a second transistor M2. The first inverter Inv1 is used to generate a first power control signal Sel1 according to the first control signal PM1; the second inverter Inv2 is used to generate a second power control signal Sela according to the second control signal PM2; the first transistor M1 is configured such that the source is connected to the first voltage, and the gate is connected to the output terminal of the first inverter Inv1; the second transistor M2 is configured such that the source is connected to the drain of the first transistor M1, the gate is connected to the output terminal of the second inverter Inv2, and the drain outputs a power supply voltage signal PbMWL with a first amplitude.

[0039] As an example, please continue to refer to Figure 2 , the second power control unit 32 includes a third transistor M3 and a fourth transistor M4. The third transistor M3 is configured such that the source is connected to the second voltage, and the gate is connected to the drain; the fourth transistor M4 is configured such that the source is connected to the drain of the third transistor M3, the gate is connected to the inverted signal Selb of the second power control signal, and the drain outputs a power supply voltage signal PbMWL with a second amplitude.

[0040] As an example, please continue to refer to Figure 2, the third power supply control unit 33 includes a fifth transistor M5, and the fifth transistor M5 is configured such that: its source is connected to the second voltage VDD2, its gate is connected to the inverted signal Sel2 of the first power supply control signal, and its drain outputs a power supply voltage signal PbMWL having a third amplitude.

[0041] As an example, please continue to refer to Figure 2 , it can be set that the first voltage VDD1 is less than the second voltage VDD2, the first amplitude is less than the second amplitude, and the second amplitude is less than or equal to the third amplitude. For example, it can be set that the amplitude of the output voltage of the first voltage VDD1 is 1.8V, and the amplitude of the output voltage of the second voltage VDD2 is 3.0V, so that the first power supply control unit 31 can output a power supply voltage signal of 1.8V, the second power supply control unit 32 can output a power supply voltage signal of 3v - Vt, and the third power supply control unit 33 can output a power supply voltage signal of 3.0V. In a state where the power supply control module 30 drives the circuit to work frequently, the third power supply control unit 33 can be controlled to output a power supply voltage signal of 3V to reduce the power consumption of frequently switching the power supply voltage signal; when the power supply control module 30 drives the circuit to be in a standby state, the second power supply control unit 32 can be controlled to output a power supply voltage signal of 3v - Vt to prepare for the working power consumption of the driving circuit while reducing the power consumption; when the power supply control module 30 drives the circuit to be in a state of not working for a longer time, the first power supply control unit 31 can be controlled to output a power supply voltage signal of 1.8V to reduce the circuit power consumption.

[0042] As an example, please refer to Figure 3 , the decoding control module 10 includes an enable control unit 11, an output inverter 12, and a second decoding control unit 13. The enable control unit 11 is configured to output a second voltage or the voltage of a second decoding output node to the output inverter 12 according to a main word line enable signal; the output inverter 12 is connected to the enable control unit 11 and is configured to output an intermediate decoding output signal MIntp to the connected sub - driving unit 20 according to the signal provided by the enable control unit 11; the second decoding control unit 13 is connected to the enable control unit 11 and is configured to provide the voltage of the second decoding output node to the enable control unit 11 according to a second decoding input signal.

[0043] As an example, please refer to Figure 4 , the second decoding control unit 13 includes a protection transistor 131 and a decoding control transistor 132. The protection transistor 131 is configured such that: its gate is connected to the third voltage VDD3, and its drain outputs the voltage of the second decoding output node; the decoding control transistor is configured such that: its gate is connected to the second decoding input signal, its source is grounded, and its drain is connected to the source of the protection transistor 131; wherein, the second voltage is greater than the third voltage. As an example, please refer to Figure 5, the second decoding input signal can be set to include a second main decoding input signal Intp2 and a second sub-decoding input signal Intp3; the decoding control transistor includes a sixth transistor M6 and a seventh transistor M7, and the protection transistor 131 includes a transistor Q1. The sixth transistor M6 is configured such that its drain is connected to the source of the transistor Q1, and its gate is connected to the second main decoding input signal Intp2; the seventh transistor M7 is configured such that its source is grounded, its drain is connected to the source of the sixth transistor M6, and its gate is connected to the second sub-decoding input signal Intp3. The second voltage can be set to 3V, and the third voltage can be set to 1.6V.

[0044] As an example, please continue to refer to Figure 5 , the i-th sub-driving unit 2i includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10, where 1 ≤ i ≤ n, and both i and n are positive integers, and n is the number of sub-driving units; the eighth transistor M8 is configured such that its source is connected to the power supply voltage signal PbMWL, and its gate is connected to the first decoding input signal Intp1; the ninth transistor M9 is configured such that its source is connected to the power supply voltage signal PbMWL, and its gate is connected to the intermediate decoding output signal MIntp; the tenth transistor M10 is configured such that its source is connected to the decoding control module 10, its drain is connected to the drains of both the eighth transistor M8 and the ninth transistor M9, and its gate is connected to the gates of both the eighth transistor M8 and the first decoding input signal Intp1. In this embodiment, by setting the eighth transistor M8 and the tenth transistor M10 to form an inverter whose control terminal is connected to the first decoding input signal Intp1, and the output terminal of this inverter is connected to the output terminal of the ninth transistor M9, and the gate of the ninth transistor M9 is connected to the intermediate decoding output signal MIntp and its input terminal is connected to the power supply voltage signal, the corresponding connected sub-driving unit generates a main word line driving signal according to the power supply voltage signal PbMWL, the first decoding input signal Intp1, and the intermediate decoding output signal MIntp to drive the word line connected to the subsequent stage, thereby realizing the control of multiple local word line driving circuits by using a decoding control module 10 to control multiple sub-driving units.

[0045] As an example, please continue to refer to Figure 5, the enable control unit 11 includes an eleventh transistor M11 and a twelfth transistor M12. The eleventh transistor M11 is configured such that its source is connected to the second voltage VDD2 and its gate is connected to the main word line enable signal bMWLEn. The twelfth transistor M12 is configured such that its source is connected to the second decoding control unit 13 and its gate is connected to both the gate of the eleventh transistor M11 and the main word line enable signal bMWLEn. The enable control unit 11 is used to output the second voltage VDD2 or the voltage of the second decoding output node to the output inverter 12 according to the main word line enable signal bMWLEn. For example, if the main word line enable signal bMWLEn is a high-level signal, the enable control unit 11 outputs the second voltage VDD2 to the output inverter 12; if the main word line enable signal bMWLEn is a low-level signal, the enable control unit 11 outputs the voltage of the second decoding output node to the output inverter 12.

[0046] As an example, please continue to refer to Figure 5 , the decoding control module 10 further includes a decoding control power supply unit 14; the decoding control power supply unit 14 includes a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The thirteenth transistor M13 is configured such that its source is connected to the second voltage VDD2 and its gate is grounded. The fourteenth transistor M14 is configured such that its source is connected to the drain of the thirteenth transistor M13, its gate is connected to the output terminal of the output inverter 12, and its drain is connected to the input terminal of the output inverter 12. The fifteenth transistor M15 is configured such that its source is grounded, its gate is connected to the gate of the fourteenth transistor M14, the output terminal of the output inverter 12, and the gate of the ninth transistor M9, and its drain is connected to the source of the tenth transistor M10. The decoding control power supply unit 14 cooperates with the enable control unit 11 and the output inverter 12 to provide an intermediate decoding output signal MIntp to the corresponding connected sub-driving unit, so that the sub-driving unit can provide a main word line driving signal in a corresponding state according to the power consumption requirements in different working states of the storage array area, to drive the word line connected at the rear stage, and to realize the control of multiple local word line driving circuits in the row decoding circuit, effectively improving the energy saving performance of the decoding driving circuit and its subsequent driving circuit.

[0047] As an example, please continue to refer to Figure 5, the output inverter 12 includes a sixteenth transistor M16 and a seventeenth transistor M17. The sixteenth transistor M16 is configured such that its source is connected to the second voltage VDD2, and its gate is connected to the drain of the fourteenth transistor M14 and the output terminal of the enable control unit 11. The seventeenth transistor M17 is configured such that its source is grounded, its gate is connected to the gate of the eleventh transistor M11, and its drain is connected to the drain of the sixteenth transistor M16. The output inverter 12 provides an intermediate decoding output signal MIntp to the corresponding connected sub-driving unit according to the second voltage VDD2 provided by the enable control unit 11 or the voltage of the second decoding output node, and the voltage provided by the decoding control power supply unit 14, enabling the sub-driving unit to provide a main word line driving signal corresponding to the power consumption requirements in different operating states of the memory array area, driving the word line connected to the subsequent stage, so as to realize the control of multiple local word line driving circuits in the row decoding circuit, effectively improving the energy saving performance of the decoding driving circuit and its subsequent driving circuit.

[0048] As an example, please refer to Figure 6 , the circuit of the local word line driver (Local Word Line Driver, LWD) includes a transistor Q3, a transistor Q4, and a transistor Q5. The transistor Q3 is configured such that its source is connected to the word line driving signal WLDV, its gate is connected to the main word line driving signal bMWL, and its drain is connected to the word line WL. The transistor Q4 is configured such that its source is grounded, its drain is connected to the drain of the transistor Q3 and the word line WL, and its gate is connected to the main word line driving signal bMWL. The transistor Q5 is configured such that its source is grounded, its drain is connected to the drain of the transistor Q3, the drain of the transistor Q4, and the word line WL, and its gate is connected to the word line reset signal WLRst. The circuit of the local word line driver drives the state of the word line WL according to the main word line driving signal bMWL, the word line reset signal WLRst, and the word line driving signal WLDV. For example, it can be set that during the period when the intermediate decoding output signal is in the first state, the main word line driving signal bMWL output by the decoding driving circuit is in a non-driving state, so that the word line WL remains in an inactive state; and during the period when the intermediate decoding output signal is in the second state, the main word line driving signal bMWL output by the decoding driving circuit is in a driving state to drive the word line WL to remain in an active state.

[0049] Regarding the word line driving signal WLDV and the word line reset signal WLRst involved in the above embodiments, they can be implemented using related existing technologies, and the specific implementation principle will not be elaborated in this application.

[0050] According to some embodiments, the present application provides a storage chip, including a decoding and driving circuit 100 in any of the embodiments of the present application. By setting a power control module 30 to generate a power supply voltage signal PbMWL with different voltage amplitudes according to a control signal; and setting a decoding control module 10 to generate an intermediate decoding output signal MIntp according to an enable control signal and a second decoding input signal and provide it to each sub-driving unit 20, so that each sub-driving unit 20 generates a main word line driving signal according to the power supply voltage signal PbMWL, a first decoding input signal Intp1, and the intermediate decoding output signal MIntp. The main word line driving signal, together with the word line driving signal and the word line reset signal, realizes the control of multiple local word line driving circuits in the row decoding circuit. The present application can provide a main word line driving signal corresponding to the working state according to the energy consumption requirements in different working states of the storage array area without reducing the storage capacity of the storage array area, so as to realize the control of multiple local word line driving circuits in the row decoding circuit, and effectively improve the energy saving performance of the decoding and driving circuit 100 and its subsequent driving circuits. Since in this embodiment, a decoding control module 10 is used to control multiple sub-driving units 20 to realize the control of multiple local word line driving circuits, the volume of the decoding and driving circuit 100 in the row decoding circuit can be reduced without reducing the storage capacity of the storage array area, so as to effectively reduce the volume of the peripheral circuit area of the semiconductor storage chip.

[0051] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present invention.

[0052] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0053] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A decoding driving circuit, characterized in that: It includes: A power control module for generating power supply voltage signals with different voltage amplitudes according to control signals; Multiple sub-driving units for generating main word line driving signals according to the power supply voltage signal, the first decoding input signal, and the intermediate decoding output signal; Several decoding control modules, the decoding control modules are connected to the multiple sub-driving units, and are used for generating the intermediate decoding output signal according to the enable control signal and the second decoding input signal; The control signal includes a first control signal and a second control signal; the power control module includes: A first power control unit, connected to the first voltage, the first control signal, and the second control signal, and is used for generating a power supply voltage signal with a first amplitude according to the first control signal and the second control signal; A second power control unit, connected to the second voltage and the second control signal, and is used for generating a power supply voltage signal with a second amplitude according to the second control signal.

2. The decoding driving circuit according to claim 1, characterized in that: The power control module further includes: A third power control unit, connected to the second voltage and the first control signal, and is used for generating a power supply voltage signal with a third amplitude according to the first control signal.

3. The decoding driving circuit according to claim 2, characterized in that: The first power control unit includes: A first inverter for generating a first power control signal according to the first control signal; A second inverter for generating a second power control signal according to the second control signal; A first transistor, configured as: the source is connected to the first voltage, and the gate is connected to the output terminal of the first inverter; A second transistor, configured as: the source is connected to the drain of the first transistor, the gate is connected to the output terminal of the second inverter, and the drain outputs the power supply voltage signal with the first amplitude.

4. The decoding driving circuit according to claim 3, characterized in that: The second power control unit includes: A third transistor, configured as: the source is connected to the second voltage, and the gate is connected to the drain; A fourth transistor, configured as: the source is connected to the drain of the third transistor, the gate is connected to the inverted signal of the second power control signal, and the drain outputs the power supply voltage signal with the second amplitude.

5. The decoding driving circuit according to claim 3, characterized in that: The third power control unit includes: A fifth transistor, configured as: the source is connected to the second voltage, the gate is connected to the inverted signal of the first power control signal, and the drain outputs the power supply voltage signal with the third amplitude.

6. The decoding driving circuit according to claim 5, characterized in that: The first voltage is less than the second voltage; The first amplitude is less than the second amplitude, and the second amplitude is less than or equal to the third amplitude.

7. The decoding driving circuit according to any one of claims 1-2, characterized in that: The decoding control module includes: An enable control unit, configured to output a second voltage or the voltage of a second decoding output node according to a main word line enable signal; An output inverter, connected to the enable control unit, configured to output the intermediate decoding output signal; A second decoding control unit, connected to the enable control unit, configured to provide the voltage of the second decoding output node to the enable control unit according to a second decoding input signal.

8. The decoding driving circuit according to claim 7, wherein: The second decoding control unit includes: A protection transistor, configured such that: its gate is connected to a third voltage, and its drain outputs the voltage of the second decoding output node; A decoding control transistor, configured such that: its gate is connected to the second decoding input signal, its source is grounded, and its drain is connected to the source of the protection transistor; Wherein, the second voltage is greater than the third voltage.

9. The decoding driving circuit according to claim 8, wherein: The second decoding input signal includes a second main decoding input signal and a second sub-decoding input signal; The decoding control transistor includes: A sixth transistor, configured such that: its drain is connected to the source of the protection transistor, and its gate is connected to the second main decoding input signal; A seventh transistor, configured such that: its source is grounded, its drain is connected to the source of the sixth transistor, and its gate is connected to the second sub-decoding input signal.

10. The decoding driving circuit according to claim 9, wherein: The sub-driving unit includes: An eighth transistor, configured such that: its source is connected to the power supply voltage signal, and its gate is connected to the first decoding input signal; A ninth transistor, configured such that: its source is connected to the power supply voltage signal, and its gate is connected to the intermediate decoding output signal; A tenth transistor, configured such that: its source is connected to the decoding control module, its drain is connected to the drains of the eighth transistor and the ninth transistor, and its gate is connected to the gate of the eighth transistor and the first decoding input signal.

11. The decoding driving circuit according to claim 10, wherein: The enable control unit includes: An eleventh transistor, configured such that: its source is connected to the second voltage, and its gate is connected to the main word line enable signal; A twelfth transistor, configured such that: its source is connected to the second decoding control unit, and its gate is connected to the gate of the eleventh transistor and the main word line enable signal.

12. The decoding driving circuit according to claim 11, wherein: The decoding control module further includes a decoding control power supply unit; The decoding control power supply unit includes: A thirteenth transistor, configured such that: its source is connected to the second voltage, and its gate is grounded; A fourteenth transistor, configured such that: its source is connected to the drain of the thirteenth transistor, its gate is connected to the output end of the output inverter, and its drain is connected to the input end of the output inverter; A fifteenth transistor, configured such that: its source is grounded, its gate is connected to the gate of the fourteenth transistor, the output end of the output inverter, and the gate of the ninth transistor, and its drain is connected to the source of the tenth transistor.

13. The decoding and driving circuit according to claim 12, wherein: The output inverter includes: A sixteenth transistor configured such that its source is connected to the second voltage, and its gate is connected to the drain of the fourteenth transistor and the output terminal of the enable control unit; A seventeenth transistor configured such that its source is grounded, its gate is connected to the gate of the eleventh transistor, and its drain is connected to the drain of the sixteenth transistor.

14. A storage chip, wherein: It includes: The decoding and driving circuit according to any one of claims 1-13.

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