Method for manufacturing semiconductor chip and semiconductor chip

Abstract

The present invention discloses a method for manufacturing a semiconductor chip, comprising the following steps: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped substrate and a lightly doped epitaxial layer, and the substrate and the epitaxial layer are doped of N-type; using the hard mask dielectric layer as a barrier layer, photolithography and etching processes are used to form a groove on the semiconductor substrate; removing the hard mask dielectric layer, and growing a first silicon oxide, silicon nitride, and a second silicon oxide; using a chemical mechanical polishing process to remove the second silicon oxide protruding from the upper surface of the silicon nitride, while retaining the second silicon oxide in the groove; using ion implantation and annealing processes to form a first P-type doped region in the epitaxial layer; and using an etching process to remove part of the second silicon oxide in the groove. The present invention provides a semiconductor chip, and the method for manufacturing a semiconductor chip and the semiconductor chip disclosed by the present invention have the advantages of reducing the on-resistance of a MOSFET chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor chip and the semiconductor chip. Background Art

[0002] MOSFET chip is a type of semiconductor chip and belongs to the category of power semiconductor chips. According to its physical structure, MOSFET chips can be classified into two major categories: planar MOSFET and trench MOSFET. Among them, trench MOSFET has a higher current density and dominates medium and low voltage MOSFETs; according to its conductivity type, MOSFET chips can be classified into N-channel MOSFET and P-channel MOSFET. Among them, the majority carriers of N-channel MOSFET are free electrons, and the majority carriers of P-channel MOSFET are holes, so N-channel MOSFET has a higher current density and a wider range of usage scenarios.

[0003] The DC parameters that measure the quality of MOSFET chips include breakdown voltage, on-resistance and threshold voltage. Generally speaking, the larger the breakdown voltage, the better, and the smaller the on-resistance, the better, but the two are contradictory to each other. Therefore, the on-resistance per unit area (Rsp) is usually used to measure the technological advancement of MOSFET chips. Summary of the Invention

[0004] The present invention provides a method for manufacturing a semiconductor chip, which has the advantages of reducing the on-resistance of a MOSFET chip and solving the problem of excessive on-resistance of the original MOSFET chip.

[0005] According to an embodiment of the present application, a method for manufacturing a semiconductor chip includes the following steps:

[0006] Growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped substrate and a lightly doped epitaxial layer, wherein the substrate and the epitaxial layer are doped in an N-type manner;

[0007] Using the hard mask dielectric layer as a barrier layer, photolithography and etching processes are used to form trenches on the semiconductor substrate;

[0008] removing the hard mask dielectric layer, and growing a first silicon oxide, a silicon nitride, and a second silicon oxide;

[0009] Using a chemical mechanical polishing process to remove the second silicon oxide protruding from the upper surface of the silicon nitride, and retaining the second silicon oxide in the groove;

[0010] forming a first P-type doped region in the epitaxial layer by using ion implantation and annealing processes;

[0011] Using an etching process to remove a portion of the second silicon oxide in the trench;

[0012] Using an ion implantation process, a second P-type doping region is formed on the upper surface layer and the side surface layer of the first P-type doping region;

[0013] Using an etching process to remove part of the second silicon oxide in the trench again;

[0014] Using an ion implantation process, an N-type doped region is formed in the epitaxial layer on the sidewall of the trench;

[0015] Using an etching process to sequentially remove all of the second silicon oxide, silicon nitride, and first silicon oxide;

[0016] A thermal oxidation process is used to grow a third silicon oxide layer, namely a gate oxide layer;

[0017] Depositing polysilicon, and removing the polysilicon above the upper surface of the third silicon oxide, leaving the polysilicon in the trench;

[0018] Photolithography, ion implantation and annealing processes are used to form the source region, and then the contact holes are made.

[0019] Preferably, the first P-type doped region is the body region of the MOSFET, the polysilicon is the polysilicon gate of the MOSFET, the substrate and the epitaxy are the drain of the MOSFET, and the depth of the trench is 0.8 to 1.6 microns and the width is 0.1 to 0.4 microns.

[0020] Preferably, the thickness of the first silicon oxide is 200 to 500 angstroms, and the process method for growing the first silicon oxide is a thermal oxidation process; the thickness of the silicon nitride is 200 to 600 angstroms, and the process method for growing the silicon nitride is chemical vapor deposition; the thickness of the second silicon oxide is 2000 to 8000 angstroms, and the process method for growing the second silicon oxide is plasma chemical vapor deposition (HDP), and the second silicon oxide fills the groove.

[0021] Preferably, after the process of growing the first silicon oxide, silicon nitride and the second silicon oxide, high temperature annealing is performed, and the temperature of the high temperature annealing is 900 to 1150 degrees Celsius.

[0022] Preferably, an ion implantation and annealing process is used to form a first P-type doped region in the epitaxial layer, wherein the dopant of the ion implantation is boron and the implantation dose is 0.6E13 to 3E13 per cm 2 The first P-type doping is distributed in the entire region from the upper surface of the epitaxial layer to a depth of D1, and the depth D1 of the first P-type doping region is 0.5 to 1.1 microns.

[0023] Preferably, an etching process is used to remove part of the second silicon oxide in the groove. The etching process is quantitative etching, and the second silicon oxide in the area from the upper surface of the epitaxial layer to the depth D2 is completely etched away. The depth D2 is 300 to 800 angstroms smaller than the depth D1.

[0024] Preferably, an ion implantation process is used to form a second P-type doping region on the upper surface and side surface of the first P-type doping region, wherein the dopant of the ion implantation is boron and the implantation dose (E1) is 1E13 to 2E14 per cm 2 .

[0025] Preferably, the etching process is used to remove part of the second silicon oxide in the trench again, and the etching process is quantitative etching, leaving the second silicon oxide with a longitudinal thickness (D3) of 0.2 to 0.5 microns at the bottom of the trench.

[0026] Preferably, an ion implantation process is used to form an N-type doped region in the epitaxial layer of the trench sidewall, the ion implanted dopant is phosphorus, the implantation dose is E2, E2 is equal to E1, the depth of the source region is 0.1 to 0.3 microns, and the depth of the first P-type doped region minus the depth of the source region is the channel length of the MOSFET chip.

[0027] In order to solve the above technical problem, the present invention provides a semiconductor chip, which is manufactured according to the above-mentioned method for manufacturing a semiconductor chip.

[0028] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0029] 1. The trench-type N-channel MOSFET chip formed by the present invention has an N-type doped region formed along the trench sidewall in the epitaxial layer below the body region. Those skilled in the art should know that Figure 14 As shown (the arrow indicates the direction of current), when the trench MOSFET chip is turned on, the carriers move along the channel of the trench sidewall in the body region. Below the body region, most of the carriers flow along the trench sidewall and then diverge at the bottom of the trench to flow across the entire epitaxial layer cross section. Therefore, an N-type doped region is made along the trench sidewall in the epitaxial layer below the body region, which can reduce the resistance of the carriers flowing through this region, thereby reducing the on-resistance of the MOSFET chip.

[0030] 2. The N-type doped region produced by the present invention is distributed below the MOSFET body region, but there is no N-type doped region distributed in the bottom area of ​​the trench. Those skilled in the art should know that the electric field at the bottom of the trench is usually the strongest, and it is the critical electric field generation point that causes the source and drain breakdown of the MOSFET. The N-type doped region produced by the present invention avoids the bottom area of ​​the trench, so the breakdown voltage of the MOSFET will not be affected (that is, it will not become smaller). It can be seen that the present invention reduces the on-resistance of the MOSFET without reducing the breakdown low voltage, that is, achieves a lower on-resistance per unit area (Rsp), and can obtain a lower on-resistance under the same chip area, thereby improving the performance of the MOSFET.

[0031] 3. The present invention prepares a body region (a first P-type doped region) before etching the oxide layer (the second silicon oxide) in the trench, then quantitatively etches the oxide layer (the second silicon oxide) in the trench twice, and designs an ion implantation process accordingly, ultimately forming an N-type doped region along the trench sidewall in the epitaxial layer below the body region, while at the same time preventing the trench sidewall in the area where the body region is located from being doped to form an N-type doped region (otherwise the threshold voltage of the MOSFET chip will become smaller or even unable to be turned off), and also preventing the trench bottom from being doped to form an N-type doped region (otherwise the breakdown voltage of the MOSFET chip will become smaller), in terms of process. A more ideal doping area distribution is achieved by a very simple and ingenious process method; on the other hand, before quantitatively etching the oxide layer (second silicon oxide) in the groove, a chemical mechanical polishing process is used to remove the second silicon oxide that is higher than the upper surface of the silicon nitride. This method can ensure that the initial position of the second silicon oxide is fixed before the quantitative etching of the second silicon oxide, thereby accurately ensuring the depth of the two quantitative etchings; the high-temperature annealing after the process of growing the first silicon oxide, silicon nitride and second silicon oxide mentioned above is also to reduce the etching rate of the second silicon oxide, so that more accurate quantitative etching can be achieved at the operational level.

[0032] 4. Compared with the traditional process method for manufacturing MOSFET chips, the present invention does not add a photolithography layer and still maintains an advantage in process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1-A A schematic flow chart of a method for manufacturing a semiconductor chip according to the present invention;

[0035] Figure 1-B A schematic flow chart of a method for manufacturing a semiconductor chip according to the present invention;

[0036] Figure 1 This is a schematic structural diagram of step S1 of the present invention;

[0037] Figure 2 This is a structural diagram of step S2 of the present invention;

[0038] Figure 3 This is a structural diagram of step S3 of the present invention;

[0039] Figure 4 This is a schematic structural diagram of step S4 of the present invention;

[0040] Figure 5 This is a schematic structural diagram of step S5 of the present invention;

[0041] Figure 6 This is a schematic structural diagram of step S6 of the present invention;

[0042] Figure 7 This is a schematic structural diagram of step S7 of the present invention;

[0043] Figure 8 This is a structural diagram of step S8 of the present invention;

[0044] Figure 9 This is a structural diagram of step S9 of the present invention;

[0045] Figure 10 This is a structural diagram of step S10 of the present invention;

[0046] Figure 11 This is a structural diagram of step S11 of the present invention;

[0047] Figure 12 This is a structural diagram of step S12 of the present invention;

[0048] Figure 13 This is a schematic structural diagram of a semiconductor chip according to the present invention;

[0049] Figure 14 This is another structural schematic diagram of a semiconductor chip of the present invention. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0051] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0052] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0053] See also Figure 1-A to Figure 1 -B, the present invention provides a method 100 for manufacturing a semiconductor chip, comprising the following steps:

[0054] Step S1: growing a hard mask dielectric layer 3 on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped substrate 1 and a lightly doped epitaxial layer 2, and the doping type of the substrate 1 and the epitaxial layer 2 is N-type (see Figure 1 );

[0055] Step S2: Using the hard mask dielectric layer 3 as a barrier layer, a photolithography and etching process is used to form a trench 4 on the semiconductor substrate (see Figure 2 );

[0056] Step S3: Remove the hard mask dielectric layer, grow the first silicon oxide 5, silicon nitride 6 and the second silicon oxide 7 (see Figure 3 );

[0057] Step S4: Using chemical mechanical polishing process, remove the second silicon oxide 7 that is higher than the upper surface of the silicon nitride 6, and retain the second silicon oxide 7 in the groove 4 (see Figure 4 );

[0058] Step S5: Using ion implantation and annealing process, a first P-type doping region 8 is formed in the epitaxial layer 2 (see Figure 5 );

[0059] Step S6: Using an etching process to remove part of the second silicon oxide 7 in the trench 4 (see Figure 6 );

[0060] Step S7: Using ion implantation process, a second P-type doping region 9 is formed on the upper surface and side surface of the first P-type doping region 8 (see Figure 7 );

[0061] Step S8: Using an etching process, remove part of the second silicon oxide 7 in the trench 4 again; (See Figure 8 )

[0062] Step S9: Using ion implantation process, an N-type doped region 10 is formed in the epitaxial layer 2 on the sidewall of the trench 4 (see Figure 9 );

[0063] Step S10: Using an etching process, remove all the second silicon oxide 7, silicon nitride 6 and first silicon oxide 5 in sequence (see Figure 10 );

[0064] Step S11: Using thermal oxidation process, grow the third silicon oxide 11, i.e. gate oxide layer (see Figure 11 );

[0065] Step S12: depositing polysilicon 12, and removing the polysilicon 12 above the upper surface of the third silicon oxide 11, leaving the polysilicon 12 in the trench 4 (see Figure 12 );

[0066] The source region 13 is formed by photolithography, ion implantation and annealing, and then the contact hole 14 is made (see Figure 13 ).

[0067] At this point, the main structure of the MOSFET chip has been formed, wherein the first P-type doped region 8 is the body region of the MOSFET, the polysilicon 12 is the polysilicon gate of the MOSFET, the substrate 1 and the epitaxial 2 are the drain of the MOSFET, and other main structures such as the source region and the gate oxide layer have been described above.

[0068] The subsequent process steps are conventional process steps and will not be described in detail.

[0069] It can be understood that in this embodiment, the depth of the groove 4 is 0.8 to 1.6 microns, and the width is 0.1 to 0.4 microns (a MOSFET chip is composed of several cells, and the schematic diagram only shows one cell).

[0070] It can be understood that in this embodiment, the thickness of the first silicon oxide 5 is 200 to 500 angstroms, and the process method for growing the first silicon oxide 5 is preferably a thermal oxidation process; the thickness of the silicon nitride 6 is 200 to 600 angstroms, and the process method for growing the silicon nitride 6 is chemical vapor deposition; the thickness of the second silicon oxide 7 is 2000 to 8000 angstroms, and the process method for growing the second silicon oxide 7 is chemical vapor deposition, preferably high-density plasma chemical vapor deposition (HDP). The advantage of the HDP process is that it has better filling properties and can better fill the corners of the groove without easily generating voids.

[0071] The first silicon oxide 5 and the silicon nitride 6 are relatively thin, and both uniformly cover the bottom and sidewalls of the trench 4 and the area outside the trench 4. The second silicon oxide 7 is relatively thick, and fills the trench 4 completely.

[0072] It can be understood that in this embodiment, after the process of growing the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7, high-temperature annealing is performed to make the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7 denser, and the temperature of the high-temperature annealing is 900 to 1150 degrees Celsius (after the high-temperature annealing, the second silicon oxide 7 becomes denser, and its corrosion rate is lower in the subsequent etching process, so that the corrosion can be quantified more accurately, thereby accurately defining its corrosion depth, see below for details).

[0073] It can be understood that in this embodiment, the ion implantation and annealing process is used to form the first P-type doping region 8 in the epitaxial layer 2. The dopant of the ion implantation is boron, and the implantation dose is 0.6E13 to 3E13 per cm. 2 The first P-type doping region 8 is distributed in the entire area from the upper surface of the epitaxial layer 2 to a depth of D1, and the depth (D1) of the first P-type doping region 8 is 0.5 to 1.1 microns.

[0074] It can be understood that in this embodiment, the etching process is used to remove part of the second silicon oxide 7 in the groove 4. The etching process is quantitative etching, and the second silicon oxide 7 from the upper surface of the epitaxial layer 2 to the area with a depth of D2 is completely etched away, and D2 is 300 to 800 angstroms smaller than D1.

[0075] It can be understood that in this embodiment, the ion implantation process is used to form the second P-type doping region 9 on the upper surface and side surface of the first P-type doping region 8. The dopant of the ion implantation is boron, and the implantation dose (E1) is 1E13 to 2E14 per cm 2 Because ion implantation has no regional selectivity, all areas will be implanted. In the upper surface layer of the first P-type doping region 8, boron ions are implanted from top to bottom. In the side surface layer of the first P-type doping region 8, boron ions penetrate the first silicon oxide 5 and silicon nitride 6 on the side wall of the trench and are implanted from the side. In the trench 4, from the depth position D2 to the bottom area of ​​the trench, boron ions will not be implanted on the side wall of the trench due to the blocking effect of the second silicon oxide 7.

[0076] It can be understood that in this embodiment, the etching process is used to remove part of the second silicon oxide 7 in the groove 4 again. The etching process is quantitative etching, and the longitudinal thickness (D3) of the second silicon oxide 7 at the bottom of the groove 4 is retained to be 0.2 to 0.5 microns.

[0077] It can be understood that in this embodiment, the ion implantation process is used to form an N-type doped region 10 in the epitaxial layer 2 on the side wall of the trench 4. The dopant of the ion implantation is phosphorus, and the implantation dose is E2, which is equal to E1. Because ion implantation has no regional selectivity, all regions will be implanted. After this step of implantation, the second P-type doped region 9 is electrically neutralized and converted into a doped region with the same resistivity as the first P-type doped region 8. Figure 9 The first P-type doped region 8 is directly shown in the figure; below the first P-type doped region 8, phosphorus ions penetrate the first silicon oxide 5 and silicon nitride 6 on the side wall of the trench and are injected from the side to form an N-type doped region 10 in the epitaxial layer 2; at the bottom of the trench 4, due to the blocking effect of the second silicon oxide 7, phosphorus ions will not be injected into this area.

[0078] It can be understood that in this embodiment, the depth of the source region 13 is 0.1-0.3 microns; the depth of the first P-type doping region 8 minus the depth of the source region 13 is the channel length of the MOSFET chip.

[0079] Another embodiment of the present invention provides a semiconductor chip, which is manufactured according to the above-mentioned method for manufacturing a semiconductor chip.

[0080] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0081] 1. The trench-type N-channel MOSFET chip formed by the present invention has an N-type doped region formed along the trench sidewall in the epitaxial layer below the body region. Those skilled in the art should know that Figure 14 As shown (the arrow indicates the direction of current), when the trench MOSFET chip is turned on, the carriers move along the channel of the trench sidewall in the body region. Below the body region, most of the carriers flow along the trench sidewall and then diverge at the bottom of the trench to flow across the entire epitaxial layer cross section. Therefore, an N-type doped region is made along the trench sidewall in the epitaxial layer below the body region, which can reduce the resistance of the carriers flowing through this region, thereby reducing the on-resistance of the MOSFET chip.

[0082] 2. The N-type doped region produced by the present invention is distributed below the MOSFET body region, but there is no N-type doped region distributed in the bottom area of ​​the trench. Those skilled in the art should know that the electric field at the bottom of the trench is usually the strongest, and it is the critical electric field generation point that causes the source and drain breakdown of the MOSFET. The N-type doped region produced by the present invention avoids the bottom area of ​​the trench, so the breakdown voltage of the MOSFET will not be affected (that is, it will not become smaller). It can be seen that the present invention reduces the on-resistance of the MOSFET without reducing the breakdown low voltage, that is, achieves a lower on-resistance per unit area (Rsp), and can obtain a lower on-resistance under the same chip area, thereby improving the performance of the MOSFET.

[0083] 3. The present invention prepares a body region (a first P-type doped region) before etching the oxide layer (the second silicon oxide) in the trench, then quantitatively etches the oxide layer (the second silicon oxide) in the trench twice, and designs an ion implantation process accordingly, ultimately forming an N-type doped region along the trench sidewall in the epitaxial layer below the body region, while at the same time preventing the trench sidewall in the area where the body region is located from being doped to form an N-type doped region (otherwise the threshold voltage of the MOSFET chip will become smaller or even unable to be turned off), and also preventing the trench bottom from being doped to form an N-type doped region (otherwise the breakdown voltage of the MOSFET chip will become smaller), in terms of process. A more ideal doping area distribution is achieved by a very simple and ingenious process method; on the other hand, before quantitatively etching the oxide layer (second silicon oxide) in the groove, a chemical mechanical polishing process is used to remove the second silicon oxide that is higher than the upper surface of the silicon nitride. This method can ensure that the initial position of the second silicon oxide is fixed before the quantitative etching of the second silicon oxide, thereby accurately ensuring the depth of the two quantitative etchings; the high-temperature annealing after the process of growing the first silicon oxide, silicon nitride and second silicon oxide mentioned above is also to reduce the etching rate of the second silicon oxide, so that more accurate quantitative etching can be achieved at the operational level.

[0084] 4. Compared with the traditional process method for manufacturing MOSFET chips, the present invention does not add a photolithography layer and still maintains an advantage in process cost.

[0085] It can be seen that the present invention is not a simple process combination, but adopts a series of ingenious process designs. Without increasing the process costs such as lithography, it achieves a more ideal doping area distribution in the key areas inside the MOSFET chip. The resulting MOSFET chip exceeds the performance of conventional process methods.

[0086] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor chip, characterized in that: The steps include: Growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped substrate and a lightly doped epitaxial layer, wherein the substrate and the epitaxial layer are doped in an N-type manner; Using the hard mask dielectric layer as a barrier layer, photolithography and etching processes are used to form trenches on the semiconductor substrate; removing the hard mask dielectric layer, and growing a first silicon oxide, a silicon nitride, and a second silicon oxide; Using a chemical mechanical polishing process to remove the second silicon oxide protruding from the upper surface of the silicon nitride, and retaining the second silicon oxide in the groove; forming a first P-type doped region in the epitaxial layer by using ion implantation and annealing processes; Using an etching process to remove a portion of the second silicon oxide in the trench; Using an ion implantation process, a second P-type doping region is formed on the upper surface layer and the side surface layer of the first P-type doping region; Using an etching process to remove part of the second silicon oxide in the trench again; Using an ion implantation process, an N-type doped region is formed in the epitaxial layer on the sidewall of the trench; Using an etching process to sequentially remove all of the second silicon oxide, silicon nitride, and first silicon oxide; A thermal oxidation process is used to grow a third silicon oxide layer, namely a gate oxide layer; Depositing polysilicon, and removing the polysilicon above the upper surface of the third silicon oxide, leaving the polysilicon in the trench; Photolithography, ion implantation and annealing processes are used to form the source region, and then the contact holes are made.

2. The method for manufacturing a semiconductor chip according to claim 1, wherein: The first P-type doped region is the body region of the MOSFET, the polysilicon is the polysilicon gate of the MOSFET, the substrate and the epitaxial are the drain of the MOSFET, and the depth of the trench is 0.8 to 1.6 microns and the width is 0.1 to 0.4 microns.

3. The method for manufacturing a semiconductor chip according to claim 1, wherein: The thickness of the first silicon oxide is 200 to 500 angstroms, and the process method for growing the first silicon oxide is a thermal oxidation process; the thickness of the silicon nitride is 200 to 600 angstroms, and the process method for growing the silicon nitride is chemical vapor deposition; the thickness of the second silicon oxide is 2000 to 8000 angstroms, and the process method for growing the second silicon oxide is plasma chemical vapor deposition (HDP), and the second silicon oxide fills the groove.

4. The method for manufacturing a semiconductor chip according to claim 3, wherein: After the process of growing the first silicon oxide, silicon nitride and the second silicon oxide, high temperature annealing is performed at a temperature of 900 to 1150 degrees Celsius.

5. The method for manufacturing a semiconductor chip according to claim 1, wherein: Ion implantation and annealing are used to form a first P-type doped region in the epitaxial layer. The dopant of the ion implantation is boron, and the implantation dose is 0.6E13 to 3E13 per cm 2 The first P-type doping is distributed in the entire region from the upper surface of the epitaxial layer to a depth of D1, and the depth D1 of the first P-type doping region is 0.5 to 1.1 microns.

6. The method for manufacturing a semiconductor chip according to claim 5, wherein: An etching process is used to remove part of the second silicon oxide in the trench. The etching process is quantitative etching, and the second silicon oxide in the area from the upper surface of the epitaxial layer to a depth D2 is completely etched away. The depth D2 is 300 to 800 angstroms smaller than the depth D1.

7. The method for manufacturing a semiconductor chip according to claim 1, wherein: The second P-type doping region is formed on the upper surface and side surface of the first P-type doping region by ion implantation process, wherein the dopant of the ion implantation is boron and the implantation dose (E1) is 1E13-2E14 per cm 2 .

8. The method for manufacturing a semiconductor chip according to claim 7, wherein: The etching process is used to remove part of the second silicon oxide in the groove again. The etching process is quantitative etching, and the second silicon oxide with a longitudinal thickness (D3) of 0.2 to 0.5 microns is retained at the bottom of the groove.

9. The method for manufacturing a semiconductor chip according to claim 7, wherein: An ion implantation process is used to form an N-type doped region in the epitaxial layer of the trench sidewall. The ion implanted dopant is phosphorus, the implantation dose is E2, E2 is equal to E1, the depth of the source region is 0.1 to 0.3 microns, and the depth of the first P-type doped region minus the depth of the source region is the channel length of the MOSFET chip.

10. A semiconductor chip, characterized in that: The semiconductor chip is manufactured according to the method for manufacturing a semiconductor chip according to claim 1.

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