Semiconductor device, method of manufacturing the same, and lead frame

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and a lead frame used for constructing the semiconductor device. The semiconductor device comprises a plurality of chips, a plurality of chip seats for bearing the chips, a plurality of first pins extending to the edge of the semiconductor device, and at least one second pin separated from the edge of the semiconductor device and arranged independently, wherein the second pin is surrounded by the plurality of chip seats, and at least two chips can be electrically connected to the same second pin.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to a semiconductor device and a method for manufacturing the same, as well as a lead frame for constructing the semiconductor device. Background Technology

[0002] Packaged products are typically obtained by mounting the chip onto a lead frame, connecting the chip and the lead frame with conductive wire bonding, and finally encapsulating them with packaging materials.

[0003] Figure 1 The diagram shows a conventional DFN / QFN package structure with multiple chips.

[0004] like Figure 1 As shown, in this conventional DFN / QFN package structure 100 with multiple chips, the multiple chips 2 need to be electrically connected to the same output pin 3. Therefore, in Figure 1 In the package structure 100 shown, the output pin 3 must have an elongated connection portion 31 due to the structural design. This elongated connection portion 31 affects the signal quality of the package structure 100, mitigating the problems of poor signal connectivity and degraded electrical performance in conventional DFN / QFN package structures 100 with multiple chips. Furthermore, in Figure 1 The packaging structure 100 shown also has the problem of redundant signal channels, which results in low internal space utilization, insufficient placement space for chip 2, and increased product size, thus increasing the risk of scrap and hindering product miniaturization.

[0005] Therefore, it is necessary to provide a new structure for semiconductor devices to overcome the above-mentioned defects. Summary of the Invention

[0006] The purpose of this application is to provide a lead frame and a semiconductor device constructed using the lead frame. By setting a specially designed second pin, the additional signal connection part inside the semiconductor device is reduced, the electrical connection quality of the semiconductor device is improved, and the waste of packaging space and pin arrangement of the semiconductor device is also reduced.

[0007] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising a plurality of chips; the semiconductor device further comprising: a plurality of chip bases for supporting the chips; a plurality of first pins extending at one end to the edge of the semiconductor device; and at least one second pin separated from and independently disposed from the edge of the semiconductor device, wherein the second pin is surrounded by a plurality of chip bases, and at least two chips are electrically connected to the same second pin.

[0008] In other words, the semiconductor device provided in this application includes a plurality of first pins and at least one second pin, wherein two of the chips are electrically connected to the same second pin, and unlike the first pins that extend toward the edge of the semiconductor device, the second pin does not extend toward the edge of the semiconductor device, but is completely separated from the edge of the semiconductor device.

[0009] In some embodiments, the chip base corresponding to the chip electrically connected to the same second pin is disposed around the second pin.

[0010] In some embodiments, the plurality of first pins are arranged along the edge of the semiconductor device.

[0011] In some embodiments, the chip base corresponding to the chip electrically connected to the same second pin is disposed at a corner of the semiconductor device.

[0012] In some embodiments, the semiconductor device further includes leads through which the plurality of chips are electrically connected to the plurality of first pins and second pins.

[0013] In some embodiments, the semiconductor device further includes a molding compound that encapsulates the plurality of chips, the plurality of chip substrates, the plurality of first pins, the second pins, and the leads to form the semiconductor device.

[0014] In some embodiments, at least a portion of the surfaces of the plurality of first pins and the second pins are exposed on a surface of the semiconductor device.

[0015] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising:

[0016] A lead frame, a carrier film, at least one metal component, and a plurality of chips are provided, wherein the lead frame defines a plurality of chip bases and a plurality of first pins;

[0017] The lead frame and the at least one metal component are respectively disposed on the carrier film;

[0018] The plurality of chips are disposed on the lead frame;

[0019] Multiple leads are formed to electrically connect the plurality of chips to the metal component and the plurality of first pins; and,

[0020] A molding compound is formed to encapsulate the plurality of chips, the plurality of chip substrates, the at least one metal component, the plurality of first pins, and the plurality of leads; and,

[0021] Furthermore, the carrier film is removed so that at least a portion of the surface of the at least one metal element and the plurality of first pins is exposed to a surface of the semiconductor device.

[0022] Those skilled in the art will understand that, in the above manufacturing method, the metal component constitutes the second pin within the final constructed semiconductor device.

[0023] In some embodiments, after the step of removing the carrier film, the manufacturing method further includes a dicing step to form a single semiconductor device.

[0024] In some embodiments, in the step of disposing the lead frame and the at least one metal member on the carrier film, the lead frame and the at least one metal member are fixed to the carrier film by an adhesive layer, and the adhesive layer has adhesiveness under heating conditions and the adhesiveness gradually decreases under cooling conditions.

[0025] Those skilled in the art will understand that the adhesive layer can be made of conventional adhesive materials used in semiconductor devices and has the property of being adhesive under heating conditions and having gradually decreasing adhesiveness under cooling conditions. The adhesive material, for example, but not limited to, acrylic adhesives, silicone adhesives, or hot melt adhesives, can achieve adhesiveness during the heating process for temporary fixation, while exhibiting low adhesiveness at room temperature for easy peeling and no residue.

[0026] According to another aspect of this application, a lead frame is also provided for constructing a semiconductor device comprising a plurality of chips; the lead frame has at least one frame unit defined by a closed package line, the frame unit comprising: a plurality of chip bases for carrying chips; a plurality of first pins extending one end to the package line; and at least one second pin separated from and independently disposed from the package line, wherein the second pin is surrounded by a plurality of chip bases, and at least two chips are electrically connected to the same second pin.

[0027] In some embodiments, the plurality of first pins are interconnected with the plurality of chip bases via an outer frame, and the second pin is independent of the outer frame.

[0028] In some embodiments, the chip base corresponding to the chip electrically connected to the same second pin is disposed around the second pin.

[0029] In some embodiments, the plurality of first pins are arranged along the package line.

[0030] In some embodiments, the chip base corresponding to the chip electrically connected to the same first pin is disposed at the corner of the frame unit.

[0031] In this application, the internal layout structure of packaged products with complex and dense designs and a large number of chips, such as DFN or QFN products containing multiple chips, is adjusted, and a special design is made for the structure and position of the second pin shared by multiple chips.

[0032] Therefore, in this application, the arrangement of the second pin is used to achieve a reasonable arrangement of the internal space of the semiconductor device. Without affecting all signal functions of the semiconductor device, the utilization rate of the internal space of the semiconductor device is improved and the arrangement of external pins is reduced, thereby reducing the structural complexity of the lead frame used to build the semiconductor device, and further reducing manufacturing costs and manufacturing difficulty.

[0033] Furthermore, the semiconductor device described in this application can achieve centralized placement of leads within the semiconductor device while ensuring that all signal functions are not affected, thereby reducing additional signal connection parts within the semiconductor device and improving electrical connection quality. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a conventional semiconductor device in this field;

[0035] Figure 2 This is a perspective view of a semiconductor device according to an embodiment of this application;

[0036] Figure 3A It is integrated into Figure 2 A top view of the semiconductor device shown, including the chip, chip base, first pin, second pin, and leads.

[0037] Figure 3B and Figure 3C yes Figure 3A Cross-sectional view at point B-B';

[0038] Figure 4A and Figure 4B This is a schematic diagram of the structure of the semiconductor device according to other embodiments of this application;

[0039] Figure 5 This is a schematic diagram of the lead frame according to an embodiment of this application;

[0040] Figure 6 This is a flowchart of a method for constructing a semiconductor device according to an embodiment of this application;

[0041] Figures 7A to 7G Is with Figure 6 The corresponding structural diagram. Detailed Implementation

[0042] The technology of this application will now be described in detail with reference to specific embodiments. It should be understood that the following specific embodiments are only used to help those skilled in the art understand this application, and are not intended to limit this application.

[0043] In this embodiment, a semiconductor device 1 is provided. Figure 2 This is a perspective view of the semiconductor device 1; Figure 3A This is a top view of the chip 20, chip base 110, first pin 121, second pin 122 and lead L integrated into the semiconductor device 1; Figure 3B yes Figure 3A Cross-sectional view at point 3B-3B'.

[0044] like Figure 2 and Figure 3A As shown, the semiconductor device 1 described in this application includes: a plurality of chips 20, a plurality of chip bases 110, a plurality of first pins 121, at least one second pin 122, a plurality of leads L, and a molding compound 30. Figure 2 and Figure 3B As shown, the molding compound 30 encapsulates the plurality of chips 20, the plurality of chip substrates 110, the plurality of first pins 121, second pins 122, and the leads L to form the semiconductor device 1, and at least a portion of the surfaces of the plurality of first pins 121 and second pins 122 are exposed to the surface S of the semiconductor device 1. Each first pin 121 and second pin 122 has a conventional stepped molding structure formed at the edge, for example, Figure 3B The stepped molding structure 1211 formed on the edge of the first pin 121 and the stepped molding structure 1221 formed on the edge of the second pin 122 are shown. Figure 3C This shows another form of the stepped mold-locking structure formed on the edges of the first pin 121 and the second pin 122.

[0045] like Figure 2 and Figure 3A As shown, the semiconductor device 1 typically has six outer surfaces. In this application, each outer surface is defined as an edge E of the semiconductor device 1.

[0046] like Figure 3A As shown, in the semiconductor device 1 described in this application, each chip 20 is disposed on a chip base 110, each chip 20 is electrically connected to a first pin 121 and a second pin 122 respectively via a lead L, and at least two chips 20 are electrically connected to the same second pin 122 via a lead L respectively.

[0047] like Figure 2 and Figure 3A As shown, the semiconductor device 1 described in this application includes: a plurality of first pins 121 and at least one second pin 122; wherein one end of each first pin 121 extends to the edge E of the semiconductor device 1, the second pin 122 is separated from and independently disposed from the edge E of the semiconductor device 1, and the second pin 122 is surrounded by a plurality of chip bases 110. That is, in the semiconductor device 1 described in this application, one end of each first pin 121 extends to the edge E of the semiconductor device 1, while the second pin 122 does not extend to the edge E of the semiconductor device 1. Preferably, as Figure 3A As shown, the chip base 110 corresponding to the chip 20 electrically connected to the same second pin 122 is disposed around the second pin 122. Particularly preferably, as... Figure 3A As shown, the plurality of first pins 121 are arranged along the edge E of the semiconductor device 1, and the chip base 110 corresponding to the chip 20 electrically connected to the same second pin 122 is disposed at the corner of the semiconductor device 1.

[0048] Specifically, in this embodiment, such as Figure 3A As shown, the semiconductor device 1 includes four chips 20, four first pins 121, and one second pin 122. Each chip 20 is disposed on a chip base 110. One end of each first pin 121 extends to the edge E of the semiconductor device 1 and is arranged along the edge E of the semiconductor device 1. The second pin 122 is separated from the edge E of the semiconductor device 1 and is disposed independently. Furthermore, the second pin 122 is surrounded by the four chip bases 110 so that the four chips 20 can be electrically connected to the second pin 122 via a lead L.

[0049] Those skilled in the art will understand that, in other embodiments, the semiconductor device 1 described in this application may include any number of multiple chips 20, and any number of these chips 20 may be electrically connected to the same second pin 122. Furthermore, in other embodiments, the semiconductor device 1 described in this application may include any number of multiple first pins 121 and at least one second pin 122.

[0050] For example, such as Figure 4A As shown, the semiconductor device 1 includes four chips 20, three of which are connected to the same second pin 122 via a lead L. Figure 4AIn the structure of the semiconductor device 1 shown, chip bases 110 corresponding to the three chips 20 electrically connected to the same second pin 122 are disposed around the second pin 122.

[0051] For example, such as Figure 4B As shown, the semiconductor device 1 includes four chips 20, wherein two chips 20 are respectively connected to the same second pin 122 via a lead, and the other two chips 20 are respectively connected to another second pin 122 via a lead L. Figure 4B In the structure of the semiconductor device 1 shown, the chip bases 110 corresponding to the two chips 20 electrically connected to the same second pin 122 are respectively disposed around the corresponding second pin 122.

[0052] Therefore, in this application, by setting the second pin 122, a reasonable arrangement of the internal space of the semiconductor device 1 is achieved, which improves the utilization rate of the internal space of the semiconductor device 1 and reduces the arrangement of external pins without affecting all signal functions of the semiconductor device 1.

[0053] This application also provides a lead frame 10, which, after cutting, can obtain the following... Figure 3A The chip base 110 and the first pin 121 are shown, and the second pin 122 is formed after the metal parts are attached.

[0054] Specifically, the lead frame 10 has at least one frame unit defined by a closed encapsulation line W, such as... Figure 5 As shown, for example, the lead frame 10 has two frame units. Figure 5 As shown, each of the frame units includes a plurality of chip bases 110 and first pins 121. One end of each first pin 121 extends to the package line W and is arranged along the package line W. The plurality of first pins 121 and the plurality of chip bases 110 are interconnected by an outer frame 11. Figure 5 As shown, the lead frame 10 further includes at least one second pin 122, which is separated from and independently disposed from the package line W. The second pin 122 is independent of the outer frame 11, and the second pin 122 is surrounded by a plurality of chip bases 110.

[0055] In this application, the chip base 110 in the lead frame 10 is used to carry external chips. The chip base 110 corresponding to the chip electrically connected to the same second pin 122 is disposed around the second pin 122, and the chip base 110 corresponding to the chip electrically connected to the same first pin 121 is disposed at the corner of the frame unit.

[0056] The following combinationFigure 6 and Figures 7A to 7G The present application describes in detail the manufacturing method of the semiconductor device 1, wherein, in Figures 7A to 7G In this example, we take a single lead frame.

[0057] like Figure 6 and Figure 7A As shown, the method for manufacturing the semiconductor device described in this application first includes step S1: providing a lead frame 10, a carrier film P, at least one metal element M, and a plurality of chips 20. The lead frame 10 has the above-described... Figure 5 The diagram shows a plurality of chip bases 110 and a plurality of first pins 121.

[0058] like Figure 6 and Figure 7B As shown, the method for manufacturing the semiconductor device according to this application includes step S21: disposing the lead frame 10 on the carrier film P. The lead frame 10 is fixed to the carrier film P with an adhesive layer, wherein the adhesive layer is adhesive under heating conditions and its adhesiveness gradually decreases under cooling conditions. The adhesive layer can be made of conventional adhesive materials used in semiconductor devices in the art, and has the characteristic of being adhesive under heating conditions and having adhesiveness that gradually decreases under cooling conditions. The adhesive material is, for example, but not limited to, acrylic adhesives, silicone adhesives, or hot melt adhesives. A specific embodiment of the carrier film P and the adhesive layer can be a commercially available QFN encapsulation tape (or QFN encapsulation support film, QFN tape, QFN carrier tape, etc.) in the art. The QFN encapsulation tape has a polyimide base layer and an adhesive material layer disposed on one surface of the polyimide base layer. It can achieve adhesion during the heating process to achieve temporary fixation, while having low adhesion at room temperature to achieve easy peeling and no residue.

[0059] like Figure 6 and Figure 7C As shown, the manufacturing method of the semiconductor device described in this application includes step S22: disposing the metal part M on the carrier film P. Similar to step S21, an adhesive layer is used to fix the metal part M to the carrier film P, and the adhesive layer has adhesiveness under heating conditions and its adhesiveness gradually decreases under cooling conditions. The metal part M thus constitutes... Figure 3A The second pin 122 in the semiconductor device 1 described in this application is shown.

[0060] like Figure 6 and Figure 7DAs shown, the method for manufacturing the semiconductor device described in this application includes step S3: placing the chip 20 on the lead frame 10, particularly on the chip substrate 110 of the lead frame 10. In this step, the chip 20 is attached to the lead frame 10 using conventional processes.

[0061] like Figure 6 and Figure 7E As shown, the method for manufacturing the semiconductor device described in this application includes step S4: forming a plurality of leads L to electrically connect each chip 20 to the metal part M and a plurality of first pins 121 of the lead frame 10. In this step, the leads L are formed using conventional processes.

[0062] like Figure 6 and Figure 7F As shown, the method for manufacturing the semiconductor device described in this application includes step S5: forming a molding compound 30 to encapsulate the plurality of chips 20, the plurality of chip bases 110, the metal part M, the plurality of first pins 121, and the plurality of leads L.

[0063] like Figure 6 and Figure 7G As shown, the manufacturing method of the semiconductor device described in this application includes step S6: removing the carrier film P and cutting it to form the semiconductor device 1. Since the molding compound 30 is formed on the carrier film P in step S5, after removing the carrier film P in this step, as... Figure 3B As shown, at least a portion of the surfaces of the first pin 121 and the second pin 122, which are made of the metal, of the semiconductor device 1 are exposed on the surface S of the semiconductor device 1.

[0064] This application has been described with reference to the above-described embodiments; however, these embodiments are merely examples for implementing this application. It must be noted that the disclosed embodiments do not limit the scope of this application. Conversely, modifications and equivalent provisions contained within the spirit and scope of the claims are included within the scope of this application.

Claims

1. A semiconductor device comprising a plurality of chips, characterized in that, The semiconductor device further includes: A plurality of chip bases for supporting the chips; A plurality of first pins, one end of which extends to the edge of the semiconductor device; and, At least one second pin is separated from and independently disposed from the edge of the semiconductor device, the second pin being made of a metal component, wherein the second pin is surrounded by a plurality of chip bases, and at least two chips are electrically connected to the same second pin; The chip base corresponding to the chip electrically connected to the same second pin is disposed around the second pin; The chip base corresponding to the chip electrically connected to the same second pin is disposed at the corner of the semiconductor device.

2. The semiconductor device as claimed in claim 1, characterized in that, A plurality of the first pins are arranged along the edge of the semiconductor device.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes leads, through which the plurality of chips are electrically connected to a plurality of the first pins and the second pins.

4. The semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes a molding compound that encapsulates the plurality of chips, the plurality of chip bases, the plurality of first pins, the second pins, and the leads to form the semiconductor device.

5. The semiconductor device as claimed in claim 4, characterized in that, At least a portion of the surfaces of the plurality of first pins and the second pins are exposed on a surface of the semiconductor device.

6. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A lead frame, a carrier film, at least one metal component, and a plurality of chips are provided, wherein the lead frame defines a plurality of chip bases and a plurality of first pins; The lead frame and the at least one metal component are respectively disposed on the carrier film; The plurality of chips are disposed on the lead frame; Multiple leads are formed to electrically connect the plurality of chips to the metal component and the plurality of first pins; and, A molding compound is formed to encapsulate the plurality of chips, the plurality of chip substrates, the at least one metal component, the plurality of first pins, and the plurality of leads; and, Furthermore, the carrier film is removed so that at least a portion of the surface of the at least one metal member and the plurality of first pins is exposed to a surface of the semiconductor device; The at least one metal component constitutes a second pin, and the chip base corresponding to the chip electrically connected to the same second pin is disposed around the second pin; the chip base corresponding to the chip electrically connected to the same second pin is disposed at the corner of the semiconductor device.

7. The manufacturing method as described in claim 6, characterized in that, After the step of removing the carrier film, the manufacturing method further includes a dicing step to form a single semiconductor device.

8. The manufacturing method as described in claim 6, characterized in that, In the step of disposing the lead frame and the at least one metal member on the carrier film, an adhesive layer is used to fix the lead frame and the at least one metal member to the carrier film, and the adhesive layer has adhesiveness under heating conditions and the adhesiveness gradually decreases under cooling conditions.

9. A lead frame for constructing a semiconductor device comprising a plurality of chips, characterized in that, The lead frame has at least one frame unit defined by a closed encapsulation line, the frame unit comprising: Multiple chip bases are used to hold the chips; A plurality of first pins, one end of which extends to the package line; and, At least one second pin is separated from and independently disposed from the package line, wherein the second pin is surrounded by a plurality of chip bases, and at least two chips are electrically connected to the same second pin; the second pin is made of metal, and the chip base corresponding to the chip electrically connected to the same second pin is disposed around the second pin; the chip base corresponding to the chip electrically connected to the same second pin is disposed at the corner of the frame unit.

10. The lead frame as described in claim 9, characterized in that, A plurality of the first pins are interconnected with the plurality of chip bases via an outer frame, and the second pins are independent of the outer frame.

11. The lead frame as described in claim 9, characterized in that, A plurality of the first pins are arranged along the package line.

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