Electrostatic protection circuit

Abstract

An embodiment of the present application provides an electrostatic protection circuit. The chip includes a first pad and a second pad. The electrostatic protection circuit includes: a trigger unit connected between the first pad and the second pad, having a first trigger terminal and a second trigger terminal, and configured to generate a first trigger signal when there is an electrostatic pulse on the first pad; a first discharge transistor, whose control terminal is connected to the first trigger terminal of the trigger unit, whose first terminal is connected to the first pad, whose second terminal is connected to the second pad, and whose substrate terminal is connected to the second trigger terminal of the trigger unit, and is configured to discharge electrostatic charges to the second pad under the trigger of the first trigger signal. In the present application, the substrate terminal of the first discharge transistor is connected to the second trigger terminal, which accelerates the conduction of the parasitic transistor in the first discharge transistor, improves the discharge ability, and the substrate terminal voltage is less than the voltage of the first pad, reducing the risk of latch-up effect.

Description

Technical Field

[0001] This application relates to, but is not limited to, an electrostatic protection circuit. Background Art

[0002] Electrostatic charges are everywhere. Without an electrostatic protection circuit, a chip will soon be damaged by electrostatic charges introduced for various reasons and will almost be fatally damaged.

[0003] Therefore, an electrostatic protection circuit is usually provided in a chip. The electrostatic protection circuit is used to timely discharge electrostatic charges to prevent the protected circuit from failing or even burning out due to the high voltage brought by the electrostatic charges. Summary of the Invention

[0004] An embodiment of this application provides an electrostatic protection circuit, aiming to provide an electrostatic protection circuit with enhanced discharge ability and reduced risk of latch-up effect.

[0005] An embodiment of this application provides an electrostatic protection circuit. The chip includes a first pad and a second pad. The electrostatic protection circuit includes:

[0006] A trigger unit, which is connected between the first pad and the second pad, and is provided with a first trigger end and a second trigger end, and is used to generate a first trigger signal when there is an electrostatic pulse on the first pad;

[0007] A first discharge transistor, whose control end is connected to the first trigger end of the trigger unit, whose first end is connected to the first pad, whose second end is connected to the second pad, and whose substrate end is connected to the second trigger end of the trigger unit, and is used to discharge electrostatic charges to the second pad under the trigger of the first trigger signal.

[0008] In one embodiment, the trigger unit includes:

[0009] A trigger capacitor, which is provided with a first end and a second end,

[0010] A first resistor, which is provided with a first end and a second end, and whose first end is connected to the second end of the trigger capacitor to form the first trigger end of the trigger unit;

[0011] A second resistor, which is provided with a first end and a second end, and whose first end is connected to the second end of the first resistor to form the second trigger end of the trigger unit.

[0012] In one embodiment, the electrostatic protection circuit further includes:

[0013] The trigger unit is further used to generate a second trigger signal when there is an electrostatic pulse on the first pad;

[0014] A second discharge transistor, whose control terminal is connected to the second trigger terminal, whose first terminal is connected to the first pad, whose second terminal is connected to the second pad, and whose substrate terminal is connected to the second trigger terminal of the trigger unit, is configured to discharge electrostatic charges to the second pad under the trigger of a second trigger signal.

[0015] In one embodiment, the distance between the projection of the first discharge transistor on the substrate and the projection of the first pad on the substrate is greater than the distance between the projection of the second discharge transistor on the substrate and the projection of the first pad on the substrate.

[0016] In one embodiment, the first discharge transistor includes a first multi-finger structure, and the second discharge transistor includes a second multi-finger structure, wherein the first multi-finger structure and the second multi-finger structure are arranged adjacent to each other.

[0017] In one embodiment, the central axis of the projection of the first multi-finger structure on the substrate coincides with the central axis of the first projection of the first pad on the substrate;

[0018] The central axis of the projection of the second multi-finger structure on the substrate does not coincide with the central axis of the first projection.

[0019] In one embodiment, the first end of the trigger capacitor is connected to the first pad, and the second end of the second resistor is connected to the second pad.

[0020] In one embodiment, the first discharge transistor is an N-type transistor.

[0021] In one embodiment, when the first discharge transistor is turned on, the parasitic NPN-type transistor in the first discharge transistor is also turned on.

[0022] In one embodiment, the first discharge transistor and the second discharge transistor are N-type transistors.

[0023] In one embodiment, the charging rate of the control terminal of the first discharge transistor is greater than the charging rate of the control terminal of the second discharge transistor, and when the first discharge transistor and the second discharge transistor are turned on, the parasitic NPN-type transistors in the first discharge transistor and the second discharge transistor are also turned on.

[0024] In one embodiment, the first end of the trigger capacitor is connected to the second pad, and the second end of the second resistor is connected to the first pad.

[0025] In one embodiment, the first discharge transistor and the second discharge transistor are P-type transistors.

[0026] In one embodiment, the discharging rate of the control terminal of the first discharge transistor is greater than the discharging rate of the control terminal of the second discharge transistor, and when the first discharge transistor and the second discharge transistor are turned on, the parasitic PNP-type transistors in the first discharge transistor and the second discharge transistor are also turned on.

[0027] In one embodiment, the resistance value of the second resistor is greater than that of the first resistor.

[0028] An embodiment of the present application provides an electrostatic protection circuit, including a first discharge transistor and a trigger unit. The trigger unit is provided with two trigger terminals. The first trigger terminal is connected to the control terminal of the first discharge transistor, and the second trigger terminal is connected to the substrate terminal of the first discharge transistor. When an electrostatic pulse arrives on the first pad, the first discharge transistor is turned on under the control of the first trigger signal output by the first trigger terminal, discharging the electrostatic charge to the second pad. The voltage of the second trigger terminal will also be raised, causing the parasitic transistor at the substrate terminal of the first discharge transistor to be turned on, enhancing the discharge capacity of the electrostatic protection circuit. Moreover, the voltage of the second trigger terminal is less than the voltage on the first pad, reducing the risk of latch-up effect in the electrostatic protection circuit and making it more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0030] Figure 1 It is a specific circuit diagram of the electrostatic protection circuit provided by an embodiment of the present application;

[0031] Figure 2 is Figure 1 a projection diagram of the electrostatic protection circuit provided by the illustrated embodiment on the substrate;

[0032] Figure 3 is for Figure 1 a semiconductor structure diagram of the electrostatic protection circuit provided by the illustrated embodiment;

[0033] Figure 4 It is a specific circuit diagram of the electrostatic protection circuit provided by another embodiment of the present application;

[0034] Figure 5 It is a specific circuit diagram of the electrostatic protection circuit provided by another embodiment of the present application;

[0035] Figure 6 is Figure 5 a projection diagram of the electrostatic protection circuit provided by the illustrated embodiment on the substrate;

[0036] Figure 7 It is a specific circuit diagram of the electrostatic protection circuit provided by another embodiment of the present application;

[0037] Figure 8 is Figure 7 a projection diagram of the electrostatic protection circuit provided by the illustrated embodiment on the substrate;

[0038] Figure 9 The specific circuit diagram of the electrostatic protection circuit provided by another embodiment of the present application.

[0039] Through the above-mentioned drawings, the specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiments

[0040] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0041] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0042] Figure 1 The circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application, Figure 2 is Figure 1 the projection diagram of the electrostatic protection circuit provided by the shown embodiment on the substrate. As Figure 1 and Figure 2 shown, an embodiment of the present application provides an electrostatic protection circuit. The chip includes a first pad VDD and a second pad GND. The internal circuit provided in the chip is located between the first pad VDD and the second pad GND. The electrostatic protection circuit includes a trigger unit 101 and a discharge transistor 102.

[0043] The trigger unit 101 is provided with a trigger terminal N0. The trigger terminal N0 of the trigger unit 101 is connected to the control terminal N0 of the discharge transistor 102. The trigger unit 101 is located between the first pad VDD and the second pad GND. The discharge transistor 102 is further provided with a first end, a second end, and a substrate end. The first end of the discharge transistor 102 is connected to the first pad VDD, the second end of the discharge transistor 102 is connected to the second pad GND, and the substrate end of the discharge transistor 102 is also connected to the trigger terminal N0.

[0044] When the trigger unit 101 detects an electrostatic pulse, a trigger signal is generated. The discharge transistor 102 is turned on under the trigger of the trigger signal, and the electrostatic charge is discharged from the first pad VDD to the second pad GND.

[0045] Among them, the trigger unit 101 includes a trigger capacitor C0 and a monitoring resistor R0. The trigger capacitor C0 and the monitoring resistor R0 are provided with a first end and a second end. The first end of the trigger capacitor C0 is connected to the first pad VDD, the second end of the trigger capacitor C0 is connected to the first end of the monitoring resistor R0, and the second end of the monitoring resistor R0 is connected to the second pad GND.

[0046] In one embodiment, the discharge transistor 102 is an N-type transistor. The drain of the N-type transistor is connected to the first pad VDD, and the source of the N-type transistor is connected to the second pad GND. When an electrostatic pulse arrives, the impedance of the trigger capacitor C0 becomes smaller, the voltage of the control terminal N0 of the discharge transistor 102 rises, the discharge transistor 102 gradually turns on, and the electrostatic charge on the first pad VDD is discharged to the second pad GND through the discharge transistor 102.

[0047] Figure 3 This Figure 1 is the semiconductor structure diagram of the electrostatic protection circuit provided by the illustrated embodiment. Refer to Figure 3 , there is also a parasitic NPN transistor in the discharge transistor 102. The base b of the parasitic NPN transistor is the substrate bottom end of the discharge transistor 102, the collector c of the parasitic NPN transistor is the drain D of the discharge transistor 102, and the emitter e of the parasitic NPN transistor is the source S of the discharge transistor 102.

[0048] The substrate bottom end of the discharge transistor 102 is connected to the trigger terminal N0. When an electrostatic pulse arrives, the discharge transistor 102 is turned on, and the channel current I DS of the discharge transistor 102 will cause the drain voltage to be greater than the source voltage, that is, the collector voltage of the parasitic NPN transistor is greater than the emitter voltage of the parasitic NPN transistor. Due to the existence of the parasitic resistance Rsub in the substrate, the base voltage of the parasitic NPN transistor is also coupled to the voltage of the first pad VDD, and the parasitic NPN transistor is turned on. Usually, the discharge capacity of the parasitic NPN transistor with the same area is greater than that of the NMOS transistor. When designing the discharge transistor, the projected area of the discharge transistor can be reduced.

[0049] Figure 4 This is the circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application. As Figure 4As shown in the figure, an embodiment of the present application provides an electrostatic protection circuit chip, which includes a first pad VDD and a second pad GND. The internal circuit provided in the chip is located between the first pad VDD and the second pad GND. The electrostatic protection circuit includes a trigger unit 201 and a first discharge transistor 202.

[0050] Among them, the trigger unit 201 is provided with a first trigger terminal N1 and a second trigger terminal N2. The trigger unit 201 is connected between the first pad VDD and the second pad GND, and is used to generate a first trigger signal when there is an electrostatic pulse on the first pad VDD and output it through the first trigger terminal N1. The first discharge transistor 202 is provided with a control terminal, a first terminal, a second terminal, and a substrate terminal. The control terminal of the first discharge transistor 202 is connected to the first trigger terminal N1, the substrate terminal of the first discharge transistor 202 is connected to the second trigger terminal N2, the first terminal of the first discharge transistor 202 is connected to the first pad VDD, and the second terminal of the first discharge transistor 202 is connected to the second pad GND. The first discharge transistor 202 is used to discharge the electrostatic charge from the first pad VDD to the second pad GND under the trigger of the first trigger signal.

[0051] In one embodiment, the discharge transistor 202 is an N-type transistor. The substrate terminal of the first discharge transistor 202 is connected to the second trigger terminal N2 of the trigger unit 201. When there is electrostatic charge on the first pad VDD, the voltage of the second trigger terminal N2 of the trigger unit 201 is raised, and the base voltage of the parasitic NPN transistor is also raised. And due to the conduction of the first discharge transistor 202, the collector voltage of the parasitic NPN transistor is greater than the emitter voltage of the parasitic NPN transistor, which can accelerate the conduction of the parasitic NPN transistor and improve the electrostatic discharge ability of the electrostatic protection circuit. And since the voltage of the second trigger terminal N2 is less than the voltage on the first pad VDD when there is electrostatic charge on the first pad VDD, the risk of generating a latch-up effect can be reduced.

[0052] In one embodiment, as Figure 5 and Figure 6 shown, the trigger unit 201 includes a trigger capacitor C1, a first resistor R1, and a second resistor R2. The trigger capacitor C1, the first resistor R1, and the second resistor R2 are all provided with a first terminal and a second terminal. The first terminal of the trigger capacitor C1 is connected to the first pad VDD, the second terminal of the trigger capacitor C1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the second pad GND. The first terminal of the first resistor R1 is connected to the second terminal of the trigger capacitor C1 to form the first trigger terminal N1 of the trigger unit 201 for connecting to the control terminal of the first discharge transistor 202, and the first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1 to form the second trigger terminal N2 of the trigger unit 201 for connecting to the substrate terminal of the first discharge transistor 202.

[0053] When there is static charge on the first pad VDD, the impedance of the trigger capacitor C1 becomes smaller, the voltage at the first trigger terminal N1 of the trigger unit 201 is coupled to the voltage on the first pad VDD, the first discharge transistor 202 conducts, the voltage at the second trigger terminal N2 of the trigger unit 201 is also raised, and the base voltage of the parasitic NPN transistor is also raised. Moreover, due to the conduction of the first discharge transistor 202, the collector voltage of the parasitic NPN transistor is greater than the emitter voltage of the parasitic NPN transistor, which can accelerate the conduction of the parasitic NPN transistor and improve the static discharge ability of the electrostatic protection circuit.

[0054] As Figures 7 to 9 shown, an embodiment of the present application provides an electrostatic protection circuit. The chip includes a first pad VDD and a second pad GND. The internal circuit provided in the chip is located between the first pad VDD and the second pad GND. The electrostatic protection circuit includes a trigger unit 201, a first discharge transistor 202, and a second discharge transistor 203.

[0055] Among them, the trigger unit 201 is provided with a first trigger terminal N1 and a second trigger terminal N2. The trigger unit 201 is connected between the first pad VDD and the second pad GND, and is used to generate a first trigger signal and a second trigger signal when there is an electrostatic pulse on the first pad VDD, output the first trigger signal through the first trigger terminal N1, and output the second trigger signal through the second trigger terminal N2.

[0056] Both the first discharge transistor 202 and the second discharge transistor 203 are provided with a control terminal, a first terminal, a second terminal, and a substrate terminal. The first terminal of the first discharge transistor 202 is connected to the first pad VDD, the second terminal of the first discharge transistor 202 is connected to the second pad GND, the control terminal of the first discharge transistor 202 is connected to the first trigger terminal N1, the substrate terminal of the first discharge transistor 202 is connected to the second trigger terminal N2, and the first discharge transistor 202 is used to discharge the static charge to the second pad GND under the trigger of the first trigger signal. The first terminal of the second discharge transistor 203 is connected to the first pad VDD, the second terminal of the second discharge transistor 203 is connected to the second pad GND, both the control terminal and the substrate terminal of the second discharge transistor 203 are connected to the second trigger terminal N2, and the second discharge transistor 203 is used to discharge the static charge to the second pad GND under the trigger of the second trigger signal.

[0057] The parasitic parameters between the terminals of the first discharge transistor 202 and the first pad VDD are different from those between the terminals of the second discharge transistor 203 and the first pad VDD. When an electrostatic pulse arrives, it will cause the conduction rates of the first discharge transistor 202 and the second discharge transistor 203 to be different. The amplitudes of the first trigger signal and the second trigger signal are different, making the charging or discharging rate of the control terminal of the first discharge transistor 202 different from that of the control terminal of the second discharge transistor 203, so that the conduction rate of the first discharge transistor 202 is different from the conduction rate of the second discharge transistor 203 turned on by the second trigger signal.

[0058] If the different parasitic parameters between the terminals of the transistor and the first pad VDD result in the conduction rate of the first discharge transistor 202 being less than that of the second discharge transistor 203, then the amplitude of the first trigger signal is greater than that of the second trigger signal, so that the charging or discharging rate of the control terminal of the first discharge transistor 202 is greater than that of the control terminal of the second discharge transistor 203, thereby accelerating the conduction rate of the first discharge transistor 202, making the conduction rates of the first discharge transistor 202 and the second discharge transistor 203 close, and the electrostatic charges flowing through the first discharge transistor 202 and the second discharge transistor 203 being similar, which can avoid burning out one of the discharge transistors after most of the electrostatic charges flow through it due to the different parasitic parameters of the two discharge transistors.

[0059] Correspondingly, if the parasitic parameters make the conduction rate of the first discharge transistor 202 greater than that of the second discharge transistor 203, the amplitude of the first trigger signal can be set to be less than that of the second trigger signal, and the charging or discharging rates of the control terminals of the two transistors can be controlled by the trigger signal to balance the conduction rates of the first discharge transistor 202 and the second discharge transistor 203, and the discharge currents of the two transistors can be balanced, thereby avoiding the failure of the transistor with a fast conduction rate due to excessive electrostatic current and improving the reliability of the electrostatic protection circuit.

[0060] Figure 8Projection of the discharge transistor and the first pad VDD provided for this application on the substrate. To improve the discharge capacity of the discharge transistor, the discharge transistor generally adopts a multi-finger structure. The first discharge transistor 202 includes a first multi-finger structure, and the second discharge transistor 203 includes a second multi-finger structure, wherein the first multi-finger structure and the second multi-finger structure are arranged adjacent to each other. The second multi-finger structure centered relative to the first pad VDD is marked as the second discharge transistor MN2, and the central axis of the second multi-finger structure coincides with the central axis of the first pad VDD, so that the gate parasitic resistance and drain parasitic resistance of the second discharge transistor MN2 relative to the first pad VDD are minimized, and it conducts first when an electrostatic pulse arrives. The second multi-finger structure arranged around the first pad VDD is marked as the first discharge transistor MN1, that is, the central axis of the first multi-finger structure does not coincide with the central axis of the first pad VDD, so that the gate parasitic resistance and drain parasitic resistance of the first discharge transistor MN1 relative to the first pad VDD are a little larger, and its conduction speed is slower than that of the second discharge transistor MN2.

[0061] To solve the problem of non-uniform conduction of the multi-finger structure transistors, the charging speed of the gate of the first-conducting multi-finger structure is slightly reduced. The charging speed of the first trigger terminal N1 of the trigger unit 201 is faster than that of the second trigger terminal N2 node. The first trigger terminal N1 is used to charge the later-conducting first multi-finger structure, and the second trigger terminal N2 is used to charge the first-conducting second multi-finger structure, so as to ensure that the second multi-finger structure in the middle and the first multi-finger structure around it can conduct simultaneously, making the discharge transistor conduct more uniformly, thereby improving the electrostatic discharge capacity.

[0062] In an embodiment, the resistance value of the second resistor R2 is greater than that of the first resistor R1. When there is electrostatic charge on the first pad VDD, the voltage amplitude difference between the second end of the trigger capacitor and the second end of the first resistor R1 is reduced, avoiding excessive adjustment of the conduction rate of the second discharge transistor MN2, so as to ensure that the conduction rates of the first discharge transistor MN1 and the second discharge transistor MN2 are similar, making the conduction of the multi-finger structure transistors more uniform.

[0063] Continue to refer to Figure 7, the trigger unit 201 includes a trigger capacitor C1, a first resistor R1, and a second resistor R2. The first end of the trigger capacitor C1 is connected to the first pad VDD, the second end of the trigger capacitor C1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the second pad GND. After the first end of the first resistor R1 is connected to the second end of the trigger capacitor C1, a first trigger terminal N1 of the trigger unit 201 is formed, which is used to be connected to the control terminal of the first discharge transistor MN1. The first end of the second resistor R2 is connected to the second end of the first resistor R1 to form a second trigger terminal N2 of the trigger unit 201, which is used to be connected to the control terminal of the second discharge transistor MN2. The second trigger terminal N2 is also connected to the substrate terminals of the first discharge transistor MN1 and the second discharge transistor MN2.

[0064] In one embodiment, the discharge transistors 202 are N-type transistors, and the substrate terminals of the first discharge transistor 202 and the second discharge transistor 203 are both connected to the first end of the second resistor R2. When there is static charge on the first pad VDD, the voltage at the first end of the second resistor R2 is raised, and the substrate terminals of the first discharge transistor 202 and the second discharge transistor 203 are both raised, which can accelerate the conduction of the parasitic NPN transistors in the first discharge transistor 202 and the parasitic NPN transistors in the second discharge transistor 203, and improve the static discharge ability of the electrostatic protection circuit.

[0065] Reference Figure 9 , the trigger unit 201 includes a trigger capacitor C1, a first resistor R1, and a second resistor R2. The first end of the trigger capacitor C1 is connected to the second pad GND, the second end of the trigger capacitor C1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the first pad VDD. After the first end of the first resistor R1 is connected to the second end of the trigger capacitor C1, a first trigger terminal N1 of the trigger unit 201 is formed, which is used to be connected to the control terminal of the first discharge transistor MP1. The first end of the second resistor R2 is connected to the second end of the first resistor R1 to form a second trigger terminal N2 of the trigger unit 201, which is used to be connected to the control terminal of the second discharge transistor MP2. The second trigger terminal N2 is also connected to the substrate terminals of the first discharge transistor MP1 and the second discharge transistor MP2.

[0066] In one embodiment, the discharge transistor MP1 is a P-type transistor, and the substrate terminals of the first discharge transistor MP1 and the second discharge transistor MP2 are both connected to the first end of the second resistor R2. When there is static charge on the first pad VDD, the voltage at the first end of the second resistor R2 is pulled down, such that the voltage at the first end of the second resistor R2 is less than the voltage on the first pad VDD. The voltages at the substrate terminals of the first discharge transistor MP1 and the second discharge transistor MP2 are less than the voltage on the second pad VDD, which can accelerate the conduction of the parasitic PNP transistors in the first discharge transistor MP1 and the second discharge transistor MP2, and improve the static discharge ability of the electrostatic protection circuit.

[0067] In the above technical solution, the electrostatic protection circuit includes a first discharge transistor and a second discharge transistor. The impedance of the parasitic device between the first discharge transistor and the first pad is greater than the impedance of the parasitic device between the second discharge transistor and the first pad. Connect the control terminal of the first discharge transistor to the first trigger terminal of the trigger unit, and connect the control terminal of the second discharge transistor to the second trigger terminal of the trigger unit. The charge and discharge rate of the first trigger terminal is greater than that of the second trigger terminal. With such an arrangement, the trigger terminal of the trigger circuit causes the conduction rate of the first discharge transistor to be higher than that of the second discharge transistor, and the impedance of the parasitic device causes the conduction rate of the first discharge transistor to be lower than that of the second discharge transistor. By balancing the two, the conduction rates of the first discharge transistor and the second discharge transistor are made close, so that the two discharge transistors conduct evenly, which is suitable for a multi-finger structure. Also, connect the substrate terminals of the first discharge transistor and the second discharge transistor to the second trigger terminal, which can accelerate the conduction of the parasitic transistors in the discharge transistors and enhance the static discharge ability. Moreover, connecting the substrate terminals of the two discharge transistors to the first trigger terminal can effectively reduce the risk of latch-up effect.

[0068] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An electrostatic protection circuit, characterized in that, The chip includes a first pad and a second pad, and the electrostatic protection circuit includes: A trigger unit, which is connected between the first pad and the second pad, and is provided with a first trigger end and a second trigger end, and is used to generate a first trigger signal when there is an electrostatic pulse on the first pad; the trigger unit is also used to generate a second trigger signal when there is the electrostatic pulse on the first pad; A first discharge transistor, whose control end is connected to the first trigger end of the trigger unit, whose first end is connected to the first pad, whose second end is connected to the second pad, and whose substrate end is connected to the second trigger end of the trigger unit, and is used to discharge electrostatic charges to the second pad under the trigger of the first trigger signal; A second discharge transistor, whose control end is connected to the second trigger end, whose first end is connected to the first pad, whose second end is connected to the second pad, and whose substrate end is connected to the second trigger end of the trigger unit, and is used to discharge the electrostatic charges to the second pad under the trigger of the second trigger signal; Wherein, the trigger unit includes: A trigger capacitor, which is provided with a first end and a second end, A first resistor, which is provided with a first end and a second end, and whose first end is connected to the second end of the trigger capacitor to form the first trigger end of the trigger unit; A second resistor, which is provided with a first end and a second end, and whose first end is connected to the second end of the first resistor to form the second trigger end of the trigger unit.

2. The electrostatic protection circuit according to claim 1, wherein The distance between the projection of the first discharge transistor on the substrate and the projection of the first pad on the substrate is greater than the distance between the projection of the second discharge transistor on the substrate and the projection of the first pad on the substrate.

3. The electrostatic protection circuit according to claim 2, wherein The first discharge transistor includes a first multi-finger structure, and the second discharge transistor includes a second multi-finger structure, wherein the first multi-finger structure and the second multi-finger structure are arranged adjacent to each other.

4. The electrostatic protection circuit according to claim 3, characterized in that, The central axis of the projection of the first multi-finger structure on the substrate coincides with the central axis of the first projection of the first pad on the substrate; The central axis of the projection of the second multi-finger structure on the substrate does not coincide with the central axis of the first projection.

5. The electrostatic protection circuit according to any one of claims 1 to 4, characterized in that, The first end of the trigger capacitor is connected to the first pad, and the second end of the second resistor is connected to the second pad.

6. The electrostatic protection circuit according to claim 5, wherein, The first discharge transistor is an N-type transistor.

7. The electrostatic protection circuit according to claim 6, wherein When the first discharge transistor is turned on, the parasitic NPN-type transistor in the first discharge transistor is also turned on.

8. The electrostatic protection circuit according to claim 5, characterized in that The first discharge transistor and the second discharge transistor are N-type transistors.

9. The electrostatic protection circuit according to claim 8, characterized in that, The charging rate of the control end of the first discharge transistor is greater than the charging rate of the control end of the second discharge transistor, and when the first discharge transistor and the second discharge transistor are turned on, the parasitic NPN-type transistor in the first discharge transistor and the parasitic NPN-type transistor in the second discharge transistor are also turned on.

10. The electrostatic protection circuit according to claim 5, wherein, The first end of the trigger capacitor is connected to the second pad, and the second end of the second resistor is connected to the first pad.

11. The electrostatic protection circuit according to claim 10, wherein The first discharge transistor and the second discharge transistor are P-type transistors.

12. The electrostatic protection circuit according to claim 11, wherein, The discharge rate of the control terminal of the first discharge transistor is greater than that of the control terminal of the second discharge transistor, and when the first discharge transistor and the second discharge transistor are turned on, the parasitic PNP transistor in the first discharge transistor and the parasitic PNP transistor in the second discharge transistor are also turned on.

13. The electrostatic protection circuit according to claim 1, characterized in that The resistance value of the second resistor is greater than that of the first resistor.

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