Signal conversion circuit, chip and electronic device

Abstract

The application discloses a signal conversion circuit, a chip and electronic equipment, wherein the circuit comprises: a first diode and a second diode, the anode of the first diode is connected with a signal input end, the cathode of the first diode is connected with the cathode of the second diode and a first connection point is formed, and the anode of the second diode is grounded, wherein the first positive and negative voltage signal of the signal input end is converted into a second positive and negative voltage signal through the first diode and the second diode, and the second positive and negative voltage signal is output through the first connection point; an inverter, the input end of the inverter is connected with the first connection point, and the output end of the inverter is connected with a signal output end, wherein the second positive and negative voltage signal is converted into a CMOS / TTL level signal through the inverter, and the CMOS / TTL level signal is output through the signal output end. Thus, the positive and negative voltage can be converted into a logic level, the withstand voltage requirement of the inverter can be reduced, the manufacturing process of the inverter can be more selectively selected, the circuit is simple, and the chip area can be saved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a signal conversion circuit, chip, and electronic device. Background Technology

[0002] As integrated circuit manufacturing processes become miniaturized, the gate voltage of MOS devices in circuits is gradually decreasing. However, in chip design, when it's necessary to convert positive and negative high-level signals to CMOS or TTL logic levels, high-gate-voltage MOS devices are generally used to construct the conversion circuit. For example, when converting ±25V levels to logic levels, MOS devices with gate voltages exceeding 25V are required, which limits the selectivity of the chip process chain. To address this, related technologies have proposed a conversion circuit, such as... Figure 1 As shown, the input voltage is first divided by a resistor, and then the signal is converted by a comparator circuit, thus realizing the function of converting positive and negative high levels to logic levels using a low gate voltage MOS device.

[0003] The drawbacks of the aforementioned technologies are that using voltage divider resistors in the circuit will occupy a large chip area, and since the comparator also has standby current when in standby mode, it will also generate high standby power consumption. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to provide a signal conversion circuit that converts an input first positive and negative voltage signal into a second positive and negative voltage signal with an adjustable voltage range using a first diode and a second diode. Subsequently, an inverter converts the second positive and negative voltage signal into a CMOS / TTL level signal, which is then output through a signal output terminal. This achieves the function of converting positive and negative voltage signals into logic level signals while reducing the voltage withstand requirement of the inverter, allowing for greater choice in the manufacturing process of the signal conversion circuit. Furthermore, the circuit is simple, effectively saving chip area and achieving circuit optimization.

[0005] The second objective of this invention is to provide a chip.

[0006] The third objective of this invention is to provide an electronic device.

[0007] To achieve the above objectives, a first aspect of the present invention provides a signal conversion circuit, comprising: a first diode and a second diode, wherein the anode of the first diode is connected to a signal input terminal, the cathode of the first diode is connected to the cathode of the second diode and forms a first connection point, and the anode of the second diode is grounded, wherein the first diode and the second diode convert a first positive and negative voltage signal at the signal input terminal into a second positive and negative voltage signal, and outputs the signal through the first connection point; and an inverter, wherein the input terminal of the inverter is connected to the first connection point, and the output terminal of the inverter is connected to a signal output terminal, wherein the inverter converts the second positive and negative voltage signal into a CMOS / TTL level signal, and outputs the signal through the signal output terminal.

[0008] According to the signal conversion circuit of the present invention, the input first positive and negative voltage signal is converted into a second positive and negative voltage signal with an adjustable voltage range through the first diode and the second diode. Then, the second positive and negative voltage signal is converted into a CMOS / TTL level signal through the inverter and output through the signal output terminal. Thus, the function of converting positive and negative voltage signals into logic level signals is realized, while reducing the voltage withstand value requirement of the inverter. This makes the manufacturing process of the signal conversion circuit more selective, and the circuit is simple, which can effectively save chip area and achieve circuit optimization.

[0009] According to one embodiment of the present invention, when the voltage at the signal input terminal is a first positive voltage and higher than the forward conduction voltage of the first diode, the first diode conducts in the forward direction, the voltage at the first connection point follows the voltage change at the signal input terminal and is clamped below the reverse breakdown voltage of the second diode, and when the voltage at the signal input terminal is a first negative voltage, the first diode is reverse cut off, the second diode conducts in the forward direction, and the voltage at the first connection point is clamped at the forward conduction voltage of the second diode, so as to convert the first positive and negative voltage signals at the signal input terminal into second positive and negative voltage signals.

[0010] According to one embodiment of the present invention, the first diode is a Schottky diode and the second diode is a Zener diode.

[0011] According to one embodiment of the present invention, the reverse withstand voltage of the first diode is higher than the maximum amplitude of the first positive and negative voltage signals.

[0012] According to one embodiment of the present invention, the reverse breakdown voltage of the second diode is N times the maximum amplitude of the CMOS / TTL level signal, where N is greater than 1.

[0013] According to one embodiment of the present invention, the signal conversion circuit further includes a resistor connected in series between the anode of the first diode and the signal input terminal.

[0014] According to one embodiment of the present invention, the inverter includes: a first switch and a second switch, the first end of the first switch and the first end of the second switch are both connected to a first connection point, the second end of the first switch is connected to a preset power supply, the third end of the first switch and the third end of the second switch are connected to form a second connection point, the second connection point is connected to a signal output terminal, and the second end of the second switch is grounded.

[0015] According to one embodiment of the present invention, the first switching transistor is a PMOS transistor and the second switching transistor is an NMOS transistor.

[0016] To achieve the above objectives, a second aspect of the present invention provides a chip including the aforementioned signal conversion circuit.

[0017] According to the chip of the present invention, the aforementioned signal conversion circuit not only realizes the function of converting positive and negative voltage signals into logic level signals, but also reduces the voltage withstand requirement of the inverter, making the chip manufacturing process more selective. At the same time, the circuit is simple, which can effectively save chip area and achieve chip optimization.

[0018] To achieve the above objectives, a third aspect of the present invention provides an electronic device including the aforementioned chip.

[0019] According to the present invention, the electronic device can convert positive and negative voltage signals into logic level signals through the aforementioned chip, while making the chip manufacturing process more selective and the chip area smaller, thereby reducing the manufacturing difficulty of the electronic device and optimizing the electronic device.

[0020] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a conversion circuit in a related technology;

[0022] Figure 2 This is a schematic diagram of a signal conversion circuit according to an embodiment of the present invention;

[0023] Figure 3 An equivalent circuit diagram of a signal conversion circuit according to an embodiment of the present invention;

[0024] Figure 4 A circuit diagram of a signal conversion circuit according to another embodiment of the present invention;

[0025] Figure 5 This is a diagram showing the relationship between the first positive and negative voltage signals and the voltage at the signal output terminal according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0028] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0029] The signal conversion circuit, chip, and electronic device proposed in the embodiments of the present invention are described below with reference to the accompanying drawings.

[0030] Figure 2 The diagram shown is a schematic representation of a signal conversion circuit according to an embodiment of the present invention. (Refer to...) Figure 2 As shown, the signal conversion circuit 100 includes a first diode D1, a second diode D2, and an inverter 110.

[0031] In this circuit, the anode of the first diode D1 is connected to the signal input terminal VI, the cathode of the first diode D1 is connected to the cathode of the second diode D2 and forms a first connection point J1, and the anode of the second diode D2 is grounded to GND. The first positive and negative voltage signals of the signal input terminal VI are converted into second positive and negative voltage signals through the first diode D1 and the second diode D2, and output through the first connection point J1. The input terminal of the inverter 110 is connected to the first connection point J1, and the output terminal of the inverter 110 is connected to the signal output terminal VO. The second positive and negative voltage signals are converted into CMOS / TTL level signals through the inverter 110, and output through the signal output terminal VO.

[0032] Specifically, the first diode D1 primarily serves an isolation function to prevent the voltage at the first connection point J1 from affecting the signal input terminal VI when the voltage of the first positive and negative voltage signals is negative. The second diode D2 forms a clamping circuit. When the voltage at the signal input terminal VI is positive, the second diode D2 clamps the voltage at the first connection point J1 below the reverse breakdown voltage of the second diode D2; when the first positive and negative voltages are negative, the second diode D2 conducts in the forward direction, thereby maintaining the voltage at the first connection point J1 at the forward conduction voltage of the second diode D2. Thus, the input first positive and negative voltage signals are converted into second positive and negative voltage signals with a fixed voltage range. The voltage range of the second positive and negative voltage signals can be adjusted by selecting different types of diodes as the second diode D2.

[0033] Inverter 110 is used to convert the second positive and negative voltage signals into CMOS / TTL level signals. Since the voltage range of the second positive and negative voltage signals is fixed and adjustable, inverter 110 does not need to be constructed from high-voltage devices. For example, a low-gate-voltage MOS device can be used to construct inverter 110, in conjunction with the first diode D1 and the second diode D2, to realize the function of converting the input first positive and negative voltage signals into CMOS / TTL level signals for output. Therefore, the signal conversion circuit 100 of this embodiment of the invention has a wider range of choices in process chain selection. At the same time, compared with the method of using multiple resistors to divide the voltage and then using a comparator to achieve level conversion in related technologies, the signal conversion circuit 100 of this embodiment of the invention uses fewer electronic components, which can effectively save chip area.

[0034] In the above embodiment, the input first positive and negative voltage signals are converted into second positive and negative voltage signals with adjustable voltage range by the first diode and the second diode. Then, the second positive and negative voltage signals are converted into CMOS / TTL level signals by the inverter and output through the signal output terminal. This not only realizes the function of converting positive and negative voltage signals into logic level signals, but also reduces the voltage withstand value requirement of the inverter, makes the manufacturing process of the signal conversion circuit more selective, and at the same time, the circuit is simple, which can effectively save chip area and achieve circuit optimization.

[0035] In some embodiments, when the voltage at signal input terminal VI is a first positive voltage and higher than the forward conduction voltage of the first diode D1, the first diode D1 is forward-biased, the voltage at the first connection point J1 follows the voltage change of signal input terminal VI and is clamped below the reverse breakdown voltage of the second diode D2, and when the voltage at signal input terminal VI is a first negative voltage, the first diode D1 is reverse-biased cut off, the second diode D2 is forward-biased, and the voltage at the first connection point J1 is clamped at the forward conduction voltage of the second diode D2, so as to convert the first positive and negative voltage signals of signal input terminal VI into second positive and negative voltage signals.

[0036] Specifically, refer to Figure 2As shown, when the voltage at signal input terminal VI is a first positive voltage and higher than the forward conduction voltage of the first diode D1, the first diode D1 conducts in the forward direction, and the voltage at the first connection point J1 follows the voltage change at signal input terminal VI. At this time, the second diode D2 forms a clamping circuit. When the first positive voltage is higher than the reverse breakdown voltage of the second diode D2, the second diode D2 breaks down in the reverse direction. At this time, the voltage at the first connection point J1 is equal to the reverse breakdown voltage of the second diode D2, thus clamping the voltage at the first connection point J1 below the reverse breakdown voltage of the second diode D2. When the voltage at signal input terminal VI is a first negative voltage, the first diode D1 is reverse cut off, and the second diode D2 conducts in the forward direction. At this time, the voltage at the first connection point J1 is negative and equal in magnitude to the forward conduction voltage of the second diode D2. Thus, the first positive and negative voltage signals at the signal input terminal are converted into second positive and negative voltage signals.

[0037] As a concrete example, assuming the forward voltage of the second diode D2 is 0.7V and the reverse breakdown voltage is 10V, the voltage range at the signal input terminal VI is ±25V, and the forward voltage of the first diode D1 is 0.1V, then it can be seen that when the voltage at the signal input terminal VI is between 10.1V and 25V, the voltage at the first connection point J1 is stable at 10V; when the voltage at the signal input terminal VI is between 0.1V and 10.1V, the voltage at the first connection point J1 follows the voltage change at the signal input terminal VI and is always 0.1V lower than the voltage at the signal input terminal VI; when the voltage at the signal input terminal is between -25V and 0.1V, the voltage at the signal input terminal is stable at -0.7V. Thus, the first positive and negative voltage signal of ±25V is converted into a second positive and negative voltage signal of -0.7V to 10V.

[0038] Furthermore, the first diode D1 is a Schottky diode, and the second diode D2 is a Zener diode.

[0039] Specifically, the Zener diode has the characteristic of Zener breakdown, that is, when it is reverse broken down, the Zener diode can play a voltage stabilizing role and can recover to the unbroken state. Therefore, by selecting a suitable Zener diode as the second diode D2, the voltage range of the second positive and negative voltage signals can be adjusted to match the withstand voltage of the inverter 110.

[0040] Since the cathode of the Schottky diode is an N-well, it forms a parasitic diode with the silicon substrate Psub. When the Schottky diode is used as the first diode D1, the equivalent circuit of the signal conversion circuit 100 is as follows: Figure 3As shown, the parasitic diode DJS can be considered as being connected in parallel across the second diode D2. When a high-amplitude positive electrostatic pulse is input to the signal input terminal VI, the parasitic diode DJS is broken down, and the second diode D2 also undergoes Zener breakdown. The signal input terminal VI is grounded to GND through the first diode D1 and the second diode D2, thereby eliminating the positive electrostatic pulse. When a high-amplitude reverse electrostatic pulse is input to the signal input terminal VI, both the parasitic diode DJS and the second diode D2 are forward-biased, causing the reverse electrostatic pulse to disappear. This provides electrostatic protection for the inverter and further improves the safety of the signal conversion circuit.

[0041] Furthermore, the reverse withstand voltage of the first diode D1 is higher than the maximum amplitude of the first positive and negative voltage signals.

[0042] Specifically, since the first diode D1 has an isolation function, when the first positive and negative voltage signals are the first negative voltage, the first diode D1 is reverse cut off, so that the signal input terminal VI will not be grounded to GND through the second diode D2. Therefore, the reverse withstand voltage of the first diode D1 needs to be higher than the maximum amplitude of the first positive and negative voltage signals to ensure that the first diode D1 will not be reverse broken down at this time, so that the voltage of the signal input terminal is not affected by the first connection point, and at the same time protects the safety of the signal conversion circuit.

[0043] Furthermore, the reverse breakdown voltage of the second diode D2 is N times the maximum amplitude of the CMOS / TTL level signal, where N is greater than 1.

[0044] Specifically, since inverter 110 converts the second positive and negative voltage signals into CMOS / TTL level signals, the reverse breakdown voltage of the second diode D2 can be set to N times the maximum amplitude of the CMOS / TTL level signal, where N is greater than 1. This ensures that the second positive and negative voltage signals can cover the operating range of inverter 110. Simultaneously, since the reverse breakdown voltage of the second diode D2 is directly applied to inverter 100, considering that the withstand voltage of inverter 100 cannot be too high, the reverse breakdown voltage of the second diode D2 also needs to be selected according to the withstand voltage of inverter 100 to ensure that inverter 100 is not damaged by the second positive and negative voltage signals. For example, when it is necessary to convert the second positive and negative voltage signals into TTL level signals, since the maximum amplitude of the TTL level signal is 5V, N can be set to 1.1, that is, the reverse breakdown voltage of the second diode D2 can be set to 5.5V. This ensures that the voltage of the second positive and negative voltage signals can cover the operating range of the inverter, and also ensures that the inverter is not damaged by the second positive and negative voltage signals.

[0045] In some embodiments, reference Figure 4As shown, the signal conversion circuit 100 also includes a resistor R, which is connected in series between the anode of the first diode D1 and the signal input terminal VI.

[0046] Specifically, resistor R can limit current to reduce the power consumption of signal conversion circuit 100, and when the second diode D2 is reverse-biased, resistor R can prevent the second diode D1 from being damaged due to large current after breakdown, thus protecting the circuit safety.

[0047] In some embodiments, reference Figure 4 As shown, the inverter 110 includes: a first switch Q1 and a second switch Q2. The first end of the first switch Q1 and the first end of the second switch Q2 are both connected to a first connection point J1. The second end of the first switch Q2 is connected to a preset power supply VDD. The third end of the first switch Q1 and the third end of the second switch Q2 are connected to form a second connection point J2. The second connection point J2 is connected to the signal output terminal VO. The second end of the second switch Q2 is grounded.

[0048] Furthermore, the first switch Q1 is a PMOS transistor, and the second switch Q2 is an NMOS transistor.

[0049] Specifically, refer to Figure 4 As shown, the first switch Q1 and the second switch Q2 form a CMOS inverter. The relationship between the voltage VI of the first positive and negative voltage signals and the voltage VO at the signal output terminal is as follows: Figure 5 As shown, when the first positive and negative voltage signal voltage is less than or equal to 0, the second positive and negative voltage signal voltage is clamped to a negative value, causing the second switch Q2 to turn off and the first switch Q1 to turn on. The signal output voltage VO is approximately equal to the preset power supply voltage VDD. When the first positive and negative voltage signal voltage is greater than or equal to the preset power supply voltage VDD, the second positive and negative voltage signal voltage is also higher than VDD. At this time, the first switch Q1 turns off and the second switch Q2 turns on, and the signal output voltage VO is approximately 0V. Thus, the second positive and negative voltage signal is converted into the corresponding CMOS / TTL level signal. Furthermore, since the CMOS inverter does not require standby current in standby mode, compared to the method of using comparators to convert signals in related technologies, the signal conversion circuit of this embodiment has lower standby power consumption, thereby optimizing the signal conversion circuit.

[0050] It should be noted that the preset power supply VDD voltage value can be set according to the type of signal level to be converted. For example, when it is necessary to convert the second positive and negative voltage signal to TTL level, the preset power supply VDD can be set to 5V.

[0051] As a specific embodiment, assuming the voltage range of the first positive and negative voltage signals is ±25V, and it is necessary to convert the first positive and negative voltage signals to TTL level, the voltage value of the preset power supply VDD can be set to 5V. At the same time, the reverse breakdown voltage of the second diode can be set to 5.5V. Then, a switching transistor with a gate withstand voltage greater than 5.5V can be selected to form an inverter 110. For example, a switching transistor with a gate withstand voltage of 6V can be selected to form an inverter 110. This can convert the first positive and negative voltage signals to TTL level while ensuring circuit safety. This realizes the function of converting positive and negative high level signals to logic level signals using a low gate withstand voltage switching transistor. This makes the inverter no longer limited to using high gate withstand voltage MOS devices, thus making the manufacturing process of the signal conversion circuit more selective.

[0052] In summary, the signal conversion circuit according to the embodiments of the present invention converts the input first positive and negative voltage signals into second positive and negative voltage signals with adjustable voltage range through the first diode and the second diode. Then, the second positive and negative voltage signals are converted into CMOS / TTL level signals through the inverter and output through the signal output terminal. This not only realizes the function of converting positive and negative voltages into logic levels, but also reduces the voltage withstand value requirement of the inverter, making the manufacturing process of the signal conversion circuit more selective. Moreover, the circuit is simple, does not require standby current, and can effectively save chip area and standby power consumption. At the same time, the use of Schottky diode as the first diode and Zener diode as the second diode gives the signal conversion circuit an anti-static function, thereby optimizing the signal conversion circuit.

[0053] In some embodiments, a chip is also provided, with reference to Figure 6 As shown, the chip 1000 includes the aforementioned signal conversion circuit 100.

[0054] According to the chip of the present invention, the aforementioned signal conversion circuit not only realizes the function of converting positive and negative voltages into logic levels, but also reduces the voltage withstand requirement of the inverter, making the chip manufacturing process more selective, and the circuit is simple, which can effectively save chip area; at the same time, the chip has an anti-static function, making the chip safer, thereby achieving chip optimization.

[0055] In some embodiments, an electronic device is also provided, with reference to Figure 7 As shown, the electronic device 10000 includes the aforementioned chip 1000.

[0056] According to the present invention, the electronic device can convert positive and negative voltages into logic levels through the aforementioned chip, while making the chip manufacturing process more selective, thereby reducing the production difficulty of the electronic device; moreover, the chip has a small area, low standby power consumption, and anti-static function, resulting in high safety and optimization of the electronic device.

[0057] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0058] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0061] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A signal conversion circuit, characterized in that, include: A first diode and a second diode are used. The anode of the first diode is connected to the signal input terminal, and the cathode of the first diode is connected to the cathode of the second diode and forms a first connection point. The anode of the second diode is grounded. The first positive and negative voltage signals of the signal input terminal are converted into second positive and negative voltage signals through the first diode and the second diode, and then output through the first connection point. An inverter, wherein the input terminal of the inverter is connected to the first connection point, and the output terminal of the inverter is connected to the signal output terminal, wherein the second positive and negative voltage signals are converted into CMOS / TTL level signals by the inverter and output through the signal output terminal; When the voltage at the signal input terminal is a first positive voltage and higher than the forward conduction voltage of the first diode, the first diode conducts forward, and the voltage at the first connection point follows the voltage change at the signal input terminal and is clamped below the reverse breakdown voltage of the second diode. When the voltage at the signal input terminal is a first negative voltage, the first diode is reverse cut off, the second diode conducts forward, and the voltage at the first connection point is clamped at the forward conduction voltage of the second diode, so as to convert the first positive and negative voltage signals at the signal input terminal into second positive and negative voltage signals. The first diode is a Schottky diode, and the second diode is a Zener diode.

2. The signal conversion circuit according to claim 1, characterized in that, The reverse withstand voltage of the first diode is higher than the maximum amplitude of the first positive and negative voltage signals.

3. The signal conversion circuit according to claim 1, characterized in that, The reverse breakdown voltage of the second diode is N times the maximum amplitude of the CMOS / TTL level signal, where N is greater than 1.

4. The signal conversion circuit according to claim 1, characterized in that, Also includes: A resistor is connected in series between the anode of the first diode and the signal input terminal.

5. The signal conversion circuit according to claim 1, characterized in that, The inverter includes: A first switch and a second switch, wherein the first end of the first switch and the first end of the second switch are both connected to the first connection point, the second end of the first switch is connected to a preset power supply, the third end of the first switch and the third end of the second switch are connected to form a second connection point, the second connection point is connected to the signal output terminal, and the second end of the second switch is grounded.

6. The signal conversion circuit according to claim 5, characterized in that, The first switch is a PMOS transistor, and the second switch is an NMOS transistor.

7. A chip, characterized in that, Includes the signal conversion circuit according to any one of claims 1-6.

8. An electronic device, characterized in that, Includes the chip according to claim 7.

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