A fractional-N sub-sampling frequency synthesizer based on the average value of current

Abstract

The present invention discloses a fractional frequency division sub-sampling frequency synthesizer based on current mean value, which includes a reference clock input terminal, a first reference voltage input terminal, a second reference voltage input terminal, a common-mode voltage input terminal, a frequency synthesis control word input terminal, a microwave signal output terminal, a radio frequency signal output terminal, a dual-phase sub-sampling phase-voltage converter, a current mean value transconductance amplifier, a low-pass loop filter, a voltage-controlled oscillator, a differential-single-ended buffer, a ÷2 frequency divider, a single-ended buffer, a sampling phase generator, a frequency division and mean value control signal generator, and a frequency discrimination branch. While having the advantage of low in-band noise of the sub-sampling phase-locked loop structure, the synthesizer can effectively suppress the phase noise generated by fractional frequency division.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a fractional-N sub-sampling frequency synthesizer based on the average value of current. Background Art

[0002] A frequency synthesizer is one of the important functional modules in radio frequency / microwave communication systems and computer systems, and is widely used in the generation of carrier signals, clock signals, frequency modulation signals, and phase modulation signals. Since the phase-locked loop has many advantages such as good frequency tracking characteristics, small spurious components, and high system stability, the frequency synthesizer is mainly implemented based on the phase-locked loop structure.

[0003] Compared with the traditional phase-locked loop based on the phase-frequency detector-charge pump structure, the sub-sampling phase-locked loop directly samples the high-frequency output of the oscillator under the control of a low-frequency reference clock to obtain phase error information, and then adjusts the output frequency of the oscillator through negative feedback control to achieve the function of the phase-locked loop. Since there is no frequency divider in the feedback loop of the sub-sampling phase-locked loop, the noise of its phase detector is only 1 / N of the noise of the phase detector of the traditional phase-locked loop based on the phase-frequency detector-charge pump structure 2 , so the in-band noise is significantly reduced, and the power consumption of frequency division is saved. However, the sub-sampling phase-locked loop lacks a phase modulation mechanism in the loop and cannot be directly used for frequency synthesis with a fractional-N ratio. To address this problem, the most commonly used method in the reported work at home and abroad today is to use a digital-time converter to calibrate the edge of the reference signal and change the sampling time to achieve fractional-N frequency division. However, the digital-time converter introduces additional noise and non-linear distortion, deteriorating the phase noise characteristics of the input reference clock, which in turn affects the phase noise characteristics of the overall frequency synthesizer. In addition, the digital-time converter used must have a high time resolution and at the same time achieve a wide dynamic range to meet the requirements of accurate fractional-N frequency division under changes in integrated circuit process, chip power supply voltage, and environmental temperature. The implementation of such a digital-time converter is very challenging and usually requires complex background circuit calibration, which not only increases the system complexity of the frequency synthesizer, but also increases the power consumption and hardware overhead.

[0004] Although the frequency synthesizer based on the sub-sampling phase-locked loop effectively suppresses the in-band noise, for the fractional-N sub-sampling phase-locked loop structure, the fractional-N frequency division introduces additional quantization noise, deteriorating the overall noise characteristics of the frequency synthesizer. In the past decade, many quantization noise suppression techniques have been proposed by researchers at home and abroad, such as feed-forward compensation techniques based on digital-to-analog converters and digital-time converters, phase interpolation techniques, and filtering preprocessing methods based on finite impulse response filters. However, these techniques have poor compatibility with the frequency synthesizer based on the sub-sampling phase-locked loop and have limitations. Summary of the Invention

[0005] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art, and provide a fractional-N subsampling frequency synthesizer based on current average value. While having the advantage of low in-band noise of the subsampling phase-locked loop structure, the synthesizer can effectively suppress the phase noise generated by fractional-N division.

[0006] To achieve the above object, the fractional-N subsampling frequency synthesizer based on current average value described in the present invention includes a reference clock input terminal, a first reference voltage input terminal, a second reference voltage input terminal, a common-mode voltage input terminal, a frequency synthesis control word input terminal, a microwave signal output terminal, a radio frequency signal output terminal, a dual-phase subsampling phase-voltage converter, a current average value transconductance amplifier, a low-pass loop filter, a voltage-controlled oscillator, a differential-single-ended buffer, a ÷2 frequency divider, a single-ended buffer, a sampling phase generator, a frequency division and average value control signal generator, and a frequency discrimination branch;

[0007] The first phase signal input terminal of the dual-phase sub-sampling phase-voltage converter is connected to the reference clock input terminal. The first voltage input terminal and the second voltage input terminal of the dual-phase sub-sampling phase-voltage converter are connected to the first reference voltage input terminal and the second reference voltage input terminal respectively. The first voltage signal output terminal and the second voltage signal output terminal of the dual-phase sub-sampling phase-voltage converter are respectively connected to the first inverting input terminal and the second inverting input terminal of the current mean transconductance amplifier. The clock pulse output terminal of the dual-phase sub-sampling phase-voltage converter is connected to the scalar control terminal of the current mean transconductance amplifier. The non-inverting input terminal of the current mean transconductance amplifier is connected to the common-mode voltage input terminal. The current output terminal of the current mean transconductance amplifier is connected to the input terminal of the low-pass loop filter and the current output terminal of the frequency discrimination branch. The output terminal of the low-pass loop filter is connected to the input terminal of the voltage-controlled oscillator. The differential output terminal of the voltage-controlled oscillator is connected to the differential input terminal of the differential-single-ended buffer, the differential input terminal of the ÷2 frequency divider, and the differential input terminal of the sampling phase generator. The first phase signal output terminal and the second phase signal output terminal of the sampling phase generator are respectively connected to the second phase signal input terminal and the third phase signal input terminal of the dual-phase sub-sampling phase-voltage converter. The second phase signal output terminal of the sampling phase generator is connected to the first phase signal input terminal of the frequency discrimination branch. The second phase signal input terminal of the frequency discrimination branch is connected to the reference clock input terminal. The input terminal of the frequency division and mean control signal generator is connected to the frequency synthesis control word input terminal. The single-phase clock input terminal of the frequency division and mean control signal generator is connected to the single-phase clock output terminal of the frequency discrimination branch. The first vector output terminal of the frequency division and mean control signal generator is connected to the vector control terminal of the current mean transconductance amplifier. The second vector output terminal of the frequency division and mean control signal generator is connected to the vector control terminal of the sampling phase generator. The scalar output terminal of the frequency division and mean control signal generator is connected to the scalar control terminal of the frequency discrimination branch. The output terminal of the differential-single-ended buffer is connected to the microwave signal output terminal. The output terminal of the ÷2 frequency divider is connected to the input terminal of the single-ended buffer. The output terminal of the single-ended buffer is connected to the radio frequency signal output terminal.

[0008] The dual-phase sub-sampling phase-voltage converter includes a first voltage signal output terminal, a second voltage signal output terminal, a clock pulse output terminal, a sampling and control clock generator, a dual-phase linear ramp generator, and a dual-phase sub-sampling phase discriminator;

[0009] The reference clock input terminal is connected to the sampling and control clock generator, the pulse signal output terminal is connected to the sampling and control clock generator, the first phase signal output terminal and the second phase signal output terminal of the sampling phase generator are connected to the dual-phase linear ramp generator, the dual-phase linear ramp generator is connected to the dual-phase sub-sampling phase detector, and the dual-phase sub-sampling phase detector is connected to the first reference voltage input terminal, the second reference voltage input terminal, the first voltage signal output terminal, and the second voltage signal output terminal.

[0010] The dual-phase linear ramp generator includes a frequency discriminator and phase detector, a first switch, a second switch, a first current source, and a second current source; the dual-phase sub-sampling phase detector includes a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a first capacitor, and a second capacitor;

[0011] The first phase signal output terminal and the second phase signal output terminal of the sampling phase generator are respectively connected to the first input terminal and the second input terminal of the frequency discriminator and phase detector. The first output terminal of the frequency discriminator and phase detector is connected to the control terminal of the first switch, and the second output terminal of the frequency discriminator and phase detector is connected to the control terminal of the second switch. One end of the first switch is connected to the output terminal of the first current source and one end of the third switch. The other end of the first switch and one end of the second switch are grounded. The other end of the second switch is connected to the output terminal of the second current source and one end of the fourth switch. The first current source and the second current source are connected to an external power supply. The other end of the third switch, one end of the first capacitor, and one end of the seventh switch are connected to one end of the ninth switch. The other end of the fourth switch, one end of the second capacitor, and one end of the eighth switch are connected to one end of the tenth switch. The control terminals of the third switch and the fourth switch are connected to the second output terminal of the sampling and control clock generator. The other end of the first capacitor and one end of the fifth switch are connected to the first voltage signal output terminal of the dual-phase sub-sampling phase-voltage converter. The other end of the second capacitor and one end of the sixth switch are connected to the second voltage signal output terminal of the dual-phase sub-sampling phase-voltage converter. The other ends of the fifth switch and the sixth switch are connected to the first reference voltage input terminal. The control terminals of the fifth switch and the sixth switch are connected to the first output terminal of the sampling and control clock generator. The other ends of the seventh switch and the eighth switch are connected to the second reference voltage input terminal. The control terminals of the seventh switch and the eighth switch are connected to the third output terminal of the sampling and control clock generator. The other ends of the ninth switch and the tenth switch are grounded. The control terminals of the ninth switch and the tenth switch are connected to the fourth output terminal of the sampling and control clock generator. The fifth output terminal of the sampling and control clock generator is connected to the clock pulse output terminal.

[0012] The sampling and control clock generator includes a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a clock pulse output terminal, a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first delay module, a second delay module, a third delay module, a fourth delay module, a fifth delay module, and a sixth delay module;

[0013] The input terminal of the first delay module is connected to the reference clock input terminal. The output terminal of the first delay module is connected to the clock input terminal of the first D flip-flop. The data input terminal of the first D flip-flop is connected to the external high-level signal terminal. The output terminal of the first D flip-flop is connected to the input terminal of the second delay module and the first output terminal;

[0014] The output terminal of the second delay module is connected to the clock input terminal of the second D flip-flop. The data input terminal of the second D flip-flop is connected to the external high-level signal terminal. The output terminal of the second D flip-flop is connected to the input terminal of the third delay module and the second output terminal;

[0015] The output terminal of the third delay module is connected to the clock input terminal of the third D flip-flop. The data input terminal of the third D flip-flop is connected to the external high-level signal terminal. The output terminal of the third D flip-flop is connected to the input terminal of the fourth delay module and the third output terminal;

[0016] The output terminal of the fourth delay module is connected to the clock input terminal of the fourth D flip-flop. The data input terminal of the fourth D flip-flop is connected to the external high-level signal terminal. The output terminal of the fourth D flip-flop is connected to the input terminal of the fifth delay module and the clock pulse output terminal;

[0017] The output terminal of the fifth delay module is connected to the clock input terminal of the fifth D flip-flop. The data input terminal of the fifth D flip-flop is connected to the external high-level signal terminal. The output terminal of the fifth D flip-flop is connected to the input terminal of the sixth delay module and the fourth output terminal;

[0018] The output terminal of the sixth delay module is respectively connected to the clear terminals of the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop, and the fifth D flip-flop.

[0019] The sampling phase generator includes a first differential signal input terminal, a second differential signal input terminal, a first phase signal output terminal, a second phase signal output terminal, a first quadrature ÷2 frequency divider, a second quadrature ÷2 frequency divider, a third quadrature ÷2 frequency divider, a fourth quadrature ÷2 frequency divider, a fifth quadrature ÷2 frequency divider, a sixth quadrature ÷2 frequency divider, a seventh quadrature ÷2 frequency divider, a multiplexer, and a dual-phase synchronizer;

[0020] The differential output terminals of the voltage-controlled oscillator are connected to the differential input terminals of the first quadrature ÷2 frequency divider through the first differential input terminal and the second differential input terminal. The first output terminal and the second output terminal of the first quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the second quadrature ÷2 frequency divider. The third output terminal and the fourth output terminal of the first quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the third quadrature ÷2 frequency divider. The first output terminal and the second output terminal of the second quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the fourth quadrature ÷2 frequency divider. The third output terminal and the fourth output terminal of the second quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the fifth quadrature ÷2 frequency divider. The first output terminal and the second output terminal of the third quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the sixth quadrature ÷2 frequency divider. The third output terminal and the fourth output terminal of the third quadrature ÷2 frequency divider are respectively connected to the differential input terminals of the seventh quadrature ÷2 frequency divider. The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the fourth quadrature ÷2 frequency divider are respectively connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the multiplexer. The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the fifth quadrature ÷2 frequency divider are respectively connected to the fifth input terminal, the sixth input terminal, the seventh input terminal and the eighth input terminal of the multiplexer. The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the sixth quadrature ÷2 frequency divider are respectively connected to the ninth input terminal, the tenth input terminal, the eleventh input terminal and the twelfth input terminal of the multiplexer. The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the seventh quadrature ÷2 frequency divider are respectively connected to the thirteenth input terminal, the fourteenth input terminal, the fifteenth input terminal and the sixteenth input terminal of the multiplexer. The vector control terminal of the multiplexer is connected to the second vector output terminal of the frequency division and mean value control signal generator. The first output terminal and the second output terminal of the multiplexer are respectively connected to the first single-ended input terminal and the second single-ended input terminal of the dual-phase synchronizer. The first differential input terminal and the second differential input terminal of the dual-phase synchronizer are respectively connected to the first differential signal input terminal and the second differential signal input terminal. The control terminal of the dual-phase synchronizer is connected to the first phase of the second vector output terminal of the frequency division and mean value control signal generator. The first output terminal and the second output terminal of the dual-phase synchronizer are respectively connected to the first phase signal output terminal and the second phase signal output terminal.

[0021] The current mean transconductance amplifier includes a non-inverting voltage input terminal, a current output terminal, a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a sixth current source, a seventh current source, an eighth current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a 64-branch voltage-controlled charge pump array;

[0022] Among them, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor constitute the bias voltage generation circuit of this module. The voltage-controlled charge pump array includes several branches, and each branch includes a first multiplexer, a second multiplexer, an inverter, a first voltage-controlled current source, a second voltage-controlled current source, a first switch, and a second switch;

[0023] The gates of the first NMOS transistor and the second NMOS transistor are connected to the positive-phase voltage input terminal. The drain of the first NMOS transistor, the output terminal of the first current source, the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor are connected to the first output terminal of the bias voltage generating circuit. The drain of the second NMOS transistor, the output terminal of the second current source, the drain of the sixth NMOS transistor, and the gate of the sixth NMOS transistor are connected to the second output terminal of the bias voltage generating circuit. The source of the first NMOS transistor is connected to the input terminal of the fifth current source and one end of the first resistor. The source of the second NMOS transistor is connected to the input terminal of the sixth current source and one end of the second resistor. The gate of the third NMOS transistor is connected to the first negative-phase voltage input terminal. The drain of the third NMOS transistor, the output terminal of the third current source, the drain of the seventh NMOS transistor, and the gate of the seventh NMOS transistor are connected to the third output terminal of the bias voltage generating circuit. The source of the third NMOS transistor is connected to the input terminal of the seventh current source and the other end of the first resistor. The gate of the fourth NMOS transistor is connected to the second negative-phase voltage input terminal. The drain of the fourth NMOS transistor, the output terminal of the fourth current source, the drain of the eighth NMOS transistor, and the gate of the eighth NMOS transistor are connected to the fourth output terminal of the bias voltage generating circuit. The source of the fourth NMOS transistor is connected to the input terminal of the eighth current source and the other end of the second resistor. The sources of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are connected to the ground. The first output terminal of the bias voltage generating circuit is connected to the 0 input terminal of the first multiplexer. The second output terminal of the bias voltage generating circuit is connected to the 1 input terminal of the first multiplexer. The output terminal of the first multiplexer is connected to the control terminal of the first voltage-controlled current source. The third output terminal of the bias voltage generating circuit is connected to the 0 input terminal of the second multiplexer. The fourth output terminal of the bias voltage generating circuit is connected to the 1 input terminal of the second multiplexer. The output terminal of the second multiplexer is connected to the control terminal of the second voltage-controlled current source. The input terminal of the first voltage-controlled current source is connected to the power supply. The output terminal of the first voltage-controlled current source is connected to one end of the first switch. The output terminal of the second voltage-controlled current source is connected to the ground. The input terminal of the second voltage-controlled current source is connected to one end of the second switch. The input terminals of the first current source, the second current source, the third current source, and the fourth current source are connected to the power supply. The output terminals of the fifth current source, the sixth current source, the seventh current source, and the eighth current source are connected to the ground. The other end of the first switch and the other end of the second switch are connected to the current output terminal. The control terminal of the first switch is connected to the pulse voltage input terminal and the input terminal of the inverter. The control terminal of the second switch is connected to the output terminal of the inverter;

[0024] The first vector output terminal includes a plurality of sub-input terminals, wherein each sub-input terminal is connected to the control terminals of the first multiplexer and the second multiplexer in the corresponding voltage-controlled charge pump branch.

[0025] The frequency division and mean control signal generator includes a scalar output terminal, a first vector output terminal, a second vector output terminal, a fractional ΔΣ modulator, an accumulator, a data weight mean module, a first adder, and a second adder. The first vector output terminal is a 64-element vector output terminal; the second vector output terminal is a 4-element vector output terminal; the scalar output terminal is a 3-bit wide digital output terminal; the frequency synthesis control word input terminal is a 25-bit wide digital input terminal;

[0026] The input terminal of the fractional ΔΣ modulator is connected to the frequency synthesis control word input terminal. The high 3-bit wide integer control word output terminal among the 13-bit wide digital output terminal of the fractional ΔΣ modulator is connected to the 3-bit wide input terminal of the first adder. The low 10-bit wide of the 13-bit wide digital output terminal of the fractional ΔΣ modulator is the fractional control word. The high 4-bit wide of the 10-bit wide fractional control word of the fractional ΔΣ modulator, which is the most significant bit of the fractional control word, is connected to the input terminal of the accumulator. The low 6-bit wide of the 10-bit wide fractional control word of the fractional ΔΣ modulator, which is the least significant bit of the fractional control word, is connected to the input terminal of the data weight mean module. The 5-bit wide output terminal of the accumulator is connected to the 5-bit wide input terminal of the second adder. The 1-bit wide output terminal of the data weight mean module is connected to the 1-bit wide input terminal of the second adder. The highest bit among the 5-bit wide output terminal of the second adder is connected to the 1-bit wide input terminal of the first adder. The low 4 bits among the 5-bit wide output terminal of the second adder are connected to the second vector output terminal. The 3-bit wide output terminal of the first adder is connected to the scalar output terminal. The 64-bit wide output terminal of the data weight mean module is connected to the first vector output terminal.

[0027] The present invention has the following beneficial effects:

[0028] When the fractional - division sub - sampling frequency synthesizer based on the current mean value of the present invention is in specific operation, a transconductance amplifier structure based on the current mean value is adopted. Without a digital - to - time converter and related calibration circuits, fractional - division is realized, overcoming the deterioration of the input reference clock phase noise characteristics by the digital - to - time converter, reducing the system complexity and power consumption, and having the advantages of small output phase noise and low power consumption. In addition, a spatial mean - value technology based on the current mean value is adopted. By using a transconductance amplifier based on the current mean value, the problem of large capacitance mismatch in the phase - detector unit array of the voltage - mean - value sampling / sub - sampling fractional - division frequency synthesizer, which deteriorates the output spurious, is overcome. In addition, the data - weight mean - value module used to control the spatial mean - value process performs a first - order high - pass shaping on the current mismatch of the voltage - controlled charge - pump array in the transconductance - amplifier unit based on the current mean value, reducing the output spurious caused by the current mismatch in the voltage - controlled charge - pump array. It should be noted that the control circuit of the spatio - temporal mean - value technology based on the current mean value in the present invention is mainly implemented by digital circuits, making the present invention have good immunity to errors caused by process, voltage, and temperature fluctuations, and having good process reconfigurability and being convenient for automated design. With the continuous progress of the integrated - circuit manufacturing process, the power consumption and hardware overhead can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of the present invention;

[0030] Figure 2 is a schematic diagram of the dual - phase sub - sampling phase - to - voltage converter in the present invention;

[0031] Figure 3 is a schematic diagram of the sampling and control clock generator in the present invention;

[0032] Figure 4 is a schematic diagram of the sampling phase generator in the present invention;

[0033] Figure 5 is a schematic diagram of the transconductance amplifier based on the current mean value in the present invention;

[0034] Figure 6 is a schematic diagram of the frequency - division and mean - value control signal generator in the present invention;

[0035] Figure 7 is a schematic diagram of the frequency - discrimination branch in the present invention;

[0036] Figure 8 is a schematic diagram of the multi - modulus frequency divider in the present invention;

[0037] Figure 9 is a schematic diagram of the frequency - discrimination and phase - discrimination detector with dead zone in the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the scope of the present invention disclosure. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts disclosed in the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0039] The schematic structural diagrams according to the disclosed embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures and their relative sizes and positional relationships are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0040] Referring to Figure 1 , the fractional-N sub-sampling frequency synthesizer based on the current mean value according to the present invention includes a reference clock input terminal Φ ref , a first reference voltage input terminal V Ref1 , a second reference voltage input terminal V Ref2 , a common-mode voltage input terminal V CM , a frequency synthesis control word input terminal N + α, a microwave signal output terminal Φ PLL,mmW , a radio frequency signal output terminal Φ PLL,RF , a dual-phase sub-sampling phase-voltage converter, a current mean transconductance amplifier, a low-pass loop filter, a voltage-controlled oscillator, a differential-single-ended buffer, a ÷2 frequency divider, a single-ended buffer, a sampling phase generator, a frequency division and mean control signal generator, and a frequency discrimination branch;

[0041] The first phase signal input terminal of the dual-phase sub-sampling phase-voltage converter is connected to the reference clock input terminal Φ ref , the first voltage input terminal and the second voltage input terminal of the dual-phase sub-sampling phase-voltage converter are connected to the first reference voltage input terminal V Ref1 and the second reference voltage input terminal V Ref2 , the first voltage signal output terminal V Lead and the second voltage signal output terminal V Lagare respectively connected to the first inverting input terminal and the second inverting input terminal of the current average transconductance amplifier. The clock pulse output terminal PULSER of the two-phase subsampling phase-voltage converter is connected to the scalar control terminal of the current average transconductance amplifier. The non-inverting input terminal of the current average transconductance amplifier is connected to the common-mode voltage input terminal V CM is connected. The current output terminal I CP,PLL of the current average transconductance amplifier is connected to the input terminal I CP of the low-pass loop filter and the current output terminal I CP,FLL of the frequency discrimination branch. The output terminal V C of the low-pass loop filter is connected to the input terminal of the voltage-controlled oscillator. The differential output terminals of the voltage-controlled oscillator are connected to the differential input terminals of the differential-single-ended buffer BUF1, the differential input terminals of the ÷2 frequency divider, and the differential input terminals of the sampling phase generator. The first phase signal output terminal Φ Lead and the second phase signal output terminal Φ Lag of the sampling phase generator are respectively connected to the second phase signal input terminal and the third phase signal input terminal of the two-phase subsampling phase-voltage converter. The second phase signal output terminal Φ Lag of the sampling phase generator is connected to the first phase signal input terminal of the frequency discrimination branch. The second phase signal input terminal of the frequency discrimination branch is connected to the reference clock input terminal Φ ref The input terminal of the frequency division and average control signal generator is connected to the frequency synthesis control word input terminal N+α. The single-phase clock input terminal of the frequency division and average control signal generator is connected to the single-phase clock output terminal CLK digital of the frequency discrimination branch. The first vector output terminal of the frequency division and average control signal generator is connected to the vector control terminal of the current average transconductance amplifier. The second vector output terminal of the frequency division and average control signal generator is connected to the vector control terminal of the sampling phase generator. The scalar output terminal N div of the frequency division and average control signal generator is connected to the scalar control terminal of the frequency discrimination branch. The output terminal of the differential-single-ended buffer is connected to the microwave signal output terminal Φ PLL,mmW The output terminal of the ÷2 frequency divider is connected to the input terminal of the single-ended buffer BUF2. The output terminal of the single-ended buffer BUF2 is connected to the radio frequency signal output terminal Φ PLL,RF is connected.

[0042] Reference Figure 2 The two-phase subsampling phase-voltage converter includes a first voltage signal output terminal V Lead , a second voltage signal output terminal V Lag , a clock pulse output terminal PULSER, a sampling and control clock generator, a two-phase linear ramp generator, and a two-phase subsampling phase discriminator;

[0043] Reference clock input terminal Φ ref is connected to the sampling and control clock generator, the pulse signal output terminal PULSER is connected to the sampling and control clock generator, and the first phase signal output terminal Φ of the sampling phase generator Lead and the second phase signal output terminal Φ Lag are connected to the dual-phase linear ramp generator, the dual-phase linear ramp generator is connected to the dual-phase subsampling phase detector, and the dual-phase subsampling phase detector is connected to the first reference voltage input terminal V Ref1 , the second reference voltage input terminal V Ref2 , the first voltage signal output terminal V Lead and the second voltage signal output terminal V Lag are connected.

[0044] The dual-phase linear ramp generator includes a frequency discriminator and phase detector, a first switch SW1, a second switch SW2, a first current source I1 and a second current source I2; the dual-phase subsampling phase detector includes a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a ninth switch SW9, a tenth switch SW 10 , a first capacitor C1 and a second capacitor C2;

[0045] The first phase signal output terminal Φ of the sampling phase generator Lead and the second phase signal output terminal Φ Lag are respectively connected to the first input terminal and the second input terminal of the frequency discriminator and phase detector. The first output terminal of the frequency discriminator and phase detector is connected to the control terminal of the first switch SW1, and the second output terminal of the frequency discriminator and phase detector is connected to the control terminal of the second switch SW2. One end of the first switch SW1 is connected to the output terminal of the first current source I1 and one end of the third switch SW3. The other end of the first switch SW1 and one end of the second switch SW2 are grounded. The other end of the second switch SW2 is connected to the output terminal of the second current source I2 and one end of the fourth switch SW4. The first current source I1 and the second current source I2 are connected to an external power supply. The other end of the third switch SW3, one end of the first capacitor C1 and one end of the seventh switch SW7 are connected to one end of the ninth switch SW9. The other end of the fourth switch SW4, one end of the second capacitor C2 and one end of the eighth switch SW8 are connected to one end of the tenth switch SW 10 The control terminals of the third switch SW3 and the fourth switch SW4 are connected to the second output terminal Φ2 of the sampling and control clock generator. The other end of the first capacitor C1 and one end of the fifth switch SW5 are connected to the first voltage signal output terminal V of the dual-phase subsampling phase-voltage converter Leadare connected. The other end of the second capacitor C2 and one end of the sixth switch SW6 are connected to the second voltage signal output terminal V of the dual-phase sub-sampling phase-voltage converter Lag are connected. The other end of the fifth switch SW5 and the other end of the sixth switch SW6 are connected to the first reference voltage input terminal V Ref1 are connected. The control terminals of the fifth switch SW5 and the sixth switch SW6 are connected to the first output terminal Φ1 of the sampling and control clock generator. The other end of the seventh switch SW7 and the other end of the eighth switch SW8 are connected to the second reference voltage input terminal V Ref2 are connected. The control terminals of the seventh switch SW7 and the eighth switch SW8 are connected to the third output terminal Φ3 of the sampling and control clock generator. The other end of the ninth switch SW9 and the other end of the tenth switch SW 10 are grounded. The control terminals of the ninth switch SW9 and the tenth switch SW 10 are connected to the fourth output terminal Φ4 of the sampling and control clock generator. The fifth output terminal of the sampling and control clock generator is connected to the clock pulse output terminal PULSER.

[0046] When the dual-phase sub-sampling phase-voltage converter is working, the two-phase input signals Φ Lead and Φ Lag are processed by the frequency discriminator and phase detector and respectively control the first switch SW1 and the second switch SW2 to output two ramp voltage signals. When the first output signal Φ1 of the sampling and control clock generator controls the fifth switch SW5 and the sixth switch SW6 to close, the second output signal Φ2 of the sampling and control clock generator respectively controls the third switch SW3 and the fourth switch SW4 to sample the two ramp voltage signals output by the dual-phase linear ramp generator onto the first capacitor C1 and the second capacitor C2 and record them in the form of charge. When the first output signal Φ1 of the sampling and control clock generator controls the fifth switch SW5 and the sixth switch SW6 to open, the third output signal Φ3 of the sampling and control clock generator respectively controls the seventh switch SW7 and the eighth switch SW8 to close, and outputs voltage signals V Lead and V Lag to complete the sampling of the lower board. The fourth output signal Φ4 of the sampling and control clock generator respectively controls the ninth switch SW9 and the tenth switch SW 10 to reset the first capacitor C1 and the second capacitor C2.

[0047] Reference Figure 3, the sampling and control clock generator includes a first output terminal Φ1, a second output terminal Φ2, a third output terminal Φ3, a fourth output terminal Φ4, a clock pulse output terminal PULSER, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a first delay module Delay1, a second delay module Delay2, a third delay module Delay3, a fourth delay module Delay4, a fifth delay module Delay5, and a sixth delay module Delay6;

[0048] The input terminal of the first delay module Delay1 is connected to the reference clock input terminal Φ ref and is connected to the clock input terminal of the first D flip-flop DFF1. The data input terminal of the first D flip-flop DFF1 is connected to the external high-level signal terminal. The output terminal of the first D flip-flop DFF1 is connected to the input terminal of the second delay module Delay2 and the first output terminal Φ1;

[0049] The output terminal of the second delay module Delay2 is connected to the clock input terminal of the second D flip-flop DFF2. The data input terminal of the second D flip-flop DFF2 is connected to the external high-level signal terminal. The output terminal of the second D flip-flop DFF2 is connected to the input terminal of the third delay module Delay3 and the second output terminal Φ2;

[0050] The output terminal of the third delay module Delay3 is connected to the clock input terminal of the third D flip-flop DFF3. The data input terminal of the third D flip-flop DFF3 is connected to the external high-level signal terminal. The output terminal of the third D flip-flop DFF3 is connected to the input terminal of the fourth delay module Delay4 and the third output terminal Φ3;

[0051] The output terminal of the fourth delay module Delay4 is connected to the clock input terminal of the fourth D flip-flop DFF4. The data input terminal of the fourth D flip-flop DFF4 is connected to the external high-level signal terminal. The output terminal of the fourth D flip-flop DFF4 is connected to the input terminal of the fifth delay module Delay5 and the clock pulse output terminal PULSER;

[0052] The output terminal of the fifth delay module Delay5 is connected to the clock input terminal of the fifth D flip-flop DFF5. The data input terminal of the fifth D flip-flop DFF5 is connected to the external high-level signal terminal. The output terminal of the fifth D flip-flop DFF5 is connected to the input terminal of the sixth delay module Delay6 and the fourth output terminal Φ4;

[0053] The output ends of the sixth delay module Delay6 are respectively connected to the clear ends of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, and the fifth D flip-flop DFF5.

[0054] Reference Figure 4 , the sampling phase generator includes a first differential signal input end Φ VCO+ , a second differential signal input end Φ VCO- , a first phase signal output end Φ Lead , a second phase signal output end Φ Lag , a first quadrature ÷2 frequency divider QDIV1, a second quadrature ÷2 frequency divider QDIV2, a third quadrature ÷2 frequency divider QDIV3, a fourth quadrature ÷2 frequency divider QDIV4, a fifth quadrature ÷2 frequency divider QDIV5, a sixth quadrature ÷2 frequency divider QDIV6, a seventh quadrature ÷2 frequency divider QDIV7, a multiplexer MUX1, and a dual-phase synchronizer;

[0055] The differential output ends of the voltage-controlled oscillator are connected to the differential input ends of the first quadrature ÷2 frequency divider QDIV1 through the first differential input end Φ VCO+ and the second differential input end Φ VCO- . The first output end Φ 1,1 and the second output end Φ 1,3 of the first quadrature ÷2 frequency divider QDIV1 are respectively connected to the differential input ends of the second quadrature ÷2 frequency divider QDIV2. The third output end Φ 1,2 and the fourth output end Φ 1,4 of the first quadrature ÷2 frequency divider QDIV1 are respectively connected to the differential input ends of the third quadrature ÷2 frequency divider QDIV3. The first output end Φ 2,1 and the second output end Φ 2,5 of the second quadrature ÷2 frequency divider QDIV2 are respectively connected to the differential input ends of the fourth quadrature ÷2 frequency divider QDIV4. The third output end Φ 2,3 and the fourth output end Φ 2,7 of the second quadrature ÷2 frequency divider QDIV2 are respectively connected to the differential input ends of the fifth quadrature ÷2 frequency divider QDIV5. The first output end Φ 2,2 and the second output end Φ 2,6 of the third quadrature ÷2 frequency divider QDIV3 are respectively connected to the differential input ends of the sixth quadrature ÷2 frequency divider QDIV6. The third output end Φ 2,4 and the fourth output end Φ 2,8 of the third quadrature ÷2 frequency divider QDIV3 are respectively connected to the differential input ends of the seventh quadrature ÷2 frequency divider QDIV7. The first output end Φ 3,1 and the second output end Φ 3,9, the third output terminal Φ 3,5 and the fourth output terminal Φ 3,13 are respectively connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the multiplexer MUX1. The first output terminal Φ 3,3 , the second output terminal Φ 3,11 , the third output terminal Φ 3,7 and the fourth output terminal Φ 3,15 of the fifth quadrature ÷2 frequency divider QDIV5 are respectively connected to the fifth input terminal, the sixth input terminal, the seventh input terminal and the eighth input terminal of the multiplexer MUX1. The first output terminal Φ 3,2 , the second output terminal Φ 3,10 , the third output terminal Φ 3,6 and the fourth output terminal Φ 3,14 of the sixth quadrature ÷2 frequency divider QDIV6 are respectively connected to the ninth input terminal, the tenth input terminal, the eleventh input terminal and the twelfth input terminal of the multiplexer MUX1. The first output terminal Φ 3,4 , the second output terminal Φ 3,12 , the third output terminal Φ 3，8 and the fourth output terminal Φ 3,16 of the seventh quadrature ÷2 frequency divider QDIV7 are respectively connected to the thirteenth input terminal, the fourteenth input terminal, the fifteenth input terminal and the sixteenth input terminal of the multiplexer MUX1. The vector control terminal of the multiplexer MUX1 is connected to the second vector output terminal of the frequency division and mean value control signal generator . The first output terminal Φ opt,1 and the second output terminal Φ opt,2 of the multiplexer MUX1 are respectively connected to the first single-ended input terminal and the second single-ended input terminal of the dual-phase synchronizer. The first differential input terminal and the second differential input terminal of the dual-phase synchronizer are respectively connected to the first differential signal input terminal Φ VCO+ and the second differential signal input terminal Φ VCO- . The control terminal of the dual-phase synchronizer is connected to the first bit N of the second vector output terminal of the frequency division and mean value control signal generator PS,0 . The first output terminal and the second output terminal of the dual-phase synchronizer are respectively connected to the first phase signal output terminal Φ Lead and the second phase signal output terminal Φ Lag .

[0056] In the sampling phase generator, the high-frequency signal output by the voltage-controlled oscillator is divided by three stages of quadrature ÷2 frequency dividers to generate sixteen eight-frequency signals with a phase difference of π / 8 from each other. The four-bit vector phase selection control terminal selects the phase of the sixteen frequency-divided signals through the multiplexer, and outputs the signals Φ opt,1 and Φ opt,2Through the dual-phase synchronizer, the high-frequency signal output by the voltage-controlled oscillator is jitter-cleaned under the control of the first bit N of the vector control signal and then the phase signal Φ PS,0 is output. Lead And Φ Lag .

[0057] Reference Figure 5 , the current mean transconductance amplifier includes a non-inverting voltage input terminal V CM , a current output terminal I CP,PLL , a first current source I3, a second current source I4, a third current source I5, a fourth current source I6, a fifth current source I7, a sixth current source I8, a seventh current source I9, an eighth current source I 10 , a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first resistor R1, a second resistor R2, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, and a voltage-controlled charge pump array with 64 branches;

[0058] Among them, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the eighth NMOS transistor M8 constitute the bias voltage generation circuit of this module. The voltage-controlled charge pump array includes several branches, and each branch includes a first multiplexer MUX2, a second multiplexer MUX3, an inverter INV1, a first voltage-controlled current source VCCS1, a second voltage-controlled current source VCCS2, a first switch SW 11 and a second switch SW 12 ;

[0059] The gates of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to the non-inverting voltage input terminal V CM . The drain of the first NMOS transistor M1, the output terminal of the first current source I3, the drain of the fifth NMOS transistor M5, and the gate of the fifth NMOS transistor M5 are connected to the first output terminal V UP,0 of the bias voltage generation circuit. The drain of the second NMOS transistor M2, the output terminal of the second current source I4, the drain of the sixth NMOS transistor M6, and the gate of the sixth NMOS transistor M6 are connected to the second output terminal V UP,1 of the bias voltage generation circuit. The source of the first NMOS transistor M1 is connected to the input terminal of the fifth current source I7 and one end of the first resistor R1. The source of the second NMOS transistor M2 is connected to the input terminal of the sixth current source I8 and one end of the second resistor R2. The gate of the third NMOS transistor M3 is connected to the first inverting voltage input terminal V Leadare connected. The drain of the third NMOS transistor M3, the output terminal of the third current source I5, the drain of the seventh NMOS transistor M7, and the gate of the seventh NMOS transistor M7 are connected to the third output terminal V of the bias voltage generating circuit DN,0 are connected. The source of the third NMOS transistor M3 is connected to the input terminal of the seventh current source I9 and the other end of the first resistor R1. The gate of the fourth NMOS transistor M4 is connected to the second negative-phase voltage input terminal V Lag are connected. The drain of the fourth NMOS transistor M4, the output terminal of the fourth current source I6, the drain of the eighth NMOS transistor M8, and the gate of the eighth NMOS transistor M8 are connected to the fourth output terminal V of the bias voltage generating circuit DN,1 are connected. The source of the fourth NMOS transistor M4 is connected to the input terminal of the eighth current source I 10 and the other end of the second resistor R2. The sources of the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the eighth NMOS transistor M8 are connected to the ground. The first output terminal V of the bias voltage generating circuit UP,0 is connected to the 0 input terminal of the first multiplexer MUX2. The second output terminal V of the bias voltage generating circuit UP,1 is connected to the 1 input terminal of the first multiplexer MUX2. The output terminal of the first multiplexer MUX2 is connected to the control terminal of the first voltage-controlled current source VCCS1. The third output terminal V of the bias voltage generating circuit DN,0 is connected to the 0 input terminal of the second multiplexer MUX3. The fourth output terminal V of the bias voltage generating circuit DN,1 is connected to the 1 input terminal of the second multiplexer MUX3. The output terminal of the second multiplexer MUX3 is connected to the control terminal of the second voltage-controlled current source VCCS2. The input terminal of the first voltage-controlled current source VCCS1 is connected to the power supply. The output terminal of the first voltage-controlled current source VCCS1 is connected to one end of the first switch SW 11 The output terminal of the second voltage-controlled current source VCCS2 is connected to the ground. The input terminal of the second voltage-controlled current source VCCS2 is connected to one end of the second switch SW 12 The input terminals of the first current source I3, the second current source I4, the third current source I5, and the fourth current source I6 are connected to the power supply. The output terminals of the fifth current source I7, the sixth current source I8, the seventh current source I9, and the eighth current source I 10 are connected to the ground. The other end of the first switch SW 11 and the other end of the second switch SW 12 are connected to the current output terminal I CP,PLL The control terminal of the first switch SW 11 is connected to the pulse voltage input terminal PULSER and the input terminal of the inverter INV1. The control terminal of the second switch SW 12Its control terminal is connected to the output terminal of the inverter INV1;

[0060] The first vector output terminal It includes a plurality of sub-input terminals, wherein each sub-input terminal is connected to the control terminals of the first multiplexer MUX2 and the second multiplexer MUX3 in the corresponding voltage-controlled charge pump branch.

[0061] In the current mean transconductance amplifier, the first output voltage V of the bias voltage generating circuit UP,0 and the second output voltage V of the bias voltage generating circuit UP,1 are determined by the positive input voltage V CM The third output voltage V of the bias voltage generating circuit DN,0 and the fourth output voltage V of the bias voltage generating circuit DN,1 track in real time the changes with the first negative input voltage V Lead and the second negative input voltage V Lag When the first negative input voltage V Lead and the second negative input voltage V Lag are the same as the positive input voltage V CM no current flows through the first resistor R1 and the second resistor R2. At this time, the third output voltage V of the bias voltage generating circuit DN,0 is the same as the first output voltage V of the bias voltage generating circuit UP,0 The fourth output voltage V of the bias voltage generating circuit DN,1 is the same as the second output voltage V of the bias voltage generating circuit UP,1 The vector input signal Each sub-input signal of controls the first multiplexer MUX2 in the corresponding charge pump branch to select V UP,0 or V UP,1 The second multiplexer MUX3 selects V DN,0 or V DN,1 Current averaging is achieved through selection to realize real-time fractional frequency division. The output voltages of the two multiplexers respectively control the currents of the first voltage-controlled current source VCCS1 and the second voltage-controlled current source VCCS2. The current of the first voltage-controlled current source VCCS1 and the current of the second voltage-controlled current source VCCS2 are respectively controlled by the pulse control voltage PULSER and its reverse voltage to control the first switch SW 11 and the second switch SW 12 to output the current to the output current I CP,PLL .

[0062] Reference Figure 6 The frequency division and mean control signal generator includes a scalar output terminal N div The first vector output terminal The second vector output terminal A fractional ΔΣ modulator, an accumulator ACC1, a data weighted averaging module, a first adder ADD1, and a second adder ADD2. The first vector output terminal is a 64-element vector output terminal; the second vector output terminal is a 4-element vector output terminal; the scalar output terminal N div is a 3-bit wide digital output terminal; the frequency synthesis control word input terminal N+α is a 25-bit wide digital input terminal;

[0063] The input terminal of the fractional ΔΣ modulator is connected to the frequency synthesis control word input terminal N+α. The high 3-bit wide integer control word d inte output terminal of the 13-bit wide digital output terminal of the fractional ΔΣ modulator is connected to the 3-bit wide input terminal of the first adder ADD1. The low 10-bit wide of the 13-bit wide digital output terminal of the fractional ΔΣ modulator is the fractional control word. The high 4-bit wide of the 10-bit wide fractional control word of the fractional ΔΣ modulator is the most significant bit d frac,MSB of the fractional control word is connected to the input terminal of the accumulator ACC1. The low 6-bit wide of the 10-bit wide fractional control word of the fractional ΔΣ modulator is the least significant bit d frac,LSB of the fractional control word is connected to the input terminal of the data weighted averaging module. The 5-bit wide output terminal of the accumulator ACC1 is connected to the 5-bit wide input terminal of the second adder ADD2. The one-bit wide output terminal N ref of the data weighted averaging module is connected to the one-bit wide input terminal of the second adder ADD2. The highest bit of the 5-bit wide output terminal of the second adder ADD2 is connected to the one-bit wide input terminal of the first adder ADD1. The low 4-bit wide of the 5-bit wide output terminal of the second adder ADD2 is connected to the second vector output terminal ; the 3-bit wide output terminal of the first adder ADD1 is connected to the scalar output terminal N div ; the 64-bit wide output terminal of the data weighted averaging module is connected to the first vector output terminal .

[0064] Reference Figure 7 , the frequency discrimination branch includes a multi-mode frequency divider, a current output terminal I CP,FLL , a single-phase clock output terminal CLK digital , a frequency discrimination and phase discrimination detector with dead zone, and a charge pump;

[0065] The reference clock input terminal Φ ref is connected to the first input terminal of the frequency discrimination and phase discrimination detector with dead zone. The second phase signal output terminal Φ Lag of the sampling phase generator is connected to the input terminal of the multi-mode frequency divider. The scalar output terminal N div of the frequency division and mean control signal generator is connected to the frequency division control terminal of the multi-mode frequency divider. The first output terminal Φ fdivIt is connected to the second input terminal of the frequency discriminator and phase detector with dead zone. The second output terminal of the multi-mode frequency divider is connected to the single-phase clock output terminal CLK digital It is connected. The first output terminal UP and the second output terminal DN of the frequency discriminator and phase detector with dead zone are respectively connected to the first input terminal and the second input terminal of the charge pump. The output terminal of the charge pump serves as the current output terminal I CP,FLL .

[0066] When the phase difference between the two input clock signals Φ ref and Φ fdiv of the frequency discriminator and phase detector with dead zone is greater than the dead zone range, the frequency discriminator and phase detector with dead zone is in the frequency discrimination and phase detection state. The two output terminals of the frequency discriminator and phase detector with dead zone control the charge pump to charge / discharge the low-pass filter, realizing the frequency locking of the phase-locked loop; when the phase difference between the two input clock signals Φ ref and Φ fdiv of the frequency discriminator and phase detector with dead zone is less than the dead zone range, the frequency discriminator and phase detector with dead zone stops working. The two output terminals of the frequency discriminator and phase detector with dead zone maintain a logical low level, turning off the charge pump, and the phase-locked loop is controlled by the phase discrimination branch to complete phase locking.

[0067] Reference Figure 8 , the multi-mode frequency divider includes the first output terminal Φ fdiv of the multi-mode frequency divider, the first control terminal N div [0], the second control terminal N div [1], the third control terminal N div [2], the first divide-by-2 / 3 frequency divider DIV1, the second divide-by-2 / 3 frequency divider DIV2 and the third divide-by-2 / 3 frequency divider DIV3;

[0068] The second phase signal output terminal Φ Lag of the sampling phase generator is connected to the first input terminal of the first divide-by-2 / 3 frequency divider DIV1. The first control terminal N div [0] is connected to the second input terminal of the first divide-by-2 / 3 frequency divider DIV1. The first output terminal of the first divide-by-2 / 3 frequency divider DIV1 is connected to the first input terminal of the second divide-by-2 / 3 frequency divider DIV2. The second output terminal of the first divide-by-2 / 3 frequency divider DIV1 is connected to the first output terminal Φ fdiv of the multi-mode frequency divider;

[0069] The second control terminal N div [1] is connected to the second input terminal of the second divide-by-2 / 3 frequency divider DIV2. The first output terminal of the second divide-by-2 / 3 frequency divider DIV2 is connected to the first input terminal of the third divide-by-2 / 3 frequency divider DIV3. The second output terminal of the second divide-by-2 / 3 frequency divider DIV2 is connected to the third input terminal of the first divide-by-2 / 3 frequency divider DIV1 and the second single-phase clock output terminal CLK digitalconnected;

[0070] Third control terminal N div [2] is connected to the second input terminal of the third 2 / 3 frequency divider DIV3. The third input terminal of the third 2 / 3 frequency divider DIV2 is connected to the high-level signal terminal. The second output terminal of the third 2 / 3 frequency divider DIV2 is connected to the third input terminal of the second 2 / 3 frequency divider DIV2;

[0071] Through the first control terminal N div [0], the second control terminal N div [1], the third control terminal N div [2] for control, the input signal Φ Lag is frequency-divided to generate the feedback signal Φ fdiv of the phase-locked loop and the clock signal CLK digital in the digital circuit of the present invention, and the frequency division ratio DivN of the multi-mode frequency divider is related to the first control terminal N div [0], the second control terminal N div [1], the third control terminal N div [2] The corresponding relationship of the output control signal is shown in the following formula:

[0072] DivN = N div [0] × 2 0 + N div [1] × 2 1 + N div [2] × 2 2

[0073] Reference Figure 9 The frequency discriminator and phase discriminator with dead zone includes a first D flip-flop DFF6, a second D flip-flop DFF7, a third D flip-flop DFF8, a fourth D flip-flop DFF9, a first delay module Delay7, a second delay module Delay8, a third delay module Delay9 and an AND gate AND1;

[0074] The reference clock input terminal Φ ref is connected to the clock input terminal of the first D flip-flop DFF6 and the input terminal of the first delay module Delay7. The data input terminal of the first D flip-flop DFF6 is connected to the high-level signal terminal. The output terminal of the first D flip-flop DFF6 is connected to the data input terminal of the third D flip-flop DFF8 and the first input terminal of the AND gate AND1. The output terminal of the first delay module Delay7 is connected to the clock input terminal of the third D flip-flop DFF8;

[0075] The first output terminal Φ fdivIt is connected to the clock input terminal of the second D flip-flop DFF7 and the input terminal of the third delay module Delay9. The data input terminal of the second D flip-flop DFF7 is connected to the high-level signal terminal. The output terminal of the second D flip-flop DFF7 is connected to the data input terminal of the fourth D flip-flop DFF9 and the second input terminal of the AND gate AND1. The output terminal of the third delay module Delay9 is connected to the clock input terminal of the fourth D flip-flop DFF9;

[0076] The output terminal of the AND gate AND1 is connected to the input terminal of the second delay module Delay8. The output terminal of the second delay module Delay8 is connected to the clear terminals of the first D flip-flop DFF6 and the second D flip-flop DFF7;

[0077] The clock Φ of the first D flip-flop DFF6 ref and the clock signal Φ of the second D flip-flop DFF7 fdiv First, sample the high level. The output signals of both are applied to the clear terminals of the first D flip-flop DFF6 and the second D flip-flop DFF7 through the AND gate and the delay unit. The delayed clock samples the output signals of the first D flip-flop DFF6 and the second D flip-flop DFF7 in the third D flip-flop DFF8 and the fourth D flip-flop DFF9. When Φ ref is ahead of Φ fdiv by a time greater than the delay times of the first delay module Delay7 and the third delay module Delay9, the output UP signal is at a high level, the charge pump charging branch is turned on, and the frequency discrimination branch starts to work to charge the low-pass loop filter; when Φ ref is ahead of Φ fdiv by a time less than the delay times of the first delay module Delay7 and the third delay module Delay9, the output UP signal is at a low level, the charge pump is turned off, and the frequency discrimination branch stops working. Similarly, when Φ ref lags behind Φ fdiv by a time greater than the delay times of the first delay module Delay7 and the third delay module Delay9, the output DN signal is at a high level, the charge pump discharging branch is turned on, and the frequency discrimination branch starts to work to discharge the low-pass loop filter; when Φ ref is ahead of Φ fdiv by a time less than the delay times of the first delay module Delay7 and the third delay module Delay9, the output DN signal is at a low level, the charge pump is turned off, and the frequency discrimination branch stops working.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: it is still possible to modify the specific implementation manners of the present invention or make equivalent replacements, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A fractional-N sub-sampling frequency synthesizer based on the average current, characterized in that including a reference clock input terminal (Φ ref ), a first reference voltage input terminal (V Ref1 ), a second reference voltage input terminal (V Ref2 ), a common-mode voltage input terminal (V CM ), a frequency synthesis control word input terminal (N + α), a microwave signal output terminal (Φ PLL,mmW ), a radio frequency signal output terminal (Φ PLL,RF ), a two-phase sub-sampling phase-voltage converter, a current mean transconductance amplifier, a low-pass loop filter, a voltage-controlled oscillator, a differential-single-ended buffer, a ÷2 frequency divider, a single-ended buffer, a sampling phase generator, a frequency division and mean control signal generator, and a frequency discrimination branch; The first phase signal input terminal of the dual-phase sub-sampling phase-voltage converter is connected to the reference clock input terminal (Φ ref ), the first voltage input terminal and the second voltage input terminal of the dual-phase sub-sampling phase-voltage converter are connected to the first reference voltage input terminal (V Ref1 ) and the second reference voltage input terminal (V Ref2 ), the first voltage signal output terminal (V Lead ) and the second voltage signal output terminal (V Lag ) of the dual-phase sub-sampling phase-voltage converter are respectively connected to the first inverting input terminal and the second inverting input terminal of the current averaging transconductance amplifier, the clock pulse output terminal (PULSER) of the dual-phase sub-sampling phase-voltage converter is connected to the scalar control terminal of the current averaging transconductance amplifier, the non-inverting input terminal of the current averaging transconductance amplifier is connected to the common-mode voltage input terminal (V CM ), the current output terminal (I CP,PLL ) of the current averaging transconductance amplifier is connected to the input terminal (I CP ) of the low-pass loop filter and the current output terminal (I CP,FLL ) of the frequency discrimination branch, the output terminal (V C ) of the low-pass loop filter is connected to the input terminal of the voltage-controlled oscillator, the differential output terminal of the voltage-controlled oscillator is connected to the differential input terminals of the differential-single-ended buffer (BUF1), the differential input terminals of the ÷2 frequency divider and the differential input terminals of the sampling phase generator, the first phase signal output terminal (Φ Lead ) and the second phase signal output terminal (Φ Lag ) of the sampling phase generator are respectively connected to the second phase signal input terminal and the third phase signal input terminal of the dual-phase sub-sampling phase-voltage converter, the second phase signal output terminal (Φ Lag ) of the sampling phase generator is connected to the first phase signal input terminal of the frequency discrimination branch, the second phase signal input terminal of the frequency discrimination branch is connected to the reference clock input terminal (Φ ref ), the input terminal of the frequency division and averaging control signal generator is connected to the frequency synthesis control word input terminal (N+α), the single-phase clock input terminal of the frequency division and averaging control signal generator is connected to the single-phase clock output terminal (CLK digital ) of the frequency discrimination branch, the first vector output terminal of the frequency division and averaging control signal generator is connected to the vector control terminal of the current averaging transconductance amplifier, the second vector output terminal of the frequency division and averaging control signal generator is connected to the vector control terminal of the sampling phase generator, the scalar output terminal (N div ) of the frequency division and averaging control signal generator is connected to the scalar control terminal of the frequency discrimination branch, the output terminal of the differential-single-ended buffer is connected to the microwave signal output terminal (Φ PLL,mmW ) are connected. The output end of the ÷2 frequency divider is connected to the input end of the single-ended buffer (BUF2), and the output end of the single-ended buffer (BUF2) is connected to the radio frequency signal output end (Φ PLL,RF ).

2. The fractional-N sub-sampling frequency synthesizer based on the average current according to claim 1, wherein The dual-phase sub-sampling phase-voltage converter includes a first voltage signal output terminal (V Lead ), a second voltage signal output terminal (V Lag ), a clock pulse output terminal (PULSER), a sampling and control clock generator, a dual-phase linear ramp generator, and a dual-phase sub-sampling phase detector; Reference clock input terminal (Φ ref ) is connected to the sampling and control clock generator, the pulse signal output terminal (PULSER) is connected to the sampling and control clock generator, the first phase signal output terminal (Φ Lead ) and the second phase signal output terminal (Φ Lag ) of the sampling phase generator are connected to the dual-phase linear ramp generator, the dual-phase linear ramp generator is connected to the dual-phase sub-sampling phase detector, and the dual-phase sub-sampling phase detector is connected to the first reference voltage input terminal (V Ref1 ), the second reference voltage input terminal (V Ref2 ), the first voltage signal output terminal (V Lead ) and the second voltage signal output terminal (V Lag ).

3. The fractional-N sub-sampling frequency synthesizer based on the average current according to claim 2, wherein The dual-phase linear ramp generator includes a frequency discriminator and phase detector, a first switch (SW1), a second switch (SW2), a first current source (I1), and a second current source (I2); the dual-phase subsampling phase detector includes a third switch (SW3), a fourth switch (SW4), a fifth switch (SW5), a sixth switch (SW6), a seventh switch (SW7), an eighth switch (SW8), a ninth switch (SW9), a tenth switch (SW 10 ), a first capacitor (C1), and a second capacitor (C2); The first phase signal output terminal (Φ Lead ) and the second phase signal output terminal (Φ Lag ) of the sampling phase generator are respectively connected to the first input terminal and the second input terminal of the frequency discriminator and phase detector. The first output terminal of the frequency discriminator and phase detector is connected to the control terminal of the first switch (SW1). The second output terminal of the frequency discriminator and phase detector is connected to the control terminal of the second switch (SW2). One end of the first switch (SW1) is connected to the output terminal of the first current source (I1) and one end of the third switch (SW3). The other end of the first switch (SW1) and one end of the second switch (SW2) are grounded. The other end of the second switch (SW2) is connected to the output terminal of the second current source (I2) and one end of the fourth switch (SW4). The first current source (I1) and the second current source (I2) are connected to an external power supply. The other end of the third switch (SW3), one end of the first capacitor (C1) and one end of the seventh switch (SW7) are connected to one end of the ninth switch (SW9). The other end of the fourth switch (SW4), one end of the second capacitor (C2) and one end of the eighth switch (SW8) are connected to one end of the tenth switch (SW 10 ). The control terminals of the third switch (SW3) and the fourth switch (SW4) are connected to the second output terminal (Φ2) of the sampling and control clock generator. The other end of the first capacitor (C1) and one end of the fifth switch (SW5) are connected to the first voltage signal output terminal (V Lead ) of the dual-phase sub-sampling phase-voltage converter. The other end of the second capacitor (C2) and one end of the sixth switch (SW6) are connected to the second voltage signal output terminal (V Lag ) of the dual-phase sub-sampling phase-voltage converter. The other ends of the fifth switch (SW5) and the sixth switch (SW6) are connected to the first reference voltage input terminal (V Ref1 ). The control terminals of the fifth switch (SW5) and the sixth switch (SW6) are connected to the first output terminal (Φ1) of the sampling and control clock generator. The other ends of the seventh switch (SW7) and the eighth switch (SW8) are connected to the second reference voltage input terminal (V Ref2 ). The control terminals of the seventh switch (SW7) and the eighth switch (SW8) are connected to the third output terminal (Φ3) of the sampling and control clock generator. The other end of the ninth switch (SW9) and the other end of the tenth switch (SW 10 ) are grounded. The control terminals of the ninth switch (SW9) and the tenth switch (SW 10 ) are connected to the fourth output terminal (Φ4) of the sampling and control clock generator. The fifth output terminal of the sampling and control clock generator is connected to the clock pulse output terminal (PULSER).

4. The fractional division sub-sampling frequency synthesizer based on the average current according to claim 3, wherein The sampling and control clock generator includes a first output terminal (Φ1), a second output terminal (Φ2), a third output terminal (Φ3), a fourth output terminal (Φ4), a clock pulse output terminal (PULSER), a first D flip-flop (DFF1), a second D flip-flop (DFF2), a third D flip-flop (DFF3), a fourth D flip-flop (DFF4), a fifth D flip-flop (DFF5), a first delay module (Delay1), a second delay module (Delay2), a third delay module (Delay3), a fourth delay module (Delay4), a fifth delay module (Delay5), and a sixth delay module (Delay6); The input end of the first delay module (Delay1) is connected to the reference clock input end (Φ ref ), the output end of the first delay module (Delay1) is connected to the clock input end of the first D flip-flop (DFF1), the data input end of the first D flip-flop (DFF1) is connected to the external high-level signal end, and the output end of the first D flip-flop (DFF1) is connected to the input end and the first output end (Φ1) of the second delay module (Delay2); The output terminal of the second delay module (Delay2) is connected to the clock input terminal of the second D flip-flop (DFF2). The data input terminal of the second D flip-flop (DFF2) is connected to an external high-level signal terminal. The output terminal of the second D flip-flop (DFF2) is connected to the input terminal of the third delay module (Delay3) and the second output terminal (Φ2); The output terminal of the third delay module (Delay3) is connected to the clock input terminal of the third D flip-flop (DFF3). The data input terminal of the third D flip-flop (DFF3) is connected to an external high-level signal terminal. The output terminal of the third D flip-flop (DFF3) is connected to the input terminal of the fourth delay module (Delay4) and the third output terminal (Φ3); The output terminal of the fourth delay module (Delay4) is connected to the clock input terminal of the fourth D flip-flop (DFF4). The data input terminal of the fourth D flip-flop (DFF4) is connected to an external high-level signal terminal. The output terminal of the fourth D flip-flop (DFF4) is connected to the input terminal of the fifth delay module (Delay5) and the clock pulse output terminal (PULSER); The output terminal of the fifth delay module (Delay5) is connected to the clock input terminal of the fifth D flip-flop (DFF5). The data input terminal of the fifth D flip-flop (DFF5) is connected to an external high-level signal terminal. The output terminal of the fifth D flip-flop (DFF5) is connected to the input terminal of the sixth delay module (Delay6) and the fourth output terminal (Φ4); The output terminal of the sixth delay module (Delay6) is respectively connected to the clear terminals of the first D flip-flop (DFF1), the second D flip-flop (DFF2), the third D flip-flop (DFF3), the fourth D flip-flop (DFF4), and the fifth D flip-flop (DFF5).

5. The fractional division sub-sampling frequency synthesizer based on the average current according to claim 1, characterized in that The sampling phase generator includes a first differential signal input terminal (Φ VCO+ ), a second differential signal input terminal (Φ VCO -), a first phase signal output terminal (Φ L ead), a second phase signal output terminal (Φ L ag), a first quadrature ÷2 frequency divider (QDIV1), a second quadrature ÷2 frequency divider (QDIV2), a third quadrature ÷2 frequency divider (QDIV3), a fourth quadrature ÷2 frequency divider (QDIV4), a fifth quadrature ÷2 frequency divider (QDIV5), a sixth quadrature ÷2 frequency divider (QDIV6), a seventh quadrature ÷2 frequency divider (QDIV7), a multiplexer (MUX1) and a dual-phase synchronizer; The differential output terminal of the voltage-controlled oscillator is connected to the differential input terminals of the first quadrature ÷2 frequency divider (QDIV1) via the first differential input terminal (Φ VCO+ ) and the second differential input terminal (Φ VCO -), the first output terminal (Φ 1,1 ) and the second output terminal (Φ 1,3 ) of the first quadrature ÷2 frequency divider (QDIV1) are respectively connected to the differential input terminals of the second quadrature ÷2 frequency divider (QDIV2), the third output terminal (Φ 1,2 ) and the fourth output terminal (Φ 1,4 ) of the first quadrature ÷2 frequency divider (QDIV1) are respectively connected to the differential input terminals of the third quadrature ÷2 frequency divider (QDIV3), the first output terminal (Φ 2,1 ) and the second output terminal (Φ 2,5 ) of the second quadrature ÷2 frequency divider (QDIV2) are respectively connected to the differential input terminals of the fourth quadrature ÷2 frequency divider (QDIV4), the third output terminal (Φ 2,3 ) and the fourth output terminal (Φ 2,7 ) of the second quadrature ÷2 frequency divider (QDIV2) are respectively connected to the differential input terminals of the fifth quadrature ÷2 frequency divider (QDIV5), the first output terminal (Φ 2,2 ) and the second output terminal (Φ 2,6 ) of the third quadrature ÷2 frequency divider (QDIV3) are respectively connected to the differential input terminals of the sixth quadrature ÷2 frequency divider (QDIV6), the third output terminal (Φ 2,4 ) and the fourth output terminal (Φ 2,8 ) of the third quadrature ÷2 frequency divider (QDIV3) are respectively connected to the differential input terminals of the seventh quadrature ÷2 frequency divider (QDIV7), the first output terminal (Φ 3,1 ), the second output terminal (Φ 3,9 ), the third output terminal (Φ 3,5 ) and the fourth output terminal (Φ 3,13 ) of the fourth quadrature ÷2 frequency divider (QDIV4) are respectively connected to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal of the multiplexer (MUX1), the first output terminal (Φ 3,3 ), the second output terminal (Φ 3,11 ), the third output terminal (Φ 3,7 ) and the fourth output terminal (Φ 3,15 ) of the fifth quadrature ÷2 frequency divider (QDIV5) are respectively connected to the fifth input terminal, the sixth input terminal, the seventh input terminal and the eighth input terminal of the multiplexer (MUX1), the first output terminal (Φ 3,2 ), the second output terminal (Φ 3,10 ), the third output terminal (Φ 3,6 ) and the fourth output terminal (Φ 3,14 ) are respectively connected to the ninth input terminal, the tenth input terminal, the eleventh input terminal and the twelfth input terminal of the multiplexer (MUX1). The first output terminal (Φ 3,4 ), the second output terminal (Φ 3,12 ), the third output terminal (Φ3, 8) and the fourth output terminal (Φ 3,16 ) of the seventh quadrature ÷2 frequency divider (QDIV7) are respectively connected to the thirteenth input terminal, the fourteenth input terminal, the fifteenth input terminal and the sixteenth input terminal of the multiplexer (MUX1). The vector control terminal of the multiplexer (MUX1) is connected to the second vector uuur of the frequency division and mean value control signal generator Output terminal (N PS ) is connected, the first output terminal (Φ opt,1 ) and the second output terminal (Φ opt,2 ) of the multiplexer (MUX1) are respectively connected to the first single-ended input terminal and the second single-ended input terminal of the dual-phase synchronizer, the first differential input terminal and the second differential input terminal of the dual-phase synchronizer are respectively connected to the first differential signal input terminal (Φ VCO+ ) and the second differential signal input terminal (Φ VCO- ) are connected, and the control terminal of the dual-phase synchronizer is connected to the second uuur of the frequency division and mean control signal generator Vector output terminal (N PS )'s first bit (N PS,0 ) are connected. The first output terminal and the second output terminal of the dual-phase synchronizer are respectively connected to the first phase signal output terminal (Φ Lead ) and the second phase signal output terminal (Φ Lag ).

6. The fractional-N sub-sampling frequency synthesizer based on the average current according to claim 1, wherein The current mean transconductance amplifier includes a non-inverting voltage input terminal (V CM ), a current output terminal (I CP,PLL ), a first current source (I3), a second current source (I4), a third current source (I5), a fourth current source (I6), a fifth current source (I7), a sixth current source (I8), a seventh current source (I9), an eighth current source (I 10 ), a first NMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a fourth NMOS transistor (M4), a first resistor (R1), a second resistor (R2), a fifth NMOS transistor (M5), a sixth NMOS transistor (M6), a seventh NMOS transistor (M7), an eighth NMOS transistor (M8), and a 64-branch voltage-controlled charge pump array; The fifth NMOS transistor (M5), the sixth NMOS transistor (M6), the seventh NMOS transistor (M7), and the eighth NMOS transistor (M8) form a bias voltage generation circuit. The voltage-controlled charge pump array includes a plurality of branches, and each branch includes a first multiplexer (MUX2), a second multiplexer (MUX3), an inverter (INV1), a first voltage-controlled current source (VCCS1), a second voltage-controlled current source (VCCS2), a first switch (SW 11 ), and a second switch (SW 12 ); The gates of the first NMOS transistor (M1) and the second NMOS transistor (M2) are connected to the positive-phase voltage input terminal (V CM ). The drain of the first NMOS transistor (M1), the output terminal of the first current source (I3), the drain of the fifth NMOS transistor (M5), and the gate of the fifth NMOS transistor (M5) are connected to the first output terminal (V UP,0 ) of the bias voltage generating circuit. The drain of the second NMOS transistor (M2), the output terminal of the second current source (I4), the drain of the sixth NMOS transistor (M6), and the gate of the sixth NMOS transistor (M6) are connected to the second output terminal (V UP,1 ) of the bias voltage generating circuit. The source of the first NMOS transistor (M1) is connected to the input terminal of the fifth current source (I7) and one end of the first resistor (R1). The source of the second NMOS transistor (M2) is connected to the input terminal of the sixth current source (I8) and one end of the second resistor (R2). The gate of the third NMOS transistor (M3) is connected to the first negative-phase voltage input terminal (V Lead ). The drain of the third NMOS transistor (M3), the output terminal of the third current source (I5), the drain of the seventh NMOS transistor (M7), and the gate of the seventh NMOS transistor (M7) are connected to the third output terminal (V DN,0 ) of the bias voltage generating circuit. The source of the third NMOS transistor (M3) is connected to the input terminal of the seventh current source (I9) and the other end of the first resistor (R1). The gate of the fourth NMOS transistor (M4) is connected to the second negative-phase voltage input terminal (V Lag ). The drain of the fourth NMOS transistor (M4), the output terminal of the fourth current source (I6), the drain of the eighth NMOS transistor (M8), and the gate of the eighth NMOS transistor (M8) are connected to the fourth output terminal (V DN,1 ) of the bias voltage generating circuit. The source of the fourth NMOS transistor (M4) is connected to the input terminal of the eighth current source (I 10 ) and the other end of the second resistor (R2). The sources of the fifth NMOS transistor (M5), the sixth NMOS transistor (M6), the seventh NMOS transistor (M7), and the eighth NMOS transistor (M8) are connected to the ground. The first output terminal (V UP,0 ) of the bias voltage generating circuit is connected to the 0 input terminal of the first multiplexer (MUX2). The second output terminal (V UP,1 ) of the bias voltage generating circuit is connected to the 1 input terminal of the first multiplexer (MUX2). The output terminal of the first multiplexer (MUX2) is connected to the control terminal of the first voltage-controlled current source (VCCS1). The third output terminal (V DN,0 ) of the bias voltage generating circuit is connected to the 0 input terminal of the second multiplexer (MUX3). The fourth output terminal (V DN,1 ) is connected to the 1 input terminal of the second multiplexer (MUX3), the output terminal of the second multiplexer (MUX3) is connected to the control terminal of the second voltage-controlled current source (VCCS2), the input terminal of the first voltage-controlled current source (VCCS1) is connected to the power supply, and the output terminal of the first voltage-controlled current source (VCCS1) is connected to one end of the first switch (SW 11 ). One end of the second voltage-controlled current source (VCCS2) is connected to the ground, and the input terminal of the second voltage-controlled current source (VCCS2) is connected to one end of the second switch (SW 12 ). The input terminals of the first current source (I3), the second current source (I4), the third current source (I5), and the fourth current source (I6) are connected to the power supply, and the output terminals of the fifth current source (I7), the sixth current source (I8), the seventh current source (I9), and the eighth current source (I 10 ) are connected to the ground. The other end of the first switch (SW 11 ) and the other end of the second switch (SW 12 ) are connected to the current output terminal (I CP,PLL ). The control terminal of the first switch (SW 11 ) is connected to the pulse voltage input terminal (PULSER) and the input terminal of the inverter (INV1), and the control terminal of the second switch (SW 12 ) is connected to the output terminal of the inverter (INV1); The first vector output terminal comprises a plurality of sub-input terminals, wherein each sub-input terminal is connected to the control terminals of a first multiplexer (MUX2) and a second multiplexer (MUX3) in a corresponding voltage-controlled charge pump branch.

7. The fractional-N sub-sampling frequency synthesizer based on the average current according to claim 1, wherein The frequency division and mean control signal generator includes a scalar output terminal (N div ), a first vector output terminal a second vector output terminal a fractional ΔΣ modulator, an accumulator (ACC1), a data weight mean module, a first adder (ADD1), and a second adder (ADD2); The input end of the fractional ΔΣ modulator is connected to the input end of the frequency synthesis control word (N + α). The high 3-bit integer control word (d inte ) output end of the 13-bit digital output end of the fractional ΔΣ modulator is connected to the 3-bit input end of the first adder (ADD1). The low 10 bits of the 13-bit digital output end of the fractional ΔΣ modulator are the fractional control word. The high 4 bits of the 10-bit fractional control word of the fractional ΔΣ modulator are the most significant bits of the fractional control word (d frac,MSB ) and are connected to the input end of the accumulator (ACC1). The low 6 bits of the 10-bit fractional control word of the fractional ΔΣ modulator are the least significant bits of the fractional control word (d frac,LSB ) and are connected to the input end of the data weighted average module. The 5-bit output end of the accumulator (ACC1) is connected to the 5-bit input end of the second adder (ADD2). The 1-bit output end of the data weighted average module (N ref ) is connected to the 1-bit input end of the second adder (ADD2). The highest bit of the 5-bit output end of the second adder (ADD2) is connected to the 1-bit input end of the first adder (ADD1). The low 4 bits of the 5-bit output end of the second adder (ADD2) are connected to the second vector output end . The 3-bit output end of the first adder (ADD1) is connected to the scalar output end (N div ). The 64-bit output end of the data weighted average module is connected to the first vector output end .

8. The fractional division sub-sampling frequency synthesizer based on the average current according to claim 7, characterized in that The first vector output terminal is a 64-cell vector output terminal; the second vector output terminal is a 4-cell vector output terminal; the scalar output terminal (N div ) is a 3-bit digital output terminal; the frequency synthesis control word input terminal (N + α) is a 25-bit digital input terminal.

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