High-frequency circuits and communication devices

Abstract

In the case of supporting APT and ET modes, the power supply voltage supplied to the power amplifier in APT mode is stabilized. The high-frequency circuit (100) includes a power amplifier (111), a control circuit (controller (107)), an on / off switch (108), a connection terminal (85), and a mounting plate. The power amplifier (111) can support both APT and ET modes. The control circuit controls the power amplifier (111) via APT and ET modes. The on / off switch (108) is connected in series with a capacitor element (320), which is connected between the path (R2) and ground. The connection terminal (85) is connected to the capacitor element (320). When viewed from the thickness direction of the mounting plate, the control circuit overlaps with the connection terminal (85).

Description

Technical Field

[0001] This invention generally relates to a high-frequency circuit and a communication device, and more specifically, to a high-frequency circuit having a power amplifier and a communication device having a high-frequency circuit. Background Technology

[0002] Patent Document 1 describes a power amplifier system (high-frequency circuit) comprising an envelope tracker, first to third power amplifiers, and first to third switched capacitors. In the power amplifier system described in Patent Document 1, the capacitive load on the envelope tracker can be reduced by enabling one of the first to third power amplifiers and disabling the remaining two power amplifiers, thereby improving the efficiency of the power amplifier system.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Publication No. 2014-502808 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] If it is a power amplifier system as described in Patent Document 1, then in order to support both average power tracking and envelope tracking modes, the power supply voltage supplied to the power amplifier in the average power tracking mode may be unstable.

[0008] The purpose of this invention is to provide a high-frequency circuit and communication device that can stabilize the power supply voltage supplied to the power amplifier in the average power tracking mode, while supporting both average power tracking and envelope tracking modes.

[0009] Solutions for solving problems

[0010] One embodiment of the present invention relates to a high-frequency circuit comprising a power amplifier, a control circuit, an on / off switch, connection terminals, and a mounting substrate. The power amplifier has a power supply terminal and supports both average power tracking (APTS) and envelope tracking (AST) modes. The control circuit is connected to the power supply terminal and controls the power amplifier using the ATS and AST modes. The on / off switch is connected in series with a capacitor element, which is connected between the path between the control circuit and the power supply terminal and ground. The connection terminals are connected to the capacitor element. The mounting substrate has a first main surface and a second main surface facing each other. When viewed from the thickness direction of the mounting substrate, the control circuit and the connection terminals overlap.

[0011] One embodiment of the present invention relates to a communication device comprising the aforementioned high-frequency circuit and signal processing circuit. The signal processing circuit is connected to the high-frequency circuit and processes the high-frequency signal.

[0012] The effects of the invention

[0013] According to the above-described high-frequency circuit and communication device of the present invention, when supporting both average power tracking and envelope tracking modes, the power supply voltage supplied to the power amplifier in the average power tracking mode can be stabilized. Attached Figure Description

[0014] Figure 1 This is a circuit structure diagram of the high-frequency circuit and communication device involved in Embodiment 1.

[0015] Figure 2 This is a top view of the aforementioned high-frequency circuit.

[0016] Figure 3 yes Figure 2 A1-A1 cross-sectional view.

[0017] Figure 4 This is a cross-sectional view of the high-frequency circuit involved in Variation 1 of Embodiment 1.

[0018] Figure 5 This is a cross-sectional view of the high-frequency circuit involved in Variation 2 of Embodiment 1.

[0019] Figure 6 This is a cross-sectional view of the high-frequency circuit involved in Variation 3 of Embodiment 1.

[0020] Figure 7 This is a circuit structure diagram of the main part of the high-frequency circuit involved in Implementation Method 2.

[0021] Figure 8 This is a cross-sectional view of the aforementioned high-frequency circuit. Detailed Implementation

[0022] Referring to the following implementation methods 1, 2, etc. Figures 2-6 as well as Figure 8 All diagrams are schematic and the size and thickness ratios of the constituent elements in the diagrams may not reflect the actual size ratios.

[0023] Furthermore, in this disclosure, "any constituent element disposed on the first main surface side of the mounting substrate" means that the aforementioned constituent element is disposed on a mounting substrate having a first main surface and a second main surface facing each other, at a position closer to the first main surface than the second main surface of the mounting substrate. Examples of "any constituent element disposed on the first main surface side of the mounting substrate" include cases where the aforementioned constituent element is disposed on the first main surface of the mounting substrate and cases where the aforementioned constituent element is disposed at a position separate from the first main surface of the mounting substrate. Examples of "the aforementioned constituent element disposed on the first main surface of the mounting substrate" include cases where the aforementioned constituent element is mounted on the first main surface of the mounting substrate and cases where a portion of the aforementioned constituent element is mounted on the first main surface of the mounting substrate and the remaining portion of the aforementioned constituent element is mounted within the mounting substrate. Examples of "the aforementioned constituent element being disposed at a position separate from the first main surface of the mounting substrate" include cases where the aforementioned constituent element is stacked with other constituent elements. In this case, other constituent elements are mounted on the first main surface of the mounting substrate, and the aforementioned constituent element is stacked on top of these other constituent elements. Alternatively, other constituent elements may also exist between the aforementioned constituent element and other constituent elements.

[0024] Similarly, in this disclosure, "any constituent element disposed on the second main surface of the mounting substrate" means that the constituent element is disposed on the mounting substrate having a first main surface and a second main surface facing each other, at a position closer to the second main surface than the first main surface of the mounting substrate. Examples of "any constituent element disposed on the second main surface of the mounting substrate" include cases where the constituent element is disposed on the second main surface of the mounting substrate and cases where the constituent element is disposed at a position separate from the second main surface of the mounting substrate. Examples of "the constituent element disposed on the second main surface of the mounting substrate" include cases where the constituent element is mounted on the second main surface of the mounting substrate and cases where a portion of the constituent element is mounted on the second main surface of the mounting substrate and the remaining portion of the constituent element is mounted within the mounting substrate. Examples of "the constituent element disposed at a position separate from the second main surface of the mounting substrate" include cases where the constituent element is stacked with other constituent elements. In this case, other constituent elements are mounted on the second main surface of the mounting substrate, and the constituent element is stacked on top of these other constituent elements. Alternatively, other constituent elements may also exist between the constituent element and other constituent elements.

[0025] (Implementation Method 1)

[0026] like Figure 1 As shown, the high-frequency circuit 100 according to Embodiment 1 includes a power amplifier 111, a controller (control circuit) 107, an on / off switch 108, a connection terminal 85, and a mounting substrate 9 (see reference). Figure 2The power amplifier 111 has a power supply terminal 1111 and supports Average Power Tracking (APT) and Envelope Tracking (ET) modes. The controller 107 is connected to the power supply terminal 1111 and controls the power amplifier 111 using both APT and ET modes. An on / off switch 108 is connected in series with a capacitor element 320, which is connected between the path R2 between the controller 107 and the power supply terminal 1111 and ground. Here, "the capacitor element is connected between the path between the controller and the power supply terminal and ground" means that the capacitor element is electrically connected to both the path and ground. A connection terminal 85 is connected to the capacitor element 320. The mounting substrate 9 has a first main surface 91 and a second main surface facing each other. In the thickness direction D1 of the mounting substrate 9 (refer to...),... Figure 3 When viewed from above, the control circuit 107 overlaps with the connection terminal 85. Therefore, the high-frequency circuit 100 according to Embodiment 1 can stabilize the power supply voltage supplied to the power amplifier 111 in average power tracking mode while supporting both average power tracking and envelope tracking modes. Furthermore, it can be designed to shorten the wiring length between the control circuit 107 and the connection terminal 85.

[0027] Below, refer to Figures 1-6 To illustrate the high-frequency circuit 100 and communication device 300 involved in Embodiment 1.

[0028] (1) High-frequency circuits and communication devices

[0029] (1.1) Circuit structure of high-frequency circuits and communication devices

[0030] First, refer to Figure 1 The circuit structure of the high-frequency circuit 100 and the communication device 300 involved in Embodiment 1 will be explained.

[0031] The high-frequency circuit 100 involved in Embodiment 1 is used, for example, in a communication device 300. The communication device 300 is, for example, a portable telephone (e.g., a smartphone), but is not limited thereto; it could also be a wearable terminal (e.g., a smartwatch). The high-frequency circuit 100 is, for example, a module capable of supporting 4G (fourth-generation mobile communication) and 5G (fifth-generation mobile communication) standards. The 4G standard is, for example, the 3GPP LTE (Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio). The high-frequency circuit 100 is a module capable of supporting carrier aggregation and dual connectivity.

[0032] The high-frequency circuit 100 is configured, for example, to amplify the transmitted signal (high-frequency signal) input from the signal processing circuit 301 and output it to the antenna 310. Additionally, the high-frequency circuit 100 is configured to amplify the received signal (high-frequency signal) input from the antenna 310 and output it to the signal processing circuit 301. The signal processing circuit 301 is not a component of the high-frequency circuit 100, but rather a component of the communication device 300 incorporating the high-frequency circuit 100. The high-frequency circuit 100 is controlled, for example, by the signal processing circuit 301 in the communication device 300. The communication device 300 includes the high-frequency circuit 100 and the signal processing circuit 301. The communication device 300 also includes the antenna 310. The communication device 300 further includes a capacitor element 320 and a circuit board 13 on which the high-frequency circuit 100 is mounted.

[0033] Capacitor element 320 is connected between connection terminal 85 of the high-frequency circuit 100 and ground. Capacitor element 320 may consist of a single capacitor, but sometimes it may include multiple capacitors. In this case, the multiple capacitors may be connected in series, in parallel, or in combination.

[0034] The circuit board 13 is, for example, a printed circuit board. The circuit board 13 has a ground electrode to which a ground potential is applied. Additionally, the circuit board 13 has a first main surface 131 and a second main surface 132 (see reference 132) facing each other in the thickness direction of the circuit board 13 (the thickness direction D1 of the mounting substrate 9 described later). Figure 3 In the communication device 300, the high-frequency circuit 100 is disposed on the first main surface 131 side of the circuit board 13. Additionally, in the communication device 300, the capacitor element 320 is disposed on the first main surface 131 side of the circuit board 13. Furthermore, in the communication device 300, the high-frequency circuit 100 and the capacitor element 320 are adjacent to each other on the first main surface 131 of the circuit board 13. Here, "two constituent elements are adjacent" means that there are no other constituent elements between the two adjacent constituent elements. Therefore, in... Figure 3 In this circuit, there are no other components between the high-frequency circuit 100 and the capacitor element 320. Thus, the high-frequency circuit 100 and the capacitor element 320 are adjacent to each other on the first main surface 131 of the circuit board 13, thereby enabling a short wiring length between the high-frequency circuit 100 and the capacitor element 320.

[0035] The signal processing circuit 301 includes, for example, an RF signal processing circuit 302 and a baseband signal processing circuit 303. The RF signal processing circuit 302 is, for example, an RFIC (Radio Frequency Integrated Circuit) that performs signal processing for high-frequency signals. The RF signal processing circuit 302 performs up-conversion and other signal processing on the high-frequency signal (transmit signal) output from the baseband signal processing circuit 303, and outputs the processed high-frequency signal. Additionally, the RF signal processing circuit 302 performs down-conversion and other signal processing on the high-frequency signal (receive signal) output from the high-frequency circuit 100, and outputs the processed high-frequency signal to the baseband signal processing circuit 303. The baseband signal processing circuit 303 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 303 generates I-phase and Q-phase signals based on the baseband signals. The baseband signals include, for example, externally input audio signals, image signals, etc. The baseband signal processing circuit 303 performs IQ modulation processing by combining the I-phase and Q-phase signals and outputs the transmit signal. At this time, the transmitted signal is generated as a modulated signal (IQ signal) obtained by amplitude modulation of a carrier signal of a specified frequency with a period longer than the period of the carrier signal. The received signal, after being processed in the baseband signal processing circuit 303, is used for example as an image signal for image display or as an audio signal for communication. The high-frequency circuit 100 transmits high-frequency signals (received signal, transmitted signal) between the antenna 310 and the RF signal processing circuit 302 of the signal processing circuit 301.

[0036] The high-frequency circuit 100 includes a power amplifier 111 and a low-noise amplifier 121. Additionally, the high-frequency circuit 100 includes multiple (two in the example) transmitting filters 112A and 112B and multiple (two in the example) receiving filters 122A and 122B. Furthermore, the high-frequency circuit 100 includes an output matching circuit 113, an input matching circuit 123, and multiple (two in the example) matching circuits 114 and 124. Furthermore, the high-frequency circuit 100 includes a first switch 104, a second switch 105, and a third switch 106. Finally, the high-frequency circuit 100 includes a controller (control circuit) 107 and an on / off switch 108.

[0037] In addition, the high-frequency circuit 100 includes multiple external connection terminals 80. These external connection terminals 80 include an antenna terminal 81, a signal input terminal 82, a signal output terminal 83, a control terminal 84, a connection terminal 85, and multiple ground terminals 86 (see reference). Figure 5 Multiple ground terminals 86 are terminals that are electrically connected to the ground electrode of the circuit board 13 described above, which is provided in the communication device 300, and thus have a ground potential applied to them.

[0038] A power amplifier 111 is disposed in the signal path T1 used for transmitting signals. The power amplifier 111 has an input terminal, an output terminal, and a power supply terminal 1111. The power amplifier 111 amplifies the transmitted signal of a first frequency band input to the input terminal and outputs it from the output terminal. The first frequency band includes, for example, a first communication band and a second communication band. The first communication band corresponds to the transmitted signal passing through the transmit filter 112A, for example, Band 11 of the 3GPP LTE standard. The second communication band corresponds to the transmitted signal passing through the transmit filter 112B, for example, Band 22 of the 3GPP LTE standard.

[0039] The input terminals of power amplifier 111 are connected to signal input terminal 82. The input terminals of power amplifier 111 are connected to signal processing circuit 301 via signal input terminal 82. Signal input terminal 82 is used to input high-frequency signals (transmit signals) from external circuitry (e.g., signal processing circuit 301) to high-frequency circuit 100. The output terminals of power amplifier 111 are connected to the common terminal 150 of second switch 105 via output matching circuit 113. The power supply terminal 1111 of power amplifier 111 is connected to controller 107. Power amplifier 111 is controlled, for example, by controller (control circuit) 107.

[0040] A low-noise amplifier 121 is disposed in the signal path R1 used for receiving signals. The low-noise amplifier 121 has an input terminal and an output terminal. The low-noise amplifier 121 amplifies the received signal of the second frequency band input to the input terminal and outputs it from the output terminal. The second frequency band is, for example, the same as the first frequency band, and includes both a first communication frequency band and a second communication frequency band.

[0041] The input terminal of the low-noise amplifier 121 is connected to the common terminal 160 of the third switch 106 via the input matching circuit 123. The output terminal of the low-noise amplifier 121 is connected to the signal output terminal 83. The output terminal of the low-noise amplifier 121 is connected to the signal processing circuit 301, for example, via the signal output terminal 83. The signal output terminal 83 is used to output the high-frequency signal (received signal) from the low-noise amplifier 121 to an external circuit (e.g., the signal processing circuit 301).

[0042] Transmitting filter 112A is, for example, a filter whose passband is the transmit band of a first communication frequency band. Transmitting filter 112B is, for example, a filter whose passband is the transmit band of a second communication frequency band. Receiving filter 122A is, for example, a filter whose passband is the receive band of the first communication frequency band. Receiving filter 122B is, for example, a filter whose passband is the receive band of the second communication frequency band. In the high-frequency circuit 100 according to Embodiment 1, transmitting filter 112A and receiving filter 122A constitute a first duplexer, and transmitting filter 112B and receiving filter 122B constitute a second duplexer.

[0043] The first switch 104 has a common terminal 140 and multiple (two in the example) selectable terminals 141 and 142. The common terminal 140 is connected to the antenna terminal 81. An antenna 310 is connected to the antenna terminal 81. Selectable terminals 141 are connected to the output terminal of the transmit filter 112A and the input terminal of the receive filter 122A. Selectable terminals 142 are connected to the output terminal of the transmit filter 112B and the input terminal of the receive filter 122B. The first switch 104 is, for example, a switch capable of connecting at least one of the multiple selectable terminals 141 and 142 to the common terminal 140. Here, the first switch 104 is, for example, a switch capable of both one-to-one and one-to-many connections.

[0044] The first switch 104 is disposed on both the signal path T1 (T11, T12) for transmitting signals and the signal path R1 (R11, R12) for receiving signals. More specifically, the first switch 104 is disposed on the signal path T11 for transmitting signals, which includes a power amplifier 111, an output matching circuit 113, a second switch 105, a transmitting filter 112A, and a matching circuit 114. Additionally, the first switch 104 is disposed on the signal path T12 for transmitting signals, which includes a power amplifier 111, an output matching circuit 113, a second switch 105, a transmitting filter 112B, and a matching circuit 124. Furthermore, the first switch 104 is disposed on the signal path R11 for receiving signals, which includes a matching circuit 114, a receiving filter 122A, a third switch 106, an input matching circuit 123, and a low-noise amplifier 121. In addition, the first switch 104 is located in the signal path R12 for receiving signals, which is provided with the matching circuit 124, the receiving filter 122B, the third switch 106, the input matching circuit 123 and the low noise amplifier 121.

[0045] The first switch 104 is controlled, for example, by the signal processing circuit 301. The first switch 104 switches the connection state between the common terminal 140 and the plurality of select terminals 141, 142 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301. The first switch 104 is, for example, a switch IC (Integrated Circuit).

[0046] The second switch 105 has a common terminal 150 and multiple (two in the example) selectable terminals 151 and 152. The common terminal 150 is connected to the output terminal of the power amplifier 111 via the output matching circuit 113. Selectable terminal 151 is connected to the input terminal of the transmit filter 112A. Selectable terminal 152 is connected to the input terminal of the transmit filter 112B. The second switch 105 is, for example, a switch capable of connecting at least one of the multiple selectable terminals 151 and 152 to the common terminal 150. Here, the second switch 105 is, for example, a switch capable of one-to-one and one-to-many connections. The second switch 105 is a switch that has the function of switching between multiple transmit signal paths T11 and T12 for different communication frequency bands.

[0047] The second switch 105 is controlled, for example, by the signal processing circuit 301. The second switch 105 switches the connection state between the common terminal 150 and the multiple select terminals 151, 152 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301. The second switch 105 is, for example, a switch IC.

[0048] The third switch 106 has a common terminal 160 and multiple (two in the example) selectable terminals 161 and 162. The common terminal 160 is connected to the input terminal of the low-noise amplifier 121 via the input matching circuit 123. Selectable terminal 161 is connected to the output terminal of the receiver filter 122A. Selectable terminal 162 is connected to the output terminal of the receiver filter 122B. The third switch 106 is, for example, a switch capable of connecting at least one of the multiple selectable terminals 161 and 162 to the common terminal 160. Here, the third switch 106 is, for example, a switch capable of one-to-one and one-to-many connections. The third switch 106 is a switch that has the function of switching between multiple signal paths R11 and R12 for received signals in different communication frequency bands.

[0049] The third switch 106 is controlled, for example, by the signal processing circuit 301. The third switch 106 switches the connection state between the common terminal 160 and the multiple select terminals 161, 162 according to the control signal from the RF signal processing circuit 302 of the signal processing circuit 301. The third switch 106 is, for example, a switch IC.

[0050] Output matching circuit 113 is disposed in the signal path between the output terminal of power amplifier 111 and the common terminal 150 of second switch 105. Output matching circuit 113 is used to achieve impedance matching between power amplifier 111 and transmitting filters 112A, 112B. Output matching circuit 113 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0051] Input matching circuit 123 is disposed in the signal path between the input terminal of low-noise amplifier 121 and the common terminal 160 of third switch 106. Input matching circuit 123 is used to achieve impedance matching between low-noise amplifier 121 and receiving filters 122A, 122B. Input matching circuit 123 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0052] Matching circuit 114 is disposed in the signal path between the output terminal of transmitting filter 112A, the input terminal of receiving filter 122A, and the selection terminal 141 of first switch 104. Matching circuit 114 is used to achieve impedance matching between transmitting filter 112A, receiving filter 122A, and first switch 104. Matching circuit 114 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0053] Matching circuit 124 is disposed in the signal path between the output terminal of transmitting filter 112B, the input terminal of receiving filter 122B, and the selection terminal 142 of first switch 104. Matching circuit 124 is used to achieve impedance matching between transmitting filter 112B, receiving filter 122B, and first switch 104. Matching circuit 124 is composed of, for example, a single inductor, but is not limited thereto; for example, it may sometimes include multiple inductors and multiple capacitors.

[0054] Controller 107 is connected to power amplifier 111. Controller 107 is connected to signal processing circuit 301, for example, via control terminal 84. Control terminal 84 is a terminal for inputting control signals from external circuitry (e.g., signal processing circuit 301) to controller 107. Controller 107 controls power amplifier 111 based on the control signals received from control terminal 84. Controller 107 controls power amplifier 111 according to control signals from RF signal processing circuit 302 of signal processing circuit 301. Here, controller 107 receives control signals from RF signal processing circuit 302 and, based on these control signals, causes power amplifier 111 to operate, for example, in a first power mode or a second power mode. When the control signal from RF signal processing circuit 302 instructs power amplifier 111 to operate in the first power mode, controller 107 causes power amplifier 111 to operate in the first power mode. Conversely, when the control signal from RF signal processing circuit 302 instructs power amplifier 111 to operate in the second power mode, controller 107 causes power amplifier 111 to operate in the second power mode.

[0055] In the first power mode, the controller 107 causes the power amplifier 111 to perform envelope tracking. That is, in the first power mode, the controller 107 controls the power amplifier 111 in an envelope tracking manner. In this case, the controller 107 controls the power amplifier 111's power supply voltage based on the input signal level of the transmitted signal (from the signal processing circuit 301) input to the power amplifier 111. More specifically, in the high-frequency circuit 100, the power supply terminal 1111 of the power amplifier 111 is supplied with a power supply voltage corresponding to the amplitude level of the transmitted signal. The controller 107 generates the power supply voltage, for example, based on the power control signal (envelope signal) from the baseband signal processing circuit 303 of the signal processing circuit 301, and provides it to the power supply terminal 1111 of the power amplifier 111. The baseband signal processing circuit 303 detects the amplitude level of the modulated signal based on the IQ signal and outputs a power control signal to the controller 107 to make the power supply voltage a level corresponding to the amplitude level of the transmitted signal.

[0056] In the second power mode, the controller 107 causes the power amplifier 111 to perform average power tracking. That is, in the second power mode, the controller 107 controls the power amplifier 111 in an average power tracking manner. In this case, the controller 107 calculates the average power amplitude of the high-frequency signal at predetermined intervals based on the power control signal from the baseband signal processing circuit 303, and controls the power supply voltage of the power amplifier 111 according to the calculated average power amplitude.

[0057] A switch 108 is connected between path R2 and connection terminal 85. Path R2 is the path between the power amplifier 111's power supply terminal 1111 and the controller 107. The switch 108 is controlled, for example, by the controller 107. In a first power mode, the switch 108 is opened according to a control signal from the controller 107, so that the capacitor element 320 connected to connection terminal 85 is not connected to path R2. In other words, when the controller 107 controls the power amplifier 111 in envelope tracking mode, the controller 107 opens the switch 108. In a second power mode, the switch 108 is closed according to a control signal from the controller 107, so that the capacitor element 320 is connected to path R2. In other words, when the controller 107 controls the power amplifier 111 in average power tracking mode, the controller 107 closes the switch 108.

[0058] (1.2) Structure of the high-frequency module

[0059] like Figure 2 and Figure 3 As shown, the high-frequency circuit 100 according to Embodiment 1 includes a mounting substrate 9. Hereinafter, the high-frequency circuit 100 including the mounting substrate 9 may also be referred to as a "high-frequency module 100". Referring to... Figure 2 and Figure 3 The structure of the high-frequency module 100 involved in Embodiment 1 will be explained.

[0060] like Figure 2 and Figure 3 As shown, the high-frequency module 100 according to Embodiment 1 includes a mounting substrate 9, a first electronic component 1, a second electronic component 2, and a plurality of external connection terminals 80 (see reference). Figure 1 The first electronic component 1 is, for example, a controller 107. The second electronic component 2 is, for example, an on / off switch 108. In the high-frequency module 100 according to Embodiment 1, the controller 107 and the on / off switch 108 are constituted by a single chip 10. That is, the chip 10 includes the controller 107 and the on / off switch 108.

[0061] Mounting substrate 9 has a first main surface 91 and a second main surface 92 facing each other in the thickness direction D1 of mounting substrate 9. Mounting substrate 9 is, for example, a multilayer substrate including multiple dielectric layers and multiple conductive layers. Multiple dielectric layers and multiple conductive layers are stacked in the thickness direction D1 of mounting substrate 9. Multiple conductive layers are formed in a predetermined pattern determined by each layer. Each of the multiple conductive layers includes one or more conductor portions in a plane orthogonal to the thickness direction D1 of mounting substrate 9. The material of each conductive layer is, for example, copper. Multiple conductive layers include a ground layer. In high-frequency module 100, multiple ground terminals 86 are electrically connected to the ground layer via conductive paths provided by mounting substrate 9. Mounting substrate 9 is, for example, an LTCC (Low Temperature Co-fired Ceramics) substrate. Mounting substrate 9 is not limited to LTCC substrates, and may also be, for example, a printed circuit board, an HTCC (High Temperature Co-fired Ceramics) substrate, or a resin multilayer substrate.

[0062] Furthermore, the mounting substrate 9 is not limited to an LTCC substrate; it can also be a wiring structure, for example. The wiring structure can be, for example, a multilayer structure. A multilayer structure includes at least one insulating layer and at least one conductive layer. The insulating layer is formed in a predetermined pattern. If there are multiple insulating layers, the multiple insulating layers are formed in a predetermined pattern determined by each layer. The conductive layer is formed in a predetermined pattern different from the predetermined pattern of the insulating layer. If there are multiple conductive layers, the multiple conductive layers are formed in a predetermined pattern determined by each layer. The conductive layer may also include one or more rewiring portions. In the wiring structure, the first surface of two surfaces facing each other in the thickness direction of the multilayer structure is the first main surface 91 of the mounting substrate 9, and the second surface is the second main surface 92 of the mounting substrate 9. The wiring structure can be, for example, an interposer. The interposer can be an interposer using a silicon substrate or a substrate composed of multiple layers.

[0063] The first main surface 91 and the second main surface 92 of the mounting substrate 9 are separated in the thickness direction D1 of the mounting substrate 9 and intersect the thickness direction D1 of the mounting substrate 9. The first main surface 91 of the mounting substrate 9 is, for example, orthogonal to the thickness direction D1 of the mounting substrate 9, but it may also be a surface that is not orthogonal to the thickness direction D1, for example, including the side surface of the conductor portion. Similarly, the second main surface 92 of the mounting substrate 9 is, for example, orthogonal to the thickness direction D1 of the mounting substrate 9, but it may also be a surface that is not orthogonal to the thickness direction D1, for example, including the side surface of the conductor portion. Furthermore, the first main surface 91 and the second main surface 92 of the mounting substrate 9 may also have minute irregularities, recesses, or protrusions. When viewed from above in the thickness direction D1 of the mounting substrate 9, the mounting substrate 9 is rectangular in shape, but is not limited to this; for example, it may also be square. In the high-frequency module 100 according to Embodiment 1, the mounting substrate 9 is a single-sided mounting substrate on which electronic components are mounted only on the first main surface 91.

[0064] The power amplifier 111 is, for example, an IC chip including a substrate having a first main surface and a second main surface facing each other, and a circuit section (IC section) with transistors formed on the first main surface side of the substrate. The substrate is, for example, a gallium arsenide substrate. The circuit section has the function of amplifying the transmission signal input to the input terminal of the power amplifier 111. The transistor is, for example, an HBT (Heterojunction Bipolar Transistor). The power amplifier 111 may include a capacitor for DC cutoff. The IC chip including the power amplifier 111 is mounted on the first main surface 91 of the mounting substrate 9 in a flip-chip mounting manner, such that the first main surface of the first main surface and the second main surface of the substrate becomes the first main surface 91 side of the mounting substrate 9. When viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of the IC chip including the power amplifier 111 is quadrilateral. The substrate of the IC chip including the power amplifier 111 is not limited to a gallium arsenide substrate, but may also be a silicon substrate, a silicon germanide substrate, or a gallium nitride substrate, etc. Furthermore, transistors are not limited to bipolar transistors such as HBTs; they can also be FETs (Field Effect Transistors). FETs include, for example, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors).

[0065] The low-noise amplifier 121 is, for example, an IC chip including a substrate having a first main surface and a second main surface facing each other, and a circuit section (IC section) formed on the first main surface side of the substrate. The substrate is, for example, a silicon substrate. The circuit section has the function of amplifying the received signal input to the input terminal of the low-noise amplifier 121. The low-noise amplifier 121 is mounted on the first main surface 91 of the mounting substrate 9 in a flip-chip mounting manner, such that the first main surface of the substrate becomes the first main surface 91 side of the mounting substrate 9. When viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of the low-noise amplifier 121 is quadrilateral.

[0066] Each filter in the plurality of transmitting filters 112A, 112B and the plurality of receiving filters 122A, 122B is, for example, a trapezoidal filter. Each filter in the plurality of transmitting filters 112A, 112B and the plurality of receiving filters 122A, 122B has a plurality of (e.g., 4) series-arm resonators and a plurality of (e.g., 3) parallel-arm resonators. Each filter in the plurality of transmitting filters 112A, 112B and the plurality of receiving filters 122A, 122B is, for example, an elastic wave filter. Regarding the elastic wave filter, each resonator in the plurality of series-arm resonators and the plurality of parallel-arm resonators is composed of elastic wave resonators. The elastic wave filter is, for example, a surface acoustic wave filter utilizing surface acoustic waves.

[0067] In surface acoustic wave filters, each resonator in multiple series arm resonators and multiple parallel arm resonators is, for example, a SAW (Surface Acoustic Wave) resonator.

[0068] A surface acoustic wave (SAW) filter includes, for example, a substrate having a first main surface and a second main surface facing each other; and a circuit section formed on the first main surface side of the substrate. The substrate is a piezoelectric substrate. The piezoelectric substrate is, for example, a lithium niobate substrate. The circuit section has multiple IDT (Interdigital Transducer) electrodes corresponding one-to-one with multiple series arm resonators and multiple IDT electrodes corresponding one-to-one with multiple parallel arm resonators.

[0069] Each of the plurality of transmitting filters 112A, 112B and receiving filters 122A, 122B is, for example, a bare-chip elastic wave filter. Viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of each of the plurality of transmitting filters 112A, 112B and receiving filters 122A, 122B is quadrilateral. Each of the plurality of transmitting filters 112A, 112B and receiving filters 122A, 122B is mounted on the first main surface 91 of the mounting substrate 9, for example, in a flip-chip mounting manner, such that the first main surface of the substrate becomes the mounting substrate 9 side.

[0070] Each of the first switch 104, the second switch 105, and the third switch 106 is a switch IC. More specifically, each of the first switch 104, the second switch 105, and the third switch 106 is, for example, an IC chip including a substrate having a first main surface and a second main surface facing each other, and a circuit section (IC section) having a FET formed on the first main surface side of the substrate. The substrate is, for example, a silicon substrate. The circuit section is a functional section that has the function of switching the connection state of a common terminal and multiple select terminals. When viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of the IC chip constituting each of the first switch 104, the second switch 105, and the third switch 106 is quadrilateral. Each of the first switch 104, the second switch 105, and the third switch 106 is mounted on the first main surface 91 of the mounting substrate 9, for example, by flip-chip mounting, such that the first main surface of the first main surface and the second main surface of the substrate becomes the first main surface 91 side of the mounting substrate 9.

[0071] like Figure 3 As shown, the controller 107 and the on / off switch 108 are composed of a single chip 10. That is, the chip 10 includes the controller 107 and the on / off switch 108. The chip 10 is mounted on the first main surface 91 of the mounting substrate 9 in a flip-chip mounting manner. When viewed from the thickness direction D1 of the mounting substrate 9, the chip 10 is, for example, quadrilateral in shape.

[0072] The inductor in the output matching circuit 113 is, for example, a chip inductor. The inductor in the output matching circuit 113 is disposed, for example, on the first main surface 91 side of the mounting substrate 9, but is not limited thereto. When viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of the inductor is quadrilateral.

[0073] The inductor in the input matching circuit 123 is, for example, a chip inductor. The inductor in the input matching circuit 123 is disposed, for example, on the first main surface 91 side of the mounting substrate 9, but is not limited thereto. When viewed from the thickness direction D1 of the mounting substrate 9, the outer periphery of the inductor is quadrilateral.

[0074] Multiple external connection terminals 80 are disposed on the second main surface 92 of the mounting substrate 9. Each terminal of the multiple external connection terminals 80 is a cylindrical (e.g., cylindrical) terminal. The material of the multiple external connection terminals 80 is metal (e.g., copper or copper alloy).

[0075] In addition to the antenna terminal 81, signal input terminal 82, signal output terminal 83, control terminal 84, and connection terminal 85 described above, the multiple external connection terminals 80 also include multiple ground terminals 86. As described above, the multiple ground terminals 86 are electrically connected to the ground plane of the mounting substrate 9. The ground plane is the circuit ground of the high-frequency module 100.

[0076] like Figure 2 and Figure 3 As shown, in the high-frequency module 100 according to Embodiment 1, the first electronic component 1 and the second electronic component 2 are constituted by a single chip 10. That is, in the high-frequency module 100 according to Embodiment 1, the controller 107 and the on / off switch 108 are constituted by a single chip 10. In addition, in the high-frequency module 100 according to Embodiment 1, the controller 107 and the on / off switch 108 included in the chip 10 are disposed on the first main surface 91 side of the mounting substrate 9.

[0077] Furthermore, in the high-frequency module 100 according to Embodiment 1, as described above, the controller 107 is disposed on the first main surface 91 side of the mounting substrate 9, and the connection terminal 85 is disposed on the second main surface 92 side of the mounting substrate 9. Moreover, as... Figure 2 As shown, when viewed from the thickness direction D1 of the mounting substrate 9, a portion of the chip 10, including the controller 107, overlaps with a portion of the connection terminal 85. Therefore, compared to the case where the controller 107 and the connection terminal 85 do not overlap, it is possible to design a shorter wiring length between the controller 107 and the connection terminal 85.

[0078] (2) Operation of high-frequency circuits

[0079] Next, the operation of the high-frequency circuit 100 according to Embodiment 1 will be explained.

[0080] In the high-frequency circuit 100 according to Embodiment 1, as described above, the controller 107 is configured to operate the power amplifier 111 in a first power mode or a second power mode. As described above, the first power mode is a mode in which the power amplifier 111 is controlled in an envelope tracking manner, and the second power mode is a mode in which the power amplifier 111 is controlled in an average power tracking manner. Specifically, when the transmit power is high, the controller 107 operates the power amplifier 111 in the first power mode, and when the transmit power is low, the controller 107 operates the power amplifier 111 in the second power mode.

[0081] In the first power mode, the controller 107 controls the power supply voltage input to the power supply terminal 1111 of the power amplifier 111 based on the input signal level of the transmit signal input to the power amplifier 111. Specifically, the controller 107 generates the power supply voltage, for example, based on the power control signal (envelope signal) from the baseband signal processing circuit 303 of the signal processing circuit 301, and provides the generated power supply voltage to the power supply terminal 1111 of the power amplifier 111.

[0082] Here, in envelope tracking operation, the control voltage is controlled with a shorter cycle than in average power tracking operation. Therefore, when capacitor element 320 is connected to path R2 during envelope tracking operation, envelope tracking operation is no longer possible. Consequently, in the first power mode that enables power amplifier 111 to perform envelope tracking operation, controller 107 opens on / off switch 108, disconnecting capacitor element 320 from path R2.

[0083] As described above, in the second power mode, the controller 107 controls the power supply voltage input to the power supply terminal 1111 of the power amplifier 111 based on the average power amplitude. Specifically, the controller 107 calculates the average power amplitude of the high-frequency signal for each specified period, for example, based on the power control signal from the baseband signal processing circuit 303, and provides the power supply voltage generated based on the calculated average power amplitude to the power supply terminal 1111 of the power amplifier 111.

[0084] Furthermore, in the second power mode, the parasitic inductance of path R2 is large, causing the power supply voltage supplied from controller 107 to the power supply terminal 1111 of power amplifier 111 to be unstable. Therefore, controller 107 turns on switch 108, connecting capacitor element 320 to path R2. This suppresses the parasitic inductance of path R2, thereby stabilizing the power supply voltage supplied to the power supply terminal 1111 of power amplifier 111 in the second power mode.

[0085] (3) Summary

[0086] (3.1) High-frequency circuits

[0087] The high-frequency circuit 100 according to Embodiment 1 includes a power amplifier 111, a controller 107, an on / off switch 108, a connection terminal 85, and a mounting substrate 9. The power amplifier 111 has a power supply terminal 1111 and supports both average power tracking (APS) and envelope tracking (AST) modes. The controller 107 is connected to the power supply terminal 1111 and controls the power amplifier 111 using both APS and AST modes. The on / off switch 108 is connected in series with a capacitor element 320, which is connected between the path R2 between the controller 107 and the power supply terminal 1111 and ground. The connection terminal 85 is connected to the capacitor element 320. The mounting substrate 9 has a first main surface 91 and a second main surface 92 facing each other. When viewed from the thickness direction D1 of the mounting substrate 9, the control circuit 107 overlaps with the connection terminal 85.

[0088] In the high-frequency circuit 100 according to Embodiment 1, in the average power tracking mode, the on / off switch 108 is turned on to connect the capacitor element 320 to the path R2. As a result, the parasitic inductance component of the path R2 can be suppressed, and thus the power supply voltage to the power supply terminal 1111 of the power amplifier 111 can be stabilized in the average power tracking mode.

[0089] Furthermore, in the high-frequency circuit 100 according to Embodiment 1, when viewed from the thickness direction D1 of the mounting substrate 9, the controller 107 overlaps with the connection terminal 85. Therefore, compared to the case where the controller 107 and the connection terminal 85 do not overlap, it is possible to design a shorter wiring length between the controller 107 and the connection terminal 85.

[0090] Furthermore, in the high-frequency circuit 100 according to Embodiment 1, the controller 107 and the on / off switch 108 are both composed of a single chip 10. As a result, compared to the case where the controller 107 and the on / off switch 108 are composed of different chips, the area of ​​the mounting substrate 9 when viewed from the thickness direction D1 is smaller.

[0091] (3.2) Communication device

[0092] The communication device 300 according to Embodiment 1 includes the high-frequency circuit 100 and the signal processing circuit 301 described above. The signal processing circuit 301 is connected to the high-frequency circuit 100 and processes high-frequency signals.

[0093] The communication device 300 according to Embodiment 1 includes a high-frequency circuit 100, which enables the power supply voltage of the power supply terminal 1111 of the power amplifier 111 to be stabilized in the average power tracking mode.

[0094] (4) Variations

[0095] The following are variations of Implementation 1. The variations described below can be appropriately combined for application.

[0096] (4.1) Variation Example 1

[0097] Reference Figure 4 The high-frequency circuit 100a according to Modification 1 of Embodiment 1 will be described below. For the high-frequency circuit 100a according to Modification 1, the same reference numerals are used for the same constituent elements as those in the high-frequency circuit 100 according to Embodiment 1, and the description is omitted.

[0098] In the high-frequency circuit 100a of Modification 1, the difference from the high-frequency circuit 100 of Embodiment 1 is that the chip 10 including the first electronic component 1 and the second electronic component 2 and the fourth electronic component 4 are stacked on the first main surface 91 of the mounting substrate 9.

[0099] like Figure 4 As shown, in the high-frequency circuit 100a according to Modification 1, the fourth electronic component 4 is mounted on the first main surface 91 of the mounting substrate 9 in a flip-chip mounting manner. The fourth electronic component 4 is, for example, a power amplifier 111. Furthermore, in the high-frequency circuit 100a according to Modification 1, the chip 10, including the first electronic component 1 and the second electronic component 2, is mounted on the main surface of the fourth electronic component 4 opposite to the mounting substrate 9 in a flip-chip mounting manner. That is, in the high-frequency circuit 100a according to Modification 1, the fourth electronic component 4 and the chip 10 (the first electronic component 1 and the second electronic component 2) are stacked in this order on the first main surface 91 of the mounting substrate 9, starting from the mounting substrate 9 side. In summary, the controller 107 and the on / off switch 108 are disposed on the side of the power amplifier 111 opposite to the mounting substrate 9.

[0100] In the high-frequency circuit 100a according to Modification 1, as described above, the first electronic component 1 and the second electronic component 2 and the fourth electronic component 4 included in the chip 10 are stacked on the first main surface 91 of the mounting substrate 9. As a result, compared with the case where the chip 10 and the fourth electronic component 4 are separately arranged on the first main surface 91 of the mounting substrate 9, the area of ​​the mounting substrate 9 when viewed from the thickness direction D1 is smaller.

[0101] Furthermore, in the high-frequency circuit 100a according to Modification 1, the chip 10, including the first electronic component 1 and the second electronic component 2, overlaps with the fourth electronic component 4 in the thickness direction D1 of the mounting substrate 9. Therefore, compared to the case where the chip 10 and the fourth electronic component 4 are separately arranged on the first main surface 91 of the mounting substrate 9, the wiring length between the first electronic component 1 and the fourth electronic component 4, as well as the wiring length between the second electronic component 2 and the fourth electronic component 4, can be shortened.

[0102] (4.2) Variation Example 2

[0103] Reference Figure 5 The high-frequency circuit 100b according to Modification 2 of Embodiment 1 will be described below. For the high-frequency circuit 100b according to Modification 2, the same reference numerals are used for the same constituent elements as those in the high-frequency circuit 100a according to Modification 1, and the description is omitted.

[0104] In the high-frequency circuit 100b of Modification 2, the difference from the high-frequency circuit 100a of Modification 1 is that the chip 10, which includes the first electronic component 1 and the second electronic component 2, is disposed on the second main surface 92 side of the mounting substrate 9.

[0105] In the high-frequency circuit 100b involved in Modification Example 2, such as Figure 5 As shown, the fourth electronic component 4 is mounted on the first main surface 91 of the mounting substrate 9 using a flip-chip mounting method. Furthermore, in the high-frequency circuit 100b according to Modification 2, the chip 10, including the first electronic component 1 and the second electronic component 2, is mounted on the second main surface 92 of the mounting substrate 9 using a flip-chip mounting method. That is, in the high-frequency circuit 100b according to Modification 2, the power amplifier 111 (fourth electronic component 4) is disposed on the first main surface 91 side of the mounting substrate 9, and the controller 107 and the on / off switch 108 (first electronic component 1 and second electronic component 2) are disposed on the second main surface 92 side of the mounting substrate 9.

[0106] In the high-frequency circuit 100b of Modification 2, as described above, the fourth electronic component 4 is disposed on the first main surface 91 side of the mounting substrate 9, and the first electronic component 1 and the second electronic component 2 included in the chip 10 are disposed on the second main surface 92 of the mounting substrate 9. Therefore, compared to the case where the chip 10 and the fourth electronic component 4 are disposed on the first main surface 91 side of the mounting substrate 9, the area of ​​the mounting substrate 9 when viewed from the thickness direction D1 is smaller.

[0107] Furthermore, in the high-frequency circuit 100b involved in Modification 2, when viewed from the thickness direction D1 of the mounting substrate 9, the chip 10, including the first electronic component 1 and the second electronic component 2, overlaps with the fourth electronic component 4. Therefore, compared to the case where the chip 10 and the fourth electronic component 4 do not overlap when viewed from the thickness direction D1 of the mounting substrate 9, the wiring length between the first electronic component 1 and the fourth electronic component 4, as well as the wiring length between the second electronic component 2 and the fourth electronic component 4, can be shortened.

[0108] (4.3) Variation Example 3

[0109] Reference Figure 6 The high-frequency circuit 100c according to Modification 3 of Embodiment 1 will be described below. Regarding the high-frequency circuit 100c according to Modification 3, the same reference numerals are used for the same constituent elements as those in the high-frequency circuit 100 according to Embodiment 1, and the description is omitted.

[0110] In the high-frequency circuit 100c involved in Modification 3, the difference from the high-frequency circuit 100 involved in Embodiment 1 is that the chip 10c includes a fifth electronic component 5 in addition to the first electronic component 1 and the second electronic component 2.

[0111] In the high-frequency circuit 100c involved in Modification Example 3, such as Figure 6As shown, the first electronic component 1, the second electronic component 2, and the fifth electronic component 5 are constituted by a single chip 10c. That is, the chip 10c includes the first electronic component 1, the second electronic component 2, and the fifth electronic component 5. The fifth electronic component 5 is, for example, the second switch 105. In other words, in the high-frequency circuit 100c involved in Modification 3, the controller 107, the on / off switch 108, and the second switch 105 are constituted by a single chip 10c. Figure 6 As shown, chip 10c is disposed on the first main surface 91 side of mounting substrate 9.

[0112] In the high-frequency circuit 100c involved in Modification 3, as described above, the first electronic component 1, the second electronic component 2, and the fifth electronic component 5 are constituted by a single chip 10c and disposed on the first main surface 91 side of the mounting substrate 9. Therefore, compared to the case where at least two of the first electronic component 1, the second electronic component 2, and the fifth electronic component 5 are separately disposed on the first main surface 91 side, the area of ​​the mounting substrate 9 in the thickness direction D1 of the mounting substrate 9 can be reduced.

[0113] (4.4) Other variations

[0114] In the high-frequency circuit 100 of embodiment 1, at least the controller 107 and the on / off switch 108 are composed of one chip 10, 10c, but for example, the controller 107 and the on / off switch 108 may be composed of different chips.

[0115] In the high-frequency circuit 100 according to Embodiment 1, between the path R2 between the controller 107 and the power supply terminal 1111 of the power amplifier 111 and ground, the on / off switch 108 and the capacitor element 320 are connected such that the on / off switch 108 is on the side opposite to ground and the capacitor element 320 is on the ground side, but this is not limited to this. That is, it is also possible that between the path R2 and ground, the on / off switch 108 and the capacitor element 320 are connected such that the on / off switch 108 is on the ground side and the capacitor element 320 is on the side opposite to ground.

[0116] In the high-frequency circuit 100 according to Embodiment 1, such as Figure 2As shown, when viewed from the thickness direction D1 of the mounting substrate 9, a portion of the controller (control circuit) 107 overlaps with the position of the connection terminal 85, but this is not limited to this. For example, when viewed from the thickness direction D1 of the mounting substrate 9, the entire controller 107 may overlap with the entire connection terminal 85, or only a portion of the controller 107 may overlap with the connection terminal 85, or only a portion of the controller 107 may overlap with the entire connection terminal 85. In short, "when viewed from the thickness direction of the mounting substrate, the controller overlaps with the connection terminal" means that at least a portion of the controller overlaps with at least a portion of the connection terminal when viewed from the thickness direction of the mounting substrate.

[0117] (Implementation Method 2)

[0118] Reference Figure 7 and Figure 8 The high-frequency circuit 100d according to Embodiment 2 will be described below. For the high-frequency circuit 100d according to Embodiment 2, the same reference numerals are used for the same constituent elements as those in the high-frequency circuit 100 according to Embodiment 1, and descriptions are omitted.

[0119] In the high-frequency circuit 100d according to Embodiment 2, the difference from the high-frequency circuit 100 according to Embodiment 1 is that, instead of the second switch 105 on the output side of the power amplifier 111, a fourth switch (switching switch) 109 is provided on the input side of a plurality of (two in the example) power amplifiers 111A, 111B.

[0120] (1) Circuit structure of high-frequency circuits

[0121] First, refer to Figure 7 The circuit structure of the high-frequency circuit 100d involved in Embodiment 1 will be explained.

[0122] The high-frequency circuit 100d according to Embodiment 2 includes multiple (two in the example) power amplifiers 111A and 111B and a low-noise amplifier 121 (see Figure 2). Figure 1 In addition, the high-frequency circuit 100d has multiple (two in the example) transmitting filters 112A and 112B (see reference). Figure 1 ) and multiple (two in the example) receiver filters 122A, 122B (see reference) Figure 1 In addition, the high-frequency circuit 100d includes an output matching circuit 113 (see reference). Figure 1 ), Input matching circuit 123 (refer to) Figure 1 ) and multiple (two in the example) matching circuits 114, 124 (see reference) Figure 1 In addition, the high-frequency circuit 100d includes a first switch 104 (see reference). Figure 1), third switch 106 (refer to) Figure 1 The high-frequency circuit 100d includes a controller (control circuit) 107 and an on / off switch 108. Additionally, the high-frequency circuit 100d includes multiple external connection terminals 80 (see reference). Figure 1 ).

[0123] Each of the multiple power amplifiers 111A and 111B has an input terminal, an output terminal, and a power supply terminal 1111. Power amplifier 111A amplifies the transmission signal of the first communication frequency band input to the input terminal and outputs it from the output terminal. Power amplifier 111B amplifies the transmission signal of the second communication frequency band input to the input terminal and outputs it from the output terminal.

[0124] The input terminal of power amplifier 111A is connected to the selection terminal 191 of the fourth switch 109. The output terminal of power amplifier 111A is connected to the transmitting filter 112A. The input terminal of power amplifier 111B is connected to the selection terminal 192 of the fourth switch 109. The output terminal of power amplifier 111B is connected to the transmitting filter 112B. The power supply terminal 1111 of each of power amplifiers 111A and 111B is connected to the controller 107. Each power amplifier in power amplifiers 111A and 111B is controlled, for example, by the controller 107.

[0125] The fourth switch 109 has a common terminal 190 and multiple (two in the example) selectable terminals 191 and 192. The common terminal 190 is connected to the signal input terminal 82. The selectable terminal 191 is connected to the input terminal of the power amplifier 111A. The selectable terminal 192 is connected to the input terminal of the power amplifier 111B. The fourth switch 109 is, for example, a switch capable of connecting at least one of the multiple selectable terminals 191 and 192 to the common terminal 190. Here, the fourth switch 109 is, for example, a switch capable of both one-to-one and one-to-many connections. The fourth switch 109 is a switch that has the function of switching between multiple signal paths T11 and T12 for transmitting signals in different communication frequency bands.

[0126] The fourth switch 109 is controlled, for example, by the controller 107. The fourth switch 109 switches the connection state between the common terminal 190 and the multiple select terminals 191, 192 according to the control signal from the controller 107.

[0127] (2) Structure of the high-frequency module

[0128] like Figure 8 As shown, the high-frequency circuit 100d according to Embodiment 2 includes a mounting substrate 9. Hereinafter, the high-frequency circuit 100d including the mounting substrate 9 may also be referred to as a "high-frequency module 100d". Referring to... Figure 8 The structure of the high-frequency module 100d involved in Embodiment 2 will be explained.

[0129] like Figure 8 As shown, the high-frequency module 100d according to Embodiment 2 includes a mounting substrate 9, a first electronic component 1, a second electronic component 2, a sixth electronic component 6, and a plurality of external connection terminals 80 (see reference). Figure 1 The first electronic component 1 is, for example, a controller 107. The second electronic component 2 is, for example, an on / off switch 108. The sixth electronic component 6 is, for example, a fourth switch 109. In the high-frequency module 100d according to Embodiment 2, the controller 107, the on / off switch 108, and the fourth switch 109 are constituted by a single chip 10d. That is, the chip 10d includes the controller 107, the switch 108, and the fourth switch 109. Moreover, the chip 10d is disposed on the first main surface 91 side of the mounting substrate 9.

[0130] In the high-frequency module 100d according to Embodiment 2, the first electronic component 1, the second electronic component 2, and the sixth electronic component 6 are each composed of a single chip 10d. As a result, compared to the case where at least two of the first electronic component 1, the second electronic component 2, and the sixth electronic component 6 are composed of different chips, the area of ​​the mounting substrate 9 when viewed from the thickness direction D1 is smaller.

[0131] In the high-frequency module 100d according to Embodiment 2, although the illustration is omitted, when viewed from the thickness direction D1 of the mounting substrate 9, a portion of the control circuit 107 included in the chip 10d overlaps with a portion of the connection terminal 85. Therefore, it is possible to design a module where the wiring length between the control circuit 107 and the connection terminal 85 is shortened.

[0132] (Way)

[0133] The following methods are disclosed in this specification.

[0134] The high-frequency circuit (100; 100a-100d) involved in the first embodiment includes a power amplifier (111; 111A, 111B), a control circuit (107), an on / off switch (108), a connection terminal (85), and a mounting substrate (9). The power amplifier (111; 111A, 111B) has a power supply terminal (1111) and can support average power tracking mode and envelope tracking mode. The control circuit (107) is connected to the power supply terminal (1111) and controls the power amplifier (111; 111A, 111B) through average power tracking mode and envelope tracking mode. The on / off switch (108) is connected in series with a capacitor element (320), which is connected between the path (R2) between the control circuit (107) and the power supply terminal (1111) and ground. The connection terminal (85) is connected to the capacitor element (320). The mounting substrate (9) has a first main surface (91) and a second main surface (92) facing each other. When viewed from the thickness direction (D1) of the mounting substrate (9), the control circuit (107) overlaps with the connection terminal (85).

[0135] According to this method, in the average power point tracking (APST) mode, the on / off switch (108) is turned on to connect the capacitor element (320) to the path (R2). This suppresses the parasitic inductance of the path (R2), thereby stabilizing the power supply voltage to the power supply terminal (1111) in the APST mode. Furthermore, according to this method, the wiring length between the control circuit (107) and the connection terminal (85) can be shortened.

[0136] In the high-frequency circuit (100; 100a to 100d) involved in the second method, in the first method, the on / off switch (108) is connected between the path (R2) and the capacitor element (320).

[0137] According to this method, in the average power tracking mode, the on / off switch (108) is turned on to connect the capacitor element (320) to the path (R2). As a result, the parasitic inductance component of the path (R2) can be suppressed, and thus the power supply voltage to the power supply terminal (1111) can be stabilized in the average power tracking mode.

[0138] In the high-frequency circuit (100; 100a-100d) involved in the third method, in the first or second method, when the control circuit (107) controls the power amplifier (111; 111A, 111B) in the average power tracking mode, the control circuit (107) turns on the on / off switch (108). When the control circuit (107) controls the power amplifier (111; 111A, 111B) in the envelope tracking mode, the control circuit (107) turns off the on / off switch (108).

[0139] According to this method, in the average power tracking mode, the on / off switch (108) is turned on to connect the capacitor element (320) to the path (R2). As a result, the parasitic inductance component of the path (R2) can be suppressed, and thus the power supply voltage to the power supply terminal (1111) can be stabilized in the average power tracking mode.

[0140] In the high-frequency circuit (100a) involved in the fourth method, in any of the first to third methods, the power amplifier (111) is disposed on the first main surface (91) side. The control circuit (107) and the on / off switch (108) are disposed on the side of the power amplifier (111) opposite to the mounting substrate (9).

[0141] According to this method, compared to the case where the power amplifier (111) and the control circuit (107) and the on / off switch (108) are separately arranged on the first main surface (91), the area of ​​the mounting substrate (9) when viewed from the thickness direction (D1) of the mounting substrate (9) can be smaller.

[0142] In the high-frequency circuit (100) involved in the fifth method, in any of the first to third methods, the control circuit (107) and the on / off switch (108) are arranged on the first main surface (91) side.

[0143] In the high-frequency circuit (100; 100a; 100b) involved in the sixth method, in any of the first to fifth methods, the control circuit (107) and the on / off switch (108) are composed of a single chip (10).

[0144] According to this method, compared to the case where the control circuit (107) and the on / off switch (108) are composed of different chips, the area of ​​the mounting substrate (9) when viewed from the thickness direction (D1) of the mounting substrate (9) can be made smaller.

[0145] In the seventh method, the high-frequency circuit (100d) further includes a switching switch (109) in any of the first to fifth methods. The switching switch (109) is connected between multiple transmitting filters (112A, 112B) with different passbands and power amplifiers (111A, 111B). The control circuit (107), the on / off switch (108), and the switching switch (109) are composed of a single chip (10d).

[0146] According to this method, compared to the case where at least two of the control circuit (107), on / off switch (108) and switching switch (109) are composed of different chips, the area of ​​the mounting substrate (9) when viewed from the thickness direction (D1) of the mounting substrate (9) can be smaller.

[0147] The communication device (300; 300d) involved in the eighth method includes a high-frequency circuit (100; 100a to 100d) of any one of the first to seventh methods and a signal processing circuit (301). The signal processing circuit (301) is connected to the high-frequency circuit (100; 100a to 100d) and processes the high-frequency signal.

[0148] According to this method, in the average power point tracking (APST) mode, the on / off switch (108) is turned on to connect the capacitor element (320) to the path (R2). This suppresses the parasitic inductance of the path (R2), thereby stabilizing the power supply voltage to the power supply terminal (1111) in the APST mode. Furthermore, according to this method, the wiring length between the control circuit (107) and the connection terminal (85) can be shortened.

[0149] Explanation of reference numerals in the attached figures

[0150] 1: First electronic component; 2: Second electronic component; 3: Third electronic component; 4: Fourth electronic component; 5: Fifth electronic component; 6: Sixth electronic component; 9: Mounting substrate; 10, 10d: Chip; 13: Circuit board; 80: External connection terminal; 81: Antenna terminal; 82: Signal input terminal; 83: Signal output terminal; 84: Control terminal; 85: Connection terminal; 86: Ground terminal; 91: First main surface; 92: Second main surface; 100, 100a~100d: High-frequency circuit; 104: First switch; 105: Second switch; 106: Third switch; 107: Controller (control circuit); 108: On / off switch; 109: Fourth switch (toggle switch); 111, 111A, 111B: Power amplifier; 112A, 112B: Transmitting filter; 14: Matching circuit; 121: Low noise amplifier; 122A, 122B: Receiver filters; 124: Matching circuit; 131: First main surface; 132: Second main surface; 140: Common terminal; 141, 142: Select terminals; 150: Common terminal; 151, 152: Select terminals; 160: Common terminal; 161, 162: Select terminals; 190: Common terminal; 191, 192: Select terminals; 300, 300a~300d: Communication device; 301: Signal processing circuit; 302: RF signal processing circuit; 303: Baseband signal processing circuit; 310: Antenna; 320: Capacitor element; 1111: Power supply terminal; D1: Thickness direction; R1, R11, R12: Signal path; R2: Path; T1, T11, T12: Signal path.

Claims

1. A high-frequency circuit, comprising: A power amplifier with power supply terminals that supports both average power tracking and envelope tracking modes; A control circuit, connected to the power supply terminal, controls the power amplifier through the average power tracking method and the envelope tracking method; An on / off switch is connected in series with a capacitor element, which is connected between the path between the control circuit and the power supply terminal and ground. A connection terminal is provided, which is connected to the capacitor element; as well as The mounting substrate has a first main surface and a second main surface facing each other. When viewed from the thickness direction of the mounting substrate, the control circuit overlaps with the connection terminal. The control circuit and the on / off switch are both composed of a single chip.

2. The high-frequency circuit according to claim 1, wherein, The on / off switch is connected between the path and the capacitor element.

3. The high-frequency circuit according to claim 1 or 2, wherein, The control circuit performs the following actions: When the control circuit controls the power amplifier using the average power tracking method, the on / off switch is turned on. When the control circuit controls the power amplifier using the envelope tracking method, the on / off switch is turned off.

4. The high-frequency circuit according to claim 1 or 2, wherein, The power amplifier is disposed on the first main surface side. The control circuit and the on / off switch are located on the side of the power amplifier opposite to the mounting substrate.

5. The high-frequency circuit according to claim 1 or 2, wherein, The control circuit and the on / off switch are disposed on the first main surface side.

6. The high-frequency circuit according to claim 1 or 2, wherein, It also includes a switching switch connected between multiple transmitting filters having different passbands and the power amplifier. The control circuit, the on / off switch, and the switching switch are all composed of a single chip.

7. A communication device comprising: The high-frequency circuit according to any one of claims 1 to 6; and A signal processing circuit, which is connected to the high-frequency circuit, processes the high-frequency signal.

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