Three-dimensional memory devices and methods for forming the same

Abstract

In some aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with source contacts of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor and a second semiconductor layer in contact with the first transistor. The third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods of manufacturing the same.

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first and second semiconductor structures, and a second bonding interface between the second and third semiconductor structures. The first semiconductor structure includes a NAND flash memory string array and a first semiconductor layer in contact with the source of the NAND flash memory string array. The second semiconductor structure includes a first peripheral circuit of the NAND flash memory string array including a first transistor and a second semiconductor layer in contact with the first transistor. The third semiconductor structure includes a second peripheral circuit of the NAND flash memory string array including a second transistor and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is located between the first bonding interface and the second semiconductor layer. The second peripheral circuit is located between the second bonding interface and the third semiconductor layer.

[0005] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first and second semiconductor structures, and a second bonding interface between the second and third semiconductor structures. The first semiconductor structure includes a NAND flash memory string array and a first semiconductor layer in contact with the source of the NAND flash memory string array. The second semiconductor structure includes a first peripheral circuit of the NAND flash memory string array including a first transistor and a second semiconductor layer in contact with the first transistor. The third semiconductor structure includes a second peripheral circuit of the NAND flash memory string array including a second transistor and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is located between the first bonding interface and the second semiconductor layer. The second peripheral circuit is located between the second bonding interface and the third semiconductor layer. The system also includes a memory controller coupled to the memory device and configured to control the memory cell array via the first and second peripheral circuits.

[0006] In another aspect, a method for forming a 3D memory device is disclosed. A NAND memory string array is formed on a first substrate. A first transistor is formed on a second substrate. A second transistor is formed on a third substrate. The first and second substrates are bonded face-to-face. The third and second substrates are bonded back-to-back.

[0007] In another aspect, a method for forming a 3D memory device is disclosed. A NAND memory string array is formed on a first substrate. A first transistor is formed on a second substrate. A semiconductor layer, comprising monocrystalline silicon, is formed over the first transistor. A second transistor is formed on the semiconductor layer. The first and second substrates are bonded face-to-face. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the textual description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0009] Figure 1A A schematic diagram showing a cross-section of a 3D memory device according to some aspects of the present disclosure.

[0010] Figure 1B A schematic diagram showing a cross-section of another 3D memory device according to some aspects of this disclosure.

[0011] Figure 1C A schematic diagram showing a cross-section of another 3D memory device according to some aspects of the present disclosure.

[0012] Figure 1D A schematic diagram showing a cross-section of yet another 3D memory device according to some aspects of this disclosure.

[0013] Figure 2 A schematic circuit diagram of a memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0014] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0015] Figure 4A A block diagram of an external circuit provided with various voltages according to some aspects of this disclosure is shown.

[0016] Figure 4B A schematic diagram is shown of peripheral circuits arranged in a discrete semiconductor structure and supplied with various voltages, according to some aspects of this disclosure.

[0017] Figure 5A and Figure 5B Perspective and side views of a planar transistor according to some aspects of this disclosure are shown respectively.

[0018] Figure 6A and Figure 6B Perspective and side views of 3D transistors according to some aspects of this disclosure are shown respectively.

[0019] Figure 7 Circuit diagrams of word line drivers and page buffers according to some aspects of this disclosure are shown.

[0020] Figures 8A-8C A side view of various NAND memory strings in a 3D memory device according to various aspects of this disclosure is shown.

[0021] Figure 9A and Figure 9B A schematic diagram of a cross-section of a 3D memory device having three stacked semiconductor structures according to various aspects of the present disclosure is shown.

[0022] Figure 10A and Figure 10B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of the cross-section of the 3D memory device.

[0023] Figure 11A-11C Showing various aspects according to this disclosure Figure 10A and Figure 10B Side view of various examples of 3D memory devices.

[0024] Figures 12A-12H This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B The manufacturing process of 3D memory devices.

[0025] Figures 13A-13H This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B Another manufacturing process for 3D memory devices.

[0026] Figure 14 This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B A flowchart of a method for using a 3D memory device.

[0027] Figure 15 This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B A flowchart of a method for using a 3D memory device.

[0028] Figure 16Aand Figure 16B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of the cross-section of the 3D memory device.

[0029] Figures 17A-17C Showing various aspects according to this disclosure Figure 16A and Figure 16B Side view of various examples of 3D memory devices.

[0030] Figures 18A-18F This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B The manufacturing process of 3D memory devices.

[0031] Figures 19A-19F This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B Another manufacturing process for 3D memory devices.

[0032] Figure 20 This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B A flowchart of a method for using a 3D memory device.

[0033] Figure 21 This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B A flowchart of a method for using a 3D memory device.

[0034] Figure 22A and Figure 22B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of the cross-section of the 3D memory device.

[0035] Figures 23A-23C Showing various aspects according to this disclosure Figure 16A and Figure 16B Side view of various examples of 3D memory devices.

[0036] Figures 24A-24F This illustrates some aspects of the method for forming according to this disclosure. Figure 22A and Figure 22B The manufacturing process of 3D memory devices.

[0037] Figure 25A-25F This illustrates some aspects of the method for forming according to this disclosure. Figure 22A and Figure 22B Another manufacturing process for 3D memory devices.

[0038] Figure 26 This illustrates some aspects of the method for forming according to this disclosure. Figure 22A and Figure 22B A flowchart of a method for using a 3D memory device.

[0039] Figure 27 This illustrates some aspects of the method for forming according to this disclosure. Figure 22A and Figure 22B A flowchart of a method for using a 3D memory device.

[0040] Figure 28A and Figure 28B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of the cross-section of the 3D memory device.

[0041] Figure 29A and Figure 29B Showing various aspects according to this disclosure Figure 28A and Figure 28B Side view of various examples of 3D memory devices.

[0042] Figures 30A-30F This illustrates some aspects of the method for forming according to this disclosure. Figure 28A and Figure 28B The manufacturing process of 3D memory devices.

[0043] Figures 31A-31F This illustrates some aspects of the method for forming according to this disclosure. Figure 28A and Figure 28B Another manufacturing process for 3D memory devices.

[0044] Figure 32 This illustrates some aspects of the method for forming according to this disclosure. Figure 28A and Figure 28B A flowchart of a method for using a 3D memory device.

[0045] Figure 33 This illustrates some aspects of the method for forming according to this disclosure. Figure 28A and Figure 28B A flowchart of a method for using a 3D memory device.

[0046] Figure 34A and Figure 34B A schematic diagram of a cross-section of a 3D memory device having three stacked semiconductor structures according to various aspects of the present disclosure is shown.

[0047] Figure 35A and Figure 35B This disclosure illustrates some aspects of the present disclosure. Figure 34A and Figure 34B A schematic diagram of the cross-section of the 3D memory device.

[0048] Figure 36A and Figure 36B Showing various aspects according to this disclosure Figure 35A and Figure 35B Side view of various examples of 3D memory devices.

[0049] Figure 37A-37G This illustrates some aspects of the method for forming according to this disclosure. Figure 35A and Figure 35B The manufacturing process of 3D memory devices.

[0050] Figure 38 This illustrates some aspects of the method for forming according to this disclosure. Figure 35A and Figure 35B A flowchart of a method for using a 3D memory device.

[0051] Figure 39A and Figure 39B A schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various aspects of the present disclosure is shown.

[0052] Figure 40A and Figure 40B Showing various aspects according to this disclosure Figure 39A and Figure 39B Side view of various examples of 3D memory devices.

[0053] Figures 41A-41E This illustrates some aspects of the method for forming according to this disclosure. Figure 39A and Figure 39B The manufacturing process of 3D memory devices.

[0054] Figure 42A-42I This illustrates some aspects of the method for forming according to this disclosure. Figure 39A and Figure 39B Another manufacturing process for 3D memory devices.

[0055] Figure 43 This illustrates some aspects of the method for forming according to this disclosure. Figure 39A and Figure 39B A flowchart of a method for using a 3D memory device.

[0056] Figure 44A and Figure 44B A schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to some aspects of this disclosure is shown.

[0057] Figure 45A and Figure 45B This disclosure illustrates some aspects of the present disclosure. Figure 44A and Figure 44BA schematic diagram of the cross-section of the 3D memory device.

[0058] Figure 46A-46G This illustrates some aspects of the method for forming according to this disclosure. Figure 44A and Figure 44B The manufacturing process of 3D memory devices.

[0059] Figure 47 This illustrates some aspects of the method for forming according to this disclosure. Figure 44A and Figure 44B A flowchart of a method for using a 3D memory device.

[0060] Figures 48A-48D The manufacturing process of transfer bonding according to some aspects of this disclosure is illustrated.

[0061] Figures 49A-49D Another manufacturing process for transfer bonding according to some aspects of this disclosure is shown.

[0062] Figure 50 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0063] Figure 51A A diagram of an exemplary memory card having a memory device is shown according to some aspects of this disclosure.

[0064] Figure 51B A diagram illustrating an exemplary solid-state drive (SSD) having a memory device according to some aspects of this disclosure is shown.

[0065] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0066] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other in a manner not specifically depicted in the drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0067] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0068] It should be readily understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” not only means directly “on” something, but also includes the meaning of being “on” something with an intermediate feature or layer in between, and that “above” or “on top” not only means being “above” or “on top” something, but can also include the meaning of being “above” or “on top” something without an intermediate feature or layer in between (i.e., directly on something).

[0069] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein can be interpreted similarly accordingly.

[0070] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0071] With the development of 3D memory devices such as 3D NAND flash memory, more stacked layers (e.g., more word lines and thus more memory cells) require more peripheral circuitry (and components forming the peripheral circuitry, such as transistors) to operate the 3D memory device. For example, the number and / or size of page buffers need to increase to match the increased number of memory cells. In another example, the number of string drivers in the word line drivers is proportional to the number of word lines in the 3D NAND flash memory. Therefore, the increasing number of word lines also increases the area occupied by the word line drivers, as well as the complexity of metal wiring, and sometimes even the number of metal layers. Furthermore, in some 3D memory devices, the memory cell array and peripheral circuitry are fabricated on different substrates and bonded together. Since the memory cell array can be vertically scaled up by increasing the number of layers rather than increasing the planar size, the increasing area of ​​the peripheral circuitry becomes a bottleneck for reducing the overall chip size.

[0072] Therefore, it is desirable to reduce the planar area occupied by the peripheral circuitry of 3D memory devices while increasing the number of peripheral circuits and their transistors. However, scaling the transistor size of peripheral circuitry in line with the advanced complementary metal-oxide-semiconductor (CMOS) technology nodes of logic devices would lead to a significant increase in cost and higher leakage current, which is undesirable for memory devices. Furthermore, because 3D NAND flash memory devices require relatively high voltages (e.g., above 5V) for certain memory operations (e.g., programming and erasing), unlike logic devices which can reduce their operating voltage with advancements in CMOS technology nodes, the voltage supplied to the memory peripheral circuitry cannot be reduced. Consequently, scaling the size of the memory peripheral circuitry in line with the advanced CMOS technology nodes, as is the case with conventional logic devices, becomes impractical.

[0073] To address one or more of the aforementioned problems, this disclosure proposes various solutions in which the peripheral circuitry of the memory device is arranged vertically in different planes (layers, steps), i.e., stacked on top of each other, to reduce the planar chip size of the peripheral circuitry and the overall chip size of the memory device. In some embodiments, the memory cell array (e.g., a NAND memory string), the memory peripheral circuitry supplied with a relatively high voltage (e.g., above 5V), and the memory peripheral circuitry supplied with a relatively low voltage (e.g., below 1.3V) are arranged vertically in different planes, i.e., stacked on top of each other, to further reduce the chip size. The 3D memory device architecture and manufacturing process disclosed in this disclosure can be easily vertically scaled up to stack more peripheral circuitry in different planes, thereby further reducing the chip size.

[0074] Based on different performance requirements, such as the voltage applied to the transistors in the peripheral circuitry (which affects transistor dimensions (e.g., gate dielectric thickness)), the dimensions of the substrate forming the transistors (e.g., substrate thickness), and the thermal budget (e.g., interconnect materials), the peripheral circuitry can be separated into different planes in the vertical direction. Therefore, peripheral circuitry with different dimensional requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budgets can be fabricated in different processes to reduce mutual design and process constraints, thereby improving device performance and manufacturing complexity.

[0075] According to some aspects of this disclosure, arrays of memory cells and various peripheral circuits with different performance and size requirements can be fabricated in parallel on different substrates and then stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding. As a result, the manufacturing cycle of the memory device can be further reduced. Furthermore, since the thermal budgets of the different devices become independent, interconnect materials with desired electrical properties but low thermal budgets, such as copper, can be used for interconnecting the memory cells and transistors of the peripheral circuits, thereby further improving device performance. Bonding techniques can also provide additional benefits. In some embodiments, hybrid bonding performed face-to-face achieves millions of parallel short interconnects between the bonded semiconductor structures to increase the throughput and input / output (I / O) speed of the memory device. In some embodiments, transfer bonding reuses a single wafer to transfer its thin semiconductor layer onto different memory devices for forming transistors thereon, which can reduce the cost of the memory device.

[0076] The 3D memory device architecture and manufacturing process disclosed in this disclosure offer flexibility in allowing for a variety of substrate materials to be used in different memory cell array designs, such as NAND memory strings suitable for gate-induced drain-leakage (GIDL) erase operations or P-type batch erase operations. In some embodiments, monocrystalline silicon (also known as single-crystal silicon or monocrystalline silicon-based silicon) with excellent carrier electronic properties—the lack of grain boundaries allows for better charge carrier flow and prevents electron recombination—is used as the substrate material for NAND memory string arrays to achieve faster memory operations. In some embodiments, polycrystalline silicon (also known as polysilicon) is used as the substrate material for NAND memory string arrays for GIDL erase operations.

[0077] The 3D memory device architecture and manufacturing process disclosed in this disclosure also offer flexibility to allow for various device pad lead-out schemes to meet the diverse needs and designs of memory cell arrays. In some embodiments, the pad lead-out interconnect layer is formed from the side of a semiconductor structure with peripheral circuitry to shorten the interconnect distance between the pad lead-out interconnect layer and the transistors of the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving electrical performance. In some embodiments, the pad lead-out interconnect layer is formed on a thinned substrate in which the memory cell array is formed to enable interlayer vias (LLVs, e.g., submicron scale) for pad lead-out interconnects with high I / O throughput and low manufacturing complexity.

[0078] Figure 1A A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. In some embodiments, at least some components of the 3D memory device 100 (e.g., memory cell arrays and peripheral circuitry) are individually formed in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process"). In some embodiments, at least one semiconductor layer is attached to another semiconductor structure using transfer bonding, and then some components of the 3D memory device 100 (e.g., memory cell arrays and peripheral circuitry) are formed on the attached semiconductor layer (a process referred to herein as a "serial process"). It should be understood that in some examples, components of the 3D memory device 100 (e.g., memory cell arrays and peripheral circuitry) can be formed by a hybrid process combining parallel and serial processes.

[0079] Note that in Figure 1A An x-axis and a y-axis have been added to further illustrate the spatial relationships of the components of a semiconductor device. The substrate of a semiconductor device (e.g., a 3D memory device 100) includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral or width direction). As used herein, when the substrate is located in the lowest surface of the semiconductor device in the y-direction (vertical or thickness direction), whether one component (e.g., a layer or device) of the semiconductor device is "above," "on top of," or "below" another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the y-direction. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0080] The 3D memory device 100 may include a first semiconductor structure 102 comprising a memory cell array (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array may be used as an example to describe a memory cell array in this disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase-change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin-transfer torque (STT) memory cell array, to name just a few.

[0081] The first semiconductor structure 102 may be a NAND flash memory device, wherein memory cells are provided in the form of a 3D NAND memory string array and / or a two-dimensional (2D) NAND memory cell array. NAND memory cells may be organized into pages or fingers, and then the pages or fingers may be organized into blocks, wherein each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in the NAND memory cell having the same vertical position may be coupled by word lines (WL) via control gates. In some embodiments, the memory surface comprises a number of blocks coupled via the same bit lines. The first semiconductor structure 102 may include one or more memory surfaces, and the peripheral circuitry required to perform all read / program (write) / erase operations may be included in the second semiconductor structure 104 and the third semiconductor structure 106.

[0082] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, with each 2D NAND memory cell including a floating-gate transistor. According to some embodiments, the 2D NAND memory cell array includes multiple 2D NAND memory strings, each 2D NAND memory string including multiple memory cells (similar to NAND gates) connected in series and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., a flat two-dimensional (2D) surface, as opposed to the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, with each 3D NAND memory string extending vertically through a stacked structure (e.g., a memory stack) above the substrate (3D). Depending on the 3D NAND technology (e.g., the number of layers / steps in the memory stack), a 3D NAND memory string typically includes a number of NAND memory cells, each NAND memory cell including a floating-gate transistor or a charge-trapping transistor.

[0083] like Figure 1A As shown, the 3D memory device 100 may further include a second semiconductor structure 104 and a third semiconductor structure 106, both of which include some peripheral circuitry of the memory cell array in the first semiconductor structure 102. That is, the peripheral circuitry of the memory cell array can be separated into at least two other semiconductor structures (e.g., Figure 1A In structures 104 and 106 of the second and third semiconductor structures, the peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array. For example, the peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the second and third semiconductor structures 104 and 106 may be implemented using CMOS technology, for example, using logic processes at any suitable technology node.

[0084] like Figure 1A As shown, according to some embodiments, the first, second, and third semiconductor structures 102, 104, and 106 are stacked on top of each other in different planes. As a result, compared to a memory device in which all peripheral circuits are disposed in the same plane, the memory cell array in the first semiconductor structure 102, the peripheral circuits in the second semiconductor structure 104, and the peripheral circuits in the third semiconductor structure 106 can be stacked on top of each other in different planes to reduce the planar size of the 3D memory device 100.

[0085] like Figure 1A As shown, the 3D memory device 100 also includes a first bonding interface 103 perpendicularly located between the first semiconductor structure 102 and the second semiconductor structure 104, and a second bonding interface 105 perpendicularly located between the second semiconductor structure 104 and the third semiconductor structure 106. The first and second bonding interfaces 103 or 105 can be interfaces between two semiconductor structures formed by any suitable bonding technique described in detail below, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and a few other examples. Figure 1A In some embodiments shown, the second semiconductor structure 104 is bonded to the other two semiconductor structures 102 and 106 on its opposite side. That is, the second semiconductor structure 104 may be vertically positioned between the first and third semiconductor structures 102 and 106.

[0086] In some embodiments, each of the second and third semiconductor structures 104 and 106 does not include any memory cells. In other words, according to some embodiments, each of the second and third semiconductor structures 104 and 106 includes only peripheral circuitry and does not include a memory cell array. As a result, the memory cell array may be included only in the first semiconductor structure 102 and not in the second or third semiconductor structure 104 or 106. Furthermore, the number of semiconductor structures including peripheral circuitry may differ from the number of semiconductor structures including memory cell arrays. In some embodiments, the number of semiconductor structures including peripheral circuitry is greater than the number of semiconductor structures including memory cell arrays. For example, as... Figure 1A As shown, the number of semiconductor structures including peripheral circuits is 2 (i.e., 104 and 106), while the number of semiconductor structures including memory cell arrays is 1 (i.e., 102).

[0087] It should be understood that the relative positions of the stacked first, second, and third semiconductor structures 102, 104, and 106 are not restricted and can vary in different examples. Figure 1B A schematic cross-sectional view of another exemplary 3D memory device 101 according to some embodiments is shown. Figure 1A In the 3D memory device 100, a second semiconductor structure 104, including some peripheral circuits, is vertically located between a first semiconductor structure 102, including a memory cell array, and a third semiconductor structure 106, including some peripheral circuits. This differs from the previous approach. Figure 1B In the 3D memory device 101, a first semiconductor structure 102, including an array of memory cells, lies between second and third semiconductor structures 104 and 106, each including some peripheral circuitry. However, in the 3D memory device 101, a first bonding interface 103 can still be formed vertically between the first and second semiconductor structures 102 and 104. Instead of a second bonding interface 105 vertically located between the second and third semiconductor structures 104 and 106, the 3D memory device 101 can include a third bonding interface 107 vertically located between the first and third semiconductor structures 102 and 106. Similar to the first and second bonding interfaces 103 and 105, the third bonding interface 107 can be an interface between two semiconductor structures formed by any suitable bonding technique as described in detail above, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name just a few. Figure 1B In some of the embodiments shown, the first semiconductor structure 102 is bonded to two other semiconductor structures 104 and 106 on its opposite sides.

[0088] As described in detail below, some or all of the first, second, and third semiconductor structures 102, 104, and 106 can be fabricated individually (and in some embodiments in parallel) through parallel processes, such that the thermal budget for fabricating one of the first, second, and third semiconductor structures 102, 104, and 106 does not limit the process for fabricating another of the first, second, and third semiconductor structures 102, 104, and 106. Furthermore, a large number of interconnects (e.g., bonding contacts and / or interlayer vias (ILVs) / through-substrate vias (TSVs)) can be formed across bonding interfaces 103, 105, and 107 to form direct, short-distance (e.g., micrometer- or submicrometer-scale) electrical connections between adjacent semiconductor structures 102, 104, and 106, as opposed to long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on circuit boards such as printed circuit boards (PCBs), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between memory cell arrays and different peripheral circuits in different semiconductor structures 102, 104, and 106 can be performed via interconnects (e.g., bonding contacts and / or ILV / TSV) across bonding interfaces 103, 105, and 107. By vertically integrating the first, second, and third semiconductor structures 102, 104, and 106, chip size can be reduced and memory cell density can be increased.

[0089] It should also be understood that the number of bonding interfaces in a 3D memory device is unlimited and can vary in different examples. Figure 1C A schematic cross-sectional view of another exemplary 3D memory device 120 according to some embodiments is shown. Similar to 3D memory devices 100 and 101, at least two portions of the memory cell array and peripheral circuitry can be stacked on top of each other in different faces of the 3D memory device 120. However, unlike 3D memory devices 100 and 101 which include two bonding interfaces 103 and 105 or 103 and 107, according to some embodiments, 3D memory device 120 includes a single bonding interface 109 perpendicularly located between a first semiconductor structure 102 in which the memory array is disposed and a fourth semiconductor structure 108 in which two separate portions of the peripheral circuitry are disposed. That is, the two vertically separated portions of the peripheral circuitry are not separated by the bonding interface due to the bonding process, but are disposed on opposite sides of the same semiconductor layer 112 (e.g., a thinned silicon substrate) in the fourth semiconductor structure 108. Depending on the thickness of the semiconductor layer 112, interconnects (e.g., submicron-level ILVs, micron-level or tens of micron-level TSVs) can be formed through the semiconductor layer 112 to form direct, short-distance (e.g., submicron to tens of micron-level) electrical connections between different portions of the peripheral circuitry on opposite sides of the semiconductor layer 112 in the fourth semiconductor structure 108.

[0090] It should also be understood that the type of device disposed on the opposite side of semiconductor layer 112 is not limited and can vary in different examples. Figure 1D A schematic cross-sectional view of another exemplary 3D memory device 121 according to some embodiments is shown. Similar to 3D memory devices 100, 101, and 120, at least two portions of the memory cell array and peripheral circuitry can be stacked on top of each other in different faces of the 3D memory device 121. Unlike Figure 1C In a 3D memory device 120, two peripheral circuits are formed on opposite sides of semiconductor layer 112. In a 3D memory device 121, a memory cell array and some peripheral circuits are formed on opposite sides of semiconductor layer 112 in a fifth semiconductor structure 110. That is, according to some embodiments, 3D memory device 121 may include a single bonding interface 111 perpendicularly located between a second semiconductor structure 104 (or a third semiconductor structure 106) having some peripheral circuits and a fifth semiconductor structure 110 in which the memory cell array and some peripheral circuits are disposed. Similar to 3D memory device 120, depending on the thickness of semiconductor layer 112, interconnects (e.g., submicron-level ILVs or micron- or tens of micron-level TSVs) can be formed through semiconductor layer 112 to form direct, short-distance (e.g., submicron to tens of micron-level) electrical connections between some peripheral circuits and the memory cell array on opposite sides of semiconductor layer 112 in the fifth semiconductor structure 110. It should be understood that the number of stacked semiconductor structures in 3D memory devices 100, 101, 120, and 121 is not limited to... Figure 1A-1D The example shown illustrates this, and additional semiconductor structures can be further stacked vertically. Figure 1A-1D Above, below, or between the semiconductor structure shown.

[0091] Figure 2A schematic circuit diagram of a memory device 200 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. 3D memory devices 100, 101, 120, and 121 may be examples of the memory device 200, wherein at least two portions of the memory cell array 201 and the peripheral circuitry 202 may be included in various stacked semiconductor structures 102, 104, 106, 108, and 110. The memory cell array 201 may be a NAND flash memory cell array, wherein memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0092] In some implementations, each memory cell 206 is a single-level cell (SLC) with two possible memory states and thus can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, while a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used for the erase state.

[0093] like Figure 2As shown, each NAND memory string 208 may include a source-select-gate (SSG) transistor 210 at its source end and a drain-select-gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate the selected NAND memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND memory strings 208 in the same block 204 are coupled to ground via the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0094] like Figure 2 As shown, NAND memory strings 208 can be organized into multiple blocks 204, each block potentially having a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is a basic data unit for program and read operations. The size of a page 220, in bits, can correspond to the number of NAND memory strings 208 coupled by word lines 218 in a block 204. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 in the corresponding page 220 and gate lines coupling the control gates.

[0095] Figures 8A-8C A side view of various NAND memory strings 208 in a 3D memory device according to various aspects of this disclosure is shown. Figure 8AAs shown, the NAND memory string 208 can extend vertically through the memory stack 804 above the substrate 802. The substrate 802 can be a semiconductor layer including silicon (e.g., single-crystal silicon, c-silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the substrate 802 includes single-crystal silicon.

[0096] The memory stack 804 may include staggered gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 in the memory stack 804 determines the number of memory cells 206 in the memory cell array 201. The gate conductive layers 806 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 806 includes a doped polysilicon layer. Each gate conductive layer 806 may include a control gate surrounding a memory cell, a gate of a DSG transistor 212, or a gate of an SSG transistor 210, and may extend laterally as a DSG line 213 at the top of the memory stack 804, an SSG line 215 at the bottom of the memory stack 804, or a word line 218 between DSG lines 213 and SSG lines 215.

[0097] like Figure 8AAs shown, the NAND memory string 208 includes a channel structure 812A extending vertically through the memory stack 804. In some embodiments, the channel structure 812A includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel 820) and a dielectric material (e.g., as a memory film 818). In some embodiments, the semiconductor channel 820 includes silicon, such as polysilicon. In some embodiments, the memory film 818 is a composite dielectric layer including a tunneling layer 826, a storage layer 824 (also referred to as a "charge trap / storage layer"), and a barrier layer 822. The channel structure 812A may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 820, tunneling layer 826, storage layer 824, and barrier layer 822 are arranged radially from the center of the pillar toward the outer surface in this order. The tunneling layer 826 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 822 may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 818 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure 812A may also include a channel plug 816 on the drain terminal of the NAND memory string 208. The channel plug 816 may comprise polysilicon and contact the semiconductor channel 820.

[0098] like Figure 8A As shown, the NAND memory string 208 may also include a semiconductor plug 814 on its source end, which contacts the semiconductor channel 820 of the channel structure 812A. The semiconductor plug 814 (also referred to as selective epitaxial growth (SEG)) can be selectively grown from the substrate 802 and therefore has the same material as the substrate 802, such as single-crystal silicon. The semiconductor plug 814 on the source end of the NAND memory string 208 (e.g., in…) Figure 8A The channel structure 812A that contacts the bottom of the NAND memory string 208 shown in the diagram is referred to herein as the “bottom plug channel structure” 812A.

[0099] like Figure 8AAs shown, the slot structure 828A can extend vertically through the memory stack 804 and contact the substrate 802. The slot structure 828A may include source contacts 830 having a conductive material such as polysilicon, metal, metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide, and wells 832 (e.g., P-wells and / or N-wells) in the substrate 802. In some embodiments, the source contacts 830 and wells 832 of the slot structure 828A, the portion of the substrate 802 between the slot structure 828A and the channel structure 812A, and the semiconductor plug 814 serve as portions of a source line 214 coupled to the source of the NAND memory string 208, for example, to apply an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0100] Unlike Figure 8A The bottom plug channel structure 812A in the middle, such as Figure 8B As shown, according to some embodiments, the NAND memory string 208 includes a sidewall plug channel structure 812B and has no semiconductor plug 814 at its source end. Instead, a sidewall semiconductor layer 803, vertically located between the substrate 802 and the memory stack 804, may contact the sidewall of the semiconductor channel 820 of the channel structure 812B. The sidewall semiconductor layer 803 may comprise a semiconductor material, such as polysilicon. Also different from... Figure 8A The slit structure 828A in the middle, such as Figure 8B As shown, according to some embodiments, the slot structure 828B does not include the well 832, and the source contact 830 of the slot structure 828B contacts the sidewall semiconductor layer 803. In some embodiments, the source contact 830 of the slot structure 828B and the sidewall semiconductor layer 803 together serve as a portion of the source line 214 coupled to the source of the NAND memory string 208, for example, to apply an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0101] like Figure 8C As shown, in some embodiments, substrate 802 (e.g., having monocrystalline silicon) is replaced by semiconductor layer 805, which contacts the semiconductor channel 820 of bottom-aperture channel structure 812C on the source end of NAND memory string 208. A portion of the memory film 818 of channel structure 812C on the source end can be removed to expose semiconductor channel 820 to contact semiconductor layer 805. In some embodiments, a portion of semiconductor channel 820 on the source end of NAND memory string 208 is doped to form a doped region 834 in contact with semiconductor layer 805. Semiconductor layer 805 may include a semiconductor material, such as polycrystalline silicon. In some embodiments, semiconductor layer 805 includes N-type doped polycrystalline silicon to enable GILD erase operations. Also different from... Figure 8A and Figure 8B The slot structures 828A and 828B in the middle, such as Figure 8C As shown, according to some embodiments, the slot structure 828C does not include the source contact 830 and therefore is not used as part of the source line 214. Instead, the source contact (not shown) may be formed on the opposite side of the semiconductor layer 805 relative to the channel structure 812C, such that the source contact and a portion of the semiconductor layer 805 may be used as portions of the source line 214 coupled to the source of the NAND memory string 208, for example, to apply an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0102] refer to Figure 2 The peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry to facilitate operation of the memory cell array 201 by applying and sensing voltage and / or current signals traveling to and from each target memory cell 206 via bit line 216 through word line 218, source line 214, SSG line 215, and DSG line 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 Some exemplary peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 may also be included in some examples.

[0103] Page buffer 304 can be configured to buffer data read from or programmed into memory cell array 201 according to control signals from control logic unit 312. In one example, page buffer 304 can store a page of programming data (write data) in a page 220 to be programmed into memory cell array 201. In another example, page buffer 304 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218.

[0104] The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and the selected block 204 of the memory cell array 201, as well as the word line 218 of the selected block 204. The row decoder / word line driver 308 can be further configured to drive the memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from the voltage generator 310 to drive a memory cell 206 coupled to the selected word line 218.

[0105] The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and to select one or more 3D NAND memory strings 208 by applying a bit line voltage generated from the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select a set of N bits of data to be output in a read operation from the page buffer 304.

[0106] The control logic unit 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. The register 314 can be coupled to the control logic unit 312 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit 202.

[0107] Interface 316 may be coupled to control logic unit 312 and configured to interface memory cell array 201 with memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from memory controller and / or host (not shown) to control logic unit 312, and to buffer and relay status information received from control logic unit 312 to memory controller and / or host. Interface 316 may also be coupled to page buffer 304 and column decoder / bit line driver 306 via data bus 318, and acts as an I / O interface and data buffer to buffer and relay programming data received from memory controller and / or host to page buffer 304, and to buffer and relay read data received from page buffer 304 to memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202.

[0108] Voltage generator 310 can be configured to be controlled by control logic unit 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 201. In some embodiments, voltage generator 310 is part of a voltage source that provides voltages at various levels of different peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 exceed certain levels sufficient to perform memory operations. For example, the voltage supplied to the page buffer circuitry in page buffer 304 and / or the logic circuitry in control logic unit 312 may be between 1.3V and 5V, such as 3.3V, and the voltage supplied to the drive circuitry in row decoder / word line driver 308 and / or column decoder / bit line driver 306 may be between 5V and 30V.

[0109] Unlike logic devices (e.g., microprocessors), memory devices such as 3D NAND flash memory require a wide range of voltages to supply various peripheral memory circuits. For example, Figure 4A Block diagrams are shown of peripheral circuitry provided with various voltages according to some aspects of this disclosure. In some embodiments, a memory device (e.g., memory device 200) includes a low-low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3). For example, Vdd3 > Vdd2 > Vdd1. Each voltage source 401, 403, or 405 can receive a voltage input of an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 may also include a voltage converter and / or voltage regulator to convert the external voltage input to the corresponding level (Vdd1, Vdd2, or Vdd3) and maintain and output the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) via a corresponding power rail. In some embodiments, a voltage generator 310 of the memory device 200 is part of voltage sources 401, 403, and 405.

[0110] In some implementations, the LLV source 401 is configured to provide a voltage below 1.3V, for example, between 0.9V and 1.2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, any range whose lower end is defined by any of these values, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 403 is configured to provide a voltage between 1.3V and 3.3V (e.g., 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range whose lower end is defined by any of these values, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, HV source 405 is configured to provide a voltage greater than 3.3V, for example, between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range whose lower end is defined by any of these values, or any range defined by any two of these values). It should be understood that the voltage ranges described above with respect to HV source 405, LV source 403, and LLV source 401 are for illustrative purposes and not limiting, and that HV source 405, LV source 403, and LLV source 401 can provide any other suitable voltage range.

[0111] Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), memory peripheral circuits (e.g., peripheral circuit 202) can be classified as LLV circuit 402, LV circuit 404, and HV circuit 406, which can be coupled to LLV source 401, LV source 403, and HV source 405, respectively. In some embodiments, HV circuit 406 includes one or more drive circuits coupled to the memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and the drive circuits are configured to drive the memory cell array by applying an appropriate level of voltage to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuit 406 may include word line drive circuitry (e.g., in row decoder / word line driver 308) coupled to the word line and applying a programming voltage (Vprog) or pass voltage (Vpass) in the range of, for example, 5V to 30V to the word line during programming operations. In another example, HV circuit 406 may include bit line drive circuitry (e.g., in column decoder / bit line driver 306) coupled to the bit line and applying an erase voltage (Veras) in the range of, for example, 5V to 30V to the bit line during erase operations. In some implementations, LV circuit 404 includes page buffer circuitry (e.g., in the latch of page buffer 304) and is configured to buffer data read from or programmed into the memory cell array. For example, a voltage of, for example, 3.3V may be provided to the page buffer via LV source 403. LV circuit 404 may also include logic circuitry (e.g., in control logic unit 312). In some implementations, the LLV circuit 402 includes I / O circuitry (e.g., in interface 316 and / or data bus 318) configured to interface the memory cell array with a memory controller. For example, the I / O circuitry may be supplied with a voltage of, for example, 1.2V by the LLV source 401.

[0112] As described above, in order to reduce the total area occupied by the memory peripheral circuitry, the peripheral circuitry 202 can be formed separately in different planes based on different performance requirements such as the applied voltage. For example, Figure 4BSchematic diagrams are shown of peripheral circuits provided with various voltages in separate semiconductor structures arranged according to some aspects of this disclosure. In some embodiments, the LLV circuit 402 and HV circuit 406 are separate, for example, in semiconductor structures 408 and 410, respectively, because they have significant voltage differences and resulting device size differences, such as different semiconductor layer (e.g., substrate or thinned substrate) thicknesses and different gate dielectric thicknesses. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the HV circuit 406 is formed in semiconductor structure 410 may be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the LLV circuit 402 is formed in semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistor forming the HV circuit 406 may be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402. For example, the thickness may differ by at least a factor of 5. It should be understood that the stacked LLV circuit 402 and HV circuit 406 on different surfaces can be formed in two semiconductor structures 408 or 410 separated by a bonding interface (e.g., in...). Figure 1A and Figure 1B (in the middle) or formed on the opposite side of the semiconductor layer (e.g., in the middle) Figure 1C and Figure 1D middle).

[0113] The LV circuit 404 can be formed in semiconductor structures 408 or 410, or in another semiconductor, i.e., in the same plane as the LLV circuit 402 or HV circuit 406, or in a different plane from the LLV circuit 402 and HV circuit 406. For example... Figure 4BAs shown, in some embodiments, some of the LV circuits 404 are formed in the semiconductor structure 408, i.e., in the same plane as the LLV circuit 402, while some of the LV circuits 404 are formed in the semiconductor structure 410, i.e., in the same plane as the HV circuit 406. That is, the LV circuits 404 can also be separated into different planes. For example, when the same voltage is applied to the LV circuits 404 in different semiconductor structures 408 and 410, the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 408 can be the same as the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 410. In some embodiments, the same voltage is applied to the LV circuits 404 in semiconductor structure 408 and 410 such that the voltage applied to the HV circuit 406 in semiconductor structure 410 is higher than the voltage applied to the LV circuits 404 in semiconductor structures 408 or 410, and this voltage is also higher than the voltage applied to the LLV circuit 402 in semiconductor structure 408. Furthermore, according to some embodiments, since the voltage applied to the LV circuit 404 is between the voltages applied to the HV circuit 406 and the LLV circuit 402, the thickness of the gate dielectric of the transistor forming the LV circuit 404 is between the thickness of the gate dielectric of the transistor forming the HV circuit 406 and the thickness of the gate dielectric of the transistor forming the LLV circuit 402. For example, the thickness of the gate dielectric of the transistor forming the LV circuit 404 can be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402, but less than the thickness of the gate dielectric of the transistor forming the HV circuit 406.

[0114] Based on different performance requirements (e.g., associated with different applied voltages), the peripheral circuitry 202 can be isolated into at least two stacked semiconductor structures 408 and 410 on different faces. In some embodiments, the I / O circuitry in the interface 316 and / or data bus 318 (as LLV circuitry 402) and the logic circuitry in the control logic unit 312 (as part of the LV circuitry) are disposed in semiconductor structure 408, while the page buffer circuitry in page buffer 304 and the drive circuitry in row decoder / word line driver 308 and column decoder / bit line driver 306 are disposed in semiconductor structure 410. For example, Figure 7 A circuit diagram of a word line driver 308 and a page buffer 304 according to some aspects of this disclosure is shown.

[0115] In some embodiments, page buffer 304 includes a plurality of page buffer circuits 702, each page buffer circuit 702 coupled to a NAND memory string 208 via a corresponding bit line 216. That is, memory device 200 may include bit lines 216 coupled to the NAND memory string 208, and page buffer 304 may include page buffer circuits 702 coupled to both bit lines 216 and the NAND memory string 208. Each page buffer circuit 702 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic units, sensing circuitry, etc. In some embodiments, each page buffer circuit 702 is configured to store sensing data corresponding to read data received from the corresponding bit line 216 and to output the stored sensing data during a read operation; each page buffer circuit 702 is also configured to store programming data and to output the stored programming data to the corresponding bit line 216 during a programming operation.

[0116] In some embodiments, word line driver 308 includes a plurality of string drivers 704 (also known as drive circuitry) respectively coupled to word line 218. Word line driver 308 may also include a plurality of local word lines 706 (LWLs) respectively coupled to string drivers 704. Each string driver 704 may include a gate coupled to a decoder (not shown), a source / drain coupled to the corresponding local word line 706, and another source / drain coupled to the corresponding word line 218. In some memory operations, the decoder may, for example, select certain string drivers 704 by applying a voltage signal greater than a threshold voltage of string driver 704 and a voltage (e.g., programming voltage, pass voltage, or erase voltage) to each local word line 706, such that each selected string driver 704 applies the voltage to the corresponding word line 218. Conversely, the decoder may also deselect certain string drivers 704, for example, by applying a voltage signal less than a threshold voltage of string driver 704, such that each deselected string driver 704 floats the corresponding word line 218 during memory operations.

[0117] In some embodiments, the page buffer circuit 702 includes a portion of the LV circuit 404 disposed in the semiconductor structures 408 and / or 410. In one example, since the number of page buffer circuits 702 increases with the number of bits, and the increase in the number of bits may occupy a large area of ​​the memory device with a large number of memory cells, the page buffer circuit 702 can be divided into semiconductor structures 408 and 410. In some embodiments, the serial driver 704 includes a portion of the HV circuit 406 disposed in the semiconductor structure 410.

[0118] Consistent with the scope of this disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (also known as planar transistors) or 3D (metal-oxide-semiconductor field-effect transistors) (MOSFETs). For example, Figure 5A and Figure 5B Perspective and side views of a planar transistor 500 according to some aspects of this disclosure are shown respectively, and Figure 6A and Figure 6B Perspective and side views of a 3D transistor 600 according to some aspects of this disclosure are shown respectively. Figure 5B Show Figure 5A A side view of the cross-section of the planar transistor 500 in the BB plane, and Figure 6B Show Figure 6A A side view of the 3D transistor 600 in the BB plane.

[0119] like Figure 5A and Figure 5B As shown, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaA, Ge, SOI, or any other suitable material. Trench isolation 503, such as shallow trench isolation (STI), may be formed in the substrate 502 and between adjacent planar transistors 500 to reduce current leakage. The trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., alumina, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric with a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, the trench isolation 503 includes silicon oxide.

[0120] like Figure 5A and Figure 5B As shown, the planar transistor 500 may further include a gate structure 508 on the substrate 502. In some embodiments, the gate structure 508 is on the top surface of the substrate 502. Figure 5BAs shown, the gate structure 508 may include a gate dielectric 507 on the substrate 502, that is, a gate dielectric 507 above and in contact with the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on the gate dielectric 507, that is, a gate electrode 509 above and in contact with the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 507 includes silicon oxide, that is, a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 509 includes doped polysilicon, that is, gate polysilicon.

[0121] like Figure 5A As shown, the planar transistor 500 may further include a pair of source and drain electrodes 506 in the substrate 502. The source and drain electrodes 506 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or with any suitable N-type dopant, such as phosphorus (P) or arsenic (As). In the planar view, the source and drain electrodes 506 may be separated by a gate structure 508. In other words, according to some embodiments, in the planar view, the gate structure 508 is formed between the source and drain electrodes 506. When the gate voltage applied to the gate electrode 509 of the gate structure 508 exceeds the threshold voltage of the planar transistor 500, a channel of the planar transistor 500 may be laterally formed in the substrate 502 below the gate structure 508, between the source and drain electrodes 506. Figure 5A and Figure 5B As shown, the gate structure 508 can be above and contacted on the top surface of the portion of the substrate 502 where a channel can be formed (the active region). That is, according to some embodiments, the gate structure 508 only contacts one side of the active region, i.e., in the plane of the top surface of the substrate 502. It should be understood that although not in... Figure 5A and Figure 5B As shown, however, the planar transistor 500 may include additional components such as wells and spacers.

[0122] like Figure 6A and Figure 6BAs shown, the 3D transistor 600 may be a MOSFET on a substrate 602, which may include silicon (e.g., monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 602 comprises monocrystalline silicon. A trench isolation 603, such as STI, may be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the trench isolation 603 comprises silicon oxide.

[0123] like Figure 6A and Figure 6B As shown, unlike the planar transistor 500, the 3D transistor 600 may also include a 3D semiconductor body 604 above the substrate 602. That is, in some embodiments, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602, thereby exposing not only the top surface of the 3D semiconductor body 604 but also both side surfaces. For example, as... Figure 6A and Figure 6B As shown, the 3D semiconductor body 604 can be a 3D structure, also referred to as a "fin," to expose its three sides. According to some embodiments, the 3D semiconductor body 604 is formed from a substrate 602 and therefore has the same semiconductor material as the substrate 602. In some embodiments, the 3D semiconductor body 604 comprises monocrystalline silicon. Since channels can be formed in the 3D semiconductor body 604 rather than in the substrate 602, the 3D semiconductor body 604 can be considered as the active region of the 3D transistor 600.

[0124] like Figure 6A and Figure 6B As shown, the 3D transistor 600 may further include a gate structure 608 on the substrate 602. Unlike the planar transistor 500, in which the gate structure 608 contacts only one side of the active region (i.e., in the plane of the top surface of the substrate 502), the gate structure 608 of the 3D transistor 600 may contact multiple sides of the active region, i.e., in multiple planes of the top and side surfaces of the 3D semiconductor body 604. In other words, the active region of the 3D transistor 600, i.e., the 3D semiconductor body 604, may be at least partially surrounded by the gate structure 608.

[0125] The gate structure 608 may include a gate dielectric 607 on top of the 3D semiconductor body 604, for example, in contact with the top surface and two side surfaces of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 on top of and in contact with the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 609 includes doped polysilicon, i.e., gate polysilicon.

[0126] like Figure 6A As shown, the 3D transistor 600 may further include a pair of source and drain electrodes 606 within a 3D semiconductor body 604. The source and drain electrodes 606 may be doped with any suitable P-type dopant, such as B or Ga, or with any suitable N-type dopant, such as P or Ar. In a planar view, the source and drain electrodes 606 may be separated by a gate structure 608. In other words, according to some embodiments, in a planar view, the gate structure 608 is formed between the source and drain electrodes 606. As a result, when the gate voltage applied to the gate electrode 609 of the gate structure 608 exceeds the threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 may be laterally formed in the 3D semiconductor body 604 between the source and drain electrodes 606 surrounded by the gate structure 608. Unlike the planar transistor 500, which forms a single channel only on the top surface of the substrate 502, in the 3D transistor 600, multiple channels may be formed on the top and side surfaces of the 3D semiconductor body 604. In some implementations, the 3D transistor 600 includes a multi-gate transistor. It can be understood that, although not in... Figure 6A and Figure 6B As shown, the 3D transistor 600 may include additional components such as wells, spacers, and stress sources (also referred to as strain elements) at the source and drain 606.

[0127] To further understand, Figure 6A and Figure 6B An example of a 3D transistor that can be used in memory peripheral circuitry is shown, and any other suitable 3D multi-gate transistor can also be used in memory peripheral circuitry, including, for example, a full-ring gate (GAA) silicon-on-nothing (SON) transistor, a multi-gate independent FET (MIGET), a tri-gate FET, a π-gate FET and an Ω-FET, a quadruple-gate FET, a cylindrical FET, or a multi-bridge / stacked nanowire FET.

[0128] Regardless of whether it's a planar transistor 500 or a 3D transistor 600, each transistor in the memory peripheral circuitry can include a transistor with a thickness T (gate dielectric thickness, e.g.) Figure 5B and Figure 6B The gate dielectric (e.g., gate dielectrics 507 and 607) shown in the diagram. The gate dielectric thickness T of the transistor can be designed to accommodate the voltage applied to the transistor. For example, refer to... Figure 4A and Figure 4B The gate dielectric thickness of the transistors in the HV circuit 406 (e.g., a drive circuit, such as a string driver 704) can be greater than the gate dielectric thickness of the transistors in the LV circuit 404 (e.g., a page buffer circuit 702 or logic circuits in the control logic unit 312), which in turn can be greater than the gate dielectric thickness of the transistors in the LLV circuit 402 (e.g., I / O circuits in the interface 316 and data bus 318). In some embodiments, the gate dielectric thickness of the transistors in the HV circuit 406 differs from that of the transistors in the LLV circuit 402 by at least a factor of 5, for example, between a factor of 5 and a factor of 50. For example, the gate dielectric thickness of the transistors in the HV circuit 406 can be at least 5 times greater than the gate dielectric thickness of the transistors in the LLV circuit 402.

[0129] In some implementations, the dielectric thickness of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range whose lower end is defined by any of these values, or any range defined by any two of these values). It should be understood that, as described in detail above, the thickness may be commensurate with the range of LLV voltages applied to the LLV circuit 402, for example, below 1.3 V (e.g., 1.2 V). In some implementations, the dielectric thickness of the transistor in the LV circuit 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range whose lower end is defined by any of these values, or any range defined by any two of these values). It should be understood that, as described in detail above, the thickness may be commensurate with the range of LV voltages applied to the LV circuit 404, for example, between 1.3 V and 3.3 V (e.g., 3.3 V). In some implementations, the dielectric thickness of the transistor in HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range whose lower end is defined by any of these values, or any range defined by any two of these values). It should be understood that, as described in detail above, the thickness may be commensurate with the range of HV voltages applied to HV circuit 406, for example, greater than 3.3 V (e.g., between 5 V and 30 V).

[0130] Figure 9A and Figure 9B A schematic cross-sectional view of 3D memory devices 900 and 901 having three stacked semiconductor structures according to various aspects of this disclosure is shown. 3D memory devices 900 and 901 may be... Figure 1AAn example of a 3D memory device 100 includes a second semiconductor structure 104, comprising some peripheral circuitry, vertically disposed between a first semiconductor structure 102, including an array of memory cells, and a third semiconductor structure 106, including some peripheral circuitry. In other words, as... Figure 9A and Figure 9B As shown, according to some embodiments, a first semiconductor structure 102 comprising an array of memory cells of 3D memory devices 900 and 901 is disposed on one side of the 3D memory devices 900 and 901, a third semiconductor structure 106 comprising some peripheral circuits is disposed on the other side of the 3D memory devices 900 and 901, and a second semiconductor structure 104 comprising some peripheral circuits is disposed vertically in the middle of the 3D memory devices 900 and 901 (i.e., between the 3D memory devices 900 and 901). The second and third semiconductor structures 104 and 106, both comprising peripheral circuits, can be directly adjacent to each other in the three stacked semiconductor structures 102, 104 and 106.

[0131] The following is about such Figure 10A , Figure 10B , Figure 16A , Figure 16B , Figure 22A , Figure 22B , Figure 28A and Figure 28BVarious examples are described in detail for the above-described arrangement of the first, second, and third semiconductor structures 102, 104, and 106, wherein the first semiconductor structure 102 is on one side of the 3D memory devices 900 and 901. The above-described arrangement of the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 can provide support for processes such as thinning, bonding, and contact formation applied to the second semiconductor structure 104 and / or the third semiconductor structure 106 by using the substrate of the first semiconductor structure 102 on which the memory cell array is formed as a base substrate, without introducing another processing substrate (carrier wafer), thereby simplifying the fabrication process. Furthermore, the electrical connections between the memory cell arrays in each of the second and third semiconductor structures 104 and 106 and the peripheral circuitry can be formed without penetrating the substrate on which the memory cell array is formed in the first semiconductor structure 102, thereby reducing wiring length and complexity. Furthermore, in some embodiments, by arranging a first semiconductor structure 102 having a memory cell array on one side of the 3D memory devices 900 and 901, the substrate on which the memory cell array is formed (e.g., a silicon substrate having monocrystalline silicon) of the first semiconductor structure 102 can be relatively easily replaced by a semiconductor layer of different materials (e.g., a polycrystalline silicon layer), which is suitable for certain channel structures of “charge-trapping” type NAND memory strings or “floating gate” type NAND memory strings (e.g., bottom-opening channel structure 812C).

[0132] In addition, such as Figure 9A and Figure 9B As shown, the 3D memory device 900 or 901 may also include a pad-out interconnect layer 902 for pad-out purposes, i.e., interconnection with external devices using contact pads on which bonding wires can be soldered. Figure 9A In one example shown, a third semiconductor structure 106 including some peripheral circuitry on one side of the 3D memory device 900 may include a pad-out interconnect layer 902, allowing the 3D memory device 900 to be led out from the peripheral circuitry-side pads to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing parasitic capacitance from the interconnects and improving the electrical performance of the 3D memory device 900. Figure 9B In another example shown, a first semiconductor structure 102 including a memory cell array on the other side of the 3D memory device 901 may include a pad-out interconnect layer 902, such that the 3D memory device 901 can be led out from the memory cell array-side pads.

[0133] Figure 10A and Figure 10B Showing various aspects according to this disclosure Figure 9A and Figure 9BA schematic diagram of a cross-section of a 3D memory device. 3D memory devices 1000 and 1001 can be... Figure 9A and Figure 9B Examples of 3D memory devices 900 and 901 in the example. Figure 10A As shown, the 3D memory device 1000 may include stacked first, second, and third semiconductor structures 102, 104, and 106. In some embodiments, the first semiconductor structure 102 on one side of the 3D memory device 1000 includes a semiconductor layer 1002, a bonding layer 1008, and a memory cell array vertically located between the semiconductor layer 1002 and the bonding layer 1008. The memory cell array may include an array of NAND memory strings (e.g., the NAND memory string 208 disclosed herein), and the source of the NAND memory string array may be in contact with the semiconductor layer 1002 (e.g., as shown in the diagram). Figures 8A-8C (As shown). Semiconductor layer 1002 may include semiconductor materials, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate) or polycrystalline silicon (e.g., a deposited layer), for example, depending on the type of channel structure of the NAND memory string (e.g., bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C). Bonding layer 1008 may include dielectrics for conductive bonding contacts (not shown) and electrically isolated bonding contacts, which can be used for hybrid bonding, for example, as described in detail below.

[0134] In some embodiments, a second semiconductor structure 104 in the middle of the 3D memory device 1000 (i.e., between the first and third semiconductor structures 102 and 106) includes a semiconductor layer 1004, a bonding layer 1010, and some peripheral circuitry of a memory cell array vertically located between the semiconductor layer 1004 and the bonding layer 1010. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. The semiconductor layer 1004 may include a semiconductor material, such as monocrystalline silicon (e.g., a layer transferred from a silicon substrate or SOI substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 may also include a dielectric for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, the bonding interface 103 is vertically located between bonding layers 1008 and 1010 and contacts bonding layers 1008 and 1010, respectively. That is, bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of bonding layer 1008 can contact the bonding contacts of bonding layer 1010 at the bonding interface 103. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 103 can form direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0135] In some embodiments, a third semiconductor structure 106 on the other side of the 3D memory device 1000 includes a semiconductor layer 1006 and peripheral circuitry of a memory cell array vertically located between the semiconductor layer 1006 and the semiconductor layer 1004. Transistors of the peripheral circuitry (e.g., planar transistors 500 and / or 3D transistors 600) may contact the semiconductor layer 1006. The semiconductor layer 1006 may comprise a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1006 on which transistors are formed may comprise monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. It should be understood that, unlike the bonding interface 103 between the first and second semiconductor structures 102 and 104, which is located between bonding layers 1008 and 1010 and is formed by mixed bonding, the bonding interface 105 between the second and third semiconductor structures 104 and 106 can be formed by transfer bonding, as described in detail below, and therefore may not be formed between the two bonding layers. That is, according to some embodiments, Figure 10AThe third semiconductor structure 106 of the 3D memory device 1000 does not include a bonding layer with bonding contacts. As a result, instead of bonding contacts, through contacts (e.g., ILV / TSV) across the bonding interface 105 and through the semiconductor layer 1004 located vertically between the second and third semiconductor structures 104 and 106 can form a direct, short-distance (e.g., submicron) electrical connection between adjacent semiconductor structures 104 and 106.

[0136] It should be understood that, in some examples, the second and third semiconductor structures 104 and 106 may further include bonding layers 1012 and 1014 respectively disposed on opposite sides of the bonding interface 105, such as Figure 10B As shown. In Figure 10B In the 3D memory device 1001, the second semiconductor structure 104 may include two bonding layers 1010 and 1012 on both sides, and the bonding layer 1012 may be vertically disposed between the semiconductor layer 1004 and the bonding interface 105. The third semiconductor structure 106 of the 3D memory device 1001 may include a bonding layer 1014 vertically disposed between the bonding interface 105 and its peripheral circuitry. Each bonding layer 1012 and 1014 may include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. The bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, the bonding contacts across the bonding interface 105, combined with through contacts (e.g., ILV / TSV) through the semiconductor layer 1004, can form a direct, short-distance (e.g., micrometer-scale) electrical connection between adjacent semiconductor structures 104 and 106.

[0137] like Figure 10A and Figure 10B As shown, according to some embodiments, since the third and second semiconductor structures 106 and 104 are bonded in a face-to-back manner (e.g., in...), Figure 10A and Figure 10B Each semiconductor layer 1006 or 1004 has a corresponding third or second semiconductor structure 106 or 104 on its top side, and the transistors in the third and second semiconductor structures 106 and 104 face the same direction (e.g., Figure 10A The negative y-direction is used. In some embodiments, the transistors of the peripheral circuit in the third semiconductor structure 106 are vertically disposed between the bonding interface 105 and the semiconductor layer 1006, while the transistors of the peripheral circuit in the second semiconductor structure 104 are vertically disposed between the bonding interface 103 and the semiconductor layer 1004. Furthermore, according to some embodiments, since the first and second semiconductor structures 102 and 104 are bonded face-to-face (e.g., in...), Figure 10A and 10BSemiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104. The transistors of the peripheral circuits in the third and second semiconductor structures 106 and 104 are arranged in the same direction, facing the memory cell array in the first semiconductor structure 102. It should be understood that... Figure 9A or Figure 9B The pads in the 902 interconnect layer can be brought out from the pads. Figure 10A and Figure 10B The 3D memory devices 1000 and 1001 are omitted for the sake of illustration, and may be included as described above regarding Figure 9A or Figure 9B In the described 3D memory devices 1000 and 1001.

[0138] As described above, the second and third semiconductor structures 104 and 106 can have peripheral circuitry, which includes transistors with different applied voltages. For example, the second semiconductor structure 104 can be... Figure 4B An example of a semiconductor structure 408 including an LLV circuit 402 (and in some examples, an LV circuit 404), and a third semiconductor structure 106 may be Figure 4B An example of a semiconductor structure 410 including an HV circuit 406 (and in some examples, an LLV circuit 404), and vice versa. Therefore, in some embodiments, the semiconductor layers 1006 and 1004 in the third and second semiconductor structures 106 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the third semiconductor structure 106 may include an HV circuit 406 and the second semiconductor structure 104 may include an LLV circuit 402, and the thickness of the semiconductor layer 1006 in the third semiconductor structure 106 may be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the third and second semiconductor structures 106 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the third semiconductor structure 106 may include an HV circuit 406 and the second semiconductor structure 104 may include an LLV circuit 402, and the thickness of the gate dielectric of the transistor in the third semiconductor structure 106 may be greater than the thickness of the gate dielectric of the transistor in the second semiconductor structure 104 (e.g., at least 5 times). Compared to the transistor in the second semiconductor structure 104, the thicker gate dielectric can withstand a higher operating voltage applied to the transistor in the third semiconductor structure 106, thus avoiding breakdown during high-voltage operation.

[0139] like Figure 10A and Figure 10BAs shown, the peripheral circuits in the second semiconductor structure 104 and / or the peripheral circuits in the third semiconductor structure 106 can be disposed between the bonding interface 103 and the semiconductor layer 1006 of the third semiconductor structure 106. Alternatively, the peripheral circuits in the second semiconductor structure 104 and / or the peripheral circuits in the third semiconductor structure 106 can also be disposed between the memory cell array in the first semiconductor structure 102 and the semiconductor layer 1006 of the third semiconductor structure 106.

[0140] Figure 11A-11C Showing various aspects according to this disclosure Figure 10A and Figure 10B Side views of various examples of 3D memory devices 1000 and 1001. (See also...) Figure 11A As shown, as Figure 10A and Figure 10B An example of 3D memory devices 1000 and 1001, according to some embodiments, 3D memory device 1100 is included in the vertical direction (e.g., Figure 11A A bonding chip comprising a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked on top of each other in different planes (in the y-direction). According to some embodiments, the first and second semiconductor structures 102 and 104 are bonded at a bonding interface 103 therebetween, and the second and third semiconductor structures 104 and 106 are bonded at a bonding interface 105 therebetween.

[0141] like Figure 11AAs shown, the third semiconductor structure 106 may include a semiconductor layer 1006 having a semiconductor material. In some embodiments, the semiconductor layer 1006 is a silicon substrate having monocrystalline silicon. The third semiconductor structure 106 may also include a device layer 1102 above and in contact with the semiconductor layer 1006. In some embodiments, the device layer 1102 includes a first peripheral circuit 1104 and a second peripheral circuit 1106. The first peripheral circuit 1104 may include an HV circuit 406, such as a driver circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the second peripheral circuit 1106 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuits (e.g., in a control logic unit 312). In some embodiments, the first peripheral circuit 1104 includes a plurality of transistors 1108 in contact with the semiconductor layer 1006, and the second peripheral circuit 1106 includes a plurality of transistors 1110 in contact with the semiconductor layer 1006. Transistors 1108 and 1110 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described above in detail with respect to transistors 500 and 600, in some embodiments, each transistor 1108 or 1110 includes a gate dielectric, and the thickness of the gate dielectric of transistor 1108 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1110 (e.g., in LV circuit 404) because the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1110. Trench isolation (e.g., STI) and doped regions (e.g., the wells, sources, and drains of transistors 1108 and 1110) may also be formed on or in the semiconductor layer 1006.

[0142] In some embodiments, the third semiconductor structure 106 further includes an interconnect layer 1112 above the device layer 1102 to transmit electrical signals to and from peripheral circuits 1106 and 1104. For example... Figure 11AAs shown, interconnect layer 1112 may be vertically positioned between bonding interface 105 and device layer 1102 (including transistors 1108 and 1110 of peripheral circuits 1104 and 1106). Interconnect layer 1112 may include multiple interconnects (also referred to herein as “contacts”), including lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-end process (MEOL) interconnects and back-end process (BEOL) interconnects. Interconnects in interconnect layer 1112 may be coupled to transistors 1108 and 1110 of peripheral circuits 1104 and 1106 in device layer 1102. Interconnect layer 1112 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which lateral lines and vias may be formed. That is, interconnect layer 1112 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1102 are coupled to each other via interconnects in interconnect layer 1112. For example, peripheral circuit 1104 can be coupled to peripheral circuit 1106 via interconnect layer 1112. The interconnects in interconnect layer 1112 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1112 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1112 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) among conductive metallic materials.

[0143] The second semiconductor structure 104 can be bonded to the top of the third semiconductor structure 106 in a back-to-back manner at the bonding interface 105. The second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the third semiconductor structure 106 by transfer bonding. In some embodiments, as a result of transfer bonding, the bonding interface 105 is vertically disposed between the interconnect layer 1112 and the semiconductor layer 1004, which transfers the semiconductor layer 1004 from another substrate and bonds the semiconductor layer 1004 to the third semiconductor structure 106, as described in detail below. In some embodiments, the bonding interface 105 is the place where the interconnect layer 1112 and the semiconductor layer 1004 meet and bond. In practice, the bonding interface 105 may be a layer of a certain thickness, which includes the top surface of the interconnect layer 1112 of the third semiconductor structure 106 and the bottom surface of the semiconductor layer 1004 of the second semiconductor structure 104. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1004 and / or between the bonding interface 105 and the interconnect layer 1112 to facilitate transfer bonding from the semiconductor layer 1004 to the interconnect layer 1112. Therefore, it can be understood that in some examples, the bonding interface 105 may include the surface of the dielectric layer.

[0144] The second semiconductor structure 104 may include a device layer 1114 situated above and in contact with the semiconductor layer 1004. In some embodiments, the device layer 1114 includes a third peripheral circuit 1116 and a fourth peripheral circuit 1118. The third peripheral circuit 1116 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the fourth peripheral circuit 1118 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic unit 312). In some embodiments, the third peripheral circuit 1116 includes a plurality of transistors 1120, and the fourth peripheral circuit 1118 also includes a plurality of transistors 1122. Transistors 1120 and 1122 may include any transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1120 or 1122 includes a gate dielectric, and the thickness of the gate dielectric of transistor 1120 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 1122 (e.g., in LV circuit 404) because the voltage applied to transistor 1120 is lower than the voltage applied to transistor 1122. Isolation trenches (e.g., STI) and doped regions (e.g., the wells, sources, and drains of transistors 1120 and 1122) may also be formed on or in semiconductor layer 1004.

[0145] Furthermore, different voltages applied to the different transistors 1120, 1122, 1108, and 1110 in the second and third semiconductor structures 104 and 106 can lead to differences in device dimensions between the second and third semiconductor structures 104 and 106. In some embodiments, the thickness of the gate dielectric of transistor 1108 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1120 (e.g., in LLV circuit 402) because the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1120. In some embodiments, the thickness of the gate dielectric of transistor 1122 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 1110 (e.g., in LV circuit 404) because the voltage applied to transistor 1122 is the same as the voltage applied to transistor 1110. In some embodiments, the thickness of the semiconductor layer 1006 in which transistor 1108 is formed (e.g., in HV circuit 406) is greater than the thickness of the semiconductor layer 1004 in which transistor 1120 is formed (e.g., in LLV circuit 402) because the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1120.

[0146] like Figure 11A As shown, the second semiconductor structure 104 may further include an interconnect layer 1126 above the device layer 1114 to transmit electrical signals to and from peripheral circuits 1116 and 1118. Figure 11A As shown, interconnect layer 1126 may be vertically located between bonding interface 103 and device layer 1114 (including transistors 1120 and 1122 of peripheral circuits 1116 and 1118). Interconnect layer 1126 may include multiple interconnects of transistors 1120 and 1122 of peripheral circuits 1116 and 1118 coupled to device layer 1114. Interconnect layer 1126 may also include one or more ILD layers in which interconnects can be formed. That is, interconnect layer 1126 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1114 are coupled to each other through interconnects in interconnect layer 1126. For example, peripheral circuit 1116 may be coupled to peripheral circuit 1118 through interconnect layer 1126. Interconnects in interconnect layer 1126 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1126 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof.

[0147] In some embodiments, the interconnects in interconnect layer 1126 comprise Cu, which has a relatively low resistivity (better electrical performance) in a conductive metallic material. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layer 1126 become feasible because the fabrication of interconnect layer 1126 can occur after the high-temperature processes forming device layers 1114 and 1102 in the second and third semiconductor structures 104 and 106, and is decoupled from the high-temperature process forming the first semiconductor structure 102.

[0148] like Figure 11AAs shown, the second semiconductor structure 104 may further include one or more contacts 1124 extending vertically through the semiconductor layer 1004. The contacts 1124 may further extend vertically through the bonding interface 105 to contact interconnects in the interconnect layer 1112. In some embodiments, the contacts 1124 couple interconnects in the interconnect layer 1126 to interconnects in the interconnect layer 1112 to form an electrical connection across the bonding interface 105 between the second and third semiconductor structures 104 and 106. The contacts 1124 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1124 include W. In some embodiments, the contacts 1124 include a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically decouple a via from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 1124 can be an ILV with a depth (in the vertical direction) in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth (in the vertical direction) in the micron or tens of micron range (e.g., between 1 μm and 100 μm).

[0149] like Figure 11A As shown, the second semiconductor structure 104 may further include a bonding layer 1010 at the bonding interface 103 and above and in contact with the interconnect layer 1126. The bonding layer 1010 may include a plurality of bonding contacts 1011 and a dielectric for electrically isolating the bonding contacts 1011. The bonding contacts 1011 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 1011 of the bonding layer 1010 include Cu. The remaining region of the bonding layer 1010 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 1011 in the bonding layer 1010 and the surrounding dielectric can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO2-to-SiO2) bonding.

[0150] like Figure 11AAs shown, the first semiconductor structure 102 may further include a bonding layer 1008 at a bonding interface 103, for example, a bonding layer 1008 on the opposite side of the bonding interface 103 relative to the bonding layer 1010 in the second semiconductor structure 104. The bonding layer 1008 may include a plurality of bonding contacts 1009 and a dielectric material for electrically isolating the bonding contacts 1009. The bonding contacts 1009 may include a conductive material, such as Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material such as silicon oxide. The bonding contacts 1009 in the bonding layer 1008 and the surrounding dielectric material may be used for mixed bonding. In some embodiments, the bonding interface 103 is where the bonding layers 1008 and 1010 meet and bond. In practice, the bonding interface 103 can be a layer with a certain thickness, which includes the top surface of the bonding layer 1010 of the second semiconductor structure 104 and the bottom surface of the bonding layer 1008 of the first semiconductor structure 102.

[0151] Although not in Figure 11A As shown, it should be understood that in some examples, similar to bonding interface 103, bonding interface 105 can be generated by hybrid bonding and thus be vertically disposed on both bonding layers (e.g., Figure 10B Between the bonding layers 1012 and 1014 of the 3D memory device 1001, each bonding layer includes bonding contacts in the second and third semiconductor structures 104 and 106, respectively.

[0152] like Figure 11A As shown, the first semiconductor structure 102 may further include an interconnect layer 1128 above the bonding layer 1008 for transmitting electrical signals. The interconnect layer 1128 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1128 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1128 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 1128 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1128 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0153] like Figure 11AAs shown, the first semiconductor structure 102 may include an array of memory cells, such as an array of NAND memory strings 208, above the interconnect layer 1128. In some embodiments, the interconnect layer 1128 is vertically positioned between the NAND memory strings 208 and the bonding interface 103. According to some embodiments, each NAND memory string 208 extends vertically through multiple pairs, each pair including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked structure, such as a memory stack 1127. The memory stack 1127 may be... Figures 8A-8C Examples of memory stacks 804 include the conductive and dielectric layers in memory stack 1127, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack 1127 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material, such as titanium nitride (TiN), which may improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating in one or more stepped structures of memory stack 1127.

[0154] In some implementations, each NAND memory string 208 is a "charge-trapping" type NAND memory string, including any suitable channel structure disclosed herein, such as those mentioned above. Figures 8A-8C The bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C are described in detail. It should be understood that the NAND memory string 208 is not limited to the "charge-trapping" type NAND memory string and may be the "floating gate" type NAND memory string in other examples.

[0155] like Figure 11A As shown, the first semiconductor structure 102 may further include a semiconductor layer 1002 disposed above the memory stack 1127 and in contact with the source of the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the bonding interface 103 and the semiconductor layer 1002. The semiconductor layer 1002 may include a semiconductor material. In some embodiments, the semiconductor layer 1002 is a thinned silicon substrate having monocrystalline silicon on which the memory stack 1727 and the NAND memory string 208 are formed (e.g., including a bottom plug channel structure 812A or a sidewall plug channel structure 812B). It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the semiconductor layer 1002.

[0156] like Figure 11AAs shown, the first semiconductor structure 102 may further include a pad-out interconnect layer 902 above and in contact with the semiconductor layer 1002. In some embodiments, the semiconductor layer 1002 is vertically disposed between the pad-out interconnect layer 902 and the NAND memory string 208. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 1132. The pad-out interconnect layer 902 and the interconnect layer 1128 may be formed on opposite sides of the semiconductor layer 1002. In some embodiments, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 1100 and an external device, for example, for pad-out purposes.

[0157] like Figure 11A As shown, the first semiconductor structure 102 may further include one or more contacts 1130 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1130 couple interconnects in the interconnect layer 1128 to pads leading out to contact pads 1132 in the interconnect layer 902 to form electrical connections through the semiconductor layer 1002. The contacts 1130 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1130 include W. In some embodiments, the contacts 1130 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contacts 1130 may be ILVs with a submicron depth (e.g., between 10 nm and 1 μm) or TSVs with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0158] As a result, the peripheral circuits 1104, 1106, 1116, and 1118 in the third and second semiconductor structures 106 and 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 1112, 1126, and 1128, bonding layers 1008 and 1010, and contact 1124. Furthermore, the peripheral circuits 1104, 1106, 1116, and 1118 in the 3D memory device 1100, as well as the NAND memory string 208, can be further coupled to external devices via contact 1130 and pads leading out from the interconnect layer 902.

[0159] It should be understood that the material of the semiconductor layer 1002 in the first semiconductor structure 102 is not limited to the above-mentioned... Figure 11A The described single-crystal silicon can be any other suitable semiconductor material. For example, such as... Figure 11BAs shown, the 3D memory device 1101 may include a semiconductor layer 1002 having polysilicon in a first semiconductor structure 102. The NAND memory string 208 of the 3D memory device 1101 in contact with the polysilicon semiconductor layer 1002 may include any suitable channel structure disclosed herein that contacts the polysilicon layer, such as a bottom-opening channel structure 812C. In some embodiments, the NAND memory string 208 of the 3D memory device 1101 is a "floating gate" type NAND memory string, and the polysilicon semiconductor layer 1002 contacts the "floating gate" type NAND memory string as its source plate. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in the 3D memory devices 1100 and 1101 will not be repeated.

[0160] It should also be understood that the pad leads of 3D memory devices are not limited to, for example... Figure 11A and Figure 11B The first semiconductor structure 102 shown has NAND memory string 208 (corresponding to) Figure 9B ) and can come from a third semiconductor structure 106 having peripheral circuitry 1104 (corresponding to Figure 9A For example, such as Figure 11C As shown, the 3D memory device 1103 may include a pad-out interconnect layer 902 in a third semiconductor structure 106. The pad-out interconnect layer 902 may contact a semiconductor layer 1006 of the third semiconductor structure 106 on which transistors 1108 forming peripheral circuitry 1104 are located. In some embodiments, the third semiconductor structure 106 further includes one or more contacts 1134 extending vertically through the semiconductor layer 1006. In some embodiments, the contacts 1134 couple interconnects in interconnect layers 1112 of the third semiconductor structure 106 to contact pads 1132 in the pad-out interconnect layer 902 to form an electrical connection through the semiconductor layer 1006. The contacts 1134 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1134 include W. In some embodiments, the contacts 1134 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically decouple the vias from the semiconductor layer 1006. Depending on the thickness of the semiconductor layer 1006, the contact 1134 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm). It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in the 3D memory devices 1100 and 1103 will not be repeated.

[0161] It should also be understood that, in some examples, similar to bonding interface 103, bonding interface 105 can be generated by hybrid bonding and thus vertically disposed between two bonding layers, each including bonding contacts in the second and third semiconductor structures 104 and 106, respectively. For example, as Figure 11C As shown, the 3D memory device 1103 may include bonding layers 1012 and 1014, respectively, in the second and third semiconductor structures 104 and 106, at a bonding interface 105 (i.e., on opposite sides of the bonding interface 105). Bonding layer 1012 or 1014 may include a plurality of bonding contacts 1013 or 1015 and a dielectric for electrically isolating the bonding contacts 1013 or 1015. Bonding contacts 1013 and 1015 may include a conductive material, such as Cu. The remaining region of bonding layer 1012 or 1014 may be formed of a dielectric material such as silicon oxide. The bonding contacts 1013 or 1015 and the surrounding dielectric in bonding layer 1012 or 1014 may be used for mixed bonding. In some embodiments, bonding interface 105 is where bonding layers 1012 and 1014 meet and bond. In practice, the bonding interface 105 can be a layer of a certain thickness, including the top surface of the bonding layer 1014 of the third semiconductor structure 106 and the bottom surface of the bonding layer 1012 of the second semiconductor structure 104. The contact 1124 can be coupled to the bonding contact 1013, and the interconnect layer 1112 can be coupled to the bonding contact 1015.

[0162] Figures 12A-12H This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B The manufacturing process of 3D memory devices. Figure 14 This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B A flowchart of the method 1400 for a 3D memory device. Figures 12A-12H and Figure 14 Examples of 3D memory devices depicted include Figure 11A-11C The 3D memory devices 1100, 1101, and 1103 depicted herein will be described together. Figures 12A-12H and Figure 14 It should be understood that the operations shown in method 1400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 14 The different execution sequences shown are illustrated. For example, operation 1402 can be executed after operation 1408 or in parallel with operations 1404-1408.

[0163] refer to Figure 14Method 1400 begins with operation 1402, wherein a NAND memory string array is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, a memory stack is formed on the first substrate to form the NAND memory string array.

[0164] like Figure 12D As shown, a stacked structure, such as a memory stack 1226 comprising staggered conductive and dielectric layers, is formed on a silicon substrate 1224. To form the memory stack 1226, in some embodiments, a dielectric stack (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 1224. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The memory stack 1226 can then be formed by a gate replacement process, such as using a wet / dry etching of the sacrificial layer selectively applied to the dielectric layer and filling the resulting recess with a conductive layer to replace the sacrificial layer. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 1226 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without using a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide (e.g., thermally grown localized oxidation of silicon (LOCOS)) is formed between the memory stack 1226 and the silicon substrate 1224.

[0165] like Figure 12D As shown, NAND memory strings 1228 are formed above a silicon substrate 1224, with each NAND memory string 1228 extending vertically through a memory stack 1226 to contact the silicon substrate 1224. In some embodiments, the fabrication process for forming the NAND memory strings 1228 includes: forming channel vias through the memory stack 1226 (or dielectric stack) and into the silicon substrate 1224 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel vias with multiple layers such as memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It should be understood that the details of fabricating the NAND memory strings 1228 can vary depending on the type of channel structure of the NAND memory strings 1228 (e.g., Figures 8A-8CThe structure varies depending on whether it is a bottom plug channel structure 812A, a side wall plug channel structure 812B, or a bottom open channel structure 812C. Therefore, it is not described in detail for ease of description.

[0166] In some implementations, an interconnect layer is formed over a NAND memory string array on a first substrate. The interconnect layer may include a first plurality of interconnects within one or more ILD layers. Figure 12D As shown, an interconnect layer 1230 is formed over the memory stack 1226 and the NAND memory string 1228. The interconnect layer 1230 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1228. In some embodiments, the interconnect layer 1230 includes a plurality of ILD layers and interconnects therein formed using a variety of processes. For example, the interconnects in the interconnect layer 1230 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 12D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1230.

[0167] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 12D As shown, a bonding layer 1232 is formed over the interconnect layer 1230. The bonding layer 1232 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1230 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1230 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0168] Method 1400 proceeds to operation 1404, such as... Figure 14 As shown, a first transistor is formed on a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 12AAs shown, a plurality of transistors 1204 and 1206 are formed on a silicon substrate 1202. Transistors 1204 and 1206 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1202 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1204 and 1206. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1202 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1204 differs from the thickness of the gate dielectric of transistor 1206 by depositing a thicker silicon oxide film in the region of transistor 1204 than in the region of transistor 1206, or by etching back portions of the silicon oxide film deposited in the region of transistor 1206. It should be understood that the details of fabricating transistors 1204 and 1206 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0169] In some embodiments, the interconnect layer 1208 is formed over the transistor on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 12A As shown, interconnect layer 1208 may be formed over transistors 1204 and 1206. Interconnect layer 1208 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect to transistors 1204 and 1206. In some embodiments, interconnect layer 1208 includes a plurality of ILD layers and interconnects therein formed by a variety of processes. For example, interconnects in interconnect layer 1208 may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 12A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1208. In some embodiments, the interconnects in interconnect layer 1208 include W, which has a relatively high thermal budget in a conductive metal material to withstand subsequent high-temperature processes.

[0170] Method 1400 proceeds to operation 1406, such as... Figure 14As shown, a semiconductor layer is formed over a first transistor. The semiconductor layer may include monocrystalline silicon. In some embodiments, to form the semiconductor layer, another substrate and a second substrate are bonded face-to-face, and the other substrate is thinned to leave the semiconductor layer. Bonding may include transfer bonding. The other substrate may be a silicon substrate having monocrystalline silicon.

[0171] like Figure 12B As shown, a semiconductor layer 1210, such as a single-crystal silicon layer, is formed over interconnect layer 1208 and transistors 1204 and 1206. Semiconductor layer 1210 may be attached over interconnect layer 1208 to form a bonding interface 1212 perpendicularly between semiconductor layer 1210 and interconnect layer 1208. According to some embodiments, the lateral dimension (e.g., dimension in the x-direction) of semiconductor layer 1210 is the same as the lateral dimension of silicon substrate 1202 or silicon substrate 1224. In some embodiments, to form semiconductor layer 1210, transfer bonding is used to bond another silicon substrate (…) face-to-face. Figure 12B (Not shown in the diagram) and a silicon substrate 1202 are bonded (i.e., components such as transistors 1204 and 1206 formed on the silicon substrate 1202 are facing the other silicon substrate), thereby forming a bonding interface 1212. The other silicon substrate can then be thinned using any suitable process to leave a semiconductor layer 1210 attached over the interconnect layer 1208. The same “face-to-face” approach as described above is applied throughout this disclosure when describing other figures.

[0172] Figures 48A-48D The manufacturing process of transfer bonding according to some aspects of this disclosure is illustrated. For example... Figure 48A As shown, functional layer 4804 can be formed on substrate 4802. Functional layer 4804 may include device layers, interconnect layers, and / or any suitable layers disclosed herein, such as Figure 12B Transistors 1204 and 1206 and interconnect layer 1208 are included. A transfer substrate 4806 is provided, such as a silicon substrate having monocrystalline silicon. In some embodiments, the transfer substrate 4806 is a monocrystalline silicon substrate. Figure 48BAs shown, the transfer substrate 4806 and the base substrate 4802 (and the functional layer 4804 formed thereon) can be bonded face-to-face using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 4810 between the transfer substrate 4806 and the base substrate 4802. In one example, fusion bonding can be performed between layers of silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide using pressure and heat. In another example, anodic bonding can be performed between layers of silicon oxide (in ionomer glass) and silicon using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 4810. For example, a silicon oxide layer can be formed on the top surface of both the transfer substrate 4806 and the functional layer 4804 to allow for SiO2-SiO2 bonding using fusion bonding. Alternatively, a silicon oxide layer may be formed only on functional layer 4804 to allow for the use of anodic bonding or fusion bonding of SiO2-Si bonds. Some embodiments in which a silicon oxide layer is formed on transfer substrate 4806 (e.g., Figure 48B In the diagram, the transfer substrate 4806 can be flipped upwards so that the silicon oxide layer on the transfer substrate 4806 faces downwards toward the base substrate 4802 before bonding.

[0173] like Figure 48C As shown, a cleavage layer 4812 can be formed in the transfer substrate 4806, for example, using ion implantation. In some embodiments, light elements such as hydrogen ions are implanted into the transfer substrate 4806 to a desired depth, for example, by controlling the energy of the ion implantation process, to form the cleavage layer 4812. Figure 48DAs shown, the transfer substrate 4806 can be thinned to leave only the semiconductor layer 4814 perpendicularly located between the dicing layer 4812 and the bonding interface 4810. In some embodiments, the transfer substrate 4806 is cleaved at the dicing layer 4812 by applying mechanical force, i.e., the remaining portion of the transfer substrate 4806 is peeled off from the semiconductor layer 4814. It should be understood that the transfer substrate 4806 can be cleaved at the dicing layer 4812 by any suitable means, not limited to mechanical force, such as thermal, acoustic, optical, etc., or any combination thereof. As a result, the semiconductor layer 4814 can be transferred from the transfer substrate 4806 and bonded to the base substrate 4802 (and the functional layer 4804) using a transfer bonding process. In some embodiments, a planarization process such as chemical mechanical polishing (CMP) is performed on the semiconductor layer 4812 to polish and smooth the top surface of the semiconductor layer 4812 and adjust the thickness of the semiconductor layer 4812. Therefore, semiconductor layer 4814 can have the same material as transfer substrate 4806, such as single-crystal silicon. The thickness of semiconductor layer 4814 can be determined by the depth of dicing layer 4812, for example, by adjusting the implantation energy and / or by a planarization process. Furthermore, the remaining portion of transfer substrate 4806 can be reused in the same manner to form semiconductor layers bonded to other substrates, thereby reducing the material cost of the transfer bonding process.

[0174] Figures 49A-49D Another manufacturing process for transfer bonding according to some aspects of this disclosure is shown. For example... Figure 49A As shown, functional layer 4804 can be formed on substrate 4802. Functional layer 4804 may include device layers, interconnect layers, and / or any suitable layers disclosed herein, such as Figure 12B The transistors 1204 and 1206 and the interconnect layer 1208 are included. The SOI substrate 4902, including the substrate / process layer 4904, the buried oxide layer (BOx) 4906, and the device layer 4908, can be flipped upside down to face the substrate 4802. Figure 49BAs shown, the SOI substrate 4902 and the base substrate 4802 (and the functional layer 4804 formed thereon) can be bonded face-to-face using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 4912 between the SOI substrate 4902 and the base substrate 4802. In one example, fusion bonding can be performed between layers of silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide using pressure and heat. In another example, anodic bonding can be performed between layers of silicon oxide (in ionomer glass) and silicon using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 4912. For example, a silicon oxide layer can be formed on the top surface of both the SOI substrate 4902 and the functional layer 4804 to allow for SiO2-SiO2 bonding using fusion bonding. Alternatively, a silicon oxide layer can be formed only on functional layer 4804 to allow for the use of anodic bonding or fusion bonding of SiO2-Si bonds.

[0175] like Figure 49C and Figure 49D As shown, SOI substrate 4902 ( Figure 49B The device layer 4908 (as shown) can be thinned by sequentially removing the substrate / processing layer 4904 and the buried oxide layer 4906, for example, using wet / dry etching and / or CMP processes, leaving only the device layer 4908 (as a semiconductor layer) at the bonding interface 4912. As a result, the device layer 4908 can be transferred from the SOI substrate 4902 and bonded to the substrate substrate 4802 (and the functional layer 4804) as a semiconductor layer using another transfer bonding process. Therefore, the transferred semiconductor layer can have the same material as the device layer 4908, such as single-crystal silicon. The thickness of the semiconductor layer can be the same as the thickness of the device layer 4908. It should be understood that in some examples, the device layer 4908 can be further thinned using wet / dry etching and / or CMP processes, such that the transferred semiconductor layer can be thinner than the device layer 4908.

[0176] refer to Figure 14 Method 1400 proceeds to operation 1408, in which a second transistor is formed on the semiconductor layer. For example... Figure 12CAs shown, a plurality of transistors 1214 and 1216 are formed on a semiconductor layer 1210 having monocrystalline silicon. Transistors 1214 and 1216 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the semiconductor layer 1210 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1214 and 1216. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 1210 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1214 differs from the thickness of the gate dielectric of transistor 1216 by depositing a thicker silicon oxide film in the region of transistor 1214 than in the region of transistor 1216, or by etching back portions of the silicon oxide film deposited in the region of transistor 1216. It should be understood that the details of fabricating transistors 1214 and 1216 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0177] In some embodiments, the interconnect layer 1220 is formed above the transistors on the semiconductor layer. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 12C As shown, interconnect layer 1220 may be formed over transistors 1214 and 1216. Interconnect layer 1220 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect to transistors 1214 and 1216. In some embodiments, interconnect layer 1220 includes a plurality of ILD layers and interconnects therein formed by a variety of processes. For example, interconnects in interconnect layer 1220 may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 12CThe ILD layer and interconnects shown can be collectively referred to as interconnect layer 1220. Unlike interconnect layer 1208, in some embodiments, the interconnects in interconnect layer 1220 include Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it may become feasible to use Cu as the conductive material for the interconnects in interconnect layer 1220 since no high-temperature processes are required after the fabrication of interconnect layer 1220.

[0178] In some implementations, contacts are formed through the semiconductor layer. For example... Figure 12C As shown, one or more contacts 1218 are formed extending vertically through semiconductor layer 1210. Contacts 1218 can couple interconnects in interconnect layers 1220 and 1208. Contacts 1218 can be formed by first patterning contact holes through dielectric layer 1210 and bonding layer 1212 to contact interconnects in interconnect layer 1208 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). Contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0179] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 12D As shown, a bonding layer 1222 is formed over an interconnect layer 1220. The bonding layer 1222 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1220 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1220 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor. For example, the adhesive layer can improve the adhesion of the conductor to avoid defects, the barrier layer can prevent metal ions (e.g., Cu ions) from diffusing from the conductor into other structures, thus preventing contamination, and the seed layer can promote the deposition of the conductor (e.g., Cu) in the contact holes to improve deposition quality and speed.

[0180] Method 1400 proceeds to operation 1410, such as... Figure 14As shown, a first substrate and a second substrate are bonded face-to-face. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0181] like Figure 12E As shown, a silicon substrate 1224 and components formed thereon (e.g., a memory stack 1226 and a NAND memory string 1228 formed therethrough) are flipped upside down. A downward-facing bonding layer 1232 is bonded to an upward-facing bonding layer 1222, i.e., face-to-face bonding, thereby forming a bonding interface 1237. That is, the silicon substrate 1224 and components formed thereon can be bonded to the silicon substrate 1202 and components formed thereon in a face-to-face manner, such that bonding contacts in the bonding layer 1232 contact bonding contacts in the bonding layer 1222 at the bonding interface 1237. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or heat treatment, is applied to the bonding surface prior to bonding. Although not explicitly stated... Figure 12E As shown, but it should be understood that in some examples, the silicon substrate 1202 and the components formed thereon (e.g., transistors 1204, 1206, 1214 and 1216) can be flipped upside down, and the downward-facing bonding layer 1222 can be bonded to the upward-facing bonding layer 1232, i.e., bonded face-to-face, thereby also forming a bonding interface 1237.

[0182] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1237 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1232 and bonding contacts in bonding layer 1222 are aligned and in contact with each other, such that the memory stack 1226 and the NAND memory string 1228 formed therethrough can be coupled to transistors 1214, 1216, 1204 and 1206 via the bonding contacts of the bonding interface 1237.

[0183] Method 1400 proceeds to operation 1412, such as Figure 14 As shown, either the first substrate or the second substrate is thinned. Figure 12F As shown, silicon substrate 1224 ( Figure 12E (As shown) the silicon substrate 1224 is thinned to form a semiconductor layer 1234 with monocrystalline silicon. The silicon substrate 1224 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. It should be understood that, although not shown in… Figure 12F As shown, however, in some examples, the silicon substrate 1202 can be thinned to become a semiconductor layer with monocrystalline silicon.

[0184] Method 1400 proceeds to operation 1414, such as... Figure 14 As shown, a pad-out interconnect layer is formed therein. This pad-out interconnect layer can be formed on a thinned second substrate or over a NAND memory string array. As... Figure 12F As shown, a pad-out interconnect layer 1236 is formed on a semiconductor layer 1234 (thinned silicon substrate 1224) above a NAND memory string 1228. The pad-out interconnect layer 1236 may include interconnects formed in one or more ILD layers, such as contact pads 1238. Contact pads 1238 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1235 extending vertically through the semiconductor layer 1234 are formed, for example, by wet / dry etching, followed by deposition of a dielectric material as spacers and deposition of a conductive material as a conductor. Contacts 1235 can couple the contact pads 1238 in the pad-out interconnect layer 1236 to interconnects in the interconnect layer 1230. It should be understood that in some examples, the contact 1235 may be formed in the silicon substrate 1224 before thinning (formation of the semiconductor layer 1234), and the contact 1235 may be exposed from the back side of the silicon substrate 1224 (where thinning occurs) after thinning. It should also be understood that, although... Figure 12F Although not shown in the figure, in some examples, pads can be formed on the thinned silicon substrate 1202 to lead out interconnect layers, and contacts can be formed across the thinned silicon substrate 1202 to couple the pads leading out interconnect layers and interconnect layers 1208 across the thinned silicon substrate 1202.

[0185] In some embodiments, a semiconductor layer with polycrystalline silicon is formed. To form the semiconductor layer, the first substrate is removed and replaced with the semiconductor layer. For example... Figure 12G As shown, for example, wafer polishing, dry etching, wet etching, CMP, or any other suitable process can be used to remove silicon substrate 1224. Figure 12F As shown in the diagram, to expose the channel structure of the NAND memory string 1228 from the source end (e.g., Figure 8C (e.g., bottom-opening channel structure 812C). Figure 12H As shown, a semiconductor layer 1240 with polysilicon is formed to contact the source of the NAND memory string 1228. The semiconductor layer 1240 can be formed by depositing polysilicon using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Similarly, a pad-out interconnect layer 1236, including contact pads 1238, can be formed on the semiconductor layer 1240. Contacts 1242 can be formed through the semiconductor layer 1240 with polysilicon after the semiconductor layer 1240 is formed.

[0186] Figures 13A-13H This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B Another manufacturing process for 3D memory devices. Figure 15 This illustrates some aspects of the method for forming according to this disclosure. Figure 10A and Figure 10B A flowchart of another method for 3D memory devices 1500. Figures 13A-13H and Figure 15 Examples of 3D memory devices depicted include Figure 11A-11C The 3D memory devices 1100, 1101, and 1103 depicted herein will be described together. Figures 13A-13H and Figure 15 It should be understood that the operations shown in method 1500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 15 The different execution sequences are shown. For example, operations 1502, 1504, and 1506 can be executed in parallel.

[0187] refer to Figure 15 Method 1500 begins with operation 1502, wherein a NAND memory string array is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, a memory stack is formed on the first substrate to form the NAND memory string array.

[0188] like Figure 13A As shown, a stacked structure, such as a memory stack 1304 including staggered conductive and dielectric layers, is formed on a silicon substrate 1302. To form the memory stack 1304, in some embodiments, a dielectric stack (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 1302. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1304 can then be formed by a gate replacement process, for example, replacing the sacrificial layers with conductive layers by wet / dry etching of the selectively dielectric sacrificial layers and filling the resulting recesses with conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 1304 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without using a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1304 and the silicon substrate 1302.

[0189] like Figure 13A As shown, NAND memory strings 1306 are formed above a silicon substrate 1302, each NAND memory string 1306 extending vertically through a memory stack 1304 to contact the silicon substrate 1302. In some embodiments, the fabrication process for forming the NAND memory strings 1306 includes: forming channel vias through the memory stack 1304 (or dielectric stack) and into the silicon substrate 1302 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers such as memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It should be understood that the details of fabricating the NAND memory strings 1306 can vary depending on the type of channel structure of the NAND memory strings 1306 (e.g., Figures 8A-8C The structure varies depending on whether it is a bottom plug channel structure 812A, a side wall plug channel structure 812B, or a bottom open channel structure 812C. Therefore, it is not described in detail for ease of description.

[0190] In some implementations, an interconnect layer is formed over a NAND memory string array on a first substrate. The interconnect layer may include a first plurality of interconnects within one or more ILD layers. Figure 13A As shown, an interconnect layer 1308 is formed over the memory stack 1304 and the NAND memory string 1306. The interconnect layer 1308 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to form an electrical connection with the NAND memory string 1306. In some embodiments, the interconnect layer 1308 includes a plurality of ILD layers and interconnects therein formed using a variety of processes. For example, the interconnects in the interconnect layer 1308 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 13A The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1308.

[0191] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 13AAs shown, a bonding layer 1310 is formed over the interconnect layer 1308. The bonding layer 1310 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1308 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1308 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0192] Method 1500 proceeds to operation 1504, such as... Figure 15 As shown, a first transistor is formed on a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 13B As shown, a plurality of transistors 1314 and 1316 are formed on a silicon substrate 1312. Transistors 1314 and 1316 can be formed by a variety of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1312 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1314 and 1316. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1312 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1314 differs from the thickness of the gate dielectric of transistor 1316 by depositing a thicker silicon oxide film in the region of transistor 1314 than in the region of transistor 1316, or by etching back portions of the silicon oxide film deposited in the region of transistor 1316. It should be understood that the details of fabricating transistors 1314 and 1316 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The specific details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore are not described in detail for ease of description.

[0193] In some embodiments, the interconnect layer 1318 is formed over the transistor on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 13BAs shown, interconnect layer 1318 may be formed over transistors 1314 and 1316. Interconnect layer 1318 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect to transistors 1314 and 1316. In some embodiments, interconnect layer 1318 includes a plurality of ILD layers and interconnects therein formed by a variety of processes. For example, interconnects in interconnect layer 1318 may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 13B The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1318.

[0194] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 13B As shown, a bonding layer 1320 is formed over an interconnect layer 1318. The bonding layer 1320 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1318 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1318 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0195] Method 1500 proceeds to operation 1506, such as... Figure 15 As shown, a second transistor is formed on a third substrate. The third substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, any two or all of operations 1502, 1504, and 1506 are performed in parallel to reduce processing time.

[0196] like Figure 13CAs shown, a plurality of transistors 1324 and 1326 are formed on a silicon substrate 1322. Transistors 1324 and 1326 can be formed by a variety of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1322 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1324 and 1326. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1322 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1324 differs from the thickness of the gate dielectric of transistor 1326 by depositing a thicker silicon oxide film in the region of transistor 1324 than in the region of transistor 1326, or by etching back portions of the silicon oxide film deposited in the region of transistor 1326. It should be understood that the details of fabricating transistors 1324 and 1326 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The specific details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore are not described in detail for ease of description.

[0197] In some embodiments, the interconnect layer 1328 is formed over the transistor on the third substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 13C As shown, interconnect layer 1328 may be formed over transistors 1324 and 1326. Interconnect layer 1328 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect to transistors 1324 and 1326. In some embodiments, interconnect layer 1328 includes a plurality of ILD layers and interconnects therein formed by a variety of processes. For example, interconnects in interconnect layer 1328 may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 13C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1328.

[0198] In some implementations, a third bonding layer is formed over the interconnect layer. The third bonding layer may include a plurality of third bonding contacts. For example... Figure 13CAs shown, a bonding layer 1330 is formed over the interconnect layer 1328. The bonding layer 1330 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1328 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1328 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0199] Method 1500 proceeds to operation 1508, such as... Figure 15 As shown, a first substrate and a second substrate are bonded face-to-face. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the first bonding interface. Bonding may include hybrid bonding.

[0200] like Figure 13D As shown, a silicon substrate 1302 and components formed thereon (e.g., a memory stack 1304 and a NAND memory string 1306 formed therethrough) are flipped over. A downward-facing bonding layer 1310 is bonded to an upward-facing bonding layer 1320, i.e., face-to-face bonding, thereby forming a bonding interface 1332. That is, the silicon substrate 1302 and components formed thereon can be bonded face-to-face to the silicon substrate 1312 and components formed thereon, such that bonding contacts in the bonding layer 1310 contact bonding contacts in the bonding layer 1320 at the bonding interface 1332. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surface prior to bonding. Although Figure 13D Not shown, but to be understood, in some examples, the silicon substrate 1312 and the components formed thereon (e.g., transistors 1314 and 1316) can be flipped upside down, and the downward-facing bonding layer 1320 can be bonded to the upward-facing bonding layer 1310, i.e., bonded face-to-face, thereby also forming a bonding interface 1332.

[0201] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1332 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1310 and bonding contacts in bonding layer 1320 are aligned and in contact with each other, such that the memory stack 1304 and the NAND memory string 1306 formed therethrough can be coupled to transistors 1314 and 1316 via the bonding contacts across bonding interface 1332.

[0202] In some embodiments, the second substrate is thinned, and contacts are formed through the thinned second substrate. For example... Figure 13E As shown, silicon substrate 1312 ( Figure 13D (As shown) Thinning to become a semiconductor layer 1334 with monocrystalline silicon. The silicon substrate 1312 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0203] like Figure 13E As shown, one or more contacts 1336 are formed, each contact 1336 extending vertically through the semiconductor layer 1334. The contacts 1336 can be coupled to interconnects in the interconnect layer 1318. The contacts 1336 can be formed by first patterning contact holes through the semiconductor layer 1334 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor. It should be understood that in some examples, thinning (the formation of the semiconductor layer 1334, e.g., in...) can be achieved... Figure 13B (In the middle) the contacts 1336 are formed in the silicon substrate 1312 and exposed from the back side of the silicon substrate 1312 (where the thinning occurs) after thinning.

[0204] In some embodiments, the bonding layer is on a thinned second substrate. The bonding layer may include multiple bonding contacts. Figure 13E As shown, after thinning, a bonding layer 1338 is formed on the semiconductor layer 1334, specifically on the back side of the silicon substrate 1312 (where thinning occurs). The bonding layer 1338 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the surface of the semiconductor layer 1334 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the contacts 1336 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor. It should be understood that in some examples, the bonding layer 1338 may be a dielectric layer without bonding contacts (e.g., a silicon oxide layer) for fusion bonding rather than hybrid bonding. It should also be understood that in some examples, bonding layer 1338 may be omitted to expose the silicon surface of semiconductor layer 1334 for anodic bonding or fusion bonding, rather than hybrid bonding.

[0205] Method 1500 proceeds to operation 1510, such as... Figure 15 As shown, a third substrate and a second substrate are bonded in a face-to-back configuration. After bonding the third and second substrates, a third bonding contact in the third bonding layer can contact a fourth bonding contact in the fourth bonding layer at the second bonding interface. Bonding may include hybrid bonding.

[0206] like Figure 13F As shown, after bonding to the silicon substrate 1312, the silicon substrate 1302 and the components formed thereon (e.g., memory stack 1304, NAND memory string 1306, and transistors 1314 and 1316) are flipped over. The downward-facing bonding layer 1338 is bonded to the upward-facing bonding layer 1330, i.e., face-to-face bonding, thereby forming a bonding interface 1340. That is, the silicon substrate 1302 and the components formed thereon can be bonded to the silicon substrate 1322 and the components formed thereon in a face-to-face manner, such that the bonding contacts in the bonding layer 1338 contact the bonding contacts in the bonding layer 1330 at the bonding interface 1340. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surface prior to bonding. Although Figure 13F Not shown, but to be understood, in some examples, the silicon substrate 1322 and the components formed thereon (e.g., transistors 1324 and 1326) can be flipped upside down, and the downward-facing bonding layer 1330 can be bonded to the upward-facing bonding layer 1338, i.e., bonded face-to-face, thereby also forming the bonding interface 1340.

[0207] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1340 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1338 and bonding contacts in bonding layer 1330 are aligned and in contact with each other, such that the memory stack 1304, NAND memory string 1306, and transistors 1314 and 1316 can be coupled to transistors 1324 and 1326 via contacts 1336 through semiconductor layer 1334 and bonding contacts across bonding interface 1340. It should be understood that in some examples, anodic bonding or fusion bonding, instead of hybrid bonding, can be performed to bond silicon substrates 1302 and 1322 (and components formed thereon) at bonding interface 1340 without the bonding contacts in bonding layer 1338.

[0208] Method 1500 proceeds to operation 1512, such as... Figure 15 As shown, either the first substrate or the third substrate is thinned. Figure 13G As shown, silicon substrate 1322 ( Figure 13FThe silicon substrate 1322 (as shown) is thinned to become a semiconductor layer 1342 with monocrystalline silicon. The silicon substrate 1322 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0209] Method 1500 proceeds to operation 1514, such as... Figure 15 As shown, a pad-out interconnect layer is formed therein. This pad-out interconnect layer can be formed on a thinned third substrate or above a NAND memory string array. For example... Figure 13G As shown, a pad-out interconnect layer 1346 is formed on a semiconductor layer 1342 (thinned silicon substrate 1322). The pad-out interconnect layer 1346 may include interconnects formed in one or more ILD layers, such as contact pads 1348. Contact pads 1348 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1344 extending vertically through the semiconductor layer 1342 are formed, for example, by wet / dry etching, followed by deposition of a dielectric material as a spacer and deposition of a conductive material as a conductor. Contacts 1344 can couple the contact pads 1348 in the pad-out interconnect layer 1346 to the interconnects in the interconnect layer 1328. It should be understood that in some examples, during the thinning (formation of semiconductor layer 1342, e.g., on...) Figure 13C (In the middle) the contacts 1344 are formed in the silicon substrate 1322 and exposed from the back side of the silicon substrate 1322 (where the thinning occurs) after thinning.

[0210] In some embodiments, the first substrate is thinned, and interconnect layers are formed on the thinned first substrate using pads. For example... Figure 13H As shown, silicon substrate 1302 ( Figure 13F (As shown) the silicon substrate 1302 is thinned to form a semiconductor layer 1303 with monocrystalline silicon. The silicon substrate 1302 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. Figure 13HAs shown, a pad-out interconnect layer 1346 is formed on semiconductor layer 1303 (thinned silicon substrate 1302). The pad-out interconnect layer 1346 may include interconnects formed in one or more ILD layers, such as contact pads 1348. In some embodiments, after bonding and thinning, contacts 1335 extending vertically through semiconductor layer 1303 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as spacers and deposition of a conductive material as a conductor. Contacts 1335 can couple the contact pads 1348 in the pad-out interconnect layer 1346 to interconnects in interconnect layer 1308. It should be understood that in some examples, thinning may be performed before thinning (i.e., before forming semiconductor layer 1303, for example, after...). Figure 13A (In the middle) a contact 1335 is formed in the silicon substrate 1302 without completely penetrating it, and the contact 1335 is exposed from the back side of the silicon substrate 1302 (where thinning occurs) after thinning. It should also be understood that in some examples, the first substrate (e.g., the thinned silicon substrate 1302 or semiconductor layer 1303) can be in accordance with the above description regarding... Figure 12G and Figure 12H The similar approach described was removed and replaced with a semiconductor layer with polycrystalline silicon.

[0211] Figure 16A and Figure 16B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of a cross-section of the 3D memory device. 3D memory devices 1600 and 1601 can be... Figure 9A and Figure 9B Examples of 3D memory devices 900 and 901 in the example. Figure 16A As shown, the 3D memory device 1600 may include stacked first, second, and third semiconductor structures 102, 104, and 106. In some embodiments, the first semiconductor structure 102 on one side of the 3D memory device 1600 includes a semiconductor layer 1002, a bonding layer 1008, and a memory cell array vertically located between the semiconductor layer 1002 and the bonding layer 1008. The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the NAND memory string array may be in contact with the semiconductor layer 1002 (e.g., as shown in the diagram). Figures 8A-8C(As shown). Semiconductor layer 1002 may include semiconductor materials, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate) or polycrystalline silicon (e.g., a deposited layer), for example, depending on the type of channel structure of the NAND memory string (e.g., bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C). Bonding layer 1008 may include dielectrics for conductive bonding contacts (not shown) and electrically isolated bonding contacts, which can be used for hybrid bonding, for example, as described in detail below.

[0212] In some embodiments, a second semiconductor structure 104 in the middle of the 3D memory device 1600 includes a semiconductor layer 1004, a bonding layer 1010, and some peripheral circuitry of a memory cell array vertically located between the semiconductor layer 1004 and the bonding layer 1010. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. The semiconductor layer 1004 may include a semiconductor material, such as monocrystalline silicon (e.g., a layer transferred from a silicon substrate or SOI substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 may also include a dielectric for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, the bonding interface 103 is vertically located between bonding layers 1008 and 1010 and contacts bonding layers 1008 and 1010, respectively. That is, bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of bonding layer 1008 can contact the bonding contacts of bonding layer 1010 at the bonding interface 103. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 103 can form direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0213] In some embodiments, a third semiconductor structure 106 on the other side of the 3D memory device 1600 includes a semiconductor layer 1006 and some peripheral circuitry for the memory cell array, such that the semiconductor layer 1006 is vertically disposed between the peripheral circuitry and the bonding interface 105. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1006. The semiconductor layer 1006 may include a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1006 on which transistors are formed may include monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. It should be understood that, unlike the bonding interface 103 between the first and second semiconductor structures 102 and 104, located between bonding layers 1008 and 1010 and formed by hybrid bonding, the bonding interface 105 between the second and third semiconductor structures 104 and 106 can be formed by transfer bonding as described in detail below, and therefore does not need to be formed between the two bonding layers. That is, according to some embodiments, Figure 16A The third semiconductor structure 106 of the 3D memory device 1600 does not include a bonding layer with bonding contacts. As a result, instead of bonding contacts, through contacts (e.g., ILV / TSV) located vertically between the second and third semiconductor structures 104 and 106, across the bonding interface 105 and through the semiconductor layers 1004 and 1006 can form direct, short-distance (e.g., submicron) electrical connections between adjacent semiconductor structures 104 and 106.

[0214] It should be understood that, in some examples, the second and third semiconductor structures 104 and 106 may further include bonding layers 1012 and 1014 respectively disposed on opposite sides of the bonding interface 105, such as Figure 16B As shown. In Figure 16B In the 3D memory device 1601, the second semiconductor structure 104 may include two bonding layers 1010 and 1012 on its two sides, and the bonding layer 1012 may be vertically disposed between the semiconductor layer 1004 and the bonding interface 105. The third semiconductor structure 106 of the 3D memory device 1601 may include a bonding layer 1014 vertically disposed between the bonding interface 105 and the semiconductor layer 1006. Each bonding layer 1012 or 1014 may include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. The bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, the bonding contacts across the bonding interface 105, combined with through contacts (e.g., ILV / TSV) through the semiconductor layers 1004 and 1006, can form a direct, short-distance (e.g., micrometer-scale) electrical connection between adjacent semiconductor structures 104 and 106.

[0215] like Figure 16A and Figure 16B As shown, according to some embodiments, since the third and second semiconductor structures 106 and 104 are bonded back-to-back (e.g., in...), Figure 16A and Figure 16B In this configuration, semiconductor layer 1006 is disposed on the bottom side of third semiconductor structure 106, while semiconductor layer 1004 is disposed on the top side of second semiconductor structure 104. Transistors in the third and second semiconductor structures 106 and 104 are arranged back-to-back. In some embodiments, semiconductor layer 1006 is vertically disposed between the transistors of the peripheral circuit in the third semiconductor structure 106 and the bonding interface 105, and transistors of the peripheral circuit in the second semiconductor structure 104 are vertically disposed between the bonding interface 103 and semiconductor layer 1004. Furthermore, according to some embodiments, since the first and second semiconductor structures 102 and 104 are bonded face-to-face (e.g., in…),… Figure 16A and Figure 16B In this configuration, semiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104. The transistors of the peripheral circuitry in the second semiconductor structure 104 and the memory cell array in the first semiconductor structure 102 are arranged facing each other. It should be understood that, for ease of description, Figure 9A or Figure 9B The pads in the 902 interconnect layer can be brought out from the pads. Figure 16A and Figure 16B The 3D memory devices 1600 and 1601 are omitted in the above description and may be included in the following description. Figure 9A and Figure 9B In the described 3D memory devices 1600 and 1601.

[0216] As described above, the second and third semiconductor structures 104 and 106 can have peripheral circuitry, which includes transistors with different applied voltages. For example, the third semiconductor structure 106 can be... Figure 4B An example of a semiconductor structure 408 including an LLV circuit 402 (and in some examples, an LV circuit 404), and the second semiconductor structure 104 may be Figure 4BAn example of a semiconductor structure 410 including an HV circuit 406 (and in some examples, an LLV circuit 404), and vice versa. Therefore, in some embodiments, the semiconductor layers 1006 and 1004 in the third and second semiconductor structures 106 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the second semiconductor structure 104 may include an HV circuit 406 and the third semiconductor structure 106 may include an LLV circuit 402, and the thickness of the semiconductor layer 1006 in the third semiconductor structure 106 may be less than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the third and second semiconductor structures 106 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the second semiconductor structure 104 may include an HV circuit 406 and the third semiconductor structure 106 may include an LLV circuit 402, and the thickness of the gate dielectric of the transistor in the second semiconductor structure 104 may be greater than the thickness of the gate dielectric of the transistor in the third semiconductor structure 106 (e.g., at least 5 times).

[0217] Figures 17A-17C Showing various aspects according to this disclosure Figure 16A and Figure 16B Side views of various examples of 3D memory devices 1600 and 1601. Figure 17A As shown, as Figure 16A and Figure 16B An example of 3D memory devices 1600 and 1601 is, according to some embodiments, a 3D memory device 1700, which is a bonded chip including a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106, which are oriented vertically (e.g., Figure 17A The semiconductor structures are stacked on top of each other in different planes (in the y-direction). According to some embodiments, the first and second semiconductor structures 102 and 104 are bonded at a bonding interface 103 therebetween, and the second and third semiconductor structures 104 and 106 are bonded at a bonding interface 105 therebetween.

[0218] like Figure 17AAs shown, the third semiconductor structure 106 may include a semiconductor layer 1006 having a semiconductor material. In some embodiments, the semiconductor layer 1006 is a silicon substrate having monocrystalline silicon. In some embodiments, the semiconductor layer 1006 is a monocrystalline silicon layer transferred from a silicon substrate or SOI substrate and attached to the back side of the second semiconductor structure 104 by transfer bonding. The third semiconductor structure 106 may also include a device layer 1702 above and in contact with the semiconductor layer 1006. In some embodiments, the device layer 1702 includes a first peripheral circuit 1704 and a second peripheral circuit 1706. The first peripheral circuit 1704 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the second peripheral circuit 1706 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic unit 312). In some embodiments, the first peripheral circuit 1704 includes a plurality of transistors 1708 in contact with the semiconductor layer 1006, and the second peripheral circuit 1706 includes a plurality of transistors 1710 in contact with the semiconductor layer 1006. Transistors 1708 and 1710 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described above in detail with respect to transistors 500 and 600, in some embodiments, each transistor 1708 or 1710 includes a gate dielectric, and the thickness of the gate dielectric of transistor 1708 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 1710 (e.g., in LV circuit 404) because the voltage applied to transistor 1708 is lower than the voltage applied to transistor 1710. Trench isolation (e.g., STI) and doped regions (well, source, and drain of transistors 1708 and 1710) may also be formed on or in the semiconductor layer 1006.

[0219] In some embodiments, the third semiconductor structure 106 further includes an interconnect layer 1712 above the device layer 1702 to transmit electrical signals to and from peripheral circuits 1706 and 1704. For example... Figure 17AAs shown, device layer 1702 (including transistors 1708 and 1710 of peripheral circuits 1704 and 1706) can be vertically disposed between bonding interface 105 and interconnect layer 1712. Interconnect layer 1712 may include multiple interconnects. Interconnects in interconnect layer 1712 can be coupled to transistors 1708 and 1710 of peripheral circuits 1704 and 1706 in device layer 1702. Interconnect layer 1712 may also include one or more ILD layers, in which lateral lines and vias can be formed. That is, interconnect layer 1712 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1702 are coupled to each other through interconnects in interconnect layer 1712. For example, peripheral circuit 1704 can be coupled to peripheral circuit 1706 through interconnect layer 1712. Interconnects in interconnect layer 1712 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1712 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0220] In some embodiments, the interconnects in interconnect layer 1712 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metallic materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with interconnect layer 1712 having Cu may become feasible because the fabrication of interconnect layer 1712 can occur after the high-temperature processes forming device layers 1714 and 1702 in the second and third semiconductor structures 104 and 106, and is decoupled from the high-temperature processes forming the first semiconductor structure 102.

[0221] like Figure 17A As shown, the second semiconductor structure 104 may further include one or more contacts 1723 extending vertically through the semiconductor layer 1006. In some embodiments, the contacts 1723 are coupled to interconnects in the interconnect layer 1712. The contacts 1723 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1723 include W. In some embodiments, the contacts 1723 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1006. Depending on the thickness of the semiconductor layer 1006, the contacts 1723 may be ILVs with submicron-level (e.g., between 10 nm and 1 μm) depths, or TSVs with micron-level or tens of micron-level (e.g., between 1 μm and 100 μm) depths.

[0222] The second semiconductor structure 104 can be bonded to the third semiconductor structure 106 in a back-to-back manner at the bonding interface 105. The second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some embodiments, as a result of transfer bonding, the bonding interface 105 is vertically disposed between the interconnect layer 1112 and the semiconductor layer 1004, and the transfer bonding transfers the semiconductor layer 1004 from another substrate and bonds the semiconductor layer 1004 to the third semiconductor structure 106, as described in detail below. In some embodiments, the bonding interface 105 is the place where the interconnect layer 1112 and the semiconductor layer 1004 meet and bond. In practice, the bonding interface 105 may be a layer of a certain thickness, including the top surface of the interconnect layer 1112 of the third semiconductor structure 106 and the bottom surface of the semiconductor layer 1004 of the second semiconductor structure 104. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1004 and / or between the bonding interface 105 and the interconnect layer 1112 to facilitate transfer bonding from the semiconductor layer 1004 to the interconnect layer 1112. Therefore, it can be understood that in some examples, the bonding interface 105 may include the surface of the dielectric layer.

[0223] The second semiconductor structure 104 may include a device layer 1714 located below and in contact with the semiconductor layer 1004. In some embodiments, the device layer 1714 includes a third peripheral circuit 1716 and a fourth peripheral circuit 1718. The third peripheral circuit 1716 may include HV circuitry 406, such as driver circuitry (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the fourth peripheral circuitry 1718 may include LV circuitry 404, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffer 304) and logic circuitry (e.g., in a control logic unit 312). In some embodiments, the third peripheral circuitry 1716 includes a plurality of transistors 1720, and the fourth peripheral circuitry 1718 also includes a plurality of transistors 1722. Transistors 1720 and 1722 may include any transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1720 or 1722 includes a gate dielectric, and the thickness of the gate dielectric of transistor 1720 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1722 (e.g., in LV circuit 404) because the voltage applied to transistor 1720 is higher than the voltage applied to transistor 1722. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 1720 and 1722) may also be formed on or in semiconductor layer 1004.

[0224] Furthermore, different voltages applied to the different transistors 1720, 1722, 1708, and 1710 in the second and third semiconductor structures 104 and 106 can lead to differences in device dimensions between the second and third semiconductor structures 104 and 106. In some embodiments, the thickness of the gate dielectric of transistor 1720 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1708 (e.g., in LLV circuit 402) because the voltage applied to transistor 1720 is higher than the voltage applied to transistor 1708. In some embodiments, the thickness of the gate dielectric of transistor 1722 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 1710 (e.g., in LV circuit 404) because the voltages applied to transistors 1722 and 1710 are the same. In some embodiments, the thickness of the semiconductor layer 1006 in which transistor 1708 is formed (e.g., in LLV circuit 402) is less than the thickness of the semiconductor layer 1004 in which transistor 1720 is formed (e.g., in HV circuit 406) because the voltage applied to transistor 1708 is lower than the voltage applied to transistor 1720.

[0225] like Figure 17A As shown, the second semiconductor structure 104 may further include an interconnect layer 1726 below the device layer 1714 to transmit electrical signals to and from peripheral circuits 1716 and 1718. Figure 17A As shown, interconnect layer 1726 may be vertically located between bonding interface 103 and device layer 1714 (including transistors 1720 and 1722 of peripheral circuits 1716 and 1718). Interconnect layer 1726 may include multiple interconnects of transistors 1720 and 1722 of peripheral circuits 1716 and 1718 coupled to device layer 1714. Interconnect layer 1726 may also include one or more ILD layers in which interconnects can be formed. That is, interconnect layer 1726 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1714 are coupled to each other through interconnects in interconnect layer 1726. For example, peripheral circuit 1716 may be coupled to peripheral circuit 1718 through interconnect layer 1726. Interconnects in interconnect layer 1726 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1726 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1726 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0226] like Figure 17A As shown, the second semiconductor structure 104 may further include one or more contacts 1724 extending vertically through the semiconductor layer 1004. In some embodiments, contacts 1724 are coupled to interconnects in interconnect layer 1726. In some embodiments, contacts 1724 contact contacts 1723 such that contacts 1723 and 1724 couple interconnects in interconnect layer 1726 to interconnects in interconnect layer 1712 to form an electrical connection across the bonding interface 105 between the second and third semiconductor structures 104 and 106 and through semiconductor layers 1004 and 1006. Contacts 1724 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, contacts 1724 include W. In some embodiments, contacts 1724 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 1724 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0227] like Figure 17A As shown, the second semiconductor structure 104 may further include a bonding layer 1010 at the bonding interface 103 and above and in contact with the interconnect layer 1726. The bonding layer 1010 may include a plurality of bonding contacts 1011 and a dielectric for electrically isolating the bonding contacts 1011. The bonding contacts 1011 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 1011 of the bonding layer 1010 include Cu. The remaining region of the bonding layer 1010 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 1011 in the bonding layer 1010 and the surrounding dielectric can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO2-to-SiO2) bonding.

[0228] like Figure 17AAs shown, the first semiconductor structure 102 may further include a bonding layer 1008 at a bonding interface 103, for example, a bonding layer 1008 on the opposite side of the bonding interface 103 relative to the bonding layer 1010 in the second semiconductor structure 104. The bonding layer 1008 may include a plurality of bonding contacts 1009 and a dielectric material for electrically isolating the bonding contacts 1009. The bonding contacts 1009 may include a conductive material, such as Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material, such as silicon oxide. The bonding contacts 1009 in the bonding layer 1008 and the surrounding dielectric material may be used for mixed bonding. In some embodiments, the bonding interface 103 is where the bonding layers 1008 and 1010 meet and bond. In practice, the bonding interface 103 may be a layer of a certain thickness, comprising the top surface of the bonding layer 1010 of the second semiconductor structure 104 and the bottom surface of the bonding layer 1008 of the first semiconductor structure 102.

[0229] like Figure 17A As shown, the first semiconductor structure 102 may further include an interconnect layer 1728 beneath and in contact with the bonding layer 1008 for transmitting electrical signals. The interconnect layer 1728 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1728 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1728 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 1728 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1728 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0230] like Figure 17A As shown, the first semiconductor structure 102 may include an array of memory cells, such as an array of NAND memory strings 208 below and in contact with the interconnect layer 1728. In some embodiments, the interconnect layer 1728 is vertically positioned between the NAND memory strings 208 and the bonding interface 103. According to some embodiments, each NAND memory string 208 extends vertically through multiple pairs, each pair including a conductive layer and a dielectric layer. Stacked and interleaved conductive and dielectric layers are also referred to herein as stacked structures, such as memory stack 1727. Memory stack 1727 may be... Figures 8A-8CExamples of memory stacks 804 include the conductive and dielectric layers in memory stack 1727, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack 1727 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating in one or more stepped structures in memory stack 1727.

[0231] In some implementations, each NAND memory string 208 is a "charge-trapping" type NAND memory string, including any suitable channel structure disclosed herein, such as those mentioned above. Figures 8A-8C The bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C are described in detail. It should be understood that the NAND memory string 208 is not limited to the "charge-trapping" type NAND memory string and may be the "floating gate" type NAND memory string in other examples.

[0232] like Figure 17A As shown, the first semiconductor structure 102 may further include a semiconductor layer 1002 disposed below the memory stack 1727 and in contact with the source of the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the bonding interface 103 and the semiconductor layer 1002. The semiconductor layer 1002 may include a semiconductor material. In some embodiments, the semiconductor layer 1002 is a thinned silicon substrate having monocrystalline silicon on which the memory stack 1727 and the NAND memory string 208 are formed (e.g., including a bottom plug channel structure 812A or a sidewall plug channel structure 812B). It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the semiconductor layer 1002.

[0233] like Figure 17A As shown, the third semiconductor structure 106 may further include a pad-out interconnect layer 902 above and in contact with the interconnect layer 1712. In some embodiments, the device layer 1702 having transistors 1708 and 1710 is vertically disposed between the pad-out interconnect layer 902 and the semiconductor layer 1006. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 1732. The pad-out interconnect layer 902 and the interconnect layer 1712 may be formed on the same side of the semiconductor layer 1006. In some embodiments, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 1700 and an external device, for example, for pad-out purposes.

[0234] As a result, the peripheral circuits 1704, 1706, 1716, and 1718 in the third and second semiconductor structures 106 and 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures including interconnect layers 1712, 1726, and 1728, bonding layers 1008 and 1010, and contacts 1723 and 1724. Furthermore, the peripheral circuits 1704, 1706, 1716, and 1718 in the 3D memory device 1700, as well as the NAND memory string 208, can be further coupled to external devices via the pad-out interconnect layer 902.

[0235] It should be understood that, in some examples, similar to bonding interface 103, bonding interface 105 can be generated by hybrid bonding and thus vertically disposed between two bonding layers, each bonding layer comprising bonding contacts in the second and third semiconductor structures 104 and 106, respectively. For example, as Figure 17B As shown, the 3D memory device 1701 may include bonding layers 1012 and 1014 in second and third semiconductor structures 104 and 106, respectively, at bonding interface 105 (i.e., on opposite sides of bonding interface 105). Bonding layer 1012 or 1014 may include a plurality of bonding contacts 1013 or 1015 and a dielectric for electrically isolating the bonding contacts 1013 or 1015. Bonding contacts 1013 and 1015 may include a conductive material, such as Cu. The remaining region of bonding layer 1012 or 1014 may be formed of a dielectric material, such as silicon oxide. The bonding contacts 1013 or 1015 and the surrounding dielectric in bonding layer 1012 or 1014 may be used for mixed bonding. In some embodiments, bonding interface 105 is where bonding layers 1012 and 1014 meet and bond. In practice, the bonding interface 105 can be a layer of a certain thickness, including the top surface of the bonding layer 1014 of the third semiconductor structure 106 and the bottom surface of the bonding layer 1012 of the second semiconductor structure 104. The contact 1723 can be coupled to the contact 1724 through the bonding contacts 1013 and 1015 across the bonding layers 1012 and 1014 of the bonding interface 105.

[0236] It should also be understood that the pad leads of 3D memory devices are not limited to those from, for example... Figure 17A The third semiconductor structure 106 shown has transistors 1708 and 1710 (corresponding to Figure 9A ) and can be obtained from the first semiconductor structure 102 having NAND memory string 208 (corresponding to Figure 9B For example, such as Figure 17BAs shown, the 3D memory device 1701 may include a pad-out interconnect layer 902 in a first semiconductor structure 102. The pad-out interconnect layer 902 may contact a semiconductor layer 1002 of the first semiconductor structure 102 on which NAND memory strings 208 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 1730 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1730 couple interconnects in interconnect layers 1728 in the first semiconductor structure 102 to contact pads 1732 in the pad-out interconnect layer 902 to form an electrical connection through the semiconductor layer 1002. The contacts 1730 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1730 include W. In some embodiments, the contacts 1730 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically decouple the vias from the semiconductor layer 1002. Depending on the thickness of semiconductor layer 1002, contact 1730 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm), or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm). In some embodiments, in Figure 17B In the 3D memory device 1701, the third semiconductor structure 106 further includes a passivation layer 1734, replacing... Figure 17B The pads in the pads lead out to interconnect layer 902. Passivation layer 1734 may include a dielectric material, such as silicon nitride and / or silicon oxide. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 1700 and 1701 will not be repeated.

[0237] It should also be understood that the material of the semiconductor layer 1002 in the first semiconductor structure 102 is not limited to the above-mentioned... Figure 17A and Figure 17B The single-crystal silicon mentioned above can be any other suitable semiconductor material. For example, such as... Figure 17CAs shown, the 3D memory device 1703 may include a polysilicon semiconductor layer 1002 in the first semiconductor structure 102. The NAND memory string 208 of the 3D memory device 1703, in contact with the polysilicon semiconductor layer 1002, may include any suitable channel structure disclosed herein that contacts the polysilicon layer, such as a bottom-opening channel structure 812C. In some embodiments, the NAND memory string 208 of the 3D memory device 1703 is a "floating gate" type NAND memory string, and the polysilicon semiconductor layer 1002 contacts the "floating gate" type NAND memory string as its source plate. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 1700 and 1703 will not be repeated.

[0238] Figures 18A-18F This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B The manufacturing process of 3D memory devices. Figure 20 This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B A flowchart of a method for a 3D memory device in 2000. Figures 18A-18F and Figure 20 Examples of 3D memory devices depicted include Figures 17A-17C The 3D memory devices 1700, 1701, and 1703 depicted in the figure will be described together. Figures 18A-18F and Figure 20 It should be understood that the operations shown in Method 2000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 20 The different execution sequences are shown. In one example, operation 2002 can be executed after operation 2008 or in parallel with operations 2004-2008. In another example, operation 2010 can be executed before operations 2006 and 2008.

[0239] refer to Figure 20 Method 2000 begins with operation 2002, wherein a NAND memory string array is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, a memory stack is formed on the first substrate to form the NAND memory string array.

[0240] like Figure 18DAs shown, a stacked structure, such as a memory stack 1826 including staggered conductive and dielectric layers, is formed on a silicon substrate 1824. To form the memory stack 1826, in some embodiments, a dielectric stack (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 1824. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1826 can then be formed by a gate replacement process, for example, replacing the sacrificial layers with conductive layers by wet / dry etching of the sacrificial layers selectively applied to the dielectric layers and filling the resulting recesses with conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 1826 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without using a gate replacement process. In some embodiments, a pad oxide layer including silicon oxide is formed between the memory stack 1826 and the silicon substrate 1824.

[0241] like Figure 18D As shown, NAND memory strings 1828 are formed above a silicon substrate 1824, with each NAND memory string 1828 extending vertically through a memory stack 1826 to contact the silicon substrate 1824. In some embodiments, the fabrication process for forming the NAND memory strings 1828 includes: forming channel vias through the memory stack 1826 (or dielectric stack) and into the silicon substrate 1824 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers such as memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It should be understood that the details of fabricating the NAND memory strings 1828 can vary depending on the type of channel structure of the NAND memory strings 1828 (e.g., Figures 8A-8C The structure varies depending on whether it is a bottom plug channel structure 812A, a side wall plug channel structure 812B, or a bottom open channel structure 812C. Therefore, it is not described in detail for ease of description.

[0242] In some implementations, an interconnect layer is formed over a NAND memory string array on a first substrate. The interconnect layer may include a first plurality of interconnects within one or more ILD layers. Figure 18DAs shown, interconnect layer 1830 is formed over memory stack 1826 and NAND memory string 1828. Interconnect layer 1830 may include interconnects of MEOL and / or BEOL in multiple ILD layers for electrical connection to NAND memory string 1828. In some embodiments, interconnect layer 1830 includes multiple ILD layers and interconnects formed therein using various processes. For example, interconnects in interconnect layer 1830 may include conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnect may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. ILD layers may include dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 18D The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1830.

[0243] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 18D As shown, a bonding layer 1832 is formed over the interconnect layer 1830. The bonding layer 1832 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1830 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1830 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0244] Method 2000 proceeds to operation 2004, such as... Figure 20 As shown, a first transistor is formed on a first side (e.g., a first surface) of a second substrate. The second substrate may be a silicon substrate having monocrystalline silicon. The first side may be the front side of the second substrate on which a device is formed.

[0245] like Figure 18AAs shown, a plurality of transistors 1804 and 1806 are formed on the front side of a silicon substrate 1802. Transistors 1804 and 1806 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1802 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1804 and 1806. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1802 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1804 differs from the thickness of the gate dielectric of transistor 1806 by depositing a thicker silicon oxide film in the region of transistor 1804 than in the region of transistor 1806, or by etching back portions of the silicon oxide film deposited in the region of transistor 1806. It should be understood that the details of fabricating transistors 1804 and 1806 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0246] In some embodiments, the interconnect layer 1808 is formed over the transistor on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 18A As shown, interconnect layer 1808 may be formed over transistors 1804 and 1806. Interconnect layer 1808 may include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect to transistors 1804 and 1806. In some embodiments, interconnect layer 1808 includes multiple ILD layers and interconnects formed therein using various processes. For example, interconnects in interconnect layer 1808 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 18A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1808. In some embodiments, the interconnects in interconnect layer 1808 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0247] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 18A As shown, a bonding layer 1822 is formed over the interconnect layer 1808. The bonding layer 1822 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1808 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1808 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0248] Method 2000 proceeds to Operation 2006, such as... Figure 20 As shown, a semiconductor layer is formed on a second side (e.g., a second surface) of a second substrate opposite to the first side. The semiconductor layer may include monocrystalline silicon. The second side may be the back side of the second substrate. In some embodiments, to form the semiconductor layer, another substrate and the second substrate are bonded together in a face-to-back manner, and the other substrate is thinned to leave the semiconductor layer. Bonding may include transfer bonding. The other substrate may be a silicon substrate having monocrystalline silicon.

[0249] In some embodiments, the second substrate is thinned before forming the semiconductor layer, such that a semiconductor layer is formed on a second side of the thinned second substrate. For example... Figure 18B As shown, silicon substrate 1802 ( Figure 18A The silicon substrate 1802 (shown in the diagram) is thinned to form a semiconductor layer 1809 having monocrystalline silicon. The silicon substrate 1802 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In some embodiments, such as... Figure 18B As shown, before thinning, for example, adhesive bonding is used to attach the processing substrate 1801 (also known as the carrier wafer) to the bonding layer 1822 to allow subsequent back-side processes on the silicon substrate 1802, such as thinning, contact formation and bonding.

[0250] In some embodiments, a first contact is formed through a thinned second substrate. For example... Figure 18BAs shown, one or more contacts 1817 are formed extending vertically through semiconductor layer 1809 (i.e., thinned silicon substrate 1802). Contacts 1817 can be coupled to interconnects in interconnect layer 1808. Contacts 1817 can be formed by first patterning contact holes through semiconductor layer 1809 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in dielectric layer). Contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., silicon oxide layer) before depositing the conductor. It should be understood that in some examples, contacts 1817 can be formed during the thinning (formation of semiconductor layer 1809, e.g., in...) Figure 18A The middle part was previously formed in the silicon substrate 1802 and was exposed from the back side of the silicon substrate 1802 (where the thinning occurred) after thinning.

[0251] like Figure 18B As shown, a semiconductor layer 1810, such as a single-crystal silicon layer, is formed on the back side (the thinned side) of semiconductor layer 1809 (i.e., the thinned silicon substrate 1802). Semiconductor layer 1810 can be attached to the back side of semiconductor layer 1810 to vertically form a bonding interface 1812 between semiconductor layer 1810 and semiconductor layer 1809. In some embodiments, to form semiconductor layer 1810, transfer bonding is used to attach another silicon substrate (… Figure 18B (Not shown in the diagram) and semiconductor layer 1809 (i.e., thinned silicon substrate 1802) are bonded in a face-to-back manner (the thinned silicon substrate 1802 is flipped upside down and components such as transistors 1804 and 1806 formed on the silicon substrate 1802 are facing away from the other silicon substrate) to form a bonding interface 1812. The other silicon substrate can then be thinned using any suitable process to leave a semiconductor layer 1810 attached to the back of semiconductor layer 1809 (i.e., thinned silicon substrate 1802). Details of various transfer bonding processes are described above regarding... Figures 48A-48D and Figures 49A-49D The description has already been provided, so it will not be repeated for the sake of clarity.

[0252] refer to Figure 20 Method 2000 proceeds to operation 2008, in which a second transistor is formed on the semiconductor layer. For example... Figure 18CAs shown, a plurality of transistors 1814 and 1816 are formed on a semiconductor layer 1810 having monocrystalline silicon. Transistors 1814 and 1816 can be formed by a variety of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the semiconductor layer 1810 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1814 and 1816. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 1810 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1814 differs from the thickness of the gate dielectric of transistor 1816 by depositing a thicker silicon oxide film in the region of transistor 1814 than in the region of transistor 1816, or by etching back portions of the silicon oxide film deposited in the region of transistor 1816. It should be understood that the details of fabricating transistors 1814 and 1816 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0253] In some implementations, the interconnect layer 1820 is formed above the transistors on the semiconductor layer. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 18C As shown, interconnect layer 1820 may be formed over transistors 1814 and 1816. Interconnect layer 1820 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect to transistors 1814 and 1816. In some embodiments, interconnect layer 1820 includes a plurality of ILD layers and interconnects therein formed by a variety of processes. For example, interconnects in interconnect layer 1820 may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 18CThe ILD layer and interconnects shown can be collectively referred to as interconnect layer 1820. Unlike interconnect layer 1808, in some embodiments, the interconnects in interconnect layer 1820 comprise Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it may become feasible to use Cu as the conductive material for the interconnects in interconnect layer 1820 because there are no further high-temperature processes after the fabrication of interconnect layer 1820.

[0254] In some implementations, a second contact is formed that passes through the semiconductor layer and is coupled to the first contact. For example... Figure 18C As shown, one or more contacts 1818 are formed, each contact 1818 extending vertically through the semiconductor layer 1810. Contacts 1818 can be aligned to contact contact 1817 at bonding interface 1812. Contacts 1818 and 1817 can couple interconnects in interconnect layers 1820 and 1808 across bonding interface 1812 and through semiconductor layers 1810 and 1809. Contacts 1818 can be formed by first patterning contact holes through semiconductor layer 1810 and aligned with contacts 1817 at bonding interface 1812 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in a dielectric layer). Contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0255] Method 2000 proceeds to operation 2010, such as... Figure 20 As shown, a first substrate and a second substrate are bonded face-to-face. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0256] like Figure 18E As shown, in the removal process of substrate 1801 (e.g., Figure 18CAfter exposing the bonding layer 1822 (as shown in the diagram), the thinned silicon substrate 1802 (i.e., semiconductor layer 1809) and the components formed thereon (e.g., transistors 1804 and 1806) are flipped over. The bottom-facing bonding layer 1822 is bonded to the top-facing bonding layer 1832, i.e., face-to-face bonding, thereby forming a bonding interface 1834. That is, the thinned silicon substrate 1802 and the components formed thereon can be bonded to the silicon substrate 1824 and the components formed thereon in a face-to-face manner, such that the bonding contacts in the bonding layer 1822 contact the bonding contacts in the bonding layer 1832 at the bonding interface 1834. Transistors 1806 and 1804 and the NAND memory string 1828 can face each other after bonding. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surface before bonding. Although Figure 18E Not shown, but it should be understood that in some examples, the silicon substrate 1824 and the components formed thereon (e.g., memory stack 1826 and NAND memory string 1828) can be flipped upside down, and the downside bonding layer 1832 can be bonded to the upside bonding layer 1822, i.e., bonded face to face, thereby also forming the bonding interface 1834.

[0257] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1834 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1832 and bonding contacts in bonding layer 1822 are aligned and in contact with each other, such that the memory stack 1826 and the NAND memory string 1828 formed therethrough can be coupled to transistors 1814, 1816, 1804, and 1806 via the bonding contacts across bonding interface 1834. It should be understood that in some examples, the bonding layer may be formed over interconnect layer 1820 instead of interconnect layer 1808, and the thinned silicon substrate 1802 and components formed thereon may be bonded to the silicon substrate 1824 and components formed thereon in a back-to-back manner, such that transistors 1816 and 1814 and the NAND memory string 1828 can face each other after bonding.

[0258] It should be understood that in some examples, operation 2010 can be performed before operations 2006 and 2008. That is, after forming a NAND memory string array on the first substrate at operation 2002 and forming a first transistor on the first side of the second substrate at operation 2004 (operations 2002 and 2004 can be performed in parallel), method 2000 can proceed to operation 2010 to bond the first and second substrates face-to-face. Method 2000 can then proceed to operation 2006 to form a semiconductor layer on the second side of the second substrate and operation 2008 to form a second transistor on the semiconductor layer. Therefore, due to the bonded first substrate (e.g., Figure 18D The silicon substrate 1824 in the process can be used as a base substrate when performing operations 2006 and 2008, so it may not be necessary to process the substrate (e.g., Figure 18B The attachment of the processing substrate 1801 in the process simplifies the process.

[0259] Method 2000 skips optional operation 2012 and proceeds to operation 2014, such as... Figure 20 As shown, a pad-out interconnect layer is formed therein. This pad-out interconnect layer can be formed above the second transistor. (As shown...) Figure 18F As shown, a pad-lead interconnect layer 1836 is formed above transistors 1814 and 1816 on interconnect layer 1820 and semiconductor layer 1810. The pad-lead interconnect layer 1836 may include interconnects formed in one or more ILD layers, such as contact pads 1838. Contact pads 1838 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0260] In some embodiments, in order to form pads to lead out interconnect layers on the first substrate, after operation 2010, method 2000 proceeds to optional operation 2012, such as... Figure 20 As shown, a first substrate is thinned. It should be understood that, although not shown, in some examples, the silicon substrate 1824 may be thinned to become a semiconductor layer having single-crystal silicon using processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. After thinning, contacts extending vertically through the thinned silicon substrate 1824 may be formed, for example by wet / dry etching, followed by deposition of a dielectric material as spacers and deposition of a conductive material as a conductor. It should be understood that in some examples, the contacts may be formed in the silicon substrate 1824 before thinning and exposed from the back side of the silicon substrate 1824 (where thinning occurs) after thinning.

[0261] Method 2000 proceeds to operation 2014, such as... Figure 20 As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned first substrate. It should be understood that, although not shown, in some examples, a pad-out interconnect layer with contact pads can be formed on a thinned silicon substrate 1824.

[0262] Figures 19A-19F This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B Another manufacturing process for 3D memory devices. Figure 21 This illustrates some aspects of the method for forming according to this disclosure. Figure 16A and Figure 16B A flowchart of another method 2100 for 3D memory devices. Figures 19A-19F and Figure 21 Examples of 3D memory devices depicted include Figures 17A-17C The 3D memory devices 1700, 1701, and 1703 depicted in the figure will be described together. Figures 19A-19F and Figure 21 It should be understood that the operations shown in method 2100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 21 The different execution orders are shown. In one example, operations 2102, 2104, and 2106 can be executed in parallel. In another example, operation 2110 can be executed before operation 2108.

[0263] refer to Figure 21 Method 2100 begins with operation 2102, wherein a NAND memory string array is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, a memory stack is formed on the first substrate to form the NAND memory string array.

[0264] like Figure 19AAs shown, a stacked structure, such as a memory stack 1904 including staggered conductive and dielectric layers, is formed on a silicon substrate 1902. To form the memory stack 1904, in some embodiments, a dielectric stack (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 1902. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1904 can then be formed by a gate replacement process, for example, replacing the sacrificial layers with conductive layers by wet / dry etching of the sacrificial layers selectively applied to the dielectric layers and filling the resulting recesses with conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 1904 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without using a gate replacement process. In some embodiments, a pad oxide layer including silicon oxide is formed between the memory stack 1904 and the silicon substrate 1902.

[0265] like Figure 19A As shown, NAND memory strings 1906 are formed above a silicon substrate 1902, each NAND memory string 1906 extending vertically through a memory stack 1904 to contact the silicon substrate 1902. In some embodiments, the fabrication process for forming the NAND memory strings 1906 includes: forming channel vias through the memory stack 1904 (or dielectric stack) and into the silicon substrate 1902 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers such as memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It should be understood that the details of fabricating the NAND memory strings 1906 can vary depending on the type of channel structure of the NAND memory strings 1906 (e.g., Figures 8A-8C The structure varies depending on whether it is a bottom plug channel structure 812A, a side wall plug channel structure 812B, or a bottom open channel structure 812C. Therefore, it is not described in detail for ease of description.

[0266] In some implementations, an interconnect layer is formed over a NAND memory string array on a first substrate. The interconnect layer may include a first plurality of interconnects within one or more ILD layers. Figure 19AAs shown, an interconnect layer 1908 is formed over the memory stack 1904 and the NAND memory string 1906. The interconnect layer 1908 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1906. In some embodiments, the interconnect layer 1908 includes a plurality of ILD layers and interconnects therein formed using a variety of processes. For example, the interconnects in the interconnect layer 1908 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 19A The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1908.

[0267] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 19A As shown, a bonding layer 1910 is formed over the interconnect layer 1308. The bonding layer 1910 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1908 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1908 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0268] Method 2100 proceeds to operation 2104, such as Figure 21 As shown, a first transistor is formed on a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 19BAs shown, a plurality of transistors 1914 and 1916 are formed on a silicon substrate 1912. Transistors 1914 and 1916 can be formed by a variety of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1912 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1914 and 1916. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1912 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1914 differs from the thickness of the gate dielectric of transistor 1916 by depositing a thicker silicon oxide film in the region of transistor 1914 than in the region of transistor 1916, or by etching back portions of the silicon oxide film deposited in the region of transistor 1916. It should be understood that the details of fabricating transistors 1914 and 1916 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0269] In some embodiments, the interconnect layer 1918 is formed over the transistor on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 19B As shown, interconnect layer 1918 may be formed over transistors 1914 and 1916. Interconnect layer 1918 may include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect to transistors 1914 and 1916. In some embodiments, interconnect layer 1918 includes multiple ILD layers and interconnects formed therein using various processes. For example, interconnects in interconnect layer 1918 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 19B The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1918.

[0270] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 19BAs shown, a bonding layer 1920 is formed over an interconnect layer 1918. The bonding layer 1920 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1918 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1918 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0271] Method 2100 proceeds to operation 2106, such as Figure 21 As shown, a second transistor is formed on a third substrate. The third substrate may be a silicon substrate having monocrystalline silicon. In some embodiments, any two or all of operations 2102, 2104, and 2106 are performed in parallel to reduce processing time.

[0272] like Figure 19C As shown, a plurality of transistors 1924 and 1926 are formed on a silicon substrate 1922. Transistors 1924 and 1926 can be formed by a variety of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1922 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1924 and 1926. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1922 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of transistor 1924 differs from the thickness of the gate dielectric of transistor 1926 by depositing a thicker silicon oxide film in the region of transistor 1924 than in the region of transistor 1926, or by etching back portions of the silicon oxide film deposited in the region of transistor 1926. It should be understood that the details of fabricating transistors 1924 and 1926 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, so no detailed description is provided for ease of explanation.

[0273] In some embodiments, the interconnect layer 1928 is formed over the transistor on the third substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 19CAs shown, interconnect layer 1928 may be formed over transistors 1924 and 1926. Interconnect layer 1928 may include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect to transistors 1924 and 1926. In some embodiments, interconnect layer 1928 includes multiple ILD layers and interconnects formed therein using various processes. For example, interconnects in interconnect layer 1928 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 19C The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1928.

[0274] In some embodiments, at least one of the second or third substrates is thinned. For example... Figure 19D As shown, silicon substrate 1912 ( Figure 19B The silicon substrate 1922 (shown) is thinned to become a semiconductor layer with single-crystal silicon 1935. Similarly, the silicon substrate 1922 (shown) Figure 19C The silicon substrate 1912 or 1922 (as shown) is thinned to become a semiconductor layer 1923 having monocrystalline silicon. The silicon substrate 1912 or 1922 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In some embodiments, as... Figure 19D As shown, before thinning, for example, bonding adhesive is used to attach the processing substrate 1901 to the bonding layer 1920 and the processing substrate 1903 to the interconnect layer 1928 to allow subsequent back-side processes on the silicon substrates 1912 and 1922, such as thinning, contact formation and bonding.

[0275] In some embodiments, a first contact is formed through a thinned second substrate. In some embodiments, a second contact is formed through a thinned third substrate, such that the second contact is coupled to the first contact after the thinned third and second substrates are bonded. Figure 19DAs shown, one or more contacts 1936 are formed, each contact 1936 extending vertically through semiconductor layer 1935 (i.e., thinned silicon substrate 1912). Contacts 1936 can be coupled to interconnects in interconnect layer 1918. Similarly, one or more contacts 1937 are formed, each contact 1937 extending vertically through semiconductor layer 1923 (i.e., thinned silicon substrate 1922). Contacts 1937 can be coupled to interconnects in interconnect layer 1928. Contacts 1937 or 1936 can be formed by first patterning contact holes through semiconductor layers 1923 or 1935 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in dielectric layers). Contact holes can be filled with conductors (e.g., W or Cu). In some embodiments, filling contact holes includes depositing spacers (e.g., silicon oxide layers) before depositing conductors. It should be understood that in some examples, contacts 1936 can be formed during the thinning (formation of semiconductor layer 1935, e.g., in...) Figure 19B The contact 1937 is formed in the silicon substrate 1912 before thinning and is exposed from the back side of the silicon substrate 1912 (where thinning occurs) after thinning. Similarly, the contact 1937 can be formed during the thinning (formation of the semiconductor layer 1923, for example, in...) Figure 19C The middle part was previously formed in the silicon substrate 1922 and was exposed from the back side of the silicon substrate 1922 (where the thinning occurred) after thinning.

[0276] In some embodiments, a third bonding layer is formed on a second side of the thinned second substrate opposite to the first side of the transistor formation, and a fourth bonding layer is formed on the second side of the thinned third substrate opposite to the first side of the transistor formation. The third bonding layer may include a plurality of third bonding contacts, and the fourth bonding layer may include a plurality of fourth bonding contacts. Figure 19D As shown, a bonding layer 1939 is formed on the back side of semiconductor layer 1935 (i.e., thinned silicon substrate 1912), and a bonding layer 1941 is formed on the back side of semiconductor layer 1923 (i.e., thinned silicon substrate 1922). Bonding layers 1939 or 1941 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the surface of semiconductor layer 1935 or 1923 by one or more thin-film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact contacts 1936 and 1937 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0277] Method 2100 proceeds to operation 2108, such as Figure 21 As shown, a third substrate and a second substrate are bonded back-to-back. After bonding the third and second substrates, a third bonding contact in the third bonding layer can contact a fourth bonding contact in the fourth bonding layer at a first bonding interface. Bonding may include hybrid bonding.

[0278] like Figure 19D As shown, a thinned silicon substrate 1922 (i.e., semiconductor layer 1923) and components formed thereon (e.g., transistors 1924 and 1926) are flipped over. A bonding layer 1941 on the back side of the upward-facing thinned silicon substrate 1922 is bonded to a bonding layer 1939 on the back side of the downward-facing thinned silicon substrate 1912, i.e., bonded back-to-back, thereby forming a bonding interface 1940. That is, the thinned silicon substrate 1922 and components formed thereon can be bonded back-to-back to the thinned silicon substrate 1912 and components formed thereon, such that the bonding contacts in the bonding layer 1941 contact the bonding contacts in the bonding layer 1939 at the bonding interface 1940. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surface prior to bonding. Although Figure 13D Not shown, but it should be understood that in some examples, the thinned silicon substrate 1912 and the components formed thereon (e.g., transistors 1914 and 1916) can be flipped upside down, and the top-facing bonding layer 1939 can be bonded to the bottom-facing bonding layer 1941, i.e., bonded back-to-back, thereby also forming a bonding interface 1940.

[0279] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1940 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1939 and bonding contacts in bonding layer 1941 are aligned and in contact with each other, such that contact 1936 can be coupled to contact 1937, and transistors 1924 and 1926 can be coupled to transistors 1914 and 1916 via the bonding contacts across bonding interface 1940 and contacts 1936 and 1937. It should be understood that in some examples, anodic bonding or fusion bonding, instead of hybrid bonding, can be performed to bond thinned silicon substrates 1912 and 1922 (and components formed thereon) back-to-back at bonding interface 1940 without the bonding contacts in bonding layers 1939 and / or 1941.

[0280] Method 2100 proceeds to operation 2110, such as Figure 21As shown, a first substrate and a second substrate are bonded face-to-face. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the first bonding interface. Bonding may include hybrid bonding.

[0281] like Figure 19E As shown, the processed substrate 1901 attached to the bonding layer 1920 ( Figure 19D The silicon substrate 1902 (shown) is removed, exposing the bonding layer 1920, and the silicon substrate 1902 and the components formed thereon (e.g., memory stack 1904 and NAND memory string 1906 formed therethrough) are flipped over. The downward-facing bonding layer 1910 is bonded to the upward-facing bonding layer 1920, i.e., face-to-face bonding, thereby forming a bonding interface 1932. That is, the silicon substrate 1902 and the components formed thereon can be bonded face-to-face to the thinned silicon substrate 1912 (i.e., semiconductor layer 1935) and the components formed thereon, such that the bonding contacts in the bonding layer 1910 contact the bonding contacts in the bonding layer 1920 at the bonding interface 1932. Transistors 1914 and 1916 and the NAND memory string 1906 can face each other after bonding. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surface prior to bonding. Although Figure 19E Not shown, but it should be understood that in some examples, the thinned silicon substrate 1912 and the components formed thereon (e.g., transistors 1914 and 1916) can be flipped upside down, and the downward-facing bonding layer 1920 can be bonded to the upward-facing bonding layer 1910, i.e., bonded face-to-face, thereby also forming a bonding interface 1932.

[0282] As a result of, for example, hybrid bonding, the bonding contacts on opposite sides of bonding interface 1932 can be mixed with each other. According to some embodiments, after bonding, the bonding contacts in bonding layer 1910 and bonding contacts in bonding layer 1920 are aligned and in contact with each other, such that the memory stack 1904 and the NAND memory string 1906 formed therethrough can be coupled to transistors 1914 and 1916 via the bonding contacts across bonding interface 1932. It should be understood that in some examples, the bonding layer may be formed over interconnect layer 1928 instead of interconnect layer 1918, and the thinned silicon substrate 1922 (i.e., semiconductor layer 1923) and components formed thereon can be bonded to the silicon substrate 1902 and components formed thereon in a face-to-face manner, such that transistors 1926 and 1924 and the NAND memory string 1906 can face each other after bonding.

[0283] It should be understood that in some examples, operation 2110 can be performed before operation 2108. That is, after forming a NAND memory string array on the first substrate at operation 2102, forming a first transistor on the second substrate at operation 2104, and forming a second transistor on the third substrate at operation 2106 (operations 2102, 2104, and 2106 can be performed in parallel), method 2100 can perform operation 2110 to bond the first and second substrates face-to-face. Then method 2100 can proceed to operation 2108 to bond the third and second substrates back-to-back. Therefore, due to the bonded first substrate (e.g., Figure 19A The silicon substrate 1902 in the middle can be used as a base substrate when performing operation 2108, so the carrier substrate can be skipped (e.g., Figure 19D The attachment of the carrier substrate (1901) in the process simplifies the process.

[0284] Method 2100 proceeds to optional operation 2112, such as Figure 21 As shown, the first substrate is thinned. Figure 19F As shown, silicon substrate 1902 ( Figure 19E The silicon substrate 1902 (shown) is thinned to become a semiconductor layer with monocrystalline silicon. The silicon substrate 1902 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0285] Method 2100 proceeds to operation 2114, such as Figure 21 As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned first substrate. As... Figure 19F As shown, a pad-out interconnect layer 1948 is formed on semiconductor layer 1934 (thinned silicon substrate 1902). The pad-out interconnect layer 1948 may include interconnects formed in one or more ILD layers, such as contact pads 1938. Contact pads 1938 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1944 extending vertically through semiconductor layer 1934 are formed, for example, by wet / dry etching, followed by deposition of dielectric material as spacers and deposition of conductive material as conductors. Contacts 1944 can couple the contact pads 1938 in the pad-out interconnect layer 1948 to interconnects in interconnect layer 1908. In some embodiments, a processing substrate 1903 attached to interconnect layer 1928 (e.g., ...) Figure 19EThe contact 1944 (as shown in the diagram) is removed to expose the interconnect layer 1928, and then a passivation layer 1942 is formed on the interconnect layer 1928 by depositing a dielectric material such as silicon nitride using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. It should be understood that in some examples, the contact 1944 may be thinned (e.g., during the formation of the semiconductor layer 1934, for example, in...) Figure 19A The middle part was previously formed in the silicon substrate 1902 and was exposed from the back side of the silicon substrate 1902 (where the thinning occurred) after thinning.

[0286] In some implementations, after operation 2110, optional operation 2112 is skipped, and method 2100 proceeds to operation 2114, such as... Figure 21 As shown, a pad-out interconnect layer is formed therein. This pad-out interconnect layer can be formed above the second transistor. Although not shown in... Figure 19F As shown, it should be understood that in some examples, after removing the processing substrate 1903, a pad-out interconnect layer with contact pads can be formed over the interconnect layer 1908 and transistors 1926 and 1924. It should further be understood that in some examples, the first substrate (e.g., silicon substrate 1902 or the thinned semiconductor layer 1934) can be configured to... Figure 12G and Figure 12H The similar approach described was removed and replaced with a semiconductor layer with polycrystalline silicon.

[0287] Figure 22A and 22B Showing various aspects according to this disclosure Figure 9A and Figure 9B A schematic diagram of a cross-section of the 3D memory device. 3D memory devices 2200 and 2201 can be... Figure 9A and Figure 9B Examples of 3D memory devices 900 and 901 in the example. Figure 22A As shown, the 3D memory device 2200 may include stacked first, second, and third semiconductor structures 102, 104, and 106. In some embodiments, the first semiconductor structure 102 on one side of the 3D memory device 2200 includes a semiconductor layer 1002 and a memory cell array vertically located between the semiconductor layer 1002 and the bonding interface 103. The memory cell array may include an array of NAND memory strings (e.g., the NAND memory string 208 disclosed herein), and the source of the NAND memory string array may be in contact with the semiconductor layer 1002 (e.g., as shown in the diagram). Figures 8A-8C(As shown). Semiconductor layer 1002 may include semiconductor materials, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate) or polycrystalline silicon (e.g., a deposited layer), depending on the type of channel structure of the NAND memory string (e.g., bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C).

[0288] In some embodiments, the second semiconductor structure 104 in the middle of the 3D memory device 2200 includes a semiconductor layer 1004, a bonding layer 1012, and peripheral circuitry of a memory cell array vertically disposed between the semiconductor layer 1004 and the bonding layer 1012. In some embodiments, the semiconductor layer 1004 is vertically disposed between the bonding interface 103 and the peripheral circuitry of the second semiconductor structure 104. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. The semiconductor layer 1004 may include a semiconductor material, such as monocrystalline silicon (e.g., a layer transferred from a silicon substrate or an SOI substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. The bonding interface 103 between the first and second semiconductor structures 102 and 104 may be created by transfer bonding. Through-the-through contacts (e.g., ILV / TSV) across bonding interface 103 and through semiconductor layer 1004 perpendicularly located between first and second semiconductor structures 102 and 104 can form direct, short-distance (e.g., submicron) electrical connections between adjacent semiconductor structures 102 and 104. Bonding layer 1012 may include dielectrics for conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for, for example, hybrid bonding.

[0289] In some embodiments, a third semiconductor structure 106 on the other side of the 3D memory device 2200 includes a semiconductor layer 1006, a bonding layer 1014, and peripheral circuitry of a memory cell array vertically located between the semiconductor layer 1006 and the bonding layer 105. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1006. The semiconductor layer 1006 may include a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the semiconductor layer 1002 in the first semiconductor structure 102, the semiconductor layer 1006 on which transistors are formed may include monocrystalline silicon but not polycrystalline silicon, because the superior carrier mobility of monocrystalline silicon is desirable for transistor performance. Similar to the bonding layer 1012, the bonding layer 1014 may also include a dielectric for conductive bonding contacts (not shown) and electrically isolating bonding contacts, which may be used for, for example, hybrid bonding. According to some embodiments, the bonding interface 105 is vertically located between bonding layers 1012 and 1014 and contacts bonding layers 1012 and 1014, respectively. That is, bonding layers 1012 and 1014 can be disposed on opposite sides of the bonding interface 105, and the bonding contacts of bonding layer 1012 can contact the bonding contacts of bonding layer 1014 at the bonding interface 105. Therefore, a large number (e.g., millions) of bonding contacts across the bonding interface 105 can form direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0290] It should be understood that, in some examples, the first and second semiconductor structures 102 and 104 may further include bonding layers 1008 and 1010 respectively disposed on opposite sides of the bonding interface 103, such as Figure 22B As shown. In Figure 22B In the 3D memory device 2201, the second semiconductor structure 104 may include two bonding layers 1010 and 1012 on its two sides, and the bonding layer 1010 may be vertically disposed between the semiconductor layer 1004 and the bonding interface 103. The first semiconductor structure 102 of the 3D memory device 2201 may include a bonding layer 1008 vertically disposed between the bonding interface 103 and the semiconductor layer 1002. Each bonding layer 1008 or 1010 may include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. The bonding contacts of the bonding layer 1008 may contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, the bonding contacts across the bonding interface 103, combined with through contacts (e.g., ILV / TSV) through the semiconductor layer 1004, can form a direct, short-distance (e.g., micrometer-scale) electrical connection between adjacent semiconductor structures 102 and 104.

[0291] like Figure 22A and Figure 22B As shown, according to some embodiments, since the third and second semiconductor structures 106 and 104 are bonded face-to-face (e.g., in... Figure 22A and Figure 22B In this configuration, semiconductor layer 1006 is disposed on the bottom side of third semiconductor structure 106, while semiconductor layer 1004 is disposed on the top side of second semiconductor structure 104. Transistors in third semiconductor structure 106 and second semiconductor structure 104 face each other. In some embodiments, semiconductor layer 1004 is vertically disposed between transistors of peripheral circuitry in second semiconductor structure 104 and bonding interface 103, and transistors of peripheral circuitry in third semiconductor structure 106 are vertically disposed between bonding interface 105 and semiconductor layer 1006. Furthermore, according to some embodiments, since the first and second semiconductor structures 102 and 104 are bonded in a face-to-back manner (e.g., in...), Figure 22A and Figure 22B In the first semiconductor structure 102, semiconductor layers 1002 and 1004 are respectively disposed on the top sides of the first and second semiconductor structures 102 and 104. The transistors of the peripheral circuit in the second semiconductor structure 104 and the memory cell array in the first semiconductor structure 102 face the same direction (e.g., Figure 22A and Figure 22B (in the negative y direction). It should be understood that, for ease of explanation, Figure 9A or Figure 9B The pads in the 902 interconnect layer can be brought out from the pads. Figure 22A and Figure 22B The 3D memory devices 2200 and 2201 are omitted from the above description and may be included in the 3D memory devices 2200 and 2201. Figure 9A and Figure 9B In the described 3D memory devices 2200 and 2201.

[0292] As described above, the second and third semiconductor structures 104 and 106 can have peripheral circuitry, which includes transistors with different applied voltages. For example, the second semiconductor structure 104 can be... Figure 4B An example of a semiconductor structure 408 including an LLV circuit 402 (and in some examples, an LV circuit 404), and a third semiconductor structure 106 may be Figure 4BAn example of a semiconductor structure 410 including an HV circuit 406 (and in some examples, an LLV circuit 404), and vice versa. Therefore, in some embodiments, the semiconductor layers 1006 and 1004 in the third and second semiconductor structures 106 and 104 have different thicknesses to accommodate transistors with different applied voltages. In one example, the third semiconductor structure 106 may include an HV circuit 406 and the second semiconductor structure 104 may include an LLV circuit 402, and the thickness of the semiconductor layer 1006 in the third semiconductor structure 106 may be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the third and second semiconductor structures 106 and 104 also have different thicknesses to accommodate different applied voltages. In one example, the third semiconductor structure 106 may include an HV circuit 406 and the second semiconductor structure 104 may include an LLV circuit 402, and the thickness of the gate dielectric of the transistor in the third semiconductor structure 106 may be greater than the thickness of the gate dielectric of the transistor in the second semiconductor structure 104 (e.g., at least 5 times).

[0293] Figures 23A-23C Showing various aspects according to this disclosure Figure 22A and Figure 22B Side views of various examples of 3D memory devices 2200 and 2201. Figure 23A As shown, as Figure 22A and Figure 22B An example of 3D memory devices 2200 and 2201, according to some embodiments, 3D memory device 2300 is included in the vertical direction (e.g., Figure 23A A bonding chip comprising a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked on top of each other in different planes (in the y-direction). According to some embodiments, the first and second semiconductor structures 102 and 104 are bonded at a bonding interface 103 therebetween, and the second and third semiconductor structures 104 and 106 are bonded at a bonding interface 105 therebetween.

[0294] like Figure 23AAs shown, the third semiconductor structure 106 may include a semiconductor layer 1006 having a semiconductor material. In some embodiments, the semiconductor layer 1006 is a silicon substrate having monocrystalline silicon. The third semiconductor structure 106 may also include a device layer 2302 above and in contact with the semiconductor layer 1006. In some embodiments, the device layer 2302 includes a first peripheral circuit 2304 and a second peripheral circuit 1106. The first peripheral circuit 2304 may include an HV circuit 406, such as a driver circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the second peripheral circuit 2306 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuitry (e.g., in a control logic unit 312). In some embodiments, the first peripheral circuit 2304 includes a plurality of transistors 2308 in contact with the semiconductor layer 1006, and the second peripheral circuit 2306 includes a plurality of transistors 2310 in contact with the semiconductor layer 1006. Transistors 2308 and 2310 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described above in detail with respect to transistors 500 and 600, in some embodiments, each transistor 2308 or 2310 includes a gate dielectric, and the thickness of the gate dielectric of transistor 2308 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 2310 (e.g., in LV circuit 404) because the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2310. Trench isolation (e.g., STI) and doped regions (e.g., the wells, sources, and drains of transistors 2308 and 2310) may also be formed on or in the semiconductor layer 1006.

[0295] In some embodiments, the third semiconductor structure 106 further includes an interconnect layer 2312 above the device layer 2302 to transmit electrical signals to and from peripheral circuits 2306 and 2304. For example... Figure 23AAs shown, interconnect layer 2312 may be vertically located between bonding interface 105 and device layer 2302 (including transistors 2308 and 2310 of peripheral circuits 2304 and 2306). Interconnect layer 2312 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 2312 may be coupled to transistors 2308 and 2310 of peripheral circuits 2304 and 2306 in device layer 2302. Interconnect layer 2312 may also include one or more ILD layers in which lateral lines and vias may be formed. That is, interconnect layer 2312 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 2302 are coupled to each other through interconnects in interconnect layer 2312. For example, peripheral circuit 2304 may be coupled to peripheral circuit 2306 through interconnect layer 2312. Interconnects in interconnect layer 2312 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 2312 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof.

[0296] In some embodiments, the interconnects in interconnect layer 2312 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu in interconnect layer 2312 may become feasible because the fabrication of interconnect layer 2312 can be decoupled from the high-temperature processes that form the first and second semiconductor structures 102 and 104.

[0297] like Figure 23A As shown, the third semiconductor structure 106 may further include a bonding layer 1014 at the bonding interface 105 and above and in contact with the interconnect layer 2312. The bonding layer 1014 may include a plurality of bonding contacts 1015 and a dielectric for electrically isolating the bonding contacts 1015. The bonding contacts 1015 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 1015 of the bonding layer 1014 include Cu. The remaining region of the bonding layer 1014 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 1015 in the bonding layer 1014 and the surrounding dielectric can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO2-to-SiO2) bonding.

[0298] like Figure 23A As shown, the second semiconductor structure 104 may further include a bonding layer 1012 at a bonding interface 105, for example, a bonding layer 1012 on the opposite side of the bonding interface 105 relative to the bonding layer 1014 in the third semiconductor structure 106. The bonding layer 1012 may include a plurality of bonding contacts 1013 and a dielectric material for electrically isolating the bonding contacts 1013. The bonding contacts 1013 may include a conductive material, such as Cu. The remaining region of the bonding layer 1012 may be formed of a dielectric material such as silicon oxide. The bonding contacts 1013 in the bonding layer 1012 and the surrounding dielectric material may be used for mixed bonding. In some embodiments, the bonding interface 105 is where the bonding layers 1014 and 1012 meet and bond. In practice, the bonding interface 105 may be a layer of a certain thickness, comprising the top surface of the bonding layer 1014 of the third semiconductor structure 106 and the bottom surface of the bonding layer 1012 of the second semiconductor structure 104.

[0299] like Figure 23A As shown, the second semiconductor structure 104 further includes an interconnect layer 2326 above and in contact with the bonding layer 1012 for transmitting electrical signals. The interconnect layer 2326 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 2326 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 2326 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2326 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0300] In some embodiments, the interconnects in interconnect layer 2326 comprise Cu, which has a relatively low resistivity (better electrical performance) among conductive metallic materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), the interconnects of interconnect layer 2326 with Cu may become feasible because the fabrication of interconnect layer 2326 can occur after the high-temperature processes forming components in the first semiconductor structure 102 (e.g., NAND memory string 208) and components in the device layer 2314 of the second semiconductor structure 104, and is decoupled from the high-temperature processes forming the third semiconductor structure 106.

[0301] like Figure 23AAs shown, the second semiconductor structure 104 may further include a device layer 2314 above and in contact with the interconnect layer 2326. In some embodiments, the device layer 2314 includes a third peripheral circuit 2316 and a fourth peripheral circuit 2318. In some embodiments, the devices in the device layer 2314 are coupled to each other via interconnects in the interconnect layer 2326. For example, the peripheral circuit 2316 can be coupled to the peripheral circuit 2318 via the interconnect layer 2326. The third peripheral circuit 2316 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the fourth peripheral circuit 2318 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic unit 312). In some embodiments, the third peripheral circuit 2316 includes a plurality of transistors 2320, and the fourth peripheral circuit 2318 also includes a plurality of transistors 2322. Transistors 2320 and 2322 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2320 or 2322 includes a gate dielectric, and the thickness of the gate dielectric of transistor 2320 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 2322 (e.g., in LV circuit 404) because the voltage applied to transistor 2320 is lower than the voltage applied to transistor 2322. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 2320 and 2322) may also be formed on or in semiconductor layer 1004.

[0302] Furthermore, the different voltages applied to the different transistors 2320, 2322, 2308, and 2310 in the second and third semiconductor structures 104 and 106 may result in differences in device dimensions between the second and third semiconductor structures 104 and 106. In some embodiments, the thickness of the gate dielectric of transistor 2308 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 2320 (e.g., in LLV circuit 402) because the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2320. In some embodiments, the thickness of the gate dielectric of transistor 2322 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 2310 (e.g., in LV circuit 404) because the voltages applied to transistors 2322 and 2310 are the same. In some embodiments, the thickness of the semiconductor layer 1006 in which transistor 2308 is formed (e.g., in HV circuit 406) is greater than the thickness of the semiconductor layer 1004 in which transistor 2320 is formed (e.g., in LLV circuit 402) because the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2320.

[0303] The first semiconductor structure 102 can be bonded to the top of the second semiconductor structure 104 in a face-to-back manner at the bonding interface 103. For example... Figure 23A As shown, the second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding. In some embodiments, as a result of transfer bonding, a bonding interface 103 is vertically disposed between the interconnect layer 2328 of the first semiconductor structure 102 and the semiconductor layer 1004, which transfers the semiconductor layer 1004 from another substrate and bonds the semiconductor layer 1004 to the first semiconductor structure 102, as described in detail below. In some embodiments, the bonding interface 103 is the place where the interconnect layer 2328 and the semiconductor layer 1004 meet and bond. In practice, the bonding interface 103 may be a layer of a certain thickness, including the bottom surface of the interconnect layer 2328 of the first semiconductor structure 102 and the top surface of the semiconductor layer 1004 of the second semiconductor structure 104. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 103 and the semiconductor layer 1004 and / or between the bonding interface 103 and the interconnect layer 2328 to facilitate transfer bonding from the semiconductor layer 1004 to the interconnect layer 2328. Therefore, it should be understood that in some examples, the bonding interface 103 may include the surface of the dielectric layer.

[0304] like Figure 23AAs shown, the second semiconductor structure 104 may further include one or more contacts 2324 extending vertically through the semiconductor layer 1004. Contacts 2324 may further extend vertically through the bonding interface 103 to contact interconnects in the interconnect layer 2328. In some embodiments, contacts 2324 are coupled to interconnects in the interconnect layer 2326. Contacts 2324 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, contacts 2324 include W. In some embodiments, contacts 2324 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, contacts 2324 may be ILVs with submicron-level (e.g., between 10 nm and 1 μm) depths, or TSVs with micron-level or tens of micron-level (e.g., between 1 μm and 100 μm) depths.

[0305] like Figure 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2328 on the opposite side of the bonding interface 103 relative to the semiconductor layer 1004 for transmitting electrical signals. The interconnect layer 2328 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 2328 may also include local interconnects, such as bit line contacts and word line contacts. Contacts 2324 through the semiconductor layer 1004 can couple the interconnects in the interconnect layer 2328 to the interconnects in the interconnect layer 2326. The interconnect layer 2328 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 2328 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2328 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0306] like Figure 23A As shown, the first semiconductor structure 102 may include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the interconnect layer 2328. In some embodiments, the interconnect layer 2328 is vertically positioned between the NAND memory strings 208 and the bonding interface 103. According to some embodiments, each NAND memory string 208 extends vertically through multiple pairs, each pair including a conductive layer and a dielectric layer. Stacked and interleaved conductive and dielectric layers are also referred to herein as stacked structures, such as memory stack 2327. Memory stack 2327 may be... Figures 8A-8CExamples of memory stacks 804 include the conductive and dielectric layers in memory stack 2327, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack 2327 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating in one or more stepped structures in memory stack 2327.

[0307] In some implementations, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those mentioned above. Figures 8A-8C The bottom plug channel structure 812A, sidewall plug channel structure 812B, or bottom open channel structure 812C are described in detail. It should be understood that the NAND memory string 208 is not limited to the "charge-trapping" type NAND memory string, and in other examples may be the "floating gate" type NAND memory string.

[0308] like Figure 23A As shown, the first semiconductor structure 102 may further include a semiconductor layer 1002 disposed above the memory stack 2327 and in contact with the source of the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the bonding interface 103 and the semiconductor layer 1002. The semiconductor layer 1002 may include a semiconductor material. In some embodiments, the semiconductor layer 1002 is a thinned silicon substrate having monocrystalline silicon on which the memory stack 2327 and the NAND memory string 208 are formed (e.g., including a bottom plug channel structure 812A or a sidewall plug channel structure 812B). It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the semiconductor layer 1002.

[0309] like Figure 23A As shown, the first semiconductor structure 102 may further include a pad-out interconnect layer 902 above and in contact with the semiconductor layer 1002. In some embodiments, the semiconductor layer 1002 is vertically disposed between the pad-out interconnect layer 902 and the NAND memory string 208. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 2332. The pad-out interconnect layer 902 and the interconnect layer 2328 may be formed on opposite sides of the semiconductor layer 1002. In some embodiments, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 2300 and an external device, for example, for pad-out purposes.

[0310] like Figure 11A As shown, the first semiconductor structure 102 may further include one or more contacts 2330 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 2330 couple interconnects in the interconnect layer 2328 to contact pads 2332 in the interconnect layer 902 to form electrical connections through the semiconductor layer 1002. The contacts 2330 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1130 include W. In some embodiments, the contacts 2330 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contacts 2330 may be ILVs with a submicron depth (e.g., between 10 nm and 1 μm) or TSVs with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0311] As a result, the peripheral circuits 2304, 2306, 2316, and 2318 in the third and second semiconductor structures 106 and 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures including interconnect layers 2312, 2326, and 2328, bonding layers 1014 and 1012, and contacts 2324. Furthermore, the peripheral circuits 2304, 2306, 2316, and 2318 in the 3D memory device 2300, as well as the NAND memory string 208, can be further coupled to external devices through contacts 2330 and pads leading out from the interconnect layer 902.

[0312] It should be understood that the material of the semic...

Claims

1. A three-dimensional (3D) memory device, comprising: The first semiconductor structure includes: NAND memory string array; and The first semiconductor layer in contact with the source of the NAND memory string array; The second semiconductor structure includes: The first peripheral circuit of the NAND memory string array, the first peripheral circuit including a first transistor; and The second semiconductor layer in contact with the first transistor; The third semiconductor structure includes: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and The third semiconductor layer in contact with the second transistor; A first bonding interface between the first semiconductor structure and the second semiconductor structure, wherein the first peripheral circuitry of the NAND memory string array is located between the first bonding interface and the second semiconductor layer; and A second bonding interface between the second semiconductor structure and the third semiconductor structure, wherein the second peripheral circuitry of the NAND memory string array is located between the second bonding interface and the third semiconductor layer. The first peripheral circuit and the second peripheral circuit are located on the same side of the NAND memory string array, and the second peripheral circuit is farther away from the NAND memory string array than the first peripheral circuit. The third semiconductor structure further includes a pad-out interconnect layer in contact with the third semiconductor layer, and the pad-out interconnect layer includes contact pads coupled to the second peripheral circuit.

2. The three-dimensional memory device according to claim 1, wherein, The first semiconductor layer comprises monocrystalline silicon.

3. The three-dimensional memory device according to claim 1, wherein, The first semiconductor layer comprises polycrystalline silicon.

4. The three-dimensional memory device according to claim 1, wherein, The thickness of the third semiconductor layer is greater than the thickness of the second semiconductor layer.

5. The three-dimensional memory device according to any one of claims 1-4, wherein The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the second gate dielectric is greater than the thickness of the first gate dielectric.

6. The three-dimensional memory device according to claim 5, wherein, The thicknesses of the first gate dielectric and the second gate dielectric differ by at least a factor of 5.

7. The three-dimensional memory device according to claim 5, wherein The second semiconductor structure further includes a third peripheral circuit of the NAND memory string array, the third peripheral circuit including a third transistor containing a third gate dielectric; The third semiconductor structure further includes a fourth peripheral circuit for the NAND memory string array, the fourth peripheral circuit including a fourth transistor containing a fourth gate dielectric; and The third gate dielectric and the fourth gate dielectric have the same thickness.

8. The three-dimensional memory device according to claim 7, wherein, The thicknesses of the third gate dielectric and the fourth gate dielectric are between the thicknesses of the first gate dielectric and the second gate dielectric.

9. The three-dimensional memory device according to claim 7 or 8, wherein, The third and fourth peripheral circuits include at least one of a page buffer circuit or a logic circuit.

10. The three-dimensional memory device according to any one of claims 1-4 and 6-8, wherein The second semiconductor structure further includes a first interconnect layer between the first bonding interface and the first peripheral circuit, the first interconnect layer including a first interconnect coupled to the first transistor; and The third semiconductor structure further includes a second interconnect layer between the second bonding interface and the second peripheral circuit, the second interconnect layer including a second interconnect coupled to the second transistor.

11. The three-dimensional memory device according to claim 10, wherein, The first interconnect comprises copper, and the second interconnect comprises tungsten.

12. The three-dimensional memory device according to any one of claims 1-4, 6-8, and 11, wherein, The second semiconductor structure also includes contacts that pass through the second semiconductor layer.

13. The three-dimensional memory device according to claim 12, wherein, The contact point extends further through the second bonding interface.

14. The three-dimensional memory device according to any one of claims 1-4, 6-8, 11, and 13, wherein, The first peripheral circuit includes an input / output (I / O) circuit, and the second peripheral circuit includes a driver circuit.

15. The three-dimensional memory device according to any one of claims 1-4, 6-8, 11, and 13, further comprising: A first voltage source is coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; as well as A second voltage source is coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit. Wherein, the second voltage is greater than the first voltage.

16. The three-dimensional memory device according to any one of claims 1-4, 6-8, 11, and 13, wherein The first semiconductor structure further includes a first bonding layer at the first bonding interface and including a first bonding contact; The second semiconductor structure further includes a second bonding layer at the first bonding interface and including second bonding contacts; and The first bonding contact contacts the second bonding contact at the first bonding interface.

17. The three-dimensional memory device according to claim 16, wherein, The first bonding contact and the second bonding contact are made of the same material.

18. The three-dimensional memory device according to any one of claims 1-4, 6-8, 11, 13, and 17, wherein, The NAND memory string array is located between the first bonding interface and the first semiconductor layer.

19. A memory system comprising: A memory device configured to store data and comprising: The first semiconductor structure includes: NAND memory string array; and The first semiconductor layer in contact with the source of the NAND memory string array; The second semiconductor structure includes: The first peripheral circuit of the NAND memory string array, the first peripheral circuit including a first transistor; and The second semiconductor layer in contact with the first transistor; The third semiconductor structure includes: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and The third semiconductor layer in contact with the second transistor; A first bonding interface between the first semiconductor structure and the second semiconductor structure, wherein the first peripheral circuitry of the NAND memory string array is located between the first bonding interface and the second semiconductor layer; and A second bonding interface exists between the second semiconductor structure and the third semiconductor structure, wherein the second peripheral circuitry of the NAND memory string array is located between the second bonding interface and the third semiconductor layer; and A memory controller, coupled to the memory device and configured to control the NAND memory string array via the first peripheral circuitry and the second peripheral circuitry. The first peripheral circuit and the second peripheral circuit are located on the same side of the NAND memory string array, and the second peripheral circuit is farther away from the NAND memory string array than the first peripheral circuit. The third semiconductor structure further includes a pad-out interconnect layer in contact with the third semiconductor layer, and the pad-out interconnect layer includes contact pads coupled to the second peripheral circuit.

20. A method for forming a three-dimensional (3D) memory device, comprising: A NAND memory string array is formed on the first substrate; A first transistor for the NAND memory string array is formed on the second substrate; A second transistor for the NAND memory string array is formed on the third substrate; The first substrate and the second substrate are bonded face-to-face; as well as The third substrate and the second substrate are bonded in a face-to-back manner. The first transistor and the second transistor are located on the same side of the NAND memory string array, and the second transistor is farther away from the NAND memory string array than the first transistor. The third semiconductor structure in which the second transistor is formed further includes a pad-out interconnect layer in contact with the thinned third substrate, and the pad-out interconnect layer includes contact pads coupled to the second transistor.

21. The method of claim 20, wherein After bonding the first substrate and the second substrate, the NAND memory string array is coupled to the first transistor; and After the third substrate and the second substrate are bonded, the second transistor is coupled to the first transistor.

22. The method according to claim 20 or 21, further comprising: After bonding the third substrate and the second substrate, the third substrate is thinned; as well as The pad lead-out interconnect layer is formed on the thinned third substrate.

23. The method according to claim 20 or 21, further comprising: After bonding the third substrate and the second substrate, the first substrate is thinned.

24. The method according to claim 20 or 21, further comprising: After bonding the third substrate and the second substrate, and bonding the first substrate and the second substrate, the first substrate is replaced with a polycrystalline silicon layer.

25. The method according to claim 20 or 21, wherein, Bonding the first substrate and the second substrate includes hybrid bonding.

26. The method according to claim 20 or 21, further comprising: A first bonding layer is formed over the NAND memory string array on the first substrate, the first bonding layer including a first bonding contact; as well as A second bonding layer is formed over the first transistor on the second substrate, the second bonding layer including second bonding contacts. Wherein, after bonding the first substrate and the second substrate, the first bonding contact contacts the second bonding contact at the first bonding interface.

27. The method according to claim 20 or 21, further comprising: Thin the second substrate; as well as Contacts are formed through the thinned second substrate.

28. The method according to claim 20 or 21, further comprising: A third bonding layer is formed over the second transistor on the third substrate, the third bonding layer including a third bonding contact; as well as A fourth bonding layer is formed on the second substrate, the fourth bonding layer including a fourth bonding contact. Wherein, after the third substrate and the second substrate are bonded, the third bonding contact comes into contact with the fourth bonding contact at the second bonding interface.

29. The method according to claim 20 or 21, wherein Forming the first transistor includes forming a first gate dielectric; and Forming the second transistor includes forming a second gate dielectric. in, The thickness of the second gate dielectric is greater than the thickness of the first gate dielectric.

30. A method for forming a three-dimensional (3D) memory device, comprising: A NAND memory string array is formed on the first substrate; A second transistor for the NAND memory string array is formed on the second substrate; A semiconductor layer is formed above the second transistor, wherein the semiconductor layer comprises monocrystalline silicon; A first transistor for the NAND memory string array is formed on the semiconductor layer; and The first substrate and the second substrate are bonded face-to-face. The first transistor and the second transistor are located on the same side of the NAND memory string array, and the second transistor is farther away from the NAND memory string array than the first transistor. The third semiconductor structure in which the second transistor is formed further includes a pad-out interconnect layer in contact with the thinned second substrate, and the pad-out interconnect layer includes contact pads coupled to the second transistor.

31. The method of claim 30, further comprising: After bonding the first substrate and the second substrate, the second substrate is thinned; as well as The pad lead-out interconnect layer is formed on the thinned second substrate.

32. The method of claim 30, further comprising: After bonding the first substrate and the second substrate, the first substrate is thinned.

33. The method of claim 30, further comprising: After bonding the first substrate and the second substrate, the first substrate is replaced with a polycrystalline silicon layer.

34. The method according to any one of claims 30-33, wherein, Bonding the first substrate and the second substrate includes hybrid bonding.

35. The method according to any one of claims 30-33, further comprising: A first bonding layer is formed over the NAND memory string array on the first substrate, the first bonding layer including a first bonding contact; as well as A second bonding layer is formed above the second transistor, the second bonding layer including second bonding contacts. After the first substrate and the second substrate are bonded, the first bonding contact contacts the second bonding contact at the bonding interface.

36. The method according to any one of claims 30-33, further comprising forming contacts through the semiconductor layer prior to bonding the first substrate and the second substrate.

37. The method according to any one of claims 30-33, wherein, Forming the semiconductor layer includes: Bonding the third substrate and the second substrate; and The third substrate is thinned to leave the semiconductor layer.

38. The method according to claim 37, wherein, Bonding the third substrate and the second substrate includes transfer bonding.

39. The method according to any one of claims 30-33 and 38, wherein Forming the first transistor includes forming a first gate dielectric; Forming the second transistor includes forming a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

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