Multi-state signal acquisition circuit and test device

Abstract

The present invention provides a multi-state signal acquisition circuit and test device, comprising: an acquisition circuit module comprising a power supply, a first resistor, a second resistor, a third resistor, a fourth resistor, a voltage regulator, a first transistor, and a second transistor; and an isolation circuit module comprising a power supply, an optocoupler, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor. When the input signal voltage is 0V, the levels acquired by the CPU's IO port C18A-T and the CPU's IO port C18B-T are both high. When the input signal voltage is 24V, the levels acquired by the CPU's IO port C18A-T and the CPU's IO port C18B-T are both low. When the input signal is left unconnected, the levels acquired by the CPU's IO port C18A-T are both low, while the levels acquired by the CPU's IO port C18B-T are both high. These devices enable acquisition of the drive circuit's output signal, solving the problem of detecting the functions of the automatic loader's control components.

Description

Technical Field

[0001] The present invention relates to the field of signal acquisition technology, in particular to a multi-state signal acquisition circuit and a test device, and more particularly to a detection device for an automatic loader control component used in military vehicles. Background Art

[0002] The loader control unit is part of the Type 96A tank firepower expansion system (referred to as the Type 96P automatic loader), developed to accommodate the Type 96, 96A, and Type 99 tanks equipped with new ammunition such as gun-launched missiles. It consists of five components: the QD-1 drive, the CJ-1 acquisition unit, the ZC-1 loading console, the BX181 reloading and unloading box, and the DR-1 display unit. To mass-produce the loader control unit, a test device for the unit was required.

[0003] A Chinese patent application with publication number CN203758355U discloses an automatic ammunition loading device for tanks, belonging to the field of information interconnection between weapons and tank platforms. The device includes a loading device consisting of a controller and an information transmitter, as well as peripheral automatic loading mechanisms, a breech block, and a fire control computer. The controller is mounted on the side of the fire control computer and is directly connected to the computer via a data cable. The information transmitter is fixedly mounted on a bracket directly below the front end of the ejection port, with the information transmitter aligned with the displacement direction of the warhead fuze. The information transmitter is connected to the controller via a wiring harness, which is arranged directly below the ejection port and does not interfere with the operation of the automatic loading mechanism.

[0004] At present, there is an urgent need for a device that can realize all the input signals required by the loader control components, detect the output signals of the loader control components, meet the detection requirements of the loader control components functions, and solve the testing needs of the production and assembly of the loader control components in the final assembly workshop. Summary of the Invention

[0005] In view of the defects in the prior art, the present invention aims to provide a multi-state signal acquisition circuit and a test device.

[0006] According to the present invention, a multi-state signal acquisition circuit includes: an acquisition circuit module: including a power supply, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a voltage regulator D1, a first transistor N1 and a second transistor N2; the positive electrode of the power supply is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, one end of the third resistor R3 and an input signal connector C18, the other end of the first resistor R1 is connected to the base of the first transistor N1, and the emitter of the first transistor N1 is grounded; the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the cathode of the voltage regulator D1, the other end of the fourth resistor R4 is grounded, the anode of the voltage regulator D1 is connected to the base of the second transistor N2, and the emitter of the second transistor N2 is grounded; an isolation circuit module: including a power supply, an optical coupler U1, the third resistor R3, a voltage regulator D1, a first transistor N1 and a second transistor N2; A fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8; the positive electrode of the power supply is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the fifth resistor R5 is connected to the first pin of the optocoupler U1, the other end of the sixth resistor R6 is connected to the third pin of the optocoupler U1, the second pin of the optocoupler U1 is connected to the collector of the first transistor N1, and the fourth pin of the optocoupler U1 is connected to the collector of the second transistor N2; the sixteenth pin of the optocoupler U1 is connected to one end of the seventh resistor R7 and the I0 port C18A-T of the CPU, the other end of the seventh resistor R7 is connected to the power supply VCC, the fourteenth pin of the optocoupler U1 is connected to one end of the eighth resistor R8 and the I0 port C18B-T of the CPU, the other end of the eighth resistor R8 is connected to the power supply VCC, and the thirteenth and fifteenth pins of the optocoupler U1 are both grounded.

[0007] Preferably, the signal input to the acquisition circuit from the input signal connector C18 includes an input signal voltage of 0V, an input signal voltage of 24V, or an input signal being left floating.

[0008] Preferably, the CPU comprises a thirty-two-bit processor MC9S12DP512.

[0009] Preferably, the first transistor N1 and the second transistor N2 are cut off, the sixteenth and fifteenth pins, and the fourteenth and thirteenth pins of the optocoupler U1 are cut off, and the levels collected by the CPU I0 port C18A-T and the CPU I0 port C18B-T are both high levels.

[0010] Preferably, the first transistor N1 and the second transistor N2 are turned on, the sixteenth pin and the fifteenth pin, and the fourteenth pin and the thirteenth pin of the optocoupler U1 are turned on, and the levels collected by the CPU I0 port C18A-T and the CPU I0 port C18B-T are both low levels.

[0011] Preferably, the first transistor N1 is turned on and the second transistor N2 is turned off, the sixteenth pin and the fifteenth pin of the optocoupler U1 are turned on, and the fourteenth pin and the thirteenth pin are turned off, the levels collected by the I0 ports C18A-T of the CPU are all low levels, and the levels collected by the I0 ports C18B-T of the CPU are all high levels.

[0012] Preferably, the voltage of the power supply comprises 24V.

[0013] Preferably, a signal input circuit module is further included, which includes a power supply, a first switch K1 and a second switch K2. The positive pole of the power supply is connected to one end of the first switch K1, the other end of the first switch K1 is connected to the input signal connector C18 and one end of the second switch K2, and the other end of the second switch K2 is grounded.

[0014] According to a testing device provided by the present invention, the acquisition circuit is integrated into a housing of the testing device.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The present invention realizes the collection of the output signal of the drive circuit in the control component of the automatic loader by collecting the following conditions: when the input signal voltage is 0V, the levels collected by the IO port C18A-T of the CPU and the IO port C18B-T of the CPU are both high; when the input signal voltage is 24V, the levels collected by the IO port C18A-T of the CPU and the IO port C18B-T of the CPU are both low; when the input signal is left unconnected, the levels collected by the IO port C18A-T of the CPU are both low, and the levels collected by the IO port C18B-T of the CPU are both high. This solves the problem of detecting the function of the control component of the automatic loader. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0018] Figure 1 This is a schematic diagram of the overall circuit structure of the signal acquisition circuit mainly embodied in the present invention. DETAILED DESCRIPTION

[0019] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0020] like Figure 1 As shown, a multi-state signal acquisition circuit provided according to the present invention includes an acquisition circuit module and an isolation circuit module.

[0021] The acquisition circuit module includes a power supply, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a voltage regulator D1, a first transistor N1, and a second transistor N2. The positive electrode of the power supply is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the first resistor R1, one end of the third resistor R3, and the input signal connector C18. The other end of the first resistor R1 is connected to the base of the first transistor N1, and the emitter of the first transistor N1 is grounded. The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the cathode of the voltage regulator D1. The other end of the fourth resistor R4 is grounded. The anode of the voltage regulator D1 is connected to the base of the second transistor N2, and the emitter of the second transistor N2 is grounded.

[0022] The isolation circuit module includes a power supply, an optocoupler U1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The positive electrode of the power supply is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6. The other end of the fifth resistor R5 is connected to the first pin of the optocoupler U1. The other end of the sixth resistor R6 is connected to the third pin of the optocoupler U1. The second pin of the optocoupler U1 is connected to the collector of the first transistor N1. The fourth pin of the optocoupler U1 is connected to the collector of the second transistor N2. The sixteenth pin of the optocoupler U1 is connected to one end of the seventh resistor R7 and the CPU's I0 port C18A-T. The other end of the seventh resistor R7 is connected to the power supply VCC. The fourteenth pin of the optocoupler U1 is connected to one end of the eighth resistor R8 and the CPU's I0 port C18B-T. The other end of the eighth resistor R8 is connected to the power supply VCC. The thirteenth and fifteenth pins of the optocoupler U1 are both grounded.

[0023] Specifically, the voltage of the power supply is 24V, the CPU includes a 32-bit processor MC9S12DP512, and the model of the optocoupler U1 is PS2805.4.

[0024] The signal input to the acquisition circuit from the input signal connector C18 includes an input signal voltage of 0V, an input signal voltage of 24V, or an input signal being left floating.

[0025] When the input signal voltage of the acquisition circuit input from the input signal connector C18 is 0V, the first transistor N1 and the second transistor N2 are cut off, the light-emitting diode between the first pin and the second pin of the optocoupler U1 is cut off, the sixteenth pin and the fifteenth pin of the optocoupler U1 are cut off, and the voltage of the I0 port C18A-T of the CPU is 5V; the light-emitting diode between the third pin and the fourth pin of the optocoupler U1 is cut off, the fourteenth pin and the thirteenth pin of the optocoupler U1 are cut off, the voltage of the I0 port C18B-T of the CPU is 5V, and the levels collected by the I0 port C18A-T of the CPU and the I0 port C18B-T of the CPU are both high levels.

[0026] When the input signal voltage input to the acquisition circuit from the input signal connector C18 is 24V, the first transistor N1 and the second transistor N2 are turned on, the light-emitting diode between the first pin and the second pin of the optocoupler U1 is turned on, the sixteenth pin and the fifteenth pin of the optocoupler U1 are turned on, and the voltage of the I0 port C18A-T of the CPU becomes 0V; the light-emitting diode between the third pin and the fourth pin of the optocoupler U1 is turned on, and the fourteenth pin and the thirteenth pin of the optocoupler U1 are turned on, the voltage of the I0 port C18B-T of the CPU becomes 0V, and the levels collected by the I0 port C18A-T of the CPU and the I0 port C18B-T of the CPU are both low levels.

[0027] When the input signal from the input signal connector C18 to the acquisition circuit is left floating, the first transistor N1 is turned on, the second transistor N2 is turned off, the light-emitting diode between the first and second pins of the optocoupler U1 is turned on, the sixteenth and fifteenth pins of the optocoupler U1 are turned on, and the voltage of the I0 port C18A-T of the CPU becomes 0V; the light-emitting diode between the third and fourth pins of the optocoupler U1 is turned off, the fourteenth and thirteenth pins of the optocoupler U1 are turned off, the voltage of the I0 port C18B-T of the CPU is 5V, the electrical levels collected by the I0 port C18A-T of the CPU are all low, and the electrical levels collected by the I0 port C18B-T of the CPU are all high.

[0028] It also includes a signal input circuit module, which includes a power supply, a first switch K1 and a second switch K2. The positive pole of the power supply is connected to one end of the first switch K1, the other end of the first switch K1 is connected to the input signal connector C18 and one end of the second switch K2, and the other end of the second switch K2 is grounded.

[0029] When the first switch K1 is closed and the second switch K2 is open, the voltage at the input signal connector C18 reaches 24V. The first resistor R1 and the BE junction of the first transistor N1 form a base, and the base circuit is conductive. The 24V power supply, the fifth resistor R5, the light-emitting diode between the first and second pins of the optocoupler U1, and the CE junction of the first transistor N1 form a collector circuit, and the collector circuit is conductive. Because the light-emitting diode between the first and second pins of the optocoupler U1 is conductive, the output terminals of the optocoupler U1, pins 16 and 15, are conductive, and the voltage at the CPU's I0 port C18A-T drops from 5V to 0V. The cathode voltage of the Zener diode D1 is equal to 24V / (R3=3K+R4=7K)×R7=16.8V, which meets the conduction condition of the Zener diode D1. Similarly, the second transistor N2 is turned on, the light-emitting diode between the third pin and the fourth pin of the optocoupler U1 is turned on, the fourteenth pin and the thirteenth pin output ends of the optocoupler U1 are turned on, and the voltage of the I0 port C18B-T of the CPU changes from 5V to 0V.

[0030] When the first switch K1 is open and the second switch K2 is closed, the voltage at the input signal connector C18 is 0V. The first resistor R1 and the BE junction of the first transistor N1 form a base, and the base circuit is cut off. The 24V power supply, the fifth resistor R5, the light-emitting diode between the first and second pins of the optocoupler U1, and the CE junction of the first transistor N1 form a collector circuit, and the collector circuit is cut off. Because the light-emitting diode between the first and second pins of the optocoupler U1 is cut off, the output terminals of the sixteenth and fifteenth pins of the optocoupler U1 are cut off, and the voltage at the CPU's I0 port C18A-T is 5V. The voltage regulator diode D1 is cut off. Similarly, the second transistor N2 is cut off, the light-emitting diode between the third and fourth pins of the optocoupler U1 is cut off, and the output terminals of the fourteenth and thirteenth pins of the optocoupler U1 are cut off, and the voltage at the CPU's I0 port C18B-T is 5V.

[0031] When the first switch K1 is open and the second switch K2 is open, the voltage at the input signal connector C18 is 24V / (R1=10K+R2=30K)×R1=6V. The input signal is left floating, and the first resistor R1 and the BE junction of the first transistor N1 form the base, making the base circuit conductive. The 24V power supply, the fifth resistor R5, the light-emitting diode between the first and second pins of the optocoupler U1, and the CE junction of the first transistor N1 form the collector circuit, making the collector circuit conductive. Because the light-emitting diode between the first and second pins of the optocoupler U1 is conductive, the output terminals of the optocoupler U1, pins 16 and 15, are conductive, and the voltage at the CPU's I0 port C18A-T drops from 5V to 0V. The voltage regulator diode D1 is turned off. Similarly, the second transistor N2 is turned off, the light-emitting diode between the third and fourth pins of the optocoupler U1 is turned off, and the output terminals of the optocoupler U1, pins 14 and 13, are turned off, making the voltage at the CPU's I0 port C18B-T 5V.

[0032] According to a testing device provided by the present invention, the multi-state signal acquisition circuit mentioned above is adopted, and the acquisition circuit is integrated into the housing of the testing device.

[0033] This application collects signals of three states and generates three corresponding outputs, thereby realizing the collection of output signals of the driving circuit in the automatic loading control component of the product, and solving the detection of the function of the automatic loading machine control component.

[0034] Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, and units provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same functions of the system and its various devices, modules, and units provided by the present invention in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; the devices, modules, and units for implementing various functions can also be considered as both software modules implementing the method and structures within the hardware component.

[0035] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0036] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A multi-state signal acquisition circuit, characterized in that: include: Acquisition circuit module: including power supply, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, voltage regulator D1, first transistor N1 and second transistor N2; The positive electrode of the power supply is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, one end of the third resistor R3, and the input signal connector, the other end of the first resistor R1 is connected to the base of the first transistor N1, and the emitter of the first transistor N1 is grounded; The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the cathode of the voltage regulator D1. The other end of the fourth resistor R4 is grounded. The anode of the voltage regulator D1 is connected to the base of the second transistor N2. The emitter of the second transistor N2 is grounded. Isolation circuit module: includes power supply, optocoupler U1, fifth resistor R5, sixth resistor R6, seventh resistor R7 and eighth resistor R8; The positive electrode of the power supply is connected to one end of a fifth resistor R5 and one end of a sixth resistor R6, the other end of the fifth resistor R5 is connected to a first pin of an optocoupler U1, the other end of the sixth resistor R6 is connected to a third pin of the optocoupler U1, the second pin of the optocoupler U1 is connected to a collector of a first transistor N1, and the fourth pin of the optocoupler U1 is connected to a collector of a second transistor N2; The sixteenth pin of the optocoupler U1 is connected to one end of the seventh resistor R7 and the I0 port AT of the CPU, and the other end of the seventh resistor R7 is connected to the power supply VCC. The fourteenth pin of the optocoupler U1 is connected to one end of the eighth resistor R8 and the I0 port BT of the CPU, and the other end of the eighth resistor R8 is connected to the power supply VCC. The thirteenth and fifteenth pins of the optocoupler U1 are both grounded.

2. The multi-state signal acquisition circuit according to claim 1, wherein: The signal inputted into the acquisition circuit from the input signal connector includes: an input signal voltage of 0V, an input signal voltage of 24V, or an input signal being left floating.

3. The multi-state signal acquisition circuit according to claim 1, wherein: The CPU includes a thirty-two-bit processor MC9S12DP512.

4. The multi-state signal acquisition circuit according to claim 1, wherein: The first transistor N1 and the second transistor N2 are turned off, the sixteenth and fifteenth pins, the fourteenth and thirteenth pins of the optocoupler U1 are turned off, and the levels collected by the CPU I0 port AT and the CPU I0 port BT are both high levels.

5. The multi-state signal acquisition circuit according to claim 1, wherein: The first transistor N1 and the second transistor N2 are turned on, the sixteenth pin and the fifteenth pin, and the fourteenth pin and the thirteenth pin of the optocoupler U1 are turned on, and the levels collected by the CPU I0 port AT and the CPU I0 port BT are both low levels.

6. The multi-state signal acquisition circuit according to claim 1, wherein: The first transistor N1 is turned on and the second transistor N2 is turned off. The sixteenth and fifteenth pins of the optocoupler U1 are turned on and the fourteenth and thirteenth pins are turned off. The levels collected by the I0 port AT of the CPU are all low levels, and the levels collected by the I0 port BT of the CPU are all high levels.

7. The multi-state signal acquisition circuit according to claim 1, wherein: The voltage of the power supply includes 24V.

8. The multi-state signal acquisition circuit according to claim 1, wherein: It also includes a signal input circuit module, which includes a power supply, a first switch K1 and a second switch K2. The positive pole of the power supply is connected to one end of the first switch K1, the other end of the first switch K1 is connected to the input signal connector and one end of the second switch K2, and the other end of the second switch K2 is grounded.

9. A testing device, characterized in that: The multi-state signal acquisition circuit according to any one of claims 1 to 7 is used, and the acquisition circuit is integrated into a housing of a test device.

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