Register stack check device, processor, write operation and read operation method

Abstract

The present invention discloses a register stack verification device, verification structure, processor, write operation, and read operation method. The register stack is provided with a write port, and the write port receives a write index signal and write data. The device includes: a check bit generation circuit set for the write port; the number of the check bit generation circuits is greater than one and less than or equal to the number of write ports; wherein the write port transmits the write data to the check bit generation circuit, and the check bit generation circuit calculates the write data to obtain first check bit data; wherein the first check bit data is used to be spliced ​​with the write data to form write target data that can be written to the write target register corresponding to the write index signal. Thus, a set of check bit generation circuits is set based on each write port of the register stack. Without affecting the normal function of the register stack, all registers can reuse fewer check bit generation circuits, which can effectively save circuit resources.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit design, and in particular to a register stack verification device, a verification structure, a processor, and a write operation and a read operation method. Background Art

[0002] The CPU (Central Processing Unit), the core unit on a chip, is widely used in various fields. As the core storage component of the CPU, the register file is crucial for ensuring the correctness of temporary variables stored in the register file during program execution.

[0003] Program execution failures can occur due to environmental influences on the CPU, such as electromagnetic interference, line crosstalk, and spatial single-particle interference. When such program execution failures occur, the register address and fault details are random and hidden. Therefore, it is necessary to test the registers in the register file.

[0004] In the related art, a separate check circuit is typically provided for each register in a register file. If the register file contains a large number of registers, a check circuit is required to test each corresponding register. However, the circuit resources occupied by the check circuit corresponding to the number of registers needs to be reduced. Summary of the Invention

[0005] The present invention aims to at least partially address one of the technical problems in the related art. To this end, a first object of the present invention is to provide a register file check device that, without affecting the normal function of the register file, can reuse fewer check bit generation circuits and check bit checking circuits across all registers, thereby conserving circuit resources and reducing the adverse impact of hardware circuits on CPU area.

[0006] A second objective of the present invention is to provide a register file checking device.

[0007] A third objective of the present invention is to provide a register file checking device.

[0008] A fourth object of the present invention is to provide a processor.

[0009] A fifth object of the present invention is to provide a register file write operation method.

[0010] A sixth object of the present invention is to provide a register file read operation method.

[0011] To achieve the above-mentioned purpose, the first aspect of the present invention proposes a register stack verification device, wherein the register stack is provided with a write port, and the write port receives a write index signal and write data; the register stack verification device includes: a check bit generation circuit set for the write port; the number of the check bit generation circuits is greater than one and less than or equal to the number of the write ports; wherein the write port transmits the write data to the check bit generation circuit, and the check bit generation circuit calculates the write data to obtain first check bit data; wherein the first check bit data is used to be spliced ​​with the write data to constitute write target data that can be written to the write target register corresponding to the write index signal.

[0012] According to one embodiment of the present invention, the register file check device further includes a write decoding circuit, which is used to decode the write index signal to generate a write hit signal; wherein the write hit signal is used to indicate the write target register in the register file.

[0013] According to one embodiment of the present invention, the write port also receives a write enable signal; the write enable signal corresponds to a target write port; when the write enable signal is valid, the write target data corresponding to the target write port is written into the write target register.

[0014] According to an embodiment of the present invention, when the number of the write ports is 2, the number of the check bit generation circuits is 1 or 2.

[0015] According to one embodiment of the present invention, when the number of the write ports is 2 and the number of the check bit generation circuits is 2, the check bit generation circuit can be multiplexed for check bit checking of read operations and check bit generation of write operations of the register file.

[0016] To achieve the above-mentioned purpose, the second embodiment of the present invention proposes a register stack verification device, wherein the register stack is provided with a read port, and the read port receives a read index signal; the device includes: a check bit check circuit set for the read port; the number of the check bit check circuits is equal to the number of the read ports; wherein the read target register corresponding to the read index signal stores target read data and first check bit data; the check bit check circuit calculates the target read data to obtain second check bit data, so as to determine whether to output the target read data from the register stack through the read port according to the comparison result of the first check bit data and the second check bit data.

[0017] According to one embodiment of the present invention, the apparatus further comprises a read decoding circuit, which is used to decode the read index signal to generate a read selection signal; wherein the read selection signal is used to specify the read target register in the register file.

[0018] According to one embodiment of the present invention, the read port also receives a read enable signal; the read enable signal corresponds to a target read port; when the read enable signal is valid and the first check bit data is consistent with the second check bit data, the target read data is output from the register stack from the target read port.

[0019] According to one embodiment of the present invention, the number of the read ports is 2.

[0020] To achieve the above objectives, a third embodiment of the present invention proposes a register stack check device, the structure of which includes the register stack check device described in any one of the first embodiment and the register stack check device described in any one of the second embodiment.

[0021] To achieve the above-mentioned object, a fourth embodiment of the present invention provides a processor, which includes the register stack checking device described in any one of the above-mentioned embodiments.

[0022] To achieve the above-mentioned purpose, the fifth embodiment of the present invention proposes a write operation method for a register stack, wherein the register stack is provided with a write port, and a check bit generation circuit is provided for the write port; the number of the check bit generation circuits is greater than one and less than or equal to the number of the write ports; the write operation method for the register stack includes: the write port receives a write index signal and write data; wherein the write index signal corresponds to a write target register; the write port transmits the write data to the check bit generation circuit; the write data is calculated using the check bit generation circuit to obtain first check bit data; the first check bit data and the write data are spliced ​​to generate write target data that can be written to the write target register.

[0023] According to one embodiment of the present invention, the register file write operation method further includes: using a write decoding circuit to decode the write index signal to generate a write hit signal; wherein the write hit signal is used to specify the write target register in the register file.

[0024] According to one embodiment of the present invention, the write operation method of the register stack also includes: receiving a write enable signal; wherein the write enable signal corresponds to a target write port; when the write enable signal is valid, writing the write target data corresponding to the target write port into the write target register.

[0025] To achieve the above-mentioned purpose, the sixth embodiment of the present invention proposes a read operation method of a register stack, wherein the register stack is provided with a read port, and a check bit check circuit is provided for the read port; the number of the check bit check circuits is equal to the number of the read ports; the read operation method of the register stack includes: the read port receives a read index signal; wherein the read target register corresponding to the read index signal stores target read data and first check bit data; the target read data and the first check bit data are obtained from the target register according to the read index signal; the target read data and the first check bit data are calculated using the check bit check circuit to obtain second check bit data; and whether to output the target read data from the register stack via the read port is determined according to the comparison result of the first check bit data and the second check bit data.

[0026] According to one embodiment of the present invention, the register file read operation method further includes: using a read decoding circuit to decode the read index signal to generate a read selection signal; wherein the read selection signal is used to specify the read target register in the register file.

[0027] According to one embodiment of the present invention, the read operation method of the register stack also includes: the read port also receives a read enable signal; wherein, the read enable signal corresponds to a target read port; when the read enable signal is valid and the first check bit data is consistent with the second check bit data, the target read data is output from the register stack from the target read port.

[0028] According to multiple embodiments provided by the present invention, a parity bit generation circuit is provided for each write port of the register file, and a parity bit checking circuit is provided for each read port of the register file. This allows all registers to reuse fewer parity bit generation and checking circuits without affecting the normal function of the register file, thereby saving circuit resources and reducing the adverse impact of hardware circuits on CPU area. Furthermore, parity bit checking only needs to be performed on the read register value, rather than on each register value separately, effectively improving verification efficiency.

[0029] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a A structural block diagram of a register file checking device provided according to one embodiment of this specification;

[0031] Figure 1bA schematic diagram of an application scenario of a register file checking device provided according to one embodiment of this specification;

[0032] Figure 2 A structural block diagram of a register file checking device provided according to one embodiment of this specification;

[0033] Figure 3a A structural block diagram of a register file checking device provided according to one embodiment of this specification;

[0034] Figure 3b A schematic diagram of an application scenario of a register file checking device provided according to one embodiment of this specification;

[0035] Figure 4 A structural block diagram of a register file checking device provided according to one embodiment of this specification;

[0036] Figure 5 A schematic diagram of an application scenario of a register file checking device provided according to one embodiment of this specification;

[0037] Figure 6a A structural block diagram of a processor provided according to one embodiment of this specification;

[0038] Figure 6b A structural block diagram of a processor provided according to one embodiment of this specification;

[0039] Figure 6c A structural block diagram of a processor provided according to one embodiment of this specification;

[0040] Figure 7 A flowchart of a register file write operation method provided according to one embodiment of this specification;

[0041] Figure 8 A flowchart of a register file write operation method provided according to one embodiment of this specification;

[0042] Figure 9 A flowchart of a register file read operation method provided according to one embodiment of this specification;

[0043] Figure 10 The figure is a flowchart of a register file read operation method provided according to one embodiment of the present specification. DETAILED DESCRIPTION

[0044] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0045] The CPU (Central Processing Unit) is the core unit on the chip and is widely used in various fields. Taking the power sector as an example, due to the particularity of the environment in which the power system is located, the CPU is extremely susceptible to factors such as electromagnetic interference, line crosstalk, and spatial single particles, resulting in program operation failures. Among them, program operation failures caused by abnormal rewriting of memory units are particularly serious. The register stack is the core storage component in the CPU and stores all temporary variables during the program execution. Once the content in the register stack is disturbed and changed, the program execution results will be seriously wrong. Therefore, in order to ensure the correctness of temporary variables during program execution, it is necessary to detect the correctness of the register contents in the register stack.

[0046] Due to the uncertainty of the external environment, the register address errors and register content errors corresponding to the above-mentioned program operation failures are random and hidden, and the effects produced by conventional software testing methods need to be improved. In the related art, a common response method is to execute the same program segment in the system multiple times and compare whether the results of the multiple executions are consistent to determine whether a failure has occurred during the program execution process. It can be seen that this method is to determine whether a failure has occurred during the program execution process by comparing the running results of the program segments that have been executed multiple times. However, in this method, on the one hand, the range of the program segment to be detected is fixed, and on the other hand, the same program segment detected in this method needs to be executed multiple times, which will reduce the operating efficiency of the system.

[0047] Related technologies also employ hardware verification of register files to determine whether register contents within the register file have been unexpectedly altered. Specifically, hardware verification of register files typically involves individually setting a check bit, a check bit generation circuit, and a check bit checking circuit for each register within the register file. Analysis has revealed that due to the large number of registers in a register file, which can reach 32 or more, the verification circuitry required consumes significant CPU hardware circuitry, hindering CPU area reduction.

[0048] In order to optimize the area of ​​the register stack check circuit without affecting the normal reading and writing of the register stack, it is necessary to propose a register stack check device, processor, write operation and read operation method. Specifically, a set of check bit generation circuits is set based on each write port of the register stack, and a set of check bit checking circuits is set based on each read port of the register stack. Without affecting the normal function of the register stack, the registers in the register stack can reuse as few check bit generation circuits and check bit checking circuits as possible, which can save circuit resources and reduce the adverse effects of hardware circuits on the CPU area. At the same time, the check bit check is performed on the register value read out, without the need to perform a check bit check on the register value of each register separately, which can improve the detection efficiency.

[0049] The embodiment of this specification provides a register file verification device, wherein the register file is provided with a write port, and the write port receives a write index signal and write data. Figure 1a As shown, the register file check device 100 may include: a check bit generation circuit 110 set for the write port. The number of the check bit generation circuit 110 is greater than one and less than or equal to the number of the write ports.

[0050] The write port transmits write data to the parity bit generation circuit, which calculates the write data to obtain first parity bit data. The first parity bit data is used to be concatenated with the write data to form write target data that can be written to the write target register corresponding to the write index signal.

[0051] The write index signal may be used to address registers in the register file to select a write target register from the register file. The write data may be data obtained by executing an instruction and needing to be written to a register in the register file. In some embodiments, the write index may be a write register index in the instruction code.

[0052] In some cases, the register file is a storage component in the CPU that stores instruction operands. It is usually composed of several registers and read-write logic, where registers are usually named with numbers or index values. During the CPU execution of a program, almost every instruction will use one or several registers in the register file, and the instruction selects the register to be accessed through the register index in the instruction code. Usually, the CPU instruction set has clear provisions on the number of registers accessed by each instruction. For example, in a CPU with a RISC (Reduced Instruction Set Computing) architecture, the number of registers in the register file accessed by each instruction is limited. Normally, each instruction will read the values ​​in one or two registers, and the execution result of each instruction will be written back to one or two registers. Therefore, for a single-issue CPU microarchitecture (which can be simply understood as executing one instruction per clock cycle), the number of read operations that the register file needs to respond to within one clock cycle is usually no more than 2, and the number of write operations that need to be responded to is usually 1 or 2; for a multi-issue CPU microarchitecture (which can be simply understood as executing multiple instructions per clock cycle), the number of read operations and / or write operations that need to be responded to simultaneously within one clock cycle will be doubled accordingly, but are usually significantly less than the number of registers in the register file. Moreover, a general register file will have a fixed number of read ports and write ports to match the maximum number of read and write operations during instruction execution. Therefore, in order to reduce the hardware circuit resources occupied by the verification circuit, a check bit generation circuit can be set according to the number of write ports of the register file. The check bit generation circuit is used to calculate the check bit based on the data currently being written, as the new check value for the write target register currently being written. Other registers that have not been written do not need to calculate new check values. It can be seen that in this embodiment, by setting the check bit generation circuit for the write port of the register file instead of setting the check bit generation circuit for each register in the register file, circuit resources can be saved.

[0053] For example, refer to Figure 1bAs shown, the register file has two write ports, write port wp1 and write port wp2. The register file can perform two write operations in the same clock cycle. The register file includes 32 registers, named R0, R1, ..., R31. When two write operations need to be performed simultaneously, the control circuit within the CPU transmits a write index signal WK1 and write data WD1 to write port wp1. This signal locates the corresponding write target register wdr1 in the register file based on the write index signal WK1 and writes the write data WD1 to the write target register wdr1. The control circuit then transmits a write index signal WK2 and write data WD2 to write port wp2. This signal locates the corresponding write target register wdr2 based on the write index signal WK2 and writes the write data WD2 to the write target register wdr2 to complete the write operation. Write port wp1 is provided with an independent check bit generation circuit 1, and write port wp2 is provided with an independent check bit generation circuit 2. Write ports wp1 and wp2 are also provided with write decoding circuits, which are used to address registers in the register file based on write index signals WK1 and WK2, and find the corresponding write target registers wdr1 and wdr2. Furthermore, check bit generation circuit 1 may include a check bit calculation module 1 and a merging module 1, and check bit generation circuit 2 may include a check bit calculation module 2 and a merging module 2. Specifically, write port wp1 transmits the write index signal WK1 to the write decoding circuit for decoding, which is used to address registers in the register file, find the corresponding write target register wdr1, and generate a write hit signal for the write target register wdr1. Write port wp1 passes write data WD1 to check bit generation circuit 1. Check bit calculation module 1 in check bit generation circuit 1 calculates and generates check bit data WC1 corresponding to write data WD1 according to a check algorithm. Merging module 1 splices the write data WD1 and the calculated check bit data WC1 together to form the entire data content to be written to the corresponding write target register wdr1 as the write target data. This write target data is then written into the write target register wdr1 to complete the write operation of write port wp1. In some embodiments, write data typically has a fixed number of bits. This can be accomplished by expanding the write data and placing the corresponding generated check bit data into the expanded number of bits of the write data to splice the write data and check bit data together to form the write target data to be written to the write target register. The process by which write port wp2 completes the corresponding write operation is consistent with the above process and will not be repeated here.

[0054] It should be noted that the check bit data may be calculated according to a parity check algorithm or a cyclic redundancy check algorithm, and the present specification does not impose any specific limitation on the check algorithm used to calculate the check bit data.

[0055] In some embodiments, each register in the register stack corresponds to an update enable signal that allows updating. When the update enable signal of the register is valid, it indicates that the register can receive written data to update the corresponding register content. After the write port receives the write index signal transmitted by the control circuit in the CPU, the write index signal can be decoded by the register write decoding circuit to generate a write hit signal corresponding to the write target register, so that the update enable signal corresponding to the write target register is valid, so that the write target data composed of the write data and the calculated check bit data can be written into the write target register. Exemplarily, the write index signal is R3, indicating that the current write operation needs to select register R3 as the write target register. After decoding the write index signal by the register write decoding circuit, a write hit signal of register R3 can be generated, so that the update enable signal corresponding to register R3 is valid, so that register R3 can receive the written data to update its own content.

[0056] Furthermore, when a write port performs a write operation, a write enable signal is also included. In some embodiments, taking write port wp1 and write port wp2 as examples, the write hit signal for write target register wdr1 generated based on write index signal WK1 and the write hit signal for write target register wdr2 generated based on write index signal WK2 within the same clock cycle may be consistent, indicating that the current write operations of write port wp1 and write port wp2 require writing data to the same write target register. It is understandable that, according to the general knowledge of CPU microarchitecture, write port wp1 and write port wp2 will not write to the same register at the same time. Therefore, it is necessary to select the data source for writing to the register between write port wp1 and write port wp2 to avoid write operation errors. For example, an OR operation can be performed on the write hit signals corresponding to the write target register of write port wp1 and write port wp2 to generate a write enable signal for the write target register. The write hit signal of write port wp1 can be used to select the data source between the write target data to be written to the write target register of write port wp1 and write port wp2. The write enable signal is used to indicate permission to write data to the register.

[0057] In the above embodiment, by providing a parity bit generation circuit for each write port of the register file, a parity bit can be calculated based on the current write data to serve as a new parity bit for the write target register hit by the current write port. New parity bits do not need to be calculated for other registers that are not hit. Consequently, there is no need to provide a parity bit generation circuit for each register in the register file, significantly reducing the number of parity bit generation circuits in the register file. In some embodiments, the register file typically has two write ports, so only two parity bit generation circuits need to be provided for the two write ports.

[0058] In some embodiments, reference Figure 2 As shown, the register file checking device 100 may further include a write decoding circuit 210, which is used to decode the write index signal to generate a write hit signal. The write hit signal is used to indicate the write target register in the register file.

[0059] For example, continue to refer to Figure 1b As shown, write port wp1 transmits write index signal WK1 to the write decoding circuit for decoding to generate a write hit signal corresponding to write target register wdr1. Since write index signal WK1 can point to any one of the 32 registers R0, R1, ..., R31 and is used to select a write target register from the register file for the current write operation, the write hit signal wp1_hit generated after decoding write index signal WK1 can include write hit signals corresponding to any one of the 32 registers R0, R1, ..., R31, namely, any one of wp1_hit0, wp1_hit1, wp1_hit2, ..., wp1_hit31. Specifically, write hit signal wp1_hit0 can indicate register R0 as the write target register for the current write operation of write port wp1 and enable the update enable signal of register R0, so that write data WD1 and its corresponding check bit data WC1 can be written into register R0. The functions of the write hit signals wp1_hit1, wp1_hit2, ..., wp1_hit31 are the same as those of the write hit signal wp1_hit0, and are not described in detail. In some embodiments, the write decoding circuit may be a register write decoding circuit for address decoding.

[0060] In some embodiments, the write port further receives a write enable signal. The write enable signal corresponds to a target write port. When the write enable signal is valid, the write target data corresponding to the target write port is written into the write target register.

[0061] The write enable signal is used to indicate permission to write to a register. The target write port is used to indicate the write port to which data needs to be written to the write target register. Specifically, when a write operation needs to be performed during instruction execution, the control circuit within the CPU can transmit a write enable signal, a write index signal, and write data to the write port of the register file, so that after the write port determines the corresponding write target register based on the write index signal, the write target data corresponding to the write port can be written to the write target register.

[0062] In some embodiments, when multiple write operations need to be performed within the same clock cycle, the write hit signals of the write target register generated by multiple write ports according to the corresponding write index signals may be the same, that is, the write operations of multiple write ports currently need to write data to the same write target register. It is understandable that, according to the general knowledge of the CPU microarchitecture, multiple write ports will not write data to the same register at the same time. Therefore, it is necessary to select the data source for writing to the same write target register among multiple write ports to avoid conflicts and write operation errors. For example, continue to refer to Figure 1b As shown, the write hit signal of write port wp1 is wp1_hit1, the write hit signal of write port wp2 is wp2_hit1, and register R1 is simultaneously the write target register of current write port wp1 and the write target register of write port wp2. The write hit signal wp1_hit1 and the write hit signal wp2_hit1 are "OR" operated to generate a write enable signal for register R1. The write hit signal wp1_hit1 of write port wp1 selects the data source between the write target data of write port wp1 and write port wp2 that need to be written to register R1, respectively, and determines that write port wp1 or write port wp2 is the target write port. When the corresponding write enable signal for register R1 is valid, the write target data corresponding to write port wp1 or write port wp2 is written into register R1.

[0063] In the above embodiment, the data source is selected after calculating the check value of the write data, so as to avoid write operation errors caused by conflicts when writing data to the same register at the same time.

[0064] In some implementations, when the number of write ports is 2, the number of parity bit generation circuits is 1 or 2.

[0065] In some cases, during instruction execution, one or two write operations can be performed in one clock cycle. Therefore, the register file is usually configured with two write ports. Two sets of parity bit generation circuits can be configured for these two write ports.

[0066] In some embodiments, typically only one of the two write ports described above needs to continuously receive a write enable signal, a write index signal, and write data transmitted by the control circuit within the CPU in order to perform a write operation on a register in the register file. The other write port may be in a continuously idle state. Therefore, the check bit generation circuit corresponding to the write port in the continuously idle state can be reused. In this case, the number of check bit checking circuits of the read port can be one. The check bit generation circuit corresponding to the idle write port is used as the check bit checking circuit of the read port. For example, when the check bit generation and check bit checking have the same check bit calculation logic, the check bit generation circuit can be reused as the check bit checking circuit of the read port of the register file. The reused check bit generation circuit can calculate the corresponding check bit based on the data retrieved from the register to check whether the data in the register has been corrupted or tampered with. When the write port receives signals and data transmitted by the control circuit within the CPU, the reused check bit generation circuit can resume operation as the check bit generation circuit corresponding to the write port after completing its current task.

[0067] In other embodiments, for the two write ports of the register file, it is not necessary to set up a dedicated parity bit generation circuit for the write port that may be in a continuously idle state. When a write operation is required on that port, the parity bit checking circuit of the read port of the register file can be reused to generate the parity bit for the write operation on that port.

[0068] In some other embodiments, when the number of write ports is 2, the number of check bit generation circuits is 1. At this time, the check bit check circuit of the read port can be reused as needed. Specifically, when the check bit generation and the check bit calculation logic of the check bit check are the same, the check bit check circuit can be reused as the check bit generation circuit of the write port of the register stack. The multiplexed check bit check circuit can calculate the write data transmitted by the write port to obtain the first check bit data, and splice the first check bit data with the write data to form the write target data. When the read port receives the signal and data transmitted by the control circuit in the CPU, the multiplexed check bit check circuit completes the current task and then resumes work as the check bit check circuit corresponding to the read port.

[0069] In some embodiments, when the number of write ports is 2 and the number of check bit generation circuits is 2, the check bit generation circuit can be multiplexed for check bit checking for read operations and check bit generation for write operations of the register file.

[0070] In some embodiments, the registers in the register file store write data written by a write operation and its corresponding check bit, and the read operation of the register file can retrieve the write data and the corresponding check bit from a specified register in the register file. The check bit check of the read operation can determine whether the write data stored in the register is corrupted by recalculating the check bit of the write data retrieved from the register and comparing the calculated check bit with the retrieved check bit. It is understandable that during the check bit check process of the read operation, the check algorithm can be the same as the check algorithm of the check bit generation circuit corresponding to the write port. Therefore, the check bit generation circuit corresponding to the write port can be multiplexed so that the check bit generation circuit can be used for both the check bit check of the register file read operation and the check bit generation of the write operation. It is understandable that the circuit that performs the multiplexing can also be the check bit check circuit corresponding to the read port.

[0071] Exemplarily, a register file has two write ports and two read ports, and when one of the two write ports needs to continuously receive a write enable signal, a write index signal, and write data transmitted by a control circuit within the CPU to perform a write operation on a register in the register file, and the other write port does not need to continuously receive signals and data transmitted by a control circuit within the CPU to perform a write operation, a check bit generation circuit can be set for the two write ports, and a check bit check circuit can be set for each of the two read ports, that is, there are two check bit check circuits. Among them, one of the two check bit check circuits can be shared by one of the write ports and one of the read ports. In other words, one check bit generation circuit can be set for each of the two write ports, that is, there are two check bit generation circuits, and one check bit check circuit can be set for the two read ports. Among them, one of the two check bit generation circuits can be shared by one of the write ports and one of the read ports.

[0072] In the above implementation, by multiplexing the parity bit generation circuit corresponding to the write port or the parity bit checking circuit corresponding to the read port of the register file, circuit resources can be further saved and the utilization efficiency of the parity bit generation circuit or the parity bit checking circuit can be improved.

[0073] The embodiment of this specification provides a register file check device, wherein the register file is provided with a read port, and the read port receives a read index signal. Figure 3a As shown, the register file checking device 300 may include: a parity bit checking circuit 310 provided for the read port. The number of the parity bit checking circuits 310 is equal to the number of the read ports.

[0074] The read target register corresponding to the read index signal stores target read data and first check bit data. The check bit check circuit calculates the target read data to obtain second check bit data, and determines whether to output the target read data from the register file via the read port based on a comparison result between the first check bit data and the second check bit data.

[0075] The read index signal may be used to address registers in the register file to select a read target register from the register file. The target read data may be write data written to a register in the register file via a write operation. In some embodiments, the read index may be a read register index in the instruction code.

[0076] In some cases, a register file typically has a fixed number of read ports to match the maximum number of read operations during instruction execution. Therefore, a parity check circuit can be configured based on the number of read ports. This circuit recalculates the parity bit of the target read data currently being read from the target register to perform a data correctness check. This completes the verification of the target register currently being read, while other unread registers do not need to be verified temporarily. This saves circuit resources, rather than configuring a parity check circuit for each register.

[0077] For example, refer to Figure 3bAs shown, the register file has two read ports, rp1 and rp2. The register file can perform two read operations in the same clock cycle. The register file includes 32 registers, designated R0, R1, ..., R31. When two read operations need to be performed simultaneously, the control circuit within the CPU transmits a read index signal RK1 to read port rp1, which locates the corresponding read target register rdr1 in the register file and reads the data based on read index signal RK1. It also transmits a read index signal RK2 to read port rp2, which locates the corresponding read target register rdr2 based on read index signal RK2 and reads the data based on read index signal RK2. Read port rp1 is equipped with an independent parity check circuit 1, and read port rp2 is equipped with an independent parity check circuit 2. Read ports rp1 and rp2 are also equipped with read decoding circuits, which address registers in the register file based on read index signals RK1 and RK2, and locate the corresponding read target registers rdr1 and rdr2. Specifically, read port rp1 transmits read index signal RK1 to the read decoding circuit for decoding. This is used to address registers in the register file, locate the corresponding read target register rdr1, and select the target read data RD1 and its corresponding check bit data RC1 for reading. The target read data RD1 is then transmitted to the corresponding check bit check circuit 1, which recalculates the check bit data RC1' for the data and compares the calculated check bit data RC1' with the read check bit data RC1. If they match, the data in the read target register rdr1 has not been corrupted, and the target read data RD1 can be output from the register file via read port rp1, completing the read operation. If they do not match, the data in the read target register rdr1 has been corrupted, and subsequent fault alarms and processing can be performed. The process by which read port rp2 reads the target read data RD2 and its corresponding check bit data RC2 and performs a check bit check is consistent with the above process and will not be further described.

[0078] In some embodiments, the check bit checking circuit may include a check bit recalculation module and a comparator module. The check bit recalculation module is used to recalculate the check bit data corresponding to the target read data according to the check algorithm, and the comparator module is used to compare the check bit data read out of the read port with the corresponding calculated check bit data to obtain a corresponding comparison result. For example, continue to refer to Figure 3bAs shown, parity check circuit 1 includes a parity recalculation module 1 and a comparator module 1, and parity check circuit 2 includes a parity recalculation module 2 and a comparator module 2. For read port rp1, comparator module 1 can compare parity data RC1' calculated by parity recalculation module 1 with the read parity data RC1 to obtain comparison result 1. For read port rp2, comparator module 2 can compare parity data RC2' calculated by parity recalculation module 2 with the read parity data RC2 to obtain comparison result 2.

[0079] Furthermore, the final verification result of the read operation can be obtained based on the comparison result of the comparator module and output from the register file. Figure 3b As shown, an OR gate is provided between the comparator module 1 and the comparator module 2, which can perform an OR operation on the comparison result result1 of the comparator module 1 and the comparison result result2 of the comparator module 2 to obtain the final verification result of the read operation of the current read port rp1 and the read port rp2 and can be output from the register stack.

[0080] In the above embodiment, by providing a parity bit checking circuit for each read port of the register file, a parity bit check can be performed on the register value being read, thereby verifying the register currently being read. Other registers not being read do not need to be checked temporarily. This significantly reduces the number of parity bit checking circuits in the register file and effectively improves verification efficiency. In some embodiments, for most register files with two read ports, only two sets of parity bit checking circuits may be required.

[0081] In some embodiments, reference Figure 4 As shown, the register file check apparatus 300 may further include a read decoding circuit 410, which is used to decode the read index signal to generate a read selection signal, wherein the read selection signal is used to specify a read target register in the register file.

[0082] For example, continue to refer to Figure 3bAs shown, read port rp1 transmits a read index signal RK1 to a read decoding circuit for decoding to generate a read select signal corresponding to the read target register rdr1. Since read index signal RK1 can point to any one of the 32 registers R0, R1, ..., R31 and is used to select a read target register from the register file for the current read port's read operation, the read select signal rp1_sel generated after decoding read index signal RK1 can include a read select signal corresponding to any one of the 32 registers R0, R1, ..., R31, namely, any one of rp1_sel0, rp1_sel1, rp1_sel2, ..., rp1_sel31. Specifically, read select signal rp1_sel0 can indicate register R0 as the read target register for the current read operation of read port rp1, enabling read port rp1 to select and read target read data RD1 and its corresponding check bit data RC1 from register R0. The functions of the read selection signals rp1_sel1, rp1_sel2, ..., rp1_sel31 are the same as those of the read selection signal rp1_sel0, and are not described in detail. In some embodiments, the read decoding circuit may be a register read decoding circuit for address decoding.

[0083] In the above implementation, first, a multi-way selection is made on the registers in the register stack through the read selection index to determine the read target register, and then the target read data and its corresponding check bit data in the read target register are selected for reading, and then the check bit of the currently read target read data is recalculated and checked to complete the verification of the read target register currently being read. There is no need to verify each register, which can significantly reduce the number of check bit check circuits in the register stack and reduce unnecessary check checks in the read operation of the current read port.

[0084] In some embodiments, the read port further receives a read enable signal corresponding to a target read port. When the read enable signal is valid and the first check bit data is consistent with the second check bit data, the target read data is output from the register file via the target read port.

[0085] The read enable signal is used to indicate that a read operation to the register is allowed.

[0086] Specifically, when a read operation is required during instruction execution, the control circuit within the CPU can transmit a read enable signal and a read index signal to a read port of the register file, so that after determining the read target register based on the read index signal, the target read port corresponding to the read enable signal can select the target read data and its corresponding check bit data from the read target register and read them. The check bit data is recalculated for the read target read data, and if the recalculated check bit data is consistent with the read check bit data, the target read data is output from the register file via the target read port. In some embodiments, the target read port can be a read port that receives the read enable signal.

[0087] In some implementations, the number of read ports is two.

[0088] In some cases, during instruction execution, one or two read operations can typically be performed within a clock cycle. Therefore, the register file typically has two read ports. Two sets of parity check circuits can be provided for these two read ports. In some embodiments, the parity check circuit corresponding to one of the read ports can be reused to generate parity bits for write operations in the register file.

[0089] In some embodiments, different check algorithms may have different complexities, and thus, the structural complexity of the corresponding check bit generation circuit and check bit checking circuit may also be different. Therefore, the number of check bit checking circuits and check bit generation circuits can be changed according to the complexity of the circuit using the check algorithm. For example, if the check bit checking circuit structure of a certain check algorithm is relatively simple and requires less circuit resources, then it can be considered to set the corresponding check bit checking circuit according to the number of registers in the register stack, rather than setting the check bit checking circuit according to the number of read ports. In this case, although the increase in the number of check bit checking circuits will lead to an increase in the area of ​​the CPU, since each register has its own corresponding dedicated check bit checking circuit, when performing a read operation, there is no need to select the register to read the target register first, so the verification result can be generated more quickly, which can be beneficial to improving the circuit working efficiency.

[0090] An embodiment of the present specification provides a register file check device, which includes the register file check device including the check bit generation circuit of any of the aforementioned embodiments, and the register file check device including the check bit checking circuit of any of the aforementioned embodiments.

[0091] For example, refer to Figure 5As shown, the register file is provided with a write port wp1, a write port wp2, a read port rp1, and a read port rp2, and includes 32 registers, namely R0, R1, ..., R31. The register file verification device is provided with a parity bit generation circuit 1 and a parity bit generation circuit 2, as well as a parity bit checking circuit 1 and a parity bit checking circuit 2. Each parity bit generation circuit may include a parity bit calculation module and a merging module, and each parity bit checking circuit may include a parity bit recalculation module and a comparator module. Parity bit generation circuit 1 is provided in correspondence with write port wp1 to receive write data WD1 transmitted from write port wp1; parity bit generation circuit 2 is provided in correspondence with write port wp2 to receive write data WD2 transmitted from write port wp2; parity bit checking circuit 1 is provided in correspondence with read port rp1 to transmit target read data RD1 that passes the parity check to read port rp1 for output; parity bit checking circuit 2 is provided in correspondence with read port rp2 to transmit target read data RD2 that passes the parity check to read port rp2 for output. Furthermore, the register file verification device also includes a write decoding circuit and a read decoding circuit. The write decoding circuit can receive write index signals WK1 and WK2 from write ports wp1 and wp2, respectively, and is used to determine, from the 32 registers in the register file, a write target register wdr1 corresponding to write port wp1 and a write target register wdr2 corresponding to write port wp2; the read decoding circuit can receive read index signals from read ports rp1 and rp2, respectively, and is used to determine, from the 32 registers in the register file, a read target register rdr1 corresponding to read port rp1 and a read target register rdr2 corresponding to read port rp2.

[0092] By way of example, the workflow of the register file checking device in the above embodiment is described. Figure 5As shown, write port wp1 needs to perform a write operation on register R0, and write port wp2 needs to perform a write operation on register R1. Specifically, write port wp1 passes the write index signal WK1 to the write decoder circuit for decoding, locates the write target register R0, and generates a write hit signal wp1_hit0 for the write target register R0. Write port wp1 passes the write data WD1 to the check bit generation circuit 1. The check bit calculation module 1 in the check bit generation circuit 1 calculates and generates the check bit data WC1 corresponding to the write data WD1. The merge module 1 concatenates the write data WD1 and the check bit data WC1 to form the write target data. This allows write port wp1 to write the write target data into register R0 based on the write enable signal and the write hit signal wp1_hit0 of register R0, completing the write operation of write port wp1. Write port wp2 passes the write index signal WK2 to the write decoder circuit for decoding, locates the write target register R1, and generates a write hit signal wp2_hit1 for the write target register R1. The write port wp2 passes the write data WD2 to the check bit generation circuit 2. The check bit calculation module 2 in the check bit generation circuit 2 calculates and generates the check bit data WC2 corresponding to the write data WD2. The merging module 2 splices the write data WD2 and the check bit data WC2 to form the write target data, so that the write port wp2 can write the write target data into the register R1 according to the write enable signal and the write hit signal wp2_hit1 of the register R1 to complete the write operation of the write port wp2.

[0093] Read port rp1 needs to select and read the target read data WD1 and its corresponding parity data WC1 from register R0. Read port rp2 needs to select and read the target read data WD2 and its corresponding parity data WC2 from register R1. Specifically, read port rp1 transmits the read index signal RK1 to the read decoding circuit for decoding, locates the read target register R0, and generates a read select signal rp1_sel0 for register R0. Read port rp1 selects data WD1 and its corresponding parity data WC1 from register R0 based on the read enable signal and the read select signal rp1_sel0. Data WD1 is then transmitted to parity check circuit 1. Parity recalculation module 1 of parity check circuit 1 calculates parity data RC1' for data WD1. Comparator module 1 of parity check circuit 1 compares parity data RC1' with parity data WC1, generating comparison result 1. If the parity data RC1' and the parity data WC1 are consistent, data WD1 can be output from the register file via read port rp1, completing the read operation of read port rp1. Read port rp2 transmits the read index signal RK2 to the read decoding circuit for decoding, locates the read target register R1, and generates a read select signal rp2_sel1 for register R1. Read port rp2 selects data WD2 and its corresponding parity data WC2 from register R1 based on the read enable signal and read select signal rp2_sel1. Data WD2 is then transmitted to parity check circuit 2. Parity recalculation module 2 of parity check circuit 2 calculates parity data RC2' for data WD2. Comparator module 2 of parity check circuit 2 compares parity data RC2' with parity data WC2, generating comparison result Result2. If the parity bit data RC2' and the parity bit data WC2 are consistent, the data WD2 can be output from the register file via the read port rp2 to complete the read operation of the read port rp2. Furthermore, the comparison result resul1 and the comparison result result2 can be ORed together to obtain the final verification result of the current read operation of the read port rp1 and the read port rp2, which can be output from the register file.

[0094] It should be noted that, for other specific limitations of the register stack verification device in the above-mentioned embodiment, reference can be made to the specific limitations of the register stack verification device including the check bit generation circuit and the register stack verification device including the check bit checking circuit in the previous text, which will not be repeated here.

[0095] An embodiment of this specification provides a processor, which includes the register file checking device of any one of the aforementioned embodiments.

[0096] For example, refer to Figure 6aAs shown, the processor 601 may include a register file 603 and a register file check device 605. The register file check device 605 includes a check bit generation circuit 607. When the check bit generation circuit 607 is running, the write operation of any of the above embodiments can be implemented.

[0097] For example, refer to Figure 6b As shown, the processor 611 may include a register file 613 and a register file check device 615. The register file check device 615 includes a check bit check circuit 617. When the check bit check circuit 617 is running, the read operation of any of the above embodiments can be implemented.

[0098] For example, refer to Figure 6c As shown, the processor 621 may include a register stack 623 and a register stack check device 625. The register stack check device 625 includes a check bit generation circuit 627 and a check bit checking circuit 629. When the check bit generation circuit 627 is running, the write operation of any of the aforementioned implementation methods can be implemented; when the check bit checking circuit 629 is running, the read operation of any of the aforementioned implementation methods can be implemented.

[0099] The embodiment of this specification provides a write operation method for a register file, wherein the register file is provided with a write port, and a check bit generation circuit is provided for the write port. The number of the check bit generation circuits is greater than one and less than or equal to the number of the write ports. Figure 7 As shown, the method may include the following steps.

[0100] S710: The write port receives a write index signal and write data, wherein the write index signal corresponds to a write target register.

[0101] S720: The write port transmits the write data to the check bit generation circuit.

[0102] S730 : Utilize the check bit generation circuit to calculate the write data to obtain first check bit data.

[0103] S740 : Concatenate the first check bit data and the write data to generate write target data that can be written into the write target register.

[0104] It should be noted that, for the description of the write operation method of the register file in the above embodiment, please refer to the description of the register file verification device in this specification, and the details will not be repeated here.

[0105] In some embodiments, the register file write operation method may further include: using a write decoding circuit to decode a write index signal to generate a write hit signal, wherein the write hit signal is used to specify a write target register in the register file.

[0106] It should be noted that, for the description of the write hit signal in the above embodiment, please refer to the description of the write hit signal of the register file check device in this specification, and the details will not be repeated here.

[0107] In some embodiments, reference Figure 8 As shown, the register file write operation method may further include the following steps.

[0108] S810: Receive a write enable signal, wherein the write enable signal corresponds to a target write port.

[0109] S820 . When the write enable signal is valid, write the write target data corresponding to the target write port into the write target register.

[0110] It should be noted that, for the description of the write enable signal in the above embodiment, please refer to the description of the write enable signal of the register stack check device in this specification, and the details will not be repeated here.

[0111] The embodiment of this specification provides a register file read operation method, the register file is provided with a read port, and a parity check circuit is provided for the read port, and the number of the parity check circuits is equal to the number of the read ports. Figure 9 As shown, the method may include the following steps.

[0112] S910: The read port receives a read index signal, wherein the read target register corresponding to the read index signal stores target read data and first check bit data.

[0113] S920 , acquiring target read data and first check bit data from a target register according to a read index signal.

[0114] S930 , using a check bit checking circuit to calculate the target read data to obtain second check bit data.

[0115] S940 , determining whether to output the target read data from the register file via the read port according to a comparison result between the first check bit data and the second check bit data.

[0116] It should be noted that, for the description of the register file read operation method in the above embodiment, please refer to the description of the register file verification device in this specification, and the details will not be repeated here.

[0117] In some embodiments, the register file read operation method may further include: using a read decoding circuit to decode a read index signal to generate a read selection signal, wherein the read selection signal is used to specify a read target register in the register file.

[0118] It should be noted that, for the description of the read selection signal in the above embodiment, please refer to the description of the read selection signal of the register stack check device in this specification, and the details will not be repeated here.

[0119] In some embodiments, reference Figure 10 As shown, the register file read operation method may further include the following steps.

[0120] S1010: The write port also receives a read enable signal, which corresponds to a target read port.

[0121] S1020 . When the read enable signal is valid and the first check bit data is consistent with the second check bit data, output the target read data from the register file through the target read port.

[0122] It should be noted that, for the description of the read enable signal in the above embodiment, please refer to the description of the read enable signal of the register stack check device in this specification, and the details will not be repeated here.

[0123] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0124] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0125] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0126] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0127] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0128] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A register file check device, characterized in that: The register file is provided with a write port, the write port receiving a write index signal and write data; the device includes: a check bit generation circuit provided for the write port; the number of the check bit generation circuits is greater than one and less than or equal to the number of the write ports; wherein the write port transmits the write data to the check bit generation circuit, and the check bit generation circuit calculates the write data to obtain first check bit data; wherein the first check bit data is used to be spliced ​​with the write data to form write target data that can be written into the write target register corresponding to the write index signal; The device further includes a write decoding circuit, which is used to decode the write index signal to generate a write hit signal; wherein the write hit signal is used to specify the write target register in the register file.

2. The device according to claim 1, characterized in that The write port also receives a write enable signal; the write enable signal corresponds to a target write port; when the write enable signal is valid, the write target data corresponding to the target write port is written into the write target register.

3. The device according to claim 1, characterized in that When the number of the write ports is 2, the number of the check bit generation circuits is 1 or 2.

4. The device according to claim 3, characterized in that When the number of the write ports is 2 and the number of the check bit generation circuits is 2, the check bit generation circuit can be multiplexed for check bit checking in a read operation and check bit generation in a write operation of the register file.

5. A register file check device, characterized in that: The register file is provided with a read port, and the read port receives a read index signal; the device comprises: a parity check circuit provided for the read port; the number of the parity check circuits is equal to the number of the read ports; The read target register corresponding to the read index signal stores target read data and first check bit data, and the first check bit data is used to be spliced ​​with the write data to form write target data that can be written to the write target register corresponding to the write index signal; the check bit check circuit calculates the target read data to obtain second check bit data, and determines whether to output the target read data from the register file through the read port based on a comparison result of the first check bit data and the second check bit data; The device further includes a read decoding circuit configured to decode the read index signal to generate a read selection signal; wherein the read selection signal is configured to specify the read target register in a register file.

6. The device according to claim 5, characterized in that The read port also receives a read enable signal; the read enable signal corresponds to a target read port; when the read enable signal is valid and the first check bit data is consistent with the second check bit data, the target read data is output from the register stack via the target read port.

7. The device according to claim 5, characterized in that The number of the read ports is 2.

8. A register file checking device, characterized in that: The device includes the register file checking device according to any one of claims 1 to 4 and the register file checking device according to any one of claims 5 to 7.

9. A processor, characterized in that: The processor comprises the register file checking device according to any one of claims 1 to 8.

10. A method for writing a register file, characterized in that: The register file is provided with a write port, and a check bit generation circuit is provided for the write port; the number of the check bit generation circuits is greater than one and less than or equal to the number of the write ports; the method includes: The write port receives a write index signal and write data; wherein the write index signal corresponds to a write target register; The write port transmits the write data to the check bit generation circuit; Calculating the write data using the check bit generation circuit to obtain first check bit data; splicing the first check bit data and the write data to generate write target data that can be written into the write target register; The write index signal is decoded by a write decoding circuit to generate a write hit signal; wherein the write hit signal is used to indicate the write target register in the register file.

11. The method according to claim 10, characterized in that The method further comprises: receiving a write enable signal; wherein the write enable signal corresponds to a target write port; When the write enable signal is valid, the write target data corresponding to the target write port is written into the write target register.

12. A register file read operation method, characterized in that: The register file is provided with a read port, and a parity bit checking circuit is provided for the read port; The number of the parity check circuits is equal to the number of the read ports; the method comprising: The read port receives a read index signal; wherein the read target register corresponding to the read index signal stores target read data and first check bit data, and the first check bit data is used to be spliced ​​with the write data to form write target data that can be written to the write target register corresponding to the write index signal; Acquire the target read data and the first check bit data from the target register according to the read index signal; Calculating the target read data using the check bit checking circuit to obtain second check bit data; determining whether to output the target read data from the register file via the read port according to a comparison result of the first check bit data and the second check bit data; The read index signal is decoded by a read decoding circuit to generate a read selection signal; wherein the read selection signal is used to specify the read target register in a register file.

13. The method according to claim 12, characterized in that The method further comprises: The read port also receives a read enable signal; wherein the read enable signal corresponds to a target read port; When the read enable signal is valid and the first check bit data is consistent with the second check bit data, the target read data is output from the register file through the target read port.

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