An implementation method, device and storage medium for efficient regression

Abstract

The present invention discloses a method, apparatus, and storage medium for realizing efficient regression. The method includes running and loading a first-level control file and storing the test excitation results in a simulation folder; after the test excitation starts, every first preset time period, traversing the simulation folder to view the log file generated by executing the first-level control file; monitoring the excitation process, and switching and loading a second-level control file to re-test the excitation simulation when an error occurs; extracting keywords in the first-level control file that has completed the excitation in the simulation folder, analyzing the passing situation of the test excitation for executing the first-level control file, and outputting a first table of the final simulation results. In the present invention, when an error occurs in the test excitation, it pauses, loads and runs a second-level control file for controlling the simulation to generate a waveform file for re-simulation, and only generates a waveform file for the erroneous test excitation, replacing the traditional storage method of storing a complete waveform file, and reducing the memory pressure caused by the amount of stored data.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly to a method, device and storage medium for realizing efficient regression. Background Art

[0002] In the later stage of the chip functional verification process, all test stimuli need to be subjected to regression testing to ensure that there are no problems with the changes in the design code.

[0003] In the existing technology, the common practice is to perform regression simulation on a high-performance server. Staff members count the regression results and complete the regression report for this time.

[0004] In the later stage of the project, the number of test stimuli is huge and the regression is frequent, resulting in a huge number of generated waveform and log files. On the one hand, designers and verifiers only focus on a small number of abnormal test cases with problems, which greatly wastes storage space and server performance. Excessive regression times will also lead to the phenomenon of full storage space and abnormal interruption of regression, greatly reducing the verification regression efficiency and occupying a large amount of machine resources; on the other hand, a large number of regression results need to be counted, and a series of cumbersome and repetitive tasks such as tabulation and email notification are completed, consuming a large amount of human resources.

[0005] In view of this, overcoming the defects of this existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is how to solve the problems of waste of storage space and memory resources and low regression efficiency in verification regression.

[0007] The present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention proposes a method for realizing efficient regression. For a control file used to control the generation of waveform files, a two-level file architecture is designed. Among them, the first-level control file controls the simulation process not to generate waveform files, and the second-level control file controls the simulation process to generate waveform files. The method includes:

[0009] All test stimuli are run and the first-level control file is loaded, and the test results are stored in the corresponding simulation folder;

[0010] After the regression starts, every first preset time period, all simulation folders are traversed to view the files in the simulation folders generated by the simulation;

[0011] If an error occurs during the traversal process, the simulation of the test stimuli is stopped, the second-level control file is switched and loaded, and the simulation operation of the test stimuli is restarted; at this time, waveform files are generated and the generated waveform files are stored in the corresponding simulation folders;

[0012] Extract the keywords in the log generated by executing the first-level control file in the simulation folder, analyze the passing situation of the test stimuli corresponding to the executed first-level control file, and generate a first table for the test stimulus results to conduct result status statistics; among them, once there is a waveform file in the simulation folder, it is confirmed that the corresponding test stimulus fails, and the result status statistics are revealed in the first table.

[0013] Preferably, the two-level file architecture is designed, wherein the first-level control file controls the simulation process not to generate waveform files, and the second-level control file controls the simulation process to generate waveform files, specifically including:

[0014] The first-level control file controls the simulation process to only generate the corresponding log file; the second-level control file controls the simulation process to generate both log files and corresponding waveform files; both are controlled by the process of test stimuli, and the difference is that the first-level control file is the file defaultly loaded during the test stimulus simulation process, while the second-level control file is the file switched and loaded when it is monitored that the test stimulus goes wrong and triggers the re-execution of the content of the corresponding time period for simulation.

[0015] Preferably, to prevent the program from misjudging and thus repeating the simulation multiple times, a protection mechanism is added. Among them, when an error occurs in the simulation is monitored during the traversal process, the simulation of the test stimulus is stopped, the second-level control file that can control the simulation to generate waveform files is switched and loaded, and after the simulation operation of the test stimulus is re-performed, the method further includes:

[0016] Freeze the current simulation folder and re-create a simulation folder for storing the waveform files and log files generated by the subsequent test stimulus simulation;

[0017] Among them, subsequently, when a corresponding waveform file is detected under the simulation folder, this judgment is skipped; finally, after all simulations are completed, only the test stimulus simulations with errors are re-simulated to generate the corresponding waveform files, and the other correctly passed test stimuli only print out the log files.

[0018] Preferably, before traversing all simulation folders and viewing the files in the generated simulation folders, it further includes:

[0019] Use the Perl scripting language to construct an excitation error monitoring program and set the first preset time period for monitoring;

[0020] Obtain the access permission of the simulation folder, and then use the excitation error monitoring program to access and view the files in the simulation folder.

[0021] Preferably, before extracting the keywords in the log generated by executing the first-level control file in the extraction simulation folder, it further includes: constraining the system and setting an error flag. When an error occurs during the test excitation process, the system stores the generated error flag in the corresponding log file and stores the log file in the simulation file.

[0022] Preferably, when an error occurs during the monitoring traversal process, stop the simulation of the test excitation, switch and load the second-level control file, which specifically includes:

[0023] Use the excitation error monitoring program to view the log files in the simulation folder and query whether an error flag appears in the log files;

[0024] If the error flag does not appear in the log file, it means that there is no error in the simulation of the test excitation, and the current test excitation simulation continues to be executed;

[0025] If the error flag appears in the log file, it means that there is an error in the simulation of the test excitation, then switch and load the second-level control file and re-perform the test excitation simulation.

[0026] Preferably, before stopping the simulation of the test excitation when an error occurs in the simulation during the traversal process, switching and loading the second-level control file that can control the simulation to generate waveform files, and re-performing the test excitation simulation operation, it further includes adjusting the first preset time period, which specifically includes:

[0027] Use the excitation error monitoring program to monitor the regression simulation process, and obtain the test excitations with errors within multiple first preset time periods, as well as the number of error flags that appear in each first preset time period;

[0028] Set the error flag number threshold and the condition for triggering the adjustment of the first preset time period;

[0029] If the number of error flags that appear is greater than the error flag number threshold, and the proportion of the number of first preset time periods corresponding to the number of error flags that appear exceeding the preset proportion, then adjust the first preset time period to the second preset time period, where the second preset time period is less than the first preset time period.

[0030] Preferably, extract the keywords in the log generated by executing the first-level control file in the simulation folder, analyze the passing situation of the test excitation corresponding to the execution of the first-level control file, and generate a first table for the test excitation results to perform result status statistics, which specifically includes:

[0031] Use an incentive error monitoring program to extract all simulation folders corresponding to the logs generated by executing the first control file, and convert the log files into corresponding strings; among them, the strings converted from the log files with error identifiers correspond to the keywords;

[0032] Analyze one by one the strings converted from the log files generated by executing the first control file in the simulation folder. If the keyword appears, it means that there is an error in the test incentive simulation process, and the test incentive fails; if the keyword does not appear, it means that there is no error in the test incentive simulation process, and the test incentive passes, and the final simulation result is output to generate the first table.

[0033] In a second aspect, the present invention also provides an implementation device for efficient regression, which is used to implement the method for implementing efficient regression described in the first aspect. The device includes:

[0034] At least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the method for implementing efficient regression described in the first aspect.

[0035] In a third aspect, the present invention also provides a non-volatile computer storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors to complete the method for implementing efficient regression described in the first aspect.

[0036] By setting a two-level file architecture, when an error occurs in the chip test incentive simulation process, the test incentive simulation is stopped, and the second-level control file for generating the waveform file is switched and loaded. Then, the test incentive corresponding to the current first preset time period with an error is re-simulated, and a waveform file is generated and stored in the corresponding simulation folder for regression verification to analyze the cause of the error. Based on the prior art, the present invention controls whether to generate a waveform file in the simulation process by setting a two-level file architecture. For normal incentive tests, no waveform file needs to be generated, and only for abnormal incentive tests will a waveform file be generated, greatly reducing the data volume occupied by the stored data in the simulation folder, avoiding excessive data volume and low efficiency during the regression verification process, and reducing the load problem on storage. Description of the Drawings

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for use in the embodiments of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 is a flowchart of an implementation method for efficient regression provided by an embodiment of the present invention;

[0039] Figure 2 is a flowchart of an implementation method for efficient regression provided by an embodiment of the present invention;

[0040] Figure 3 is a flowchart of an implementation method for efficient regression provided by an embodiment of the present invention;

[0041] Figure 4 is a flowchart of an implementation method for efficient regression provided by an embodiment of the present invention;

[0042] Figure 5 is a flowchart of an implementation method for efficient regression provided by an embodiment of the present invention;

[0043] Figure 6 is a schematic structural diagram of an implementation device for efficient regression provided by an embodiment of the present invention. Detailed implementation manners

[0044] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following further details the present invention in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0045] In the description of the present invention, the orientation or positional relationships indicated by the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present invention and do not require the present invention to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0046] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] The embodiment of the present invention provides an implementation method for efficient regression. For a control file used to control the generation of a waveform file, a two-level file architecture is designed. Among them, the first-level control file controls the simulation process not to generate a waveform file, and the second-level control file controls the simulation process to generate a waveform file. As Figure 1 shown, the method includes:

[0048] Step 201: Run and load the first-level control file for all test stimuli, and store the test results in the corresponding simulation folder.

[0049] During the chip design process, it is necessary to perform functional verification on the design code. During the verification of the chip design code, by constructing test stimuli, verify the design code, discover the hidden bugs, and modify them to ensure the correctness and functional completeness of the design code. At the later stage of chip design verification, regression verification is required, that is, run all the previous test stimuli and perform verification. Without knowing whether there are errors in the upcoming test stimuli, all test stimuli run and load the first-level control file; when the program (the stimulus error monitoring program built with the Perl scripting language) scans for the keywords corresponding to the errors in the generated log file (the log file is stored in the simulation file), it means that the test stimulus is incorrect, and then run the second-level control file. It should be noted that in the embodiments of the present invention, the first-level control file and the second-level control file for controlling the simulation process will generate corresponding log files, and the generated log files are stored in the corresponding simulation folders. The waveform files generated by the second-level control file for controlling the simulation are also stored in the corresponding simulation folders. It should be noted that the control files (the first-level control file and the second-level control file) of the present invention are specifically used but not limited to TCL (Tool-Command-Language) files.

[0050] Step 202: After the regression starts, every first preset time period, traverse all simulation folders and view the files in the simulation folders generated by the simulation.

[0051] In the embodiments of the present invention, while performing the test stimulus simulation process on the chip, regression verification of the chip is also being carried out. The process of regression verification is actually scanning the log file generated by running and loading the first control file. When the test stimulus simulation of the chip starts, the first-level control file will be run and loaded, and the first-level control file will control the test stimulus simulation process to generate corresponding log files. It should be noted that the first preset time period in the embodiments of the present invention is set according to the actual situation. In order to distinguish the first preset time period from the second preset time period mentioned later in the embodiments of the present invention, the first preset time period and the second preset time period will be described uniformly later.

[0052] Step 203: If an error occurs during the traversal process, stop the simulation of the test stimulus, switch and load the second-level control file, and re-perform the simulation operation of the test stimulus; at this time, generate waveform files and store the generated waveform files in the corresponding simulation folders.

[0053] During the regression verification process, the logs generated by the current and previous runs of the test stimulus simulation with the first-level control file loaded are traversed and monitored. Once an error occurs in the test stimulus (as indicated by the keyword in the log corresponding to the test stimulus), the test stimulus simulation is stopped, and the second-level control file is loaded. The test stimulus within the first preset time period with the error is re-simulated, and the corresponding waveform file is generated.

[0054] In this embodiment, the incentive error monitoring program is used to view the log file in the simulation folder and check whether an error flag appears in the log file. If the error flag does not appear in the log file, it means that there is no error in the simulation of the test stimulus, and the current test stimulus simulation continues to be executed. If the error flag appears in the log file, it means that there is an error in the simulation of the test stimulus, and the second-level control file is switched and loaded, and the test stimulus simulation is re-performed, and the corresponding waveform file is generated. Here, the error flag is a specified keyword. For example, the keyword can be "Error" or "Fatal", and the present invention is not limited thereto.

[0055] It can be understood that if the corresponding keywords "Error" or "Fatal" are found in the log file, the script program is used to interrupt the corresponding simulation thread, switch the first-level control file to the second-level control file, and then perform re-simulation to generate the corresponding waveform file.

[0056] In the embodiment of the present invention, when running the test stimulus simulation for loading the second-level control file, waveform files and log files will be generated; when running the test stimulus for loading the first-level control file, only the corresponding log files will be generated, and no waveform files will be generated. The design has a two-level file architecture. Among them, the first-level control file controls the simulation process not to generate waveform files, and the second-level control file controls the simulation process to generate waveform files. Specifically, the first-level control file controls the simulation process to only generate the corresponding log files; the second-level control file controls the simulation process to generate both log files and the corresponding waveform files; both are by controlling the test stimulus process, and the difference is that the first-level control file is the file defaultly loaded during the test stimulus simulation process, while the second-level control file is the file switched and loaded when it is monitored that the test stimulus goes wrong and triggers the re-execution of the content for a corresponding time period for simulation. In the embodiment of the present invention, the first-level control file and the second-level control file can be respectively understood as a program or an instruction. Running and loading which control file (the first-level control file or the second-level control) can determine whether waveform files are generated during the test stimulus process. Compared with the log files, the waveform files occupy a large storage space. Therefore, through the first-level control file set in the embodiment of the present invention, waveform files are not generated during normal test stimuli. The second-level control file is used to re-simulate the wrong test stimuli to generate the corresponding waveform files, so as to facilitate the analysis of the reasons for the errors. In the embodiment of the present invention, it is judged whether the test stimulus passes by analyzing whether the keyword is carried in the log file; if the keyword is carried in the log file, it means that the corresponding test stimulus fails. At this time, the wrong test stimulus needs to be re-simulated. Before re-simulating, switch to load the second-level control file and generate waveform files, so as to facilitate the restoration of the reasons for the errors that occurred during the test stimulus simulation process through the waveforms.

[0057] Step 204: Extract the keywords in the log generated by executing the first-level control file in the simulation folder, analyze the passing situation of the test stimulus corresponding to the execution of the first-level control file, and generate a first table for the test stimulus results to perform result status statistics; among them, once there are waveform files in the simulation folder, it is confirmed that the corresponding test stimulus fails, and the result status statistics are revealed in the first table.

[0058] In the prior art, by simulating the chip design code, after all test stimuli simulations are completed, the simulation results are output. During the process of prior art test stimulus simulation, it is usually stored in a way that carries a complete waveform file (for each test stimulus, whether correct or incorrect, a corresponding waveform file will be generated and stored in the corresponding simulation folder). Theoretically speaking, when most of the test results are correct, or even all test structures are correct, still using the prior art method to perform stimulus simulation testing on the chip will result in an excessive amount of data loaded during the subsequent regression simulation process, causing the regression simulation efficiency to be extremely low, and moreover, bringing a huge burden to storage. Compared with the prior art, the present invention sets a two-level file architecture. When the chip test stimulus is normal, the first-level control file is run and loaded, and only log files are generated (waveform files are not generated); when the regression verification detects an error during the test stimulus simulation process, the test stimulus simulation is stopped, the second-level control file is switched and loaded to re-simulate, and waveform files are generated and stored in the simulation folder. The present invention only re-simulates the incorrect test stimuli within the current first preset time period, and switches from the first-level control file to the second control file for the regression verification to analyze the cause of the error. Based on the prior art, the present invention selects a two-level file architecture for simulation. For normal stimulus tests, waveform files do not need to be generated, and waveform files are only generated for abnormal stimulus tests, greatly reducing the amount of data occupied by the stored data in the simulation folder, avoiding excessive data loading and low efficiency during the regression verification process, and reducing the burden on storage. It should be noted that the first table in the embodiment of the present invention can be, but is not limited to, an Excel table.

[0059] In order to elaborate on the complete solution of the present invention, the specific details of the present invention will be explained in detail next. Further, to prevent the program from misjudging and thus repeating the simulation multiple times, a protection mechanism is added. Among them, when an error occurs during the simulation is detected during the traversal process, the simulation of the test stimulus is stopped, the second-level control file that can control the simulation to generate waveform files is switched and loaded, and after the simulation operation of the test stimulus is re-performed, the method further includes: freezing the current simulation folder and re-creating a simulation folder for storing the waveform files and log files generated by the subsequent test stimulus simulation; among them, subsequently, when a corresponding waveform file is detected under the simulation folder, this judgment is skipped; finally, after all simulations are completed, only the incorrect test stimulus simulations that have been re-simulated to generate the corresponding waveform files, and the other correctly passed test stimuli only print out the log files.

[0060] Since each regression verification halts the test stimulus simulation when an error is detected in the test stimulus simulation, switches and loads the second-level control file, then retests the stimulus simulation for this time segment and generates the corresponding waveform file. During the retest simulation, the regression verification will repeat the identification and extraction of files in the simulation folder that have been extracted before. To avoid repetitive work, the embodiment of the present invention freezes the current simulation folder after the chip undergoes the test stimulus simulation. Usually, after the chip undergoes the test stimulus simulation, it can be ensured that the files in the current and previous test stimulus simulation folders are all normal (no error occurred during the current and previous test stimulus simulation processes). At this time, the current simulation folder is frozen, and a new simulation folder is created as the storage for the waveform files and log files generated during the subsequent test stimulus simulation. The subsequent regression verification only needs to identify and extract the simulation folder in the storage, greatly reducing the workload in the data processing process and improving the efficiency of the regression verification process. It should be noted that the simulation file frozen in the embodiment of the present invention is: the simulation file with normal monitored test stimuli.

[0061] Further, before traversing all simulation folders and viewing the files in the simulation folder generated by the simulation, as Figure 2 shown, it further includes:

[0062] Step 301: Use Perl scripting language to construct an excitation error monitoring program and set the first preset time segment for monitoring.

[0063] The embodiment of the present invention uses Perl scripting language to construct an excitation error monitoring program. Through the excitation error monitoring program, the files in the simulation folder are identified and extracted, and then it is determined whether an error occurs in the test stimulus simulation.

[0064] Step 302: Obtain the access permission of the simulation folder, and then use the excitation error monitoring program to access and view the files in the simulation folder.

[0065] Before accessing the simulation folder, it is also necessary to obtain the access permission of the simulation file. The test stimulus simulation and the regression verification (actually scanning) belong to two different processes. Among them, the excitation error monitoring program is used to perform the regression verification. Through the excitation error monitoring program, the files in the simulation file are extracted and viewed to determine whether an error occurs during the test stimulus simulation process.

[0066] Further, before extracting the keywords in the log generated by executing the first-level control file in the simulation folder, it also includes: constraining the system and setting an error flag. When an error occurs during the test stimulus process, the system stores the generated error flag in the corresponding log file and stores the log file in the simulation file.

[0067] The difference between the first-level control file and the second-level control file in the embodiments of the present invention is that the second-level control file can control the generation of waveform files during the test excitation process. When a waveform file appears in the simulation folder, it proves that the regression verification has detected an error during the test excitation simulation process. To facilitate the excitation error monitoring program to quickly detect whether an error occurs during the test excitation simulation process, the embodiments of the present invention impose constraints on the system and set an error flag. When an error occurs during the test excitation process, the system stores the error flag that appears in the corresponding simulation file (actually stored in the log generated by the simulation). The function of the error flag is similar to the waveform file in the embodiments of the present invention, but the difference is that the waveform files in the embodiments of the present invention are generated under different time periods and different test excitation simulation contents, and the waveform files generated by the simulation are usually different, so as to facilitate the program or system to specifically analyze the cause of the error for different test excitation simulation contents. The error flags in the embodiments of the present invention are usually set to be exactly the same, so as to facilitate the subsequent adjustment of the parameters (such as: the first preset time period) in the excitation error monitoring program.

[0068] Further, when an error occurs during the monitoring traversal process, stop the simulation of the test excitation, switch and load the second-level control file, as Figure 3 shown, specifically including:

[0069] Step 401: Use the excitation error monitoring program to view the log file in the simulation folder and query whether an error flag appears in the log file;

[0070] Step 402: If the error flag does not appear in the log file, it means that no error occurs in the simulation of the test excitation, and the current test excitation simulation continues; if the error flag appears in the log file, it means that an error occurs in the simulation of the test excitation, then switch and load the second-level control file and re-perform the test excitation simulation.

[0071] Further, referring to Figure 4 , before stopping the simulation of the test excitation when an error is detected in the simulation during the traversal process, switching and loading the second-level control file that can control the generation of waveform files by the simulation, and re-performing the simulation operation of the test excitation, it also includes the adjustment of the first preset time period, specifically including:

[0072] Step 501: Use the excitation error monitoring program to monitor the regression simulation process, and obtain the test excitations with errors within multiple first preset time periods, and the number of error flags that appear in each first preset time period.

[0073] During the simulation of test stimuli, to avoid unreasonable situations in the set first preset time period. For example, the value set for the first preset time period is very large, and there are many occurrences of errors, resulting in great difficulty and complexity in analyzing each node with an error within this preset time period one by one when conducting a specific analysis later. Therefore, it is necessary to further adjust the first preset time period reasonably so that the number of errors occurring within the first preset time period does not exceed a certain value at most, facilitating subsequent processing and reducing the pressure on the system to analyze the specific error principle during this process. In addition, shortening the length of the first preset time period can also reduce the workload of regression verification simulation to identify and extract the simulation folder.

[0074] Step 502: Set a threshold for the number of error flags and a condition for triggering the adjustment of the first preset time period. If the number of error flags that appear is greater than the threshold for the number of error flags, and the proportion of the number of first preset time periods corresponding to the number of error flags that appear and greater than the threshold for the number of error flags exceeds a preset proportion, then adjust the first preset time period to a second preset time period, where the second preset time period is less than the first preset time period.

[0075] According to the actual situation of the system of the present invention, set a threshold for the number of error flags. When the number of error flags that appear within the first preset time period is greater than the threshold for the number of error flags, it is necessary to shorten the time interval of the first preset time period. However, to avoid the situation where the number of error flags that appear in only one first preset time period is greater than the threshold for the number of error flags due to other reasons (such as operation errors or unstable test stimulus simulation at the beginning), the embodiment of the present invention obtains the regression verification situation of errors occurring within multiple first preset time periods. If the number of error flags that appear is greater than the threshold for the number of error flags, and the proportion of the number of first preset time periods corresponding to the number of error flags that appear and greater than the threshold for the number of error flags exceeds a preset proportion, then shorten the first preset time period and adjust the first preset time period to a second preset time period. Thereby shortening the time spent on retesting the stimulus simulation.

[0076] Further, extract the keywords in the log generated by executing the first-level control file in the simulation folder, analyze the passing situation of the test stimuli corresponding to the execution of the first-level control file, and generate a first table for the test stimulus results to perform result status statistics, as Figure 5 shown, specifically including:

[0077] Step 601: Use the incentive error monitoring program to extract all simulation folders corresponding to the log generated by executing the first control file, and convert the log file into a corresponding string; the string converted from the log file with an error flag corresponds to the keyword.

[0078] In the embodiment of the present invention, a regression verification scan is performed on the test stimulus simulation process by using an excitation error monitoring program, the log file generated during the excitation test simulation under the first-level control file is identified and extracted (stored in the simulation folder), and the log file in the simulation folder is converted into a string. Among them, the string generated by converting the log with an error identifier corresponds to the keyword, and then the number of errors occurring in the test stimulus simulation can be found out through the keyword.

[0079] Step 602: Analyze each string converted from the log file generated by executing the first control file in the simulation folder one by one. If the keyword appears, it means that an error occurs in the test stimulus simulation process, and the test stimulus fails; if the keyword does not appear, it means that no error occurs in the test stimulus simulation process, and the test stimulus passes, and the final simulation result is output to generate the first table.

[0080] In the present invention, by setting a two-level file architecture, when an error occurs in the chip test stimulus simulation process, the test stimulus simulation is stopped, and the second-level control file for generating the waveform file is switched and loaded. Then, the test stimulus corresponding to the current first preset time period with an error is re-simulated, and a waveform file is generated and stored in the corresponding simulation folder for regression verification to analyze the cause of the error. On the basis of the prior art, the present invention controls whether to generate a waveform file during the simulation process by setting a two-level file architecture. For normal excitation tests, no waveform file needs to be generated, and only for abnormal excitation tests will a waveform file be generated, greatly reducing the amount of data occupied by the data stored in the simulation folder, avoiding excessive data loading and low efficiency during the regression verification process, and reducing the load problem on storage. In addition, according to actual needs, the first preset time period is adjusted and shortened, so that the time spent on re-testing the stimulus simulation is reduced, and the workload of re-simulation is reduced as much as possible.

[0081] As Figure 6 shown, it is a schematic structural diagram of the device for realizing efficient regression in the embodiment of the present invention. The device for realizing efficient regression in this embodiment includes one or more processors 21 and a memory 22. Among them, Figure 6 One processor 21 is taken as an example.

[0082] The processor 21 and the memory 22 can be connected through a bus or other means, Figure 6 Taking the connection through the bus as an example.

[0083] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the implementation method of efficient regression in the above embodiments. The processor 21 executes the implementation method of efficient regression by running the non-volatile software programs and instructions stored in the memory 22.

[0084] The memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 optionally includes a memory remotely disposed relative to the processor 21, and these remote memories can be connected to the processor 21 through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0085] The program instructions / modules are stored in the memory 22 and, when executed by the one or more processors 21, execute the implementation method of efficient regression in the above embodiments. For example, execute each of the Figures 1-5 steps shown above.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An implementation method of efficient regression, characterized in that, The control file for controlling the generation of waveform files has a two-level file architecture. Among them, the first-level control file controls that no waveform files are generated during the simulation process, and the second-level control file controls that waveform files are generated during the simulation process. The method includes: All test stimuli are run and the first-level control file is loaded, and the test results are stored in the corresponding simulation folder; After the regression starts, using the Perl scripting language, construct an excitation error monitoring program and set the first preset time period for monitoring; obtain the access permission to the simulation folder, and then use the excitation error monitoring program to access and view the files in the simulation folder. Every first preset time period, traverse all simulation folders and view the files in the simulation folder generated by the simulation; Use the excitation error monitoring program to monitor the regression simulation process, and obtain the test stimuli with errors in multiple first preset time periods, and the number of error flags that appear in each first preset time period; Set the error flag number threshold and the condition for triggering the adjustment of the first preset time period; If the number of error flags that appear is greater than the error flag number threshold, and the proportion of the number of first preset time periods corresponding to the number of error flags that appear and greater than the error flag number threshold exceeds the preset proportion, then adjust the first preset time period to the second preset time period, where the second preset time period is less than the first preset time period; When an error occurs during the traversal process, stop the simulation of the test stimulus, switch and load the second-level control file, and re-perform the simulation operation of the test stimulus; generate a waveform file and store the generated waveform file in the corresponding simulation folder; Extract the keywords in the log generated by executing the first-level control file in the simulation folder, analyze the passing situation of the test stimuli corresponding to the execution of the first-level control file, and generate a first table for the test stimulus results to perform result status statistics; once there is a waveform file in the simulation folder, it is confirmed that the corresponding test stimulus fails, and the result status statistics are revealed in the first table.

2. The implementation method of efficient regression according to claim 1, wherein The first-level control file controls that no waveform files are generated during the simulation process, and the second-level control file controls that waveform files are generated during the simulation process, including: The first-level control file controls that only the corresponding log files are generated during the simulation process; the second-level control file controls that both log files and corresponding waveform files are generated during the simulation process; the first-level control file is the file that is default loaded during the test stimulus simulation process, and the second-level control file is the file that is switched and loaded when it is detected that the test stimulus has an error and triggers the re-execution of the content of the corresponding time period for simulation.

3. The implementation method of efficient regression according to claim 2, characterized in that, When an error occurs in the simulation during the traversal process, stop the simulation of the test stimulus, switch and load the second-level control file that can control the generation of waveform files during the simulation, and after re-performing the simulation operation of the test stimulus, the method further includes: Freeze the current simulation folder and re-create a simulation folder as the depository for the waveform files and log files generated by the subsequent test stimulus simulation; Among them, when a corresponding waveform file is detected in the simulation folder later, this judgment will be skipped; after all simulations are finally completed, only the simulation of the test stimulus with errors will be re-simulated to generate the corresponding waveform file, while the other correctly passed test stimuli will only print out the log file.

4. The implementation method of efficient regression according to claim 1, wherein Before extracting the keywords in the log generated by executing the first-level control file in the simulation folder, it further includes: constraining the system and setting an error flag. When an error occurs during the test stimulus process, the system stores the generated error flag in the corresponding log file and stores the log file in the simulation file.

5. The implementation method of efficient regression according to claim 4, characterized in that, When an error occurs during the monitoring traversal process and the simulation of the test stimulus is stopped, switching and loading the second-level control file includes: Using the excitation error monitoring program to view the log files in the simulation folder and query whether the error flag appears in the log files; If the error flag does not appear in the log file, it means that the simulation of the test stimulus has no error, and the current test stimulus simulation continues to be executed; If the error flag appears in the log file, it means that the simulation of the test stimulus has an error, switch and load the second-level control file, and re-perform the test stimulus simulation.

6. The implementation method of efficient regression according to claim 1, characterized in that Extracting the keywords in the log generated by executing the first-level control file in the simulation folder, analyzing the passing situation of the test stimulus corresponding to the execution of the first-level control file, and generating a first table for the test stimulus results to perform result status statistics includes: Using the excitation error monitoring program to extract all simulation folders corresponding to the log files generated by executing the first control file, and converting the log files into corresponding strings; among them, the strings converted from the log files with error flags correspond to the keywords; Analyze each log file converted into a corresponding string generated by executing the first control file in the simulation folder one by one. If the keyword appears, it means that an error has occurred during the test stimulus simulation process, and the test stimulus fails; if the keyword does not appear, it means that no error has occurred during the test stimulus simulation process, and the test stimulus passes, and the final simulation result is output to generate a first table.

7. An implementation device for efficient regression, characterized in that, It includes: At least one processor; At least one memory; Among them, the at least one processor and the at least one memory are communicatively connected to each other. The at least one memory stores instructions executable by the at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the implementation method of efficient regression as described in any one of claims 1-6.

8. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors to complete the implementation method of efficient regression as described in any one of claims 1-6.

Images