Improved memory performance during program pause protocol

Abstract

The present disclosure relates to improved memory performance during program suspend protocol. Systems and methods including a processing device operatively coupled to a memory device are disclosed. The processing device performs operations including receiving a sequence of read commands from a memory subsystem controller, retrieving first data by executing a first read command of a set of read commands, storing the first data in a first portion of a cache of the memory device, in response to determining that the memory device is in a suspend state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands, in response to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache, transferring the first data and the second data to the controller.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to improved memory performance during program pause protocols. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure relates to a system comprising: a memory device; and a processing means operably coupled to the memory device to perform operations including: receiving a sequence of read commands from a memory subsystem controller; retrieving first data by executing a first read command from a set of read commands; storing the first data in a first portion of a cache of the memory device; determining, in response to determining that the memory device is in a suspended state, whether a first address range specified by the first read command overlaps with a second address range specified by a second read command from the set of read commands; retrieving second data by executing a second read command and storing the second data in a second portion of the cache in response to determining that the first address range does not overlap with the second address range; and transmitting the first data and the second data to the memory subsystem controller.

[0004] Another aspect of this disclosure relates to a method comprising: receiving a first read command from a memory subsystem controller by a local media controller of a memory device; retrieving first data by executing the first read command; storing the first data in a first portion of a cache of the memory device; determining that the memory device is in a suspended state in response to receiving a second read command from the memory subsystem controller; retrieving second data by executing the second read command and storing the second data in a second portion of the cache in response to determining that a first address range specified by the first read command does not overlap with a second address range specified by the second read command; and transmitting the first data and the second data to the memory subsystem controller.

[0005] Another aspect of this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a memory device, perform operations including: receiving a sequence of read command commands from a memory subsystem controller; retrieving first data by executing a first read command from a set of read commands; storing the first data in a first portion of a cache of the memory device; determining, in response to determining that the memory device is in a suspended state, whether a first address range specified by the first read command overlaps with a second address range specified by a second read command from the set of read commands; retrieving second data by executing a second read command and storing the second data in a second portion of the cache in response to determining that the first address range does not overlap with the second address range; and transmitting the first data and the second data to the memory subsystem controller. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 A block diagram illustrating a memory subsystem that performs multiple read operations during a program pause protocol according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of an instance memory device method for performing multiple read operations during a program pause protocol according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of a memory subsystem controller method for performing multiple read operations during a program pause protocol according to some embodiments of the present disclosure.

[0011] Figure 5 This is an illustration of a page cache that receives data from multiple read operations according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to aspects of improved memory performance during program pause protocols. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0015] A memory device may comprise multiple memory cells arranged in a two-dimensional grid. The memory cells are etched onto a silicon wafer in the form of column (hereinafter also referred to as bit lines) and row (hereinafter also referred to as word lines) arrays. A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and may comprise a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device may include circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device may include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages on two or more memory planes containing different page types. For ease of description, these circuits may generally be referred to as independent plane driver circuitry. Depending on the memory architecture employed, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a segment of data (e.g., corresponding to one or more data addresses) can result in a read operation performed on two or more of the memory planes of the memory device.

[0016] A page cache (or buffer) is a block of circuitry comprising several memory elements and additional circuitry. Each page cache is coupled to a bit line and is used to latch data sensed from the memory array during a read operation and to store data to be programmed into the memory array (e.g., the page cache stores data read from the memory array or host data to be written to the memory array). The page cache includes static memory elements, such as a main data cache (PDC) and a secondary data cache (SDC). The PDC holds data used to maintain the bit line at a voltage level sufficient to shift a threshold voltage of a memory cell during programming, or to sense data from the bit line during a read operation. The SDC is a memory element accessible by the host system and used as a data read / write buffer. The PDC and SDC are independent of each other. The page cache may further include a sense amplifier to read data from memory cells and dynamic memory elements. The memory subsystem controller may move data from the PDC to the SDC to allow the data to be read by the host system, or move it to either of the dynamic memory elements for use in logical operations.

[0017] Memory access operations can be performed by the memory subsystem. Memory access operations can be initiated by the host or by the memory subsystem controller. For example, the host system can initiate memory access operations (e.g., write operations, read operations, erase operations, etc.) on the memory subsystem. The host system can send memory access commands (e.g., write commands, read commands) to the memory subsystem to, for example, store data on and read data from memory devices on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata for the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., expiration date for distinguishing written data), validity bitmap (whose LBA or logical transfer unit contains valid data), etc. The memory access operations initiated by the memory subsystem controller may involve maintenance operations, such as garbage collection, wear leveling, bad block management, and block refresh operations.

[0018] The memory subsystem can receive requests to perform memory access operations, such as a write operation to program data supplied by the host, and then, before the program operation is completed, receive requests to perform another memory access operation, such as a read operation to the same address. When the memory device of the memory subsystem (e.g., NAND flash memory) is programmed, the memory subsystem can hold the programmed data in controller memory (e.g., dynamic random access memory (DRAM)) and then flush the controller memory when the program operation is complete. A reasonably sized controller memory can accommodate the data to be programmed, provided the programming time (i.e., the time for performing the program operation on the memory device) is relatively short. However, if the memory device uses certain types of memory cells, such as three-level cell (TLC) or four-level cell (QLC), the programming time can increase significantly. Consequently, the command processing latency associated with subsequently received memory access operations increases significantly. If a subsequent request to perform a read operation is received while the program operation is still in progress, some memory subsystems will wait until the program operation is complete before performing the read operation on the memory device. This can lead to significant delays in responding to requests from the host system.

[0019] To reduce latency in mixed workloads (e.g., combinations of write and read operations, such as a read operation immediately following a write operation), some memory subsystems utilize program pause protocols to allow subsequently received memory access commands (e.g., read commands) to access the memory device on which a write operation is currently being performed. Program pause protocols can temporarily pause write operations to allow access to the memory array. Specifically, when the memory subsystem receives a request to perform a memory access operation on data stored in a specific page of the memory device while a write operation is in progress, the memory subsystem controller can issue a program pause command, which causes the memory device to enter a paused state.

[0020] In some memory subsystems, a pause protocol may require the memory device to fully process a read command before the memory subsystem processes subsequent read commands. For example, while paused, the memory device may receive a read command, retrieve the requested data from the memory array into a page cache (e.g., SDC), and transfer the retrieved host data from the page cache to the memory subsystem controller. Once the data has been transferred, the memory device can process subsequent read commands. However, when the memory device is paused, this process can increase latency when responding to multiple read commands from the host system, and thus adversely affect the quality of service provided by the memory subsystem. For example, while the page cache may have memory space to store data from multiple read commands (e.g., the page cache may contain 16 kilobytes (KiB) of pages, and the read command may request 4 or 8 KiB of data), the memory device must wait until each read command is fully processed before any subsequent read commands can be initialized.

[0021] The present disclosure addresses the above and other drawbacks by implementing a memory device capable of storing data from multiple read commands in a page cache when the memory device is in a suspended state. Specifically, the memory device receives a sequence of read commands from the memory subsystem controller. The read commands may request host data residing on the memory device. The memory device may initiate a read command in a set of read commands via the memory access component of the memory device. Specifically, using a physical address range corresponding to the logical address range specified by the initial read command, the memory access component may retrieve data from the memory array of the memory device. The memory access component may then cache the data in a portion of the page cache of the memory device. For example, data from a four-kiB read command may be stored in the first four-kiB portion of a 16-kiB page cache. Before transferring the data cached in the page cache (to the memory subsystem controller), the memory access component may determine whether the memory device is in a suspended state. In some embodiments, the memory access component may check whether the memory subsystem controller has issued a pause procedure command without issuing a subsequent resume procedure operation. In some embodiments, the memory access component may maintain an indicator (e.g., a bit flag) in a data structure to indicate the paused state of the memory device. If the memory device is not in a paused state, the memory access component may transfer cached data to the memory subsystem controller and initiate the next read command for the set.

[0022] If the memory device is in a suspended state, the memory access component can check whether the address range corresponding to the initial read command overlaps with the address range of the next read command in the sequence. If the address range of one read command overlaps with the address range of another read instruction, then the read command overlaps with the other read command. If the address ranges overlap, the memory access component can transfer the cached data to the memory subsystem controller and initiate the next read command for the set. When the address ranges do not overlap, the memory access component can initiate the next read command by retrieving the corresponding data from the memory array of the memory device. The memory access component can then cache the data in another portion of the page cache of the memory device. For example, an eight-kiB read command can be stored in the second four-kiB portion of a 16-kiB page cache. Thus, data is cached in the first 12 kiBs of the 16-kiB page cache space. The memory access component can retrieve data from the sequence of additional non-overlapping read commands until the page cache is full or there is insufficient memory space to cache data from any additional non-overlapping read commands. At this point, the memory device can transfer all data from the page cache to the memory subsystem controller in a single transfer operation.

[0023] The advantages of this disclosure include, but are not limited to, improved memory device performance and enhanced host system quality of service by caching data from multiple memory access commands in the page cache of the memory device and transferring the data in a single transfer operation. This allows the memory device to process multiple memory access commands without the latency incurred by immediately transferring data from each memory access command. In addition to the possibility of having sufficient latches to store the paused state of data from multiple read access commands, embodiments of this disclosure also enable the sharing of a single cache to store data from multiple reads. By reading data from two or more read commands into the SDC, the memory device avoids having to transfer data from the PDC to the SDC. In a memory subsystem where latch resources for storing data from multiple read access commands are lacking when the memory device is in a paused state (available latches can be used to store data from paused write operations), this disclosure enables the memory device to store read data from multiple read access commands. Furthermore, reading data into the same latch prevents the die from being idle in situations where the memory subsystem controller is busy performing operations on other dies and cannot easily roll out data. Therefore, embodiments of this disclosure reduce the amount of time a memory device can process multiple memory access commands, which reduces latency and improves the performance of the memory device.

[0024] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Memory subsystem 110 includes a memory interface component 113, which includes a memory access manager 114. The memory interface component 113 is responsible for handling interactions between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may send a memory access command corresponding to a request received from the host system 120 to the memory device 130, such as a write (program) command, a read command, an erase command, or other commands. Additionally, the memory interface component 113 may receive data from the memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a write (program) command. In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory access manager 114. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory interface component 113 is part of the host system 120, an application program, or an operating system. In one embodiment, memory interface component 113 includes memory access manager 114 and other sub-components. Memory access manager 114 can direct specific commands, including pause and resume commands, to memory device 130 to manage conflicts between different memory access operations. Conflicts may occur when pending memory access operations are being performed on specific data blocks, subblocks, and word lines of memory device 130, when a request to perform a subsequent memory access operation is received for the same data block, subblock, and word line. In response to such conflicts, memory access manager 114 can determine how to proceed. In some embodiments, memory access manager 114 can suspend pending memory access operations by issuing a specified pause command to memory device 130 and then issuing a request to perform a subsequent memory access operation while suspending the pending memory access operation.

[0042] In some embodiments, while pending memory access operations are performed on cells of a data block, subblock, and word line of memory device 130, memory interface 113 may receive additional memory access commands to perform multiple additional memory access operations on cells of the same data block, subblock, and word line. In such cases, memory access manager 114 may first determine whether the address range of one of the additional memory access commands overlaps with the address range of another of the additional memory access commands. In response to determining that the address ranges of at least two additional memory access commands overlap, memory access manager 114 may present the additional memory access commands to memory device 130 one at a time. For example, memory access manager 114 may present a first additional memory access command to memory device 130, receive host data associated with the first additional memory access command, then present a second additional memory access command to memory device 130, receive host data associated with the second additional memory access command, and so on. By issuing additional memory access commands one at a time, memory access manager 114 prevents read-overwrite operations in the page cache. In response to determining that the address ranges of additional memory access commands do not overlap (referred to herein as "non-overlapping memory access commands"), memory access manager 114 may collectively present the additional memory access commands to memory device 130. Memory device 130 may retrieve the host data associated with the additional memory access commands and store it in its page cache, and send the host data to memory interface 113 in a single transfer operation (e.g., timing output). Further details regarding the operation of memory access manager 114 are described below.

[0043] In one embodiment, memory device 130 includes a memory access component 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from memory access manager 114. In some embodiments, local media controller 135 includes at least a portion of memory access component 134 and is configured to perform the functionality described herein. In some embodiments, memory access component 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In some embodiments, memory access component 134 receives a request from a requesting party, such as memory access manager 114, to suspend the execution of an ongoing memory access operation (e.g., a TLC program operation) with a long operation time. In response, memory access component 134 may cause memory device 130 to enter a suspended state, wherein pending memory access operations are suspended during the suspended state. Memory access component 134 may further receive one or more requests to perform additional memory access operations (e.g., multiple read operations) while memory device 130 is in a suspended state. Memory access component 134 can initiate multiple additional memory access operations, notify memory access manager 114 upon completion of an additional memory access operation, and send a request to resume suspended memory access operations. Further details regarding the operation of memory access component 134 are described below.

[0044] Figure 2A block diagram 200 illustrates a memory subsystem that performs multiple memory access operations during a program pause protocol according to some embodiments of the present disclosure. In one embodiment, a memory interface 113 is operatively coupled to a memory device 130. In one embodiment, the memory device 130 includes a page cache 240 and a memory array 250. The memory array 250 may comprise an array of memory cells formed at the intersection of a word line and a bit line (not shown), for example, a word line 252. In one embodiment, the memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line of, for example, word line 252 is shared across several sub-blocks 254a, 254b, 254c, 254d. In one embodiment, each sub-block corresponds to a separate plane in the memory array 250. The group of memory cells associated with a word line within a sub-block is called a physical page. Each physical page in one of the sub-blocks may contain multiple page types. For example, a physical page formed by a single level cell (SLC) has a single page type called a lower logical page (LP). Multilevel cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types are LP, UP, and additional logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data different from the data stored in other logical pages associated with that physical page.

[0045] Depending on the programming scheme used, each logical page of the memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP can be programmed in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are also possible. However, in this example, before programming UP, XP, and TP in the second pass, data from LP is first read from the physical page in memory array 250, and the data can be stored in page cache 240 of memory device 130. Page cache 240 is a buffer for temporarily storing data read from or written to memory array 250 of memory device 130, and may include cache register 242 and one or more data registers 244 to 246. For a read operation, data is read from memory array 250 into one of data registers 244 to 246, and then into cache register 242. Memory interface 113 can then read data from cache register 242. For program operations, memory interface 113 writes data to cache register 242, which is then passed to one of data registers 244 to 246 and finally programmed into memory array 250. If the program operation involves multiple pages (e.g., UP, XP, and TP), each page may have a dedicated data register to hold the data for that page.

[0046] In some embodiments, the memory access manager 114 may send a request to pause a memory access operation (e.g., a pause command) to the memory device 130 while a memory access operation is currently being performed. The pause command may be received by the memory access component 134, which may put the memory device 130 into a paused state. In the paused state, an ongoing memory access operation performed on the memory array 250 (e.g., on word line 252 of the memory array 250) is paused. In one embodiment, the memory access component 134 stores process information associated with the paused memory access operation in a page cache 240. For example, in response to receiving a pause command, the memory access component 134 may store data already programmed into the memory array 250 in the page cache 240 (e.g., in one of data registers 244 to 246), where such data may be used to resume the paused memory access operation at a later time.

[0047] Once the original memory access operation is paused, the memory access manager 114 may send a request to perform two or more other memory access operations (e.g., multiple read operations on the memory array 250) while the memory device 130 is paused. The memory access component 134 may receive the request and initiate read operations on the memory array 250. Each of the two or more read access operations (or any other operations) may have a ready / busy signal to indicate the completion of each read access operation. After at least one of the read operations is completed, the memory access component 134 may provide a notification to the requesting party indicating that one or more of the read operations are completed. For example, the memory access component 134 may set the ready / busy signal to a level (e.g., a high voltage representing a logic "1") to indicate that the memory device 130 is ready to receive subsequent commands. The memory access component 134 may indicate when each individual read access operation or when a group of read access operations is completed.

[0048] In response, memory access manager 114 may send a request (e.g., a resume command) to memory device 130 to resume a previously suspended memory access operation. Memory access component 134 may receive the request, causing memory device 130 to exit the suspended state, and resume the original memory access operation to memory array 250 using process information from page cache 240. For example, memory access component 134 may read data previously written to page cache 240 of memory array 250 and compare the data with the data in the resume command to determine where the memory access operation stopped when suspended. Therefore, memory access component 134 may resume programming the data used for memory access operations to memory array 250 from that point.

[0049] Although memory device 130 is in a suspended state and in response to receiving two or more read commands, memory access component 134 or memory access manager 114 can determine whether the two or more memory access commands overlap. A memory access command overlaps with another memory access command when at least a portion of the address range of one memory access command overlaps with the address range of another memory access command. Non-overlapping memory access commands (e.g., read commands) may be on different word lines and / or memory pages in a plane. When two or more read operations overlap, memory access component 134 may process the read operations one at a time. Specifically, memory access component 134 may process the first read operation by retrieving host data associated with the first read command from memory array 250, caching the host data in page cache 240, transferring the host data from page cache 240 to memory subsystem controller 115, and then processing the next read command.

[0050] When two or more read commands do not overlap (e.g., their address ranges do not overlap), the memory access component 134 retrieves host data associated with each of the two or more read commands from the memory array 250 (depending on space cache limits), caches the host data in the page cache 240, and transfers the host data from the page cache 240 to the memory subsystem controller 115 in a single transfer operation.

[0051] In some embodiments, when the memory device 130 is not in a suspended state, the memory access component 134 may cache data from both of several non-overlapping read commands. Specifically, when the memory device is not in a suspended state and in response to receiving two or more read commands from the memory subsystem controller, the memory access component 134 may determine whether the two or more read commands overlap. In response to determining that the read commands do not overlap, the memory access component 134 may store the data associated with the read commands in the page cache 240 and transfer the data from the read commands to the memory subsystem controller 115 in a single transfer operation.

[0052] Figure 3 This is a flowchart illustrating an instance memory device method for performing multiple read operations during a program pause protocol according to some embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means) or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 and Figure 2 The memory access component 134 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] At operation 310, the processing logic receives a sequence of read commands from the memory subsystem controller. For example, the processing logic (e.g., memory access component 134) may receive multiple requests from memory access manager 114 to perform read operations on the memory array 250 of memory device 130. In some embodiments, memory access manager 114 sends a request to perform a memory access operation to memory device 130, the request being received by memory access component 134. In some embodiments, memory access manager 114 sends the request in response to a request received from other components, such as host system 120.

[0054] In operation 320, the processing logic processes an initial read command from the read command sequence. For example, the processing logic may initiate an initial read command on memory array 250. In one embodiment, memory access component 134 may apply one or more read reference voltages specified by the address range of the initial read command to the corresponding word line of memory array 250. The corresponding data read from memory array 250 may be stored in a portion of cache page 240. For example, page cache 240 may contain 16 KiB of memory pages, and the initial read command may request four KiB of data. Therefore, memory access component 134 may store the four KiB of data retrieved by the initial read command on a first portion (e.g., a first four KiB) of the 16 KiB memory page.

[0055] At operation 330, processing logic (e.g., memory access component 134) determines whether a memory device (e.g., memory device 130) is in a suspended state. In some embodiments, the processing logic may determine that the memory device 130 is in a suspended state based on a previous program pause command received from memory access manager 114, which requests the memory device 130 to enter a suspended state without a subsequent resume command. In some embodiments, the processing logic may maintain an indicator (e.g., a bit flag) in a data structure to indicate whether the memory device 130 is in a suspended state. For example, the flag may be set to 1 in response to the processing logic receiving a program pause command, and set to 0 in response to the processing logic receiving a program resume command. In response to memory access component 134 determining that the memory device 130 is not in a suspended state, the processing logic proceeds to operation 340. In response to determining that the memory device 130 is in a suspended state, the processing logic proceeds to operation 350.

[0056] At operation 340, the processing logic transfers data from page cache 240 to memory subsystem controller 115. For example, the processing logic may perform a data transfer operation. The processing logic may then process the next read command from the read command sequence.

[0057] At operation 350, the processing logic determines whether the next read command from the read command sequence overlaps with the initial read command. For example, the processing logic may determine whether the address range associated with the initial read command overlaps with the address range associated with the next read command. In response to determining that the read commands overlap, the processing logic proceeds to operation 340. In response to determining that the read commands do not overlap, the processing logic proceeds to operation 360.

[0058] At operation 360, the processing logic processes the next read command from the read command sequence. For example, the processing logic can initiate a next read command for memory array 250 by applying one or more read reference voltages specified by the address range of the next read command to the corresponding word line of memory array 250. The corresponding data read from memory array 250 can be stored in another portion of cache page 240. For example, the next read command may also request four KiB of data. Therefore, memory access component 134 can store the four KiB of data retrieved by the next read command in a second portion (e.g., a second four KiB) of a 16 KiB memory page.

[0059] The processing logic can repeat operation 350 for each additional read command in the read command sequence until the page cache 240 is full or there is no memory space to store another read command. At this point, the processing logic can transfer the data stored in the page cache 240 to the memory subsystem controller 115.

[0060] In some embodiments, the processing logic may receive a single read command and the corresponding data retrieved from the cache page cache. The processing logic may then receive another read command before transferring the cached data to the memory subsystem controller 115. In response, the processing logic may determine whether the memory device 130 is in a suspended state and whether the corresponding address ranges for each read command overlap. In response to determining that the read commands do not overlap, the processing logic may retrieve and cache data corresponding to the other read command from another portion of the page cache 240. The processing logic may then transfer the data from both read commands to the memory subsystem controller 115 in a single transfer operation.

[0061] Figure 4 This is a flowchart illustrating an instance controller method executed during a program pause protocol according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is executed by… Figure 1 and Figure 2 The memory access manager 114 executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 410, the processing logic receives a sequence of read commands from the host system. For example, the processing logic (e.g., memory access manager 114) may receive multiple requests from the host system 120 to perform read operations on the memory array of the memory device (e.g., memory array 250 of memory device 130).

[0063] At operation 420, the processing logic determines that the memory device (e.g., memory device 130) is in a suspended state. In some embodiments, the processing logic (e.g., memory access manager 114) may determine that the memory device 130 is in a suspended state based on the processing logic previously utilizing a program pause protocol and issuing a program pause command requesting the memory device 130 to enter a suspended state. For example, the memory access manager 114 may track whether a program pause command was previously issued and whether a subsequent program resume command was issued. When a program pause command is issued without a subsequent program resume command, the processing logic may determine that the memory device 130 is in a suspended state. In some embodiments, the processing logic may maintain a flag (e.g., a bit) indicating whether the memory device 130 is in a suspended state. For example, the flag may be set to 1 in response to the processing logic issuing a program pause command and set to 0 in response to the processing logic issuing a program resume command.

[0064] At operation 430, the processing logic determines whether the read commands overlap. For example, the processing logic may determine whether the address range specified by one read command overlaps with the address range specified by another read command. In response to determining that the read commands overlap, the processing logic proceeds to operation 440. In response to determining that the read commands do not overlap, the processing logic proceeds to operation 450.

[0065] At operation 440, the processing logic issues each read command (from the read command sequence) to the memory device one at a time. For example, memory access component 134 may issue a first read command from the read command sequence to memory device 130, receive host data corresponding to the address range of the first read command, then issue another read command from the read command sequence, and so on, until each read command from the sequence has been processed. For each read command, memory device 130 may retrieve the host data associated with the read command from memory array 250, cache the host data in page cache 240, and transfer the host data from page cache 240 to memory access component 134.

[0066] At operation 450, the processing logic collectively issues each read command (from the read command sequence) to the memory device. For example, memory access component 134 can issue each read command from the read command sequence to memory device 130 without needing to time output (transfer) data from memory device 130. For each received read command, memory device 130 (via memory access component 134).

[0067] For each read command, memory device 130 may retrieve data associated with the read command from memory array 250, cache the data in page cache 240, and transfer the data from page cache 240 to memory access component 134 in a single transfer operation.

[0068] Figure 5 This illustration shows a page cache 500 receiving data from multiple read operations according to some embodiments of the present disclosure. In some embodiments, page cache 500 may be similar to or the same as page cache 240. Page cache 500 may contain memory pages capable of caching 16 KiB of data. As illustrated, memory access component 134 may perform read operation A 510 to retrieve four KiB of data from a memory array (e.g., memory array 250) and store the four KiB of data at a first four KiB portion of page cache 500. Read operation B 512 may be a read command requesting four KiB of data from memory array 250. In response to the memory subsystem controller 115 (via memory access manager 114) or memory device 130 (via memory access component 134) determining that the memory range associated with read operation B 512 does not overlap with the memory range associated with read operation A 510, memory access component 134 may perform read operation B to retrieve four KiB of data from memory array 250 and store the four KiB of data in the second four KiB portion of page cache 500.

[0069] Read operation C 514 may be a read command that requests four KiB of data from memory array 250. In response to the memory subsystem controller 115 (via memory access manager 114) or memory device 130 (via memory access component 134) determining that the memory range associated with read operation C 514 does not overlap with the memory range associated with read operation A 510 or read operation B 512, memory access component 134 may execute read operation C to retrieve four KiB of data from memory array 250 and store the four KiB of data at the third four KiB portion of page cache 500. Read operation D 516 may be a read command that requests four KiB of data from memory array 250. In response to the memory subsystem controller 115 (via memory access manager 114) or memory device 130 (via memory access component 134) determining that the memory range associated with read operation D516 does not overlap with the memory range associated with read operation A510, read operation B512, or read operation C514, memory access component 134 may perform read operation D to retrieve four KiB of data from memory array 250 and store the four KiB of data in the last four KiB portion of page cache 500. Memory access component 134 may then transfer 16 KiB of data from page cache 240 to subsystem controller 115.

[0070] It should be noted that the size of read commands and page cache portions can vary. For example, a 16-KiB page cache can store four non-overlapping 4-KiB reads, two non-overlapping 8-KiB reads, two non-overlapping 4-KiB reads, and one non-overlapping 8-KiB read, etc. Similarly, 32-KiB or 64-KiB memory pages can store any combination of non-overlapping reads of different sizes.

[0071] Figure 6 An example machine illustrating computer system 600 is described, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120), which includes or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1The operation of memory access component 134 and / or memory access manager 114 (not shown). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0072] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions that will take a specified action by said machine. Furthermore, although a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0073] The example computer system 600 includes processing devices 602 communicating with each other via a bus 630, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618. Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 that communicates via a network 620.

[0074] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0075] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The machine-readable storage medium 624 contains functional instructions for the memory access component 134 and / or the memory access manager 114 (not shown). Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0076] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms described herein generally refer to a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical control over a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0077] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0078] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0080] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the invention without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a sequence of read commands from a memory subsystem controller; retrieving first data by executing a first read command of a set of read commands; storing the first data in a first portion of a cache of the memory device; in response to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps a second address range specified by a second read command of the set of read commands; in response to determining that the first address range does not overlap the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; and transmitting the first data and the second data to the memory subsystem controller.

2. The system of claim 1, wherein the processing device determines that the memory device is in the suspended state based on the memory device receiving a program suspend command.

3. The system of claim 1, wherein the processing device maintains a bit flag in a data structure indicating whether a memory device is in a suspended state.

4. The system of claim 1, wherein the processing device is to further perform operations comprising: in response to determining that the first address range overlaps the second address range, transmitting the first data to the memory subsystem controller.

5. The system of claim 1, wherein the cache comprises a page cache to temporarily store data being read from or written to a memory array of the memory device.

6. The system of claim 1, wherein transmitting the first data and the second data is performed in response to receiving a subsequent read command requesting data greater than a remaining unused portion of the cache.

7. The system of claim 1, wherein transmitting the first data and the second data is performed in response to the cache having no remaining unused portion.

8. A method comprising: receiving, by a local media controller of a memory device, a first read command from a memory subsystem controller; retrieving first data by executing the first read command; storing the first data in a first portion of a cache of the memory device; in response to receiving a second read command from the memory subsystem controller, determining that the memory device is in a suspended state; in response to determining that a first address range specified by the first read command does not overlap a second address range specified by the second read command, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; and transmitting the first data and the second data to the memory subsystem controller.

9. The method of claim 8, wherein the memory device is determined to be in the suspended state based on the memory device receiving a program suspend command. ​ ​ 10. The method of claim 8, further comprising: maintaining, in a data structure, a bit flag indicating whether a memory device is in a suspended state.

11. The method of claim 8, further comprising: in response to determining that the first address range overlaps the second address range, transferring the first data to the memory sub-system controller.

12. The method of claim 8, wherein the cache comprises a page cache to temporarily store data being read from or written to a memory array of the memory device.

13. The method of claim 8, wherein transferring the first data and the second data is performed in response to receiving a subsequent read command requesting data that is greater than a remaining unused portion of the cache.

14. The method of claim 8, wherein transferring the first data and the second data is performed in response to the cache having no remaining unused portion.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory device, perform operations comprising: receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of a set of read commands; storing the first data in a first portion of a cache of the memory device; in response to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps a second address range specified by a second read command of the set of read commands; in response to determining that the first address range does not overlap the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; and transferring the first data and the second data to the memory sub-system controller.

16. The non-transitory computer-readable storage medium of claim 15, wherein the processing device determines that the memory device is in the suspended state based on the memory device receiving a program suspend command.

17. The non-transitory computer-readable storage medium of claim 15, wherein the processing device maintains, in a data structure, a bit flag indicating whether a memory device is in a suspended state.

18. The non-transitory computer-readable storage medium of claim 15, wherein the processing device will further perform operations comprising: in response to determining that the first address range overlaps the second address range, transferring the first data to the memory sub-system controller.

19. The non-transitory computer-readable storage medium of claim 15, wherein transferring the first data and the second data is performed in response to at least one of receiving a subsequent read command requesting data that is greater than a remaining unused portion of the cache or the cache having no remaining unused portion.

20. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is to further perform operations comprising: in response to determining that the memory device is not in the suspend state, determining that the first address range does not overlap with the second address range; and retrieving second data by executing the second read command and storing the second data in a second portion of the cache.

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