Layout map repairing method and device, computer device and storage medium
By forming a power fill grid on the semiconductor integrated circuit layout, the problems of increased resistance and voltage drop in semiconductor devices are solved, achieving the effects of reducing power consumption and improving performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-09-02
- Publication Date
- 2026-06-26
AI Technical Summary
As the integration of semiconductor devices increases, the narrowing of conductive lines leads to an increase in resistance, which in turn increases the voltage drop across the chip, affecting switching speed and device reliability.
A power fill grid is formed on the initial layout of the semiconductor integrated circuit, including slots that overlap with metal interconnects. If the area of the slot portion is less than the lower limit of the threshold, the area of that portion is increased to form a repaired layout.
By increasing the width of metal interconnects, the resistance value is reduced, power consumption is lowered, device performance and reliability are improved, physical verification errors are avoided, and the work efficiency of layout engineers is increased.
Smart Images
Figure CN115758986B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus, computer equipment, and storage medium for repairing layout patterns. Background Technology
[0002] With the rapid development of integrated circuit technology, the requirements for the integration level of semiconductor products are becoming increasingly higher. As semiconductor products become more integrated, the size of individual semiconductor devices needs to be smaller and smaller, and the width of individual conductive lines in semiconductor devices needs to be smaller and smaller, resulting in an increase in the resistance of the conductive lines; at the same time, the power supply voltage of the chip is constantly decreasing, causing the voltage drop effect of the chip to become more and more obvious.
[0003] However, a severe voltage drop effect can slow down the switching speed of semiconductor switches, increase the power consumption of semiconductor devices, and affect the overall performance and reliability of semiconductor devices. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, and storage medium for repairing the layout of semiconductor devices that can effectively reduce the voltage drop effect, so as to reduce the power consumption of the semiconductor devices and improve the overall performance and reliability of the semiconductor devices.
[0005] To achieve the above and other related objectives, the first aspect of this application provides a method for repairing a layout, comprising:
[0006] Obtain an initial layout pattern of a semiconductor integrated circuit, wherein metal interconnects are formed on the initial layout pattern;
[0007] A power fill grid is formed on the initial layout, the power fill grid including slots that overlap with the orthographic projection of the metal interconnect on the power fill grid, the slots including a first portion that overlaps with the metal interconnect and at least one second portion that is offset from the metal interconnect;
[0008] If the area of the second part is less than the lower limit of the threshold, then the area of the second part is increased to form the repaired layout.
[0009] In one embodiment, increasing the area of the second portion if its area is less than a lower threshold includes:
[0010] The area of each of the second parts is obtained in real time;
[0011] Based on the area of each of the second portions, the second portions with an area smaller than the lower threshold are obtained;
[0012] On the initial layout, trim the second portions whose area is smaller than the lower threshold limit until the area of each second portion is greater than the lower threshold limit.
[0013] In one embodiment, the step of trimming the second portion whose area is less than the lower threshold on the initial layout includes: iteratively trimming the second portion whose area is less than the lower threshold, wherein the area of the second portion is increased by a preset area after each trimming.
[0014] In one embodiment, before trimming the second portion whose area is less than the lower threshold on the initial layout, the method further includes: determining the trimming direction of the second portion to be trimmed based on the initial layout after forming the power fill grid;
[0015] Based on the trimming direction, the second portion of the initial layout where the trimming area is less than the lower threshold limit is trimmed.
[0016] In one embodiment, the trimming direction includes a direction away from the metal wire adjacent to the second portion and / or a direction parallel to the extension direction of the metal wire.
[0017] In one embodiment, in the repaired layout, at least one of the slots includes two second portions located on opposite sides of a metal interconnect.
[0018] In one embodiment, the layout pattern repair method further includes:
[0019] If the area of the second part is less than the lower limit of the threshold, an alarm message is output.
[0020] In one embodiment, the metal interconnect includes a power metal interconnect and a signal metal interconnect, wherein a portion of the power filling grid overlaps with the power metal interconnect and there is a predetermined distance between the power filling grid and the signal metal interconnect.
[0021] A second aspect of this application provides a layout pattern repair apparatus, including an acquisition module, a filling module, and a correction module. The acquisition module is used to acquire an initial layout pattern of a semiconductor integrated circuit, wherein metal interconnects are formed on the initial layout pattern. The filling module is used to form a power fill grid on the initial layout pattern, wherein the power fill grid includes slots that overlap with the orthographic projection of the metal interconnects on the power fill grid, and the slots include a first portion overlapping the metal interconnects and at least one second portion offset from the metal interconnects. The correction module is used to increase the area of the second portion if the area of the second portion is less than a lower threshold limit, so as to form a repaired layout pattern.
[0022] In one embodiment, the correction module includes an area acquisition unit, a judgment unit, and a trimming unit. The area acquisition unit is used to acquire the area of each second part in real time. The judgment unit is used to determine the second part whose area is less than the lower threshold based on the area of each second part. The trimming unit is used to trim the second part whose area is less than the lower threshold on the initial layout until the area of each second part is greater than the lower threshold.
[0023] In one embodiment, the trimming unit iteratively trims the second part whose area is less than the lower threshold, and the area of the second part increases by a preset area after each trimming.
[0024] In one embodiment, the correction module further includes a trimming direction determination unit, which is used to determine the trimming direction of the second part to be trimmed based on the initial layout after forming the power fill grid;
[0025] The trimming unit trims the corresponding second part based on the trimming direction.
[0026] In one embodiment, the layout repair device further includes an alarm module, which outputs alarm information when the area of the second part is less than the lower threshold.
[0027] In one embodiment, the metal interconnect includes a power metal interconnect and a signal metal interconnect, wherein a portion of the power filling grid overlaps with the power metal interconnect and there is a predetermined distance between the power filling grid and the signal metal interconnect.
[0028] A third aspect of this application provides a computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in any of the preceding claims.
[0029] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.
[0030] In the aforementioned layout repair method, apparatus, computer equipment, and storage medium, a power fill grid with a first slot is formed on the initial layout of the semiconductor integrated circuit. The power fill grid includes slots that overlap with the orthographic projection of the metal interconnects onto the power fill grid. Each slot includes a first portion overlapping the metal interconnects and at least one second portion offset from the metal interconnects. This utilizes the power fill grid to increase the width of the metal interconnects, thereby effectively reducing the resistance of the metal interconnects, lowering the power consumption of the manufactured semiconductor device, and improving the overall performance and reliability of the manufactured semiconductor device. Since the power fill grid at least partially overlaps with the metal interconnects on the initial layout, the overlapping area forms an equivalent capacitance, increasing the number of electrons stored in the power fill grid and improving the electron mobility on the power fill grid, further reducing the voltage drop effect. This embodiment can obtain the area of the second portion in real time. If the area of the second portion is less than a lower threshold, the area of the second portion is increased to form a repaired layout, avoiding physical verification errors caused by the existence of a second portion with an area less than or equal to the minimum area of a hole on the metal interconnect. The fully automated layout repair process effectively improves the work efficiency of layout engineers and avoids errors in manual operation. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a flowchart illustrating a layout pattern repair method provided in one embodiment of this application;
[0033] Figure 2 A flowchart illustrating a layout pattern repair method provided in another embodiment of this application;
[0034] Figure 3 This is a top view of the initial layout obtained in step S110 of one embodiment of this application;
[0035] Figure 4a This is a top view schematic diagram of the layout obtained in step S120 in one embodiment of this application;
[0036] Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 5 This is a top view schematic diagram of the layout obtained in step S130 in different embodiments of this application;
[0037] Figure 6 This is a structural block diagram of a layout repair device provided in one embodiment of this application;
[0038] Figure 7 This is a structural block diagram of a layout repair device provided in another embodiment of this application;
[0039] Figure 8 This is a structural block diagram of a layout repair device provided in another embodiment of this application;
[0040] Figure 9 This is a structural block diagram of a layout pattern repair device provided in another embodiment of this application;
[0041] Explanation of reference numerals in the attached figures:
[0042] 10. Initial layout; 11. Metal wiring; 111. Power metal wiring; 112. Signal metal wiring; 12. Power fill grid; 120. Slot; 121. First part; 122. Second part; 30. Layout repair device; 31. Acquisition module; 32. Filling module; 33. Correction module; 331. Area acquisition unit; 332. Judgment unit; 333. Trimming unit; 334. Trimming direction determination unit; 34. Alarm module. Detailed Implementation
[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0048] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0049] Please note that the object area mentioned in this application refers to the area of the orthographic projection onto the upper surface of the initial layout. In this application embodiment, "overlapping" of the slot and metal connection means that the orthographic projection of the metal connection onto the upper surface of the power fill grid overlaps with the orthographic projection of the slot onto the upper surface of the power fill grid; in this application embodiment, "misaligned" of the slot and metal connection means that the orthographic projection of the metal connection onto the upper surface of the power fill grid is misaligned with the orthographic projection of the slot onto the upper surface of the power fill grid.
[0050] Please see Figure 1 This application provides a method for repairing a layout, comprising the following steps:
[0051] Step S110: Obtain the initial layout of the semiconductor integrated circuit, wherein metal interconnects are formed on the initial layout.
[0052] Step S120: A power fill grid is formed on the initial layout. The power fill grid includes slots that overlap with the orthographic projection of the metal interconnect on the power fill grid. The slots include a first portion that overlaps with the metal interconnect and at least one second portion that is offset from the metal interconnect.
[0053] Step S130: If the area of the second part is less than the lower limit of the threshold, then increase the area of the second part to form the repaired layout.
[0054] Specifically, a power fill grid with a first slot is formed on the initial layout of a semiconductor integrated circuit. The power fill grid includes slots that overlap with the orthographic projection of the metal interconnects onto the power fill grid. Each slot includes a first portion overlapping the metal interconnect and at least one second portion offset from the metal interconnect. This power fill grid increases the width of the metal interconnects, effectively reducing their resistance. Since the power fill grid at least partially overlaps with the metal interconnects on the initial layout, the overlapping area forms an equivalent capacitance, increasing the number of electrons stored in the power fill grid and improving electron mobility. This further reduces voltage drop, lowers the power consumption of the manufactured semiconductor device, and improves the overall performance and reliability of the manufactured semiconductor device. This embodiment can obtain the area of the second portion in real time. If the area of the second portion is less than a lower threshold, the area of the second portion is increased to form a repaired layout, avoiding physical verification errors caused by the existence of a second portion with an area less than or equal to the minimum area of a hole on the metal interconnect. The fully automated layout repair process effectively improves the work efficiency of layout engineers and avoids errors during manual operation.
[0055] Further, please refer to Figure 2 In one embodiment of this application, step S130 includes:
[0056] Step S131: Obtain the area of each of the second parts in real time;
[0057] Step S132: Based on the area of each second part, obtain the second part whose area is less than the lower threshold limit;
[0058] Step S133: Trim the second portions with areas smaller than the lower threshold on the initial layout until the area of each second portion is greater than the lower threshold.
[0059] Specifically, in the initial layout, metal interconnects typically use metal mesh lines to reduce their impedance and minimize noise interference in transmitted signals. However, a power fill mesh is added to the initial layout. The initial layout includes both power and signal metal interconnects, electrically connected to the power metal interconnects. The power fill mesh includes slots that overlap with the orthographic projections of the metal interconnects onto its plane. Each slot includes a first portion overlapping the orthographic projection of the metal interconnect onto its plane and at least one second portion offset from the orthographic projection of the metal interconnect onto its plane. A predetermined distance exists between the power fill mesh and the signal metal interconnect. If the area of the second portion is smaller than the minimum area of a hole on the metal interconnect in the initial layout, it leads to physical verification errors and affects the subsequent fabrication of the metal interconnect mask. This application obtains the area of all second portions on the initial layout of a semiconductor integrated circuit in real time. Based on the area of each second portion, it identifies all second portions with areas smaller than a lower threshold. This process trims second portions with areas smaller than the lower threshold on the initial layout until the area of all second portions on the initial layout is greater than the lower threshold. The lower threshold is greater than or equal to the minimum area of holes on metal interconnects on the initial layout. This avoids physical verification errors caused by the existence of second portions with areas smaller than or equal to the minimum area of holes on metal interconnects, thereby improving the quality of subsequent metal interconnect mask manufacturing.
[0060] For further information, please refer to [link / reference]. Figure 2In one embodiment of this application, step S133, which involves trimming the second portion with an area smaller than the lower threshold on the initial layout, includes iteratively trimming the second portion with an area smaller than the lower threshold, increasing the area of the second portion by a preset area after each trimming. The trimming direction of the second portion to be trimmed can be determined to include directions away from the metal interconnects adjacent to the second portion and / or directions parallel to the extension direction of the metal interconnects. Then, the corresponding second portion is trimmed based on the determined trimming direction, avoiding the trimming of some metal interconnects during the process of trimming the power fill mesh to increase the area of the trimmed second portion. By iteratively trimming all second portions with areas less than or equal to the lower threshold on the initial layout, in each trimming process, second portions with areas greater than the lower threshold are not trimmed, and the area of the trimmed second portions is increased by a preset area. After several iterations of trimming, the area of all second portions on the initial layout is greater than the lower threshold. In the repaired layout, at least one slot includes two second portions located on opposite sides of a metal interconnect. This avoids physical verification errors caused by the existence of second portions with areas less than or equal to the minimum area of holes on the metal interconnect, and ensures that there are enough power fill grids left on the trimmed layout, reducing the power consumption of the manufactured semiconductor device and improving the overall performance and reliability of the manufactured semiconductor device.
[0061] As an example, in step S110, please refer to Figure 1 Step S110 in the middle and Figure 3 An initial layout pattern 10 of a semiconductor integrated circuit is obtained, on which metal interconnects 11 are formed. The metal interconnects 11 may include power metal interconnects 111 and signal metal interconnects 112. A portion of the power filling grid (not shown) overlaps with the power metal interconnects 111, and there is a preset distance between the power filling grid and the signal metal interconnects 112.
[0062] Further, in step S120, please refer to Figure 1 Step S120 in the middle and Figure 4aSince the metal interconnects 11 on the initial layout 10 generally use metal mesh lines to reduce the impedance of the metal interconnects 11 and reduce noise interference in the transmitted electrical signals, after adding a power fill mesh to the initial layout 10, the power fill mesh 12 is located above and electrically connected to the power metal interconnects 111, thereby reducing the resistance of the power metal interconnects 111 and reducing signal attenuation on the power metal interconnects 111. The power fill mesh 12 includes a slot 120 that overlaps with the orthographic projection of the power metal interconnects 111 on the power fill mesh 12. The slot 120 includes a first portion 121 that overlaps with the power metal interconnects 111 and at least one second portion 122 that is offset from the power metal interconnects 111. If the area of the second portion 122 is less than a lower threshold, it will cause a physical verification error and affect the subsequent fabrication of the metal interconnect mask.
[0063] Further, in step S130, please refer to Figure 1 Step S130 in the middle Figure 4b , Figure 4c and Figure 4d This application obtains the area of all second portions 122 on the initial layout 10 of the semiconductor integrated circuit in real time. Based on the area of each second portion 122, it identifies all second portions 122 with areas smaller than a lower threshold. This process trims the second portions 122 with areas smaller than the lower threshold on the initial layout 10 until the area of all second portions 122 on the initial layout 10 is greater than the lower threshold. The lower threshold is greater than or equal to the minimum area of holes on the metal interconnects on the initial layout 10. This avoids physical verification errors caused by the existence of second portions 122 with areas smaller than the minimum area of holes on the metal interconnects, thus improving the quality of subsequent metal interconnect mask manufacturing. The trimming direction of the second portions 122 to be trimmed can be determined to include directions away from the metal interconnects 11 adjacent to the second portions 122 and / or directions parallel to the extension direction of the metal interconnects 11. For example, Figure 4b The oy direction shown Figure 4c The ox direction shown and Figure 4d The oz direction shown indicates that the second portion 122 to be trimmed is trimmed based on the determined trimming direction, avoiding the trimming of part of the power metal interconnect 111 during the process of trimming the power fill mesh 12 to increase the area of the trimmed second portion 122. Please note that Figure 4b , Figure 4c and Figure 4d The pruning directions shown are intended to illustrate the implementation principle of this application, and all pruning directions under this implementation principle should fall within the protection scope of this application.
[0064] As an example, in step S130, please refer to... Figure 1 Step S130 in the middle Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 5 By iteratively trimming all second portions 122 on the initial layout 10 whose area is less than or equal to the lower threshold, in each trimming process, second portions 122 with an area greater than the lower threshold are not trimmed, and the area of each trimmed second portion 122 is increased by a preset area. After several iterations of this trimming, the area of all second portions 122 on the initial layout 10 is made greater than the lower threshold. For example, if Figure 4a The area of the second part 122 of row R1 is S1, and the area of the second part 122 of row R2 is S2. Both S1 and S2 are less than or equal to the lower threshold, and the lower threshold is greater than or equal to the minimum area of the hole on the metal interconnect 11 on the initial layout 10. This can be used for... Figure 4a The second part 122 of row R1 with area S1 and the second part 122 of row R2 with area S2 are both trimmed along any one of the ox, oy, or oz directions, such that the area of the trimmed second part 122 of row R1 increases by a preset area to S3 and the area of the trimmed second part 122 of row R2 increases by a preset area to S4, where S4 is greater than the lower threshold and S3 is less than or equal to the lower threshold. Figure 4c Taking the trimmed layout as an example, we will continue to analyze... Figure 4c The area of row R1 in S3 is the second part 122 according to Figure 5 The oy direction shown is trimmed, and no trimming is performed. Figure 4c The area of row R2 in S4 is 122, which makes... Figure 4c The area of row R1 in the equation is the second part of S3, 122. After trimming, the area is increased by the preset area to S5, resulting in the following: Figure 5 In the layout shown, the area S4 of the second portion 122 in row R2 and the area S5 of the second portion 122 in row R1 are both greater than the lower threshold. In the repaired layout, at least one slot 120 includes two second portions 122 located on opposite sides of a metal interconnect 11, avoiding physical verification errors caused by the existence of second portions 122 with areas smaller than the minimum area of holes on the metal interconnect, and ensuring that sufficient power fill grids 12 remain on the trimmed layout.
[0065] Further, please refer to Figure 6In one embodiment of this application, a layout pattern repair device 30 is provided, including an acquisition module 31, a filling module 32, and a correction module 33. The acquisition module 31 is used to acquire an initial layout pattern 10 of a semiconductor integrated circuit, on which metal interconnects are formed. The filling module 32 is used to form a power fill grid 12 on the initial layout pattern 10. The power fill grid 12 includes slots 120 that overlap with the orthographic projection of the metal interconnects 11 on the power fill grid 12. The slots 120 include a first portion 121 that overlaps with the metal interconnects 11 and at least one second portion 122 that is offset from the metal interconnects 11. The correction module 33 is used to increase the area of the second portion 122 if the area of the second portion 122 is less than a lower threshold limit, so as to form a repaired layout pattern.
[0066] Further, please refer to Figure 7 In one embodiment of this application, the correction module 33 includes an area acquisition unit 331, a judgment unit 332, and a trimming unit 333. The area acquisition unit 331 is used to acquire the area of each second part 122 in real time; the judgment unit 332 is used to obtain the second part 122 with an area less than the lower threshold based on the area of each second part 122; the trimming unit 333 is used to trim the second part 122 with an area less than the lower threshold on the initial layout 10 until the area of each second part 122 is greater than the lower threshold.
[0067] As an example, please continue reading Figure 7 The trimming unit 333 iteratively trims the second part 122 whose area is less than the lower limit of the threshold, and the area of the second part 122 increases by a preset area after each trimming.
[0068] Further, please refer to Figure 8 In one embodiment of this application, the correction module 33 further includes a trimming direction determination unit 334, which is used to determine the trimming direction of the second part 122 to be trimmed based on the initial layout 10 after the power filling grid 12 is formed; the trimming unit 333 trims the corresponding second part 122 to be trimmed based on the trimming direction.
[0069] Since the metal interconnects 11 on the initial layout 10 generally use metal mesh lines to reduce the impedance value of the metal interconnects 11 and reduce noise interference in the transmitted electrical signals, metal interconnects 11 are formed on the initial layout 10. The metal interconnects 11 may include power metal interconnects 111 and signal metal interconnects 112. However, after the fill module 32 adds a power fill mesh on the initial layout 10, the power fill mesh 12 includes slots 120 that overlap with the orthographic projection of the metal interconnects 11 on the power fill mesh 12. The slots 120 include a first portion 121 that overlaps with the metal interconnects 11 and at least one second portion 122 that is offset from the metal interconnects 11. If the area of the second portion 122 is smaller than the minimum area of the hole on the metal interconnect on the initial layout, it will cause a physical verification error and affect the subsequent manufacturing of the metal interconnect mask. This application uses a correction module 33 to obtain the area of all second portions 122 on the initial layout 10 of the semiconductor integrated circuit in real time. Based on the area of each second portion 122, it identifies all second portions 122 with areas smaller than a lower threshold. This process trims the second portions 122 with areas smaller than the lower threshold on the initial layout 10 until the area of all second portions 122 on the initial layout 10 is greater than the lower threshold. The lower threshold is greater than or equal to the minimum area of holes on the metal interconnects on the initial layout 10. This avoids physical verification errors caused by the existence of second portions 122 with areas smaller than the minimum area of holes on the metal interconnects, thus improving the quality of subsequent metal interconnect mask manufacturing. The trimming direction of the second portions 122 to be trimmed can be determined by the trimming direction determination unit 334, including directions away from the metal interconnects 11 adjacent to the second portions 122 and / or directions parallel to the extension direction of the metal interconnects 11. For example... Figure 4b The oy direction shown Figure 4c The ox direction shown or Figure 4d The oz direction shown indicates that the second portion 122 that needs to be trimmed is trimmed based on the determined trimming direction, avoiding the trimming of some metal interconnects during the process of trimming the power fill mesh 12 to increase the area of the trimmed second portion 122. Please note that Figure 4b , Figure 4c and Figure 4d The pruning directions shown are intended to illustrate the implementation principle of this application, and all pruning directions under this implementation principle should fall within the protection scope of this application.
[0070] Further, please refer to Figure 9 In one embodiment of this application, the layout repair device 30 further includes an alarm module 34, which is used to output alarm information when the area of the second part 122 is less than the lower threshold, so as to promptly remind relevant personnel that there is a second part 122 that needs to be trimmed.
[0071] Furthermore, in one embodiment of this application, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.
[0072] Furthermore, in one embodiment of this application, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the above embodiments.
[0073] In the aforementioned layout repair method, apparatus, computer equipment, and storage medium, a power fill grid with a first slot is formed on the initial layout of the semiconductor integrated circuit. The power fill grid includes slots that overlap with the orthographic projection of metal interconnects onto the power fill grid. Each slot includes a first portion overlapping the metal interconnect and at least one second portion offset from the metal interconnect. This utilizes the power fill grid to increase the width of the metal interconnect, thereby effectively reducing the resistance value of the metal interconnect. Since the power fill grid at least partially overlaps with the metal interconnect on the initial layout, the overlapping area forms an equivalent capacitance, increasing the number of electrons stored in the power fill grid and improving the electron mobility on the power fill grid, further reducing the voltage drop effect. This embodiment can obtain the area of the second portion in real time. If the area of the second portion is less than a lower threshold, the area of the second portion is increased to form a repaired layout. This avoids physical verification errors caused by the existence of a second portion with an area smaller than the minimum area of a hole on a metal interconnect, reducing the power consumption of the manufactured semiconductor device and improving the overall performance and reliability of the manufactured semiconductor device. The fully automated layout repair process effectively improves the work efficiency of layout engineers and avoids errors in manual operation.
[0074] It should be understood that, although Figure 1 , Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0075] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.
[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0077] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for repairing a layout diagram, characterized in that, include: Obtain an initial layout pattern of a semiconductor integrated circuit, wherein metal interconnects are formed on the initial layout pattern; A power fill grid is formed on the initial layout, the power fill grid including slots that overlap with the orthographic projection of the metal interconnect on the power fill grid, the slots including a first portion that overlaps with the metal interconnect and at least one second portion that is offset from the metal interconnect; If the area of the second part is less than the lower threshold, the area of the second part is increased to form a repaired layout; wherein the lower threshold is greater than or equal to the minimum area of the hole on the metal connection.
2. The method for repairing the layout according to claim 1, characterized in that, The step of increasing the area of the second part if its area is less than the lower threshold includes: The area of each of the second parts is obtained in real time; Based on the area of each of the second portions, the second portions with an area smaller than the lower threshold are obtained; On the initial layout, trim the second portions whose area is smaller than the lower threshold limit until the area of each second portion is greater than the lower threshold limit.
3. The layout repair method according to claim 2, characterized in that, The step of trimming the second part whose area is less than the lower threshold on the initial layout includes: iteratively trimming the second part whose area is less than the lower threshold, and increasing the area of the second part by a preset area after each trimming.
4. The method for repairing the layout according to claim 2 or 3, characterized in that, Before trimming the second portion whose area is less than the lower threshold on the initial layout, the method further includes: determining the trimming direction of the second portion to be trimmed based on the initial layout after forming the power fill grid; Based on the trimming direction, the second portion of the initial layout where the trimming area is less than the lower threshold limit is trimmed.
5. The layout repair method according to claim 4, characterized in that, The trimming direction includes a direction away from the metal connection adjacent to the second portion and / or a direction parallel to the extension direction of the metal connection.
6. The layout repair method according to claim 4, characterized in that, In the repaired layout, at least one of the slots includes two second portions located on opposite sides of a metal line perpendicular to its extension direction.
7. The method for repairing a layout according to any one of claims 1-3, characterized in that, Also includes: If the area of the second part is less than the lower limit of the threshold, an alarm message is output.
8. The method for repairing a layout according to any one of claims 1-3, characterized in that, The metal interconnects include power metal interconnects and signal metal interconnects. A portion of the power filling grid overlaps with the power metal interconnects, and there is a preset distance between the power filling grid and the signal metal interconnects.
9. A layout pattern repair device, characterized in that, include: An acquisition module is used to acquire an initial layout pattern of a semiconductor integrated circuit, wherein metal interconnects are formed on the initial layout pattern; A fill module is used to form a power fill grid on the initial layout, the power fill grid including slots that overlap with the orthographic projection of the metal interconnects on the power fill grid, the slots including a first portion that overlaps with the metal interconnects and at least one second portion that is offset from the metal interconnects; The correction module is used to increase the area of the second part if the area of the second part is less than the lower threshold limit, so as to form a repaired layout; wherein the lower threshold limit is greater than or equal to the minimum area of the hole on the metal interconnect.
10. The layout repair apparatus according to claim 9, characterized in that, The correction module includes: An area acquisition unit is used to acquire the area of each of the second parts in real time; The judgment unit is used to determine the second part whose area is less than the lower threshold based on the area of each second part; A trimming unit is used to trim the second portion with an area smaller than the lower threshold on the initial layout, until the area of each second portion is greater than the lower threshold.
11. The layout repair apparatus according to claim 10, characterized in that, The trimming unit iteratively trims the second part whose area is less than the lower threshold limit, and the area of the second part increases by a preset area after each trimming.
12. The layout repair apparatus according to claim 10 or 11, characterized in that, The correction module further includes a trimming direction determination unit, which is used to determine the trimming direction of the second part that needs to be trimmed based on the initial layout pattern after the power filling grid is formed; The trimming unit trims the corresponding second part based on the trimming direction.
13. The layout repair apparatus according to any one of claims 9-11, characterized in that, Also includes: An alarm module is used to output alarm information when the area of the second part is less than the lower limit of the threshold.
14. The layout repair apparatus according to any one of claims 9-11, characterized in that, The metal interconnects include power metal interconnects and signal metal interconnects. A portion of the power filling grid overlaps with the power metal interconnects, and there is a preset distance between the power filling grid and the signal metal interconnects.
15. A layout repair tool, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.
16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.