A method for compensating a channel pair for an in-plane offset of a differential via

Abstract

The application discloses a method for compensating internal skew of a differential via channel, comprising the steps of: calculating skew time between differential signals; using obtained material parameters to establish a model of a PCB and a differential via; simulating the established high-precision differential model to obtain S parameters of the differential via structure through simulation; obtaining S parameters and differential internal skew values of a design measurement to calibrate a scale factor of 3D modeling; optimizing stub length difference h in the differential via structure; comparing whether the optimization result meets a design allowed differential internal skew target value, if yes, optimization is completed, and if not, stub length difference h is continuously optimized. The application occupies small layout and wiring space, and the proposed differential via structure compensates for skew of differential phase in time, effectively avoiding the influence of internal skew.

Description

Technical Field

[0001] This invention belongs to the field of printed circuit board technology, and particularly relates to a method for compensating for channel offset using differential vias. Background Technology

[0002] With the continuous advancement of modern information processing technology and increasing demands, as well as the growing popularity of technologies such as big data, cloud computing, and the Internet of Things, the demand for ultra-high-speed and high-bandwidth communication products is becoming increasingly strong. The widespread application of differential lines in PCB design, and the rational optimization of differential signal integrity, have become crucial to the success of modern system design. Differential signals involve the driver sending two equal but opposite signals, and the receiver determining the logic state ("0" or "1") by comparing the difference between these two voltages. The pair of PCB traces carrying the differential signals is called a differential trace.

[0003] Intra-pair skew is a crucial factor affecting the quality of differential signals. The JEDEC standard defines logic device skew as "the time difference between two events that should occur simultaneously." Intra-pair skew is the difference in delay between the positive and negative terminals of a differential pair. Differential signals arrive at their terminals at different times after being transmitted through differential lines on the PCB, resulting in a delay difference that affects signal quality.

[0004] The shrinking size of PCB boards and the reduction in chip packaging, coupled with increased system complexity, have led to a sharp decrease in PCB routing space, placing higher demands on differential pair in-line offset compensation methods. Existing differential pair in-line offset design methods, regardless of whether the bulge is large or small, consume a lot of design space and are prone to introducing impedance abrupt changes, making it difficult to guarantee signal quality.

[0005] There are many reasons for differential pair misalignment, such as right-angle routing, BGA pin design limitations, driver rise and fall time mismatch, and fiber optic effects. In particular, BGA pin design limitations make it unavoidable during the routing of PCB differential signal lines. The quantification unit for PCB differential pair misalignment is time. In the design process, this time is combined with the signal propagation speed on the PCB channel to determine the length that needs to be compensated, and then the length deviation of the in-pair is compensated using wire routing.

[0006] In existing technologies, methods for compensating for differential via channel offset require compensating for shorter signal lines by winding them. Chinese patent CN 113420527 B, entitled "A Method, Apparatus, System, and Storage Medium for Calculating Equal Length of Differential Lines," provides a calculation method that, in addition to the traditional method of calculating the differential line NP offset length error using design software, automatically determines the number of arcs required to arrive at the number of bulges to be compensated for and incorporates this compensation into the design.

[0007] Chinese patent CN 108630650A, "A Method and Apparatus for BGA Fan-Out Phase Compensation," describes a method that involves fanning out differential signals in a BGA region to form fan-out vias for the differential signals; and then performing winding compensation on the differential signal lines at the fan-out vias using a preset pattern. Both of these patents require layout and routing space to perform winding compensation, and the winding methods vary, but are generally determined by shape or location. This inevitably requires layout and routing space, and the winding introduces new impedance discontinuities. Furthermore, due to the need for additional space on the same layer, local compensation is often not possible, leading to an increase in the length of the differential phase mismatch. Summary of the Invention

[0008] In view of this, this invention proposes a method for minimizing the internal offset of differential pairs in PCBs, combining existing design and manufacturing processes. This method is used to optimize PCB design in order to minimize the internal offset of differential pairs, thereby improving the integrity of differential signals.

[0009] The differential via compensation method for channel in-line offset disclosed in this invention includes the following steps:

[0010] Obtain the PCB design that requires uncompensated differential offset, filter whether the link has differential vias, and if so, continue with the following steps;

[0011] Calculate the offset time between the differential signals NP;

[0012] Using the obtained material parameters, models of the PCB and differential vias are established;

[0013] The high-precision differential model was simulated, and the S-parameters of the differential via structure were obtained through simulation, including insertion loss, return loss and differential pair internal offset skew value.

[0014] The measured S-parameters and differential pair in-line offset skew values ​​are obtained to calibrate the scaling factor σ of the 3D model;

[0015] On a 3D model that meets the required accuracy, the stub length difference h in the differential via structure is simulated and optimized to minimize the offset skew of the differential structure and meet the predetermined design objectives.

[0016] Compare the optimization results to see if they meet the design's allowed target value for the inner offset of the differential pair. If they do, the optimization is complete; otherwise, continue optimizing the stub length difference h.

[0017] Furthermore, the differential via compensation for the internal offset delay is fitted, and the fitting formula is shown below:

[0018]

[0019] In the formula: f is the frequency of the transmitted signal, σ is the adjustment scaling factor, and ε r denoted as the relative permittivity of the PCB substrate, h as the length difference of the residual posts between differential vias, d as the via diameter, D1 as the diameter of the via pad, and D2 as the diameter of the via isolation.

[0020] Furthermore, the parameters f, σ, and ε r A high-precision 3D structural simulation model was built using h, d, D1, and D2 in the HFSS 3D module. The adjusted scaling factor σ was obtained after fitting and optimization through actual measurement.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] The technical solution proposed in this invention minimizes the space occupied by the layout and routing. Through a specially calculated differential via structure, the differential lines designed on the PCB can promptly compensate for differential phase shifts, effectively avoiding the impact of inward offset. Practical testing verifies that, with the optimized differential via structure compensation, the differential pair inward offset is less than 0.5ps, meeting the error requirements for differential pair inward offset. Furthermore, since the optimization method provided by this technical solution is applicable to the same design with a defined signal frequency, it significantly reduces the difficulty of optimization in actual mass applications. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the traditional differential via compensation method for channel in-line offset. Figure 1(a) is a PCB design diagram without differential offset compensation. Figure 1(b) is a simplified schematic diagram of Figure 1(a). Figure 1(c) is a schematic diagram of traditional same-layer winding compensation for in-line offset and differential via compensation for in-line offset.

[0024] Figure 2 Overall flowchart of the present invention;

[0025] Figure 3 is a schematic diagram of the differential via compensation channel internal offset method of the present invention. Figure 3(a) is a 3D view of the differential via, Figure 3(b) is a top view of the differential via, and Figure 3(c) is a 3D modeling diagram of the differential via.

[0026] Figure 4 (a) The traditional winding compensation structure is used. Figure 4 (b) is the differential via compensation structure for internal offset of the present invention. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings, but this is not intended to limit the present invention in any way. Any modifications or substitutions made based on the teachings of the present invention shall fall within the protection scope of the present invention.

[0028] The present invention provides a method for minimizing the in-line offset of differential pairs in PCBs, specifically including a differential via structure and its design optimization method. PCB, or Printed Circuit Board, is an important electronic component, serving as the support for electronic components and the carrier for their electrical connections. Because it is manufactured using electronic printing techniques, it is called a "printed" circuit board. Figure 1 is a schematic diagram of a traditional method for compensating for in-line offset of differential vias. Figure 2 This is the main flowchart of the technical solution of this invention. For example... Figure 2 As shown, the method for differential via compensation of channel in-pair offset proposed in this invention includes the following steps:

[0029] (1) Obtain the PCB design that requires uncompensated differential offset and screen whether the link has differential vias. If it is the compensation scheme of this invention, (most differential channels have differential vias). If there are no differential vias, use the traditional internal compensation method for routing. Differential line definition: A differential signal is two equal and opposite signals sent by the driver. The receiver determines the logic state "0" or "1" by comparing the difference between these two voltages. The pair of PCB traces carrying the differential signal is called a differential trace. Differential via: A signal layer switching via that appears in pairs in a differential channel.

[0030] (2) Calculate the offset time between differential signals NP using design software or PCB simulation software. PCB design software includes, but is not limited to, Cadence Allegro, Altium Designer, and Mentor. PCB simulation software includes, but is not limited to, Cadence Sigrity, Ansys Siwave, Mentor, CST, and Ansys HFSS. Most of the above PCB simulation software support 3D modeling.

[0031] (3) Using the obtained material parameters, 3D modeling software is used to create models of the PCB and differential vias. Commonly used 3D modeling software includes, but is not limited to, 3ds Max, Maya, ZBrush, C4D, Blender, SketchUp, CST, and ADS.

[0032] (4) Simulate the established high-precision differential model to obtain the S-parameters of the differential via structure, including insertion loss, return loss, and differential pair skew value. S-parameters are a tool for describing the electrical behavior of components under high-frequency signal excitation exhibiting radio frequency characteristics. They are described by measuring the measurable physical quantities "scattered" from the outside of the component after the component "responds" to the incident signal (i.e., "scatters"). The magnitude of the measured physical quantity reflects the different degrees to which components with different characteristics will "scatter" the same input signal. This different degree of scattering can be used to describe the characteristics of the component, and this method of expression has become a very useful electrical model. PCB traces and other transmission media exhibit this characteristic, and therefore can be characterized using S-parameters.

[0033] (5) The 3D model is calibrated using a scaling factor σ by obtaining the measured S-parameters and differential pair in-place offset skew values ​​from an advanced network analyzer. In some embodiments, the network analyzer used in this invention is a vector network analyzer.

[0034] (6) On a 3D model that meets the required accuracy, the length difference h of the stub (residual pile in the hole) in the differential through-hole structure is optimized by simulation to minimize the offset skew of the differential structure and meet the predetermined design goal.

[0035] (7) Compare whether the optimization results meet the design allowable differential pair internal offset target value. If they meet the target value, the optimization is completed. If they do not meet the target value, the stub length difference h is optimized.

[0036] Example

[0037] The design board has a relative permittivity of 4, a differential line length of 25.4 mm, an original P signal line length of 25.4 mm, an original N signal line length of 24.638 mm, and an original length offset of 0.762 mm. The via diameter is 0.254 mm, the via pad is 0.457 mm, and the via isolation diameter is 0.6604 mm. The difference between the internal offset of traditional in-layer wire-wound compensation and differential via compensation is as follows: Figure 4 As shown in the table below, the specific parameters of the wiring structure are as follows:

[0038]

[0039] The differential via compensation internal offset structure has one longer P signal line (original signal line length 25.4mm) and another longer N signal line (original signal line length 24.638mm). The internal offset compensation methods for traditional in-layer routing and differential via compensation are shown in Figure 1(c). Figure 4Figure (a) shows the differential via compensation structure for internal offset. The 3D model of the differential via is shown in Figure 3(c), where the difference h of the via residual is 1.016 mm. In Figure 3(c), the light-colored portion of the via is created using the blind via method, and the dark-colored portion is created using the back-drilling method. A blind via connects the inner layer trace of the PCB to the outer layer trace of the PCB; this via does not penetrate the entire board. Back-drilling removes through-hole segments that do not have a connecting or transmission function. Blind vias offer high precision but are also expensive, while back-drilling methods are less expensive. In some embodiments, if high via residual accuracy is required, the present invention uses the blind via method in the forward direction of the via. In some embodiments, if high via residual accuracy is not required but low cost is a priority, the present invention uses the back-drilling method in the reverse direction of the via.

[0040] The differential via compensation for internal offset delay can be fitted to Formula 1, where σ is a scaling factor used to adjust the calibration accuracy of the via structure. Under the same substrate and the same hole diameter, the via delay calculation formula, after modification, can approximately replace 3D modeling and simulation, thereby enabling rapid batch application.

[0041]

[0042] In the formula: f is the frequency of the transmitted signal (GHz), σ is the adjustment scaling factor, and ε r denoted as the relative permittivity of the PCB substrate, h as the length difference of the residual posts between differential vias (mm), d as the via diameter (mm), D1 as the diameter of the via pad (mm), and D2 as the diameter of the via isolation (mm).

[0043] A high-precision 3D structural simulation model was established in the HFSS 3D module using the above parameters. After the fitting scale factor was optimized to σ = 3.29 by actual measurement, the 3D simulation and actual measurement results of traditional differential winding compensation and differential via pair compensation were compared. It can be concluded that the differential pair offset was minimized without occupying the wiring space. Moreover, since this invention can compensate for the differential phase offset at the via, compared with other traditional winding schemes that require winding in an open area, the phase compensation is more timely and meets the requirement of maintaining the differential phase at 180 degrees to the greatest extent.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] 1) This invention utilizes the Z-axis space of the PCB to achieve inward skew compensation, which saves space (no need for winding) and is suitable for the needs of miniaturized PCBs.

[0046] 2) This invention will not introduce new impedance abrupt changes due to the need for winding bulges.

[0047] 3) This invention minimizes the space occupied by the routing layout. Through a specially calculated differential via structure, the differential lines on the PCB can promptly compensate for differential phase shifts, effectively mitigating the impact of inward offset. Actual testing confirms that with the optimized differential via structure, the differential pair inward offset is less than 0.5ps, meeting the error requirements for differential pair inward offset.

[0048] 4) Since the optimization method provided by this technical solution can be applied to the same design with a fixed signal frequency, it can greatly reduce the difficulty of optimization in actual batch applications.

[0049] 5) Compared to traditional winding schemes that require winding in open areas, this invention compensates for differential phase shift at vias, making phase compensation more timely and meeting the requirement of maintaining differential phase at 180 degrees to the greatest extent.

[0050] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X uses A or B" means that either permutation is naturally included. That is, "X uses A or B" is satisfied in any of the foregoing examples if X uses A; X uses B; or X uses both A and B.

[0051] In summary, the above embodiments are one implementation of the present invention, but the implementation of the present invention is not limited to the embodiments described above. Any changes, modifications, substitutions, combinations, or simplifications made that deviate from the spirit and principle of the present invention should be considered equivalent substitutions and are included within the protection scope of the present invention.

Claims

1. A method for differential via compensation of channel in-line offset, characterized in that, Includes the following steps: Obtain the PCB design that requires uncompensated differential offset, filter whether the link has differential vias, and if so, continue with the following steps; Calculate the offset time between the differential signals NP; Using the obtained material parameters, models of the PCB and differential vias are established; The high-precision differential model was simulated, and the S-parameters of the differential via structure were obtained through simulation, including insertion loss, return loss and differential pair internal offset skew value. Obtain the measured S-parameters and differential pair in-line offset skew values ​​from the design to calibrate the scaling factor for the 3D model. ; On a 3D model that meets the required accuracy, the stub length difference h in the differential via structure is simulated and optimized to minimize the offset skew of the differential structure and meet the predetermined design objectives. Compare the optimization results to see if they meet the design's allowed target value for the inner offset of the differential pair. If they do, the optimization is complete; otherwise, continue optimizing the stub length difference h. The differential via compensation internal offset delay is fitted using the following formula: In the formula: Td is the differential via compensation internal offset delay. f For the frequency of the transmitted signal, σ To adjust the scaling factor, The relative permittivity of the PCB substrate. h The difference in length between the residual piles in the differential boreholes. d The diameter of the via. D 1 represents the diameter of the via pad. D 2 represents the diameter of the via isolation; parameters f、σ , , h , d , D 1. D 2. A high-precision 3D structural simulation model was established in the HFSS 3D module, and the optimized adjustment scaling factor was obtained through actual measurement. σ .

2. The method for differential via compensation of channel inward offset according to claim 1, characterized in that, If the link does not have differential vias, internal compensation is performed using a wire wrapping method.

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