A method for parallel addressing of texture caches in a graphics processor
By optimizing texture cache access through parallel addressing methods, the problem of high texture cache latency in graphics processors is solved, thereby improving rendering performance and efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN LINGJIU MICROELECTRONICS CO LTD
- Filing Date
- 2022-11-22
- Publication Date
- 2026-05-15
AI Technical Summary
The high latency of texture cache addressing methods in existing graphics processors leads to insufficient rendering performance.
A parallel addressing method is adopted. By obtaining the texture memory address and calculating the texture cache access address, the address distribution of texture data in the memory and the coordinate characteristics of the fragment shading's demand for texture data are utilized. The top left texture unit is searched first, and parallel writing and reading are performed to avoid access conflicts and improve parallelism.
It improves texture cache hit rate and rendering performance, reduces access latency, and enhances the rendering efficiency of the graphics processor.
Smart Images
Figure CN115760545B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of graphics processor technology, and particularly relates to a parallel addressing method for texture cache in a graphics processor. Background Technology
[0002] In graphics processing units (GPUs), numerous access operations to texture data are required to represent the texture details of graphics. Due to the large volume of texture data, it is typically stored in off-chip memory, resulting in significant access latency. Setting up an appropriate on-chip texture cache can help reduce the number of off-chip memory accesses and the latency, thereby improving the performance of graphics rendering.
[0003] Since actual texture coordinates are typically decimals when mapped to texture patterns, rendering a single pixel often requires reading and interpolating the data from four horizontally and vertically adjacent textures to obtain the actual texture element data. Furthermore, the number of texture fragments that need to be rendered in a shader is enormous, and the size of the texture buffer is limited by hardware overhead, resulting in numerous texture buffer replacement and read operations.
[0004] When mapping off-chip memory texture data to the texture cache, an addressing method can be designed to effectively improve the parallelism of texture cache read and write. Combined with the coordinate characteristics of the texture data requirements of fragment shading, the hit rate of the texture cache can be improved, the access latency of texture data can be reduced, and the rendering performance of the graphics processor can be improved. Summary of the Invention
[0005] In view of the above problems, the purpose of this invention is to provide a parallel addressing method for texture cache in a graphics processor, which aims to solve the technical problem of high latency in existing texture cache addressing methods in graphics processors.
[0006] The present invention adopts the following technical solution:
[0007] The parallel addressing method for texture buffers in the graphics processor includes the following steps:
[0008] Step S1: Obtain the texture memory address to be accessed. Take the texture unit with the smaller LOD layer value and the upper left corner as the texture unit to be accessed. The texture memory address corresponding to the texture unit to be accessed is the texture memory address to be accessed. Extract the texture memory row address and the offset address within the row from it.
[0009] Step S2: Perform a modulo-4 operation on the texture memory row address and in-row offset address, and record the result as {m_offset, n_offset}. The access address of the texture unit to be accessed to the texture cache is: the base address of the texture cache of the 4x4 texture unit block where the texture unit to be accessed is located + (n_offset>>1) + (m_offset>>1)*2, where >> means right shift by several bits;
[0010] Step S3: Search the tag in the tag cache with {mipmap layer number, (texture memory line address >> 2), (line offset address >> 2)} as the tag to be accessed;
[0011] Step S4: If the target tag is not found in the tag cache, calculate the base address of the 4x4 texture unit block texture cache to be replaced and the corresponding tag.
[0012] Step S5: Calculate the 16 texture unit memory addresses corresponding to the 4x4 texture unit block based on the texture memory address of the texture unit to be accessed, and traverse the texture unit block in a 2x2 grid to read texture data from the memory.
[0013] Step S6: Perform modulo-2 operations on the texture memory row address and in-row offset address of each texture unit in the 2x2 grid in parallel, and select the corresponding valid texture cache according to the operation result.
[0014] Step S7: Write the 16 texture units in parallel to the four texture buffers for replacement;
[0015] Step S8: Read the required texture data from the texture cache in parallel, perform interpolation calculations, and then apply the texture mapping to the shader.
[0016] Furthermore, in step S3, if the target tag is hit in the tag cache, proceed directly to step S8.
[0017] Furthermore, in step S1, if the texture coordinates of the texture pattern obtained after transforming the fragment coordinates of the required texture map are non-integers, after rounding the adjacent horizontal and vertical coordinates of the texture coordinates and the adjacent LOD layer coordinates, there are a total of 8 texture units. The texture unit with the smallest LOD layer value and the top left corner is selected as the texture unit to be accessed.
[0018] Furthermore, in step S2, the initial value of the texture cache base address of the 4x4 texture unit block is 0, and the texture cache is filled first by the replacement algorithm.
[0019] Furthermore, in step S5, starting from the minimum memory address of the 16 texture units, the texture data is read from the memory by traversing the 4x4 texture unit block in a 2x2 grid, with the grid arranged from left to right and from top to bottom.
[0020] The beneficial effects of this invention are as follows: This invention utilizes the address distribution of texture data in video memory and the coordinate characteristics of fragment shading's demand for texture data. By calculating, sorting, addressing, mapping, writing, and reading texture video memory request addresses in parallel, it improves the parallelism of large-scale data access in the texture cache. In specific implementation, by rounding adjacent texture coordinates of decimals, the top-left texture unit is prioritized for searching, and replacement is performed in a 2x2 grid from left to right and top to bottom. Then, based on the relative position of the top-left texture unit with the 4x4 texture unit block, it is determined whether to continue searching and replacing the top-right, bottom-left, and bottom-right texture unit marks. This address sorting and addressing mapping avoids a large number of access conflicts, improves parallelism, and reduces access latency. Attached Figure Description
[0021] Figure 1 This is a flowchart of a parallel addressing method for texture buffers in a graphics processor provided in an embodiment of the present invention;
[0022] Figure 2 This is a diagram showing the relationship between the fragment to be colored and the texture unit provided in an embodiment of the present invention;
[0023] Figure 3 This is a diagram showing the relationship between video memory texture addresses and texture cache addressing provided in an embodiment of the present invention. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0025] To illustrate the technical solution described in this invention, specific embodiments are described below.
[0026] Figure 1 The flowchart of the parallel addressing method for texture cache in a graphics processor provided by an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown.
[0027] like Figure 1 As shown, the parallel addressing method for texture buffers in a graphics processor provided in this embodiment includes the following steps:
[0028] Step S1: Obtain the texture memory address to be accessed. Take the texture unit with the smaller LOD layer value and the upper left corner as the texture unit to be accessed. The texture memory address corresponding to the texture unit to be accessed is the texture memory address to be accessed. Extract the texture memory row address and the offset address within the row from it.
[0029] For fragment coordinates requiring texture mapping, a transformation is first performed, typically yielding texture coordinates within the mipmap texture patterns of two adjacent LOD layers, denoted as (s0, t0) and (s1, t1) respectively. If s0, t0, s1, and t1 are non-integers, such as... Figure 2 As shown, this illustrates the relationship between the fragment to be shaded and the texture units. It is necessary to sample the texture coordinates of adjacent positions. Specifically, after rounding the adjacent horizontal and vertical coordinates of the texture coordinates and rounding the adjacent LOD layers, there are a total of 8 texture units. Figure 2 In the diagram, the coordinates of the fragment to be shaded are represented by a solid circle. Since the coordinates are non-integer, the four adjacent texture units are selected, represented by the hollow circles in the diagram. Two adjacent LOD layers have a total of eight adjacent texture units with coordinates (s00, t00), (s01, t01), (s02, t02), (s03, t03), (s10, t10), (s11, t11), (s12, t12), and (s13, s13). The texture unit with the smaller LOD value, located in the upper left corner, is selected as the texture unit to be accessed. The corresponding texture memory address of the texture unit to be accessed is the texture memory address to be accessed.
[0030] Of course, if one or more of the LOD value, texture coordinates (x-coordinate, y-coordinate, etc.) are integers, the corresponding rounding may result in only 4, 2, or 1 adjacent texture units.
[0031] The memory address of the texture unit to be accessed can be represented as {base address, texture row address, in-row offset address}.
[0032] Step S2: Perform a modulo-4 operation on the texture memory row address and the in-row offset address, and record the result as {m_offset, n_offset}. The access address of the texture unit to be accessed to the texture cache is: the base address of the texture cache of the 4x4 texture unit block where the texture unit to be accessed is located + (n_offset>>1) + (m_offset>>1)*2, where >> means right shift by several bits.
[0033] The initial value of the 4x4 texture unit block texture cache base address is 0. The texture cache is filled first by the replacement algorithm before the texture cache base address that has been previously written with texture data is replaced. In this embodiment, a texture cache replacement algorithm based on the least recently used algorithm is selected.
[0034] Step S3: Search the tag in the tag cache with {mipmap layer number, (texture memory line address >> 2), (inline offset address >> 2)} as the tag to be accessed.
[0035] Step S4: If the target tag is not found in the tag cache, calculate the base address of the 4x4 texture unit block texture cache to be replaced and the corresponding tag.
[0036] If the target marker is not found in the marker cache, a replacement algorithm is used to obtain the base address of the texture cache to be replaced for the 4x4 texture unit block corresponding to the target marker, as well as the corresponding marker. If the target marker is found in the marker cache, there is no need to replace the base address of the 4x4 texture unit block texture cache and the marker cache; proceed directly to step S8. The initial value of the base address of the 4x4 texture unit block texture cache is 0. The replacement algorithm can first fill the texture cache before replacing the base address of the texture cache that has already been written with texture data.
[0037] Step S5: Calculate the 16 texture unit memory addresses corresponding to the 4x4 texture unit block based on the texture memory address of the texture unit to be accessed, and traverse the texture unit block in a 2x2 grid to read texture data from the memory.
[0038] During traversal, starting from the smallest memory address of the 16 texture units, the texture data is read from the memory of the 4x4 texture unit blocks in a 2x2 grid, with the grids arranged from left to right and from top to bottom.
[0039] Performing a modulo-4 operation on the texture memory row address yields the location of the texture unit to be accessed in the m_offset row within the 4x4 texture unit block. Performing a modulo-4 operation on the offset address within the texture memory row yields the location of the texture unit to be accessed in the n_offset column within the 4x4 texture unit block. In a 4x4 texture unit block, each texture buffer is mapped to 4 texture units.
[0040] The memory addresses of 16 texture units can be uniformly represented as {base address, texture row address: ±0~3, in-row offset address: ±(0~3)*(number of addresses occupied by one texture unit)}. Specifically:
[0041] When {m_offset}={0}, the addresses of the four texture rows in the memory addresses of the 16 texture units are +0, +1, +2, and +3, respectively.
[0042] When {m_offset}={1}, the addresses of four texture rows in the memory addresses of the 16 texture units are -1, +0, +1, and +2.
[0043] When {m_offset}={2}, the addresses of four texture rows in the memory addresses of the 16 texture units are -2, -1, +0, and +1.
[0044] When {m_offset}={3}, the addresses of four texture rows in the memory addresses of the 16 texture units are -3, -2, -1, and +0.
[0045] When {n_offset}={0}, the offset addresses within the four texture rows of the 16 texture units are (+0, +1, +2, +3)*(the number of addresses occupied by one texture unit)}.
[0046] When {n_offset}={1}, the offset addresses within the four texture rows in the memory addresses of the 16 texture units are (-1, +0, +1, +2)*(the number of addresses occupied by one texture unit)}.
[0047] When {n_offset}={2}, the offset addresses within the four texture rows in the memory addresses of the 16 texture units are (-2, -1, +0, +1)*(the number of addresses occupied by one texture unit)}.
[0048] When {n_offset}={3}, the offset addresses within the four texture rows of the 16 texture units are (-3, -2, -1, +0)*(the number of addresses occupied by one texture unit)}.
[0049] Step S6: Perform modulo-2 operations on the texture memory row address and in-row offset address of each texture unit in the 2x2 grid in parallel, and select the corresponding valid texture cache according to the operation result.
[0050] For example, there are four texture caches, numbered 0, 1, 2, and 3. The texture memory address resulting in {00} is selected as the valid texture cache chip 0; the address resulting in {01} is selected as the valid texture cache chip 1; the address resulting in {10} is selected as the valid texture cache chip 2; and the address resulting in {11} is selected as the valid texture cache chip 3. Here, the first bit from the left inside the curly braces is the result of the modulo-2 operation on the texture memory row address, and the second bit from the left is the result of the modulo-2 operation on the offset address within the row.
[0051] A modulo-2 operation on the texture memory row address results in a result of 0, indicating that the texture unit is in an even-numbered row, and a result of 1, indicating that the texture unit is in an odd-numbered row. A modulo-2 operation on the texture memory offset address within a row results in a result of 0, indicating that the texture unit is in an even-numbered column, and a result of 1, indicating that the texture unit is in an odd-numbered column.
[0052] Texture cache 0 is effective for texture unit selection in even rows and even columns, texture cache 1 is effective for texture unit selection in even rows and odd columns, texture cache 2 is effective for texture unit selection in odd rows and even columns, and texture cache 3 is effective for texture unit selection in odd rows and odd columns. Thus, four adjacent texture units (top, bottom, left, and right) are mapped in parallel to different texture caches.
[0053] Step S7: Write the 16 texture units in parallel to the four texture buffers for replacement.
[0054] The base address of the 16 texture units written to the texture cache is updated to the base address of the texture cache to be replaced according to the S4 method, and the marker is replaced with the marker to be replaced in the marker cache.
[0055] Combination Figure 3 The diagram showing the relationship between memory texture addresses and texture cache addressing shows that each time a 2x2 square texture unit is written in parallel to the texture cache, the cache address is updated to the base address of the texture cache to be replaced + (n_offset>>1) + (m_offset>>1)*2. These 4 texture units are written in parallel to texture caches 0, 1, 2, and 3 at the same cache address.
[0056] Step S8: Read the required texture data from the texture cache in parallel, perform interpolation calculations, and then apply the texture mapping to the shader.
[0057] The number of texture data required for parallel reading is determined by the relative position of the texture unit and the 4x4 texture unit block.
[0058] If the top-left texture unit to be accessed is located in the bottom row or right column of a 4x4 texture unit block, perform operations on the texture units located in the adjacent 4x4 texture unit blocks according to the aforementioned steps S2 to S7, and then read the required texture data from the texture cache in parallel.
[0059] If the top-left texture unit to be accessed is located in a non-bottom row and non-right column of a 4x4 texture unit block, then the texture units required for the current lod value can be read in parallel from the four texture buffers, and then the texture units of the (lod+1) value can be operated on according to the steps described above.
[0060] This invention selects the texture memory address of the top-left texture unit whose texture coordinates are adjacent and rounded down. It then extracts the texture memory row address and in-row offset address from this address. Next, it performs a modulo-4 operation on the texture memory row address and in-row offset address to calculate the access address of the texture cache corresponding to the texture unit. Then, it calculates the tag of the texture unit and searches in the tag cache. Using a replacement algorithm, it obtains the base address of the texture cache to be replaced for the corresponding 4x4 texture unit block and its corresponding tag. It calculates the memory address of the 4x4 texture unit block containing the texture unit, traverses the 4x4 texture unit block using a 2x2 grid to calculate the cache chip select and cache address, and writes these values in parallel to the texture cache for replacement. Finally, it reads the required data from the texture cache in parallel, performs subsequent interpolation operations, and then applies the data to the shader for texture mapping.
[0061] This invention improves the parallelism of large-scale data access to the texture cache by calculating, sorting, addressing, mapping, writing, and reading texture memory request addresses in parallel. By prioritizing the lookup of the top-left texture unit marker based on adjacent integer texture coordinates, and replacing addresses in a 2x2 grid from left to right and top to bottom, the invention avoids numerous access conflicts, thereby improving parallelism and reducing access latency.
[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A parallel addressing method for texture buffers in a graphics processor, characterized in that, The parallel addressing method includes the following steps: Step S1: Obtain the texture memory address to be accessed. Take the texture unit with the smaller LOD layer value and the upper left corner as the texture unit to be accessed. The texture memory address corresponding to the texture unit to be accessed is the texture memory address to be accessed. Extract the texture memory row address and the offset address within the row from it. Step S2: Perform a modulo-4 operation on the texture memory row address and in-row offset address, and record the result as {m_offset, n_offset}. The access address of the texture unit to be accessed to the texture cache is: the base address of the texture cache of the 4x4 texture unit block where the texture unit to be accessed is located + (n_offset>>1) + (m_offset>>1)*2, where >> means right shift by several bits; Step S3: Search the tag in the tag cache with {mipmap layer number, (texture memory line address >> 2), (line offset address >> 2)} as the tag to be accessed; Step S4: If the target tag is not found in the tag cache, calculate the base address of the 4x4 texture unit block texture cache to be replaced and the corresponding tag. Step S5: Calculate the 16 texture unit memory addresses corresponding to the 4x4 texture unit block based on the texture memory address of the texture unit to be accessed, and traverse the texture unit block in a 2x2 grid to read texture data from the memory. Step S6: Perform modulo-2 operations on the texture memory row address and in-row offset address of each texture unit in the 2x2 grid in parallel, and select the corresponding valid texture cache according to the operation result. Step S7: Write the 16 texture units in parallel to the four texture buffers for replacement; Step S8: Read the required texture data from the texture cache in parallel, perform interpolation calculations, and then apply the texture mapping to the shader.
2. The parallel addressing method for texture buffers in a graphics processor as described in claim 1, characterized in that, In step S3, if the target tag is hit in the tag cache, proceed directly to step S8.
3. The parallel addressing method for texture buffers in a graphics processor as described in claim 2, characterized in that, In step S1, if the texture coordinates of the texture pattern obtained after transforming the fragment coordinates of the required texture map are not integers, after rounding the adjacent horizontal and vertical coordinates of the texture coordinates and the adjacent LOD layer coordinates, there are a total of 8 texture units. The texture unit with the smallest LOD layer value and the top left corner is selected as the texture unit to be accessed.
4. The parallel addressing method for texture buffers in a graphics processor as described in claim 3, characterized in that, In step S2, the initial value of the texture cache base address of the 4x4 texture unit block is 0, and the texture cache is filled first by the replacement algorithm.
5. The parallel addressing method for texture buffers in a graphics processor as described in claim 4, characterized in that, In step S5, starting from the minimum memory address of the 16 texture units, the texture data is read from the memory by traversing the 4x4 texture unit block in a 2x2 grid, with the grid arranged from left to right and from top to bottom.
6. The parallel addressing method for texture buffers in a graphics processor as described in claim 5, characterized in that, In step S8, if the texture unit to be accessed is located in the bottom row or right column of the current 4x4 texture unit block, the texture units located in the adjacent 4x4 texture unit blocks that are adjacent to the current decimal texture coordinates are operated according to the aforementioned steps S2 to S7, and then the required texture data is read from the texture cache in parallel.